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From: Marek Vasut <marex@denx.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Marek Vasut <marex@denx.de>, Fabio Estevam <festevam@denx.de>,
	Peng Fan <peng.fan@nxp.com>, Richard Zhu <hongxing.zhu@nxp.com>,
	Shawn Guo <shawnguo@kernel.org>,
	NXP Linux Team <linux-imx@nxp.com>
Subject: [PATCH 2/3] arm64: dts: imx8mp: Deduplicate PCIe clock-names property
Date: Wed,  2 Nov 2022 22:22:47 +0100	[thread overview]
Message-ID: <20221102212248.138284-2-marex@denx.de> (raw)
In-Reply-To: <20221102212248.138284-1-marex@denx.de>

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts           | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi              | 1 +
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d3..aa1cfa337c1ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -380,9 +380,8 @@ &pcie {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-		 <&clk IMX8MP_CLK_PCIE_ROOT>,
-		 <&clk IMX8MP_CLK_HSIO_AXI>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+		 <&clk IMX8MP_CLK_HSIO_AXI>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>;
 	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 	assigned-clock-rates = <10000000>;
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index ceeca4966fc5c..8a8f2a7b7a5e8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -594,9 +594,8 @@ &pcie {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-		 <&clk IMX8MP_CLK_PCIE_ROOT>,
-		 <&clk IMX8MP_CLK_HSIO_AXI>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+		 <&clk IMX8MP_CLK_HSIO_AXI>,
+		 <&clk IMX8MP_CLK_PCIE_ROOT>;
 	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 	assigned-clock-rates = <10000000>;
 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index d7039d9fe61ad..69f8b2a42528a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1192,6 +1192,7 @@ pcie: pcie@33800000 {
 					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <3>;
 			linux,pci-domain = <0>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
 			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
 			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
 				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
-- 
2.35.1


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  reply	other threads:[~2022-11-02 21:24 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-02 21:22 [PATCH 1/3] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
2022-11-02 21:22 ` Marek Vasut [this message]
2022-11-03  8:00   ` [PATCH 2/3] arm64: dts: imx8mp: " Alexander Stein
2022-11-02 21:22 ` [PATCH 3/3] arm64: dts: imx8mq: " Marek Vasut
2022-11-03  7:56   ` Alexander Stein
2022-11-03  7:58 ` [PATCH 1/3] arm64: dts: imx8mm: " Alexander Stein
2022-11-11  6:33 ` Shawn Guo
2022-11-11 14:03   ` Marek Vasut

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