* [PATCH v2 0/6] add adc0 flexspi lpspi to 8dxl evk board dts
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add adc0 flexspi lpspi and adc to 8dxl evk board dts
Change from v1 to v2:
split SOC and board change to two patches.
Frank Li (6):
arm64: dts: imx8dxl: add adc0 support
arm64: dts: imx8dxl_evk: add adc0 support
arm64: dts: imx8dxl: add flexspi0 support
arm64: dts: imx8dxl_evk: add flexspi0 support
arm64: dts: imx8dxl: add lpspi support
arm64: dts: imx8dxl_evk: add lpspi0 support
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 164 ++++++++++++++++++
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 17 +-
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 63 +++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 20 +++
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +
5 files changed, 268 insertions(+), 1 deletion(-)
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/6] arm64: dts: imx8dxl: add adc0 support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add adc0 and adc1 node at imx8 common dma subsystem.
imx8dxl have only adc0. Change irq number for adc0.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index d7b4229bb4a2..bdbb660c2682 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -156,6 +156,34 @@ i2c3: i2c@5a830000 {
status = "disabled";
};
+ adc0: adc@5a880000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a880000 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc0_lpcg 0>,
+ <&adc0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ status = "disabled";
+ };
+
+ adc1: adc@5a890000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a890000 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc1_lpcg 0>,
+ <&adc1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ status = "disabled";
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 {
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
+
+ adc0_lpcg: clock-controller@5ac80000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac80000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc0_lpcg_clk",
+ "adc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ };
+
+ adc1_lpcg: clock-controller@5ac90000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac90000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc1_lpcg_clk",
+ "adc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 795d1d472fae..ac3362e32811 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -11,6 +11,10 @@ &dma_ipg_clk {
clock-frequency = <160000000>;
};
+&adc0 {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 1/6] arm64: dts: imx8dxl: add adc0 support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add adc0 and adc1 node at imx8 common dma subsystem.
imx8dxl have only adc0. Change irq number for adc0.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index d7b4229bb4a2..bdbb660c2682 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -156,6 +156,34 @@ i2c3: i2c@5a830000 {
status = "disabled";
};
+ adc0: adc@5a880000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a880000 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc0_lpcg 0>,
+ <&adc0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ status = "disabled";
+ };
+
+ adc1: adc@5a890000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a890000 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc1_lpcg 0>,
+ <&adc1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ status = "disabled";
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 {
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
+
+ adc0_lpcg: clock-controller@5ac80000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac80000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc0_lpcg_clk",
+ "adc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ };
+
+ adc1_lpcg: clock-controller@5ac90000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac90000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc1_lpcg_clk",
+ "adc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 795d1d472fae..ac3362e32811 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -11,6 +11,10 @@ &dma_ipg_clk {
clock-frequency = <160000000>;
};
+&adc0 {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/6] arm64: dts: imx8dxl_evk: add adc0 support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable adc0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index fc9647ea50e9..11b1ff90c06d 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -91,6 +91,13 @@ reg_usdhc2_vmmc: regulator-3 {
off-on-delay-us = <3480>;
};
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
mii_select: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "mii-select";
@@ -102,6 +109,11 @@ mii_select: regulator-4 {
};
};
+&adc0 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/6] arm64: dts: imx8dxl_evk: add adc0 support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable adc0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index fc9647ea50e9..11b1ff90c06d 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -91,6 +91,13 @@ reg_usdhc2_vmmc: regulator-3 {
off-on-delay-us = <3480>;
};
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
mii_select: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "mii-select";
@@ -102,6 +109,11 @@ mii_select: regulator-4 {
};
};
+&adc0 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/6] arm64: dts: imx8dxl: add flexspi0 support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add flexspi0 node at common lsio subsystem.
Change flexspi0 irq number for imx8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 17 ++++++++++++++++-
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 6446e6df7a9a..1f3d225e64ec 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
+ <0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
@@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
+ flexspi0: spi@5d120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8qxp-fspi";
+ reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
+ clock-names = "fspi", "fspi_en";
+ power-domains = <&pd IMX_SC_R_FSPI_0>;
+ status = "disabled";
+ };
+
lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
index 815bd987b09b..85e6131ec406 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -3,6 +3,11 @@
* Copyright 2019~2020, 2022 NXP
*/
+&flexspi0 {
+ compatible = "nxp,imx8dxl-fspi";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&lsio_gpio0 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 3/6] arm64: dts: imx8dxl: add flexspi0 support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add flexspi0 node at common lsio subsystem.
Change flexspi0 irq number for imx8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 17 ++++++++++++++++-
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index 6446e6df7a9a..1f3d225e64ec 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
+ ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
+ <0x08000000 0x0 0x08000000 0x10000000>;
lsio_mem_clk: clock-lsio-mem {
compatible = "fixed-clock";
@@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 {
power-domains = <&pd IMX_SC_R_GPIO_7>;
};
+ flexspi0: spi@5d120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8qxp-fspi";
+ reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>;
+ clock-names = "fspi", "fspi_en";
+ power-domains = <&pd IMX_SC_R_FSPI_0>;
+ status = "disabled";
+ };
+
lsio_mu0: mailbox@5d1b0000 {
reg = <0x5d1b0000 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
index 815bd987b09b..85e6131ec406 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -3,6 +3,11 @@
* Copyright 2019~2020, 2022 NXP
*/
+&flexspi0 {
+ compatible = "nxp,imx8dxl-fspi";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&lsio_gpio0 {
compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 4/6] arm64: dts: imx8dxl_evk: add flexspi0 support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable flexspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 11b1ff90c06d..f8d416f7fd92 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -181,6 +181,23 @@ vddio1: vddio-regulator {
};
};
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ nxp,fspi-dll-slvdly = <4>;
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <133000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -386,6 +403,25 @@ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 4/6] arm64: dts: imx8dxl_evk: add flexspi0 support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable flexspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 11b1ff90c06d..f8d416f7fd92 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -181,6 +181,23 @@ vddio1: vddio-regulator {
};
};
+&flexspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ nxp,fspi-dll-slvdly = <4>;
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <133000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
@@ -386,6 +403,25 @@ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
+ IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
+ IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
+ IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
+ IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
+ IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
+ IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
+ IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
+ IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
+ IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
+ IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
+ IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
+ IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
+ IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
+ >;
+ };
+
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 5/6] arm64: dts: imx8dxl: add lpspi support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem.
Change irq number for 8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 112 ++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 16 +++
2 files changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index bdbb660c2682..a943a1e2797f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg {
clock-output-names = "dma_ipg_clk";
};
+ lpspi0: spi@5a000000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi0_lpcg 0>,
+ <&spi0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <20000000>;
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi1_lpcg 0>,
+ <&spi1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ status = "disabled";
+ };
+
+ lpspi2: spi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi2_lpcg 0>,
+ <&spi2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@5a030000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi3_lpcg 0>,
+ <&spi3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ status = "disabled";
+ };
+
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,6 +124,54 @@ lpuart3: serial@5a090000 {
status = "disabled";
};
+ spi0_lpcg: clock-controller@5a400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi0_lpcg_clk",
+ "spi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ };
+
+ spi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
+ spi2_lpcg: clock-controller@5a420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi2_lpcg_clk",
+ "spi2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ };
+
+ spi3_lpcg: clock-controller@5a430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi3_lpcg_clk",
+ "spi3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ };
+
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index ac3362e32811..6881330ab4c6 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -54,3 +54,19 @@ &lpuart3 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&lpspi0 {
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi1 {
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi2 {
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi3 {
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 5/6] arm64: dts: imx8dxl: add lpspi support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem.
Change irq number for 8dxl.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 112 ++++++++++++++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 16 +++
2 files changed, 128 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index bdbb660c2682..a943a1e2797f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg {
clock-output-names = "dma_ipg_clk";
};
+ lpspi0: spi@5a000000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi0_lpcg 0>,
+ <&spi0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <20000000>;
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi1_lpcg 0>,
+ <&spi1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ status = "disabled";
+ };
+
+ lpspi2: spi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi2_lpcg 0>,
+ <&spi2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@5a030000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi3_lpcg 0>,
+ <&spi3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ status = "disabled";
+ };
+
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,6 +124,54 @@ lpuart3: serial@5a090000 {
status = "disabled";
};
+ spi0_lpcg: clock-controller@5a400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi0_lpcg_clk",
+ "spi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ };
+
+ spi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
+ spi2_lpcg: clock-controller@5a420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi2_lpcg_clk",
+ "spi2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ };
+
+ spi3_lpcg: clock-controller@5a430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi3_lpcg_clk",
+ "spi3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ };
+
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index ac3362e32811..6881330ab4c6 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -54,3 +54,19 @@ &lpuart3 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};
+
+&lpspi0 {
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi1 {
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi2 {
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpspi3 {
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 6/6] arm64: dts: imx8dxl_evk: add lpspi0 support
2022-11-11 15:47 ` Frank Li
@ 2022-11-11 15:47 ` Frank Li
-1 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable lpspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index f8d416f7fd92..280a9c9d8bd9 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -359,6 +359,21 @@ &usdhc2 {
status = "okay";
};
+&lpspi3 {
+ fsl,spi-num-chipselects = <1>;
+ fsl,spi-only-use-cs1-sel;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi3>;
+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <30000000>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 6/6] arm64: dts: imx8dxl_evk: add lpspi0 support
@ 2022-11-11 15:47 ` Frank Li
0 siblings, 0 replies; 16+ messages in thread
From: Frank Li @ 2022-11-11 15:47 UTC (permalink / raw)
To: shawnguo
Cc: Frank.Li, aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
Enable lpspi0 at imx8dxl_evk boards dts.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index f8d416f7fd92..280a9c9d8bd9 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -359,6 +359,21 @@ &usdhc2 {
status = "okay";
};
+&lpspi3 {
+ fsl,spi-num-chipselects = <1>;
+ fsl,spi-only-use-cs1-sel;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi3>;
+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <30000000>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 0/6] add adc0 flexspi lpspi to 8dxl evk board dts
2022-11-11 15:47 ` Frank Li
@ 2022-11-14 8:49 ` Shawn Guo
-1 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2022-11-14 8:49 UTC (permalink / raw)
To: Frank Li
Cc: aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
On Fri, Nov 11, 2022 at 10:47:36AM -0500, Frank Li wrote:
> Add adc0 flexspi lpspi and adc to 8dxl evk board dts
>
> Change from v1 to v2:
> split SOC and board change to two patches.
>
> Frank Li (6):
> arm64: dts: imx8dxl: add adc0 support
> arm64: dts: imx8dxl_evk: add adc0 support
> arm64: dts: imx8dxl: add flexspi0 support
> arm64: dts: imx8dxl_evk: add flexspi0 support
> arm64: dts: imx8dxl: add lpspi support
> arm64: dts: imx8dxl_evk: add lpspi0 support
Applied all, thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 0/6] add adc0 flexspi lpspi to 8dxl evk board dts
@ 2022-11-14 8:49 ` Shawn Guo
0 siblings, 0 replies; 16+ messages in thread
From: Shawn Guo @ 2022-11-14 8:49 UTC (permalink / raw)
To: Frank Li
Cc: aisheng.dong, devicetree, festevam, han.xu, imx, kernel,
krzysztof.kozlowski+dt, linux-arm-kernel, linux-imx, linux-kernel,
peng.fan, robh+dt, s.hauer, shenwei.wang
On Fri, Nov 11, 2022 at 10:47:36AM -0500, Frank Li wrote:
> Add adc0 flexspi lpspi and adc to 8dxl evk board dts
>
> Change from v1 to v2:
> split SOC and board change to two patches.
>
> Frank Li (6):
> arm64: dts: imx8dxl: add adc0 support
> arm64: dts: imx8dxl_evk: add adc0 support
> arm64: dts: imx8dxl: add flexspi0 support
> arm64: dts: imx8dxl_evk: add flexspi0 support
> arm64: dts: imx8dxl: add lpspi support
> arm64: dts: imx8dxl_evk: add lpspi0 support
Applied all, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread