From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Michael Rolnik" <mrolnik@gmail.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Taylor Simpson" <tsimpson@quicinc.com>,
"Song Gao" <gaosong@loongson.cn>,
"Xiaojuan Yang" <yangxiaojuan@loongson.cn>,
"Laurent Vivier" <laurent@vivier.eu>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Chris Wulff" <crwulff@gmail.com>, "Marek Vasut" <marex@denx.de>,
"Stafford Horne" <shorne@gmail.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Greg Kurz" <groug@kaod.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Max Filippov" <jcmvbkbc@gmail.com>,
qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH for-8.0 00/19] Convert most CPU classes to 3-phase reset
Date: Thu, 24 Nov 2022 11:50:03 +0000 [thread overview]
Message-ID: <20221124115023.2437291-1-peter.maydell@linaro.org> (raw)
This patchset converts the TYPE_CPU base class and most subclasses
to use 3-phase reset. (The exception is s390, which is doing
something a bit odd with its reset, so the conversion there isn't
going to be simple like these others. So I'll do that one
separately.)
The rationale here is that we should be able to get rid of
all the remaining uses of device_class_set_parent_reset()
and remove/simplify some of the transitional code that's
currently bridging between "legacy" reset and 3-phase reset.
NB: even with this series, it's not possible to usefully do
anything requiring 3-phase reset of a CPU yet, because all
CPU objects get ad-hoc reset by some code somewhere doing
a cpu_reset() call on them, which will just do all 3 phases
in order. I would like to try to address that eventually,
but it's not trivial.
thanks
-- PMM
Peter Maydell (19):
hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset
target/arm: Convert to 3-phase reset
target/avr: Convert to 3-phase reset
target/cris: Convert to 3-phase reset
target/hexagon: Convert to 3-phase reset
target/i386: Convert to 3-phase reset
target/loongarch: Convert to 3-phase reset
target/m68k: Convert to 3-phase reset
target/microblaze: Convert to 3-phase reset
target/mips: Convert to 3-phase reset
target/nios2: Convert to 3-phase reset
target/openrisc: Convert to 3-phase reset
target/ppc: Convert to 3-phase reset
target/riscv: Convert to 3-phase reset
target/rx: Convert to 3-phase reset
target/sh4: Convert to 3-phase reset
target/sparc: Convert to 3-phase reset
target/tricore: Convert to 3-phase reset
target/xtensa: Convert to 3-phase reset
target/arm/cpu-qom.h | 4 ++--
target/avr/cpu-qom.h | 4 ++--
target/cris/cpu-qom.h | 4 ++--
target/hexagon/cpu.h | 2 +-
target/i386/cpu-qom.h | 4 ++--
target/loongarch/cpu.h | 4 ++--
target/m68k/cpu-qom.h | 4 ++--
target/microblaze/cpu-qom.h | 4 ++--
target/mips/cpu-qom.h | 4 ++--
target/nios2/cpu.h | 4 ++--
target/openrisc/cpu.h | 4 ++--
target/ppc/cpu-qom.h | 4 ++--
target/riscv/cpu.h | 4 ++--
target/rx/cpu-qom.h | 4 ++--
target/sh4/cpu-qom.h | 4 ++--
target/sparc/cpu-qom.h | 4 ++--
target/tricore/cpu-qom.h | 2 +-
target/xtensa/cpu-qom.h | 4 ++--
hw/core/cpu-common.c | 7 ++++---
target/arm/cpu.c | 13 +++++++++----
target/avr/cpu.c | 13 +++++++++----
target/cris/cpu.c | 12 ++++++++----
target/hexagon/cpu.c | 12 ++++++++----
target/i386/cpu.c | 12 ++++++++----
target/loongarch/cpu.c | 12 ++++++++----
target/m68k/cpu.c | 12 ++++++++----
target/microblaze/cpu.c | 12 ++++++++----
target/mips/cpu.c | 12 ++++++++----
target/nios2/cpu.c | 12 ++++++++----
target/openrisc/cpu.c | 12 ++++++++----
target/ppc/cpu_init.c | 12 ++++++++----
target/riscv/cpu.c | 12 ++++++++----
target/rx/cpu.c | 13 ++++++++-----
target/sh4/cpu.c | 12 ++++++++----
target/sparc/cpu.c | 12 ++++++++----
target/tricore/cpu.c | 12 ++++++++----
target/xtensa/cpu.c | 12 ++++++++----
37 files changed, 184 insertions(+), 110 deletions(-)
--
2.25.1
next reply other threads:[~2022-11-24 11:50 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-24 11:50 Peter Maydell [this message]
2022-11-24 11:50 ` [PATCH for-8.0 01/19] hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset Peter Maydell
2022-11-27 22:30 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 02/19] target/arm: Convert " Peter Maydell
2022-11-24 15:15 ` Cédric Le Goater
2022-11-27 22:28 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 03/19] target/avr: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 04/19] target/cris: " Peter Maydell
2022-11-24 14:44 ` Edgar E. Iglesias
2022-11-24 11:50 ` [PATCH for-8.0 05/19] target/hexagon: " Peter Maydell
2022-11-30 4:38 ` Taylor Simpson
2022-11-24 11:50 ` [PATCH for-8.0 06/19] target/i386: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 07/19] target/loongarch: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 08/19] target/m68k: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 09/19] target/microblaze: " Peter Maydell
2022-11-24 14:44 ` Edgar E. Iglesias
2022-11-24 11:50 ` [PATCH for-8.0 10/19] target/mips: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 11/19] target/nios2: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 12/19] target/openrisc: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 13/19] target/ppc: " Peter Maydell
2022-11-24 15:15 ` Cédric Le Goater
2022-11-24 15:18 ` Greg Kurz
2022-11-24 11:50 ` [PATCH for-8.0 14/19] target/riscv: " Peter Maydell
2022-11-27 22:29 ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 15/19] target/rx: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 16/19] target/sh4: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 17/19] target/sparc: " Peter Maydell
2022-11-30 9:23 ` Mark Cave-Ayland
2022-11-24 11:50 ` [PATCH for-8.0 18/19] target/tricore: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 19/19] target/xtensa: " Peter Maydell
2022-11-24 13:46 ` [PATCH for-8.0 00/19] Convert most CPU classes " Philippe Mathieu-Daudé
2022-11-30 10:51 ` Philippe Mathieu-Daudé
2022-11-30 12:38 ` Peter Maydell
2022-11-30 13:22 ` Philippe Mathieu-Daudé
2022-11-26 15:50 ` Richard Henderson
2022-12-16 16:02 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221124115023.2437291-1-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=aleksandar.rikalo@syrmia.com \
--cc=alistair.francis@wdc.com \
--cc=atar4qemu@gmail.com \
--cc=aurelien@aurel32.net \
--cc=bin.meng@windriver.com \
--cc=clg@kaod.org \
--cc=crwulff@gmail.com \
--cc=danielhb413@gmail.com \
--cc=david@gibson.dropbear.id.au \
--cc=edgar.iglesias@gmail.com \
--cc=gaosong@loongson.cn \
--cc=groug@kaod.org \
--cc=jcmvbkbc@gmail.com \
--cc=jiaxun.yang@flygoat.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=laurent@vivier.eu \
--cc=marex@denx.de \
--cc=mark.cave-ayland@ilande.co.uk \
--cc=mrolnik@gmail.com \
--cc=palmer@dabbelt.com \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=shorne@gmail.com \
--cc=tsimpson@quicinc.com \
--cc=yangxiaojuan@loongson.cn \
--cc=ysato@users.sourceforge.jp \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.