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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Taylor Simpson" <tsimpson@quicinc.com>,
	"Song Gao" <gaosong@loongson.cn>,
	"Xiaojuan Yang" <yangxiaojuan@loongson.cn>,
	"Laurent Vivier" <laurent@vivier.eu>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Chris Wulff" <crwulff@gmail.com>, "Marek Vasut" <marex@denx.de>,
	"Stafford Horne" <shorne@gmail.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	"Greg Kurz" <groug@kaod.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Artyom Tarasenko" <atar4qemu@gmail.com>,
	"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
	"Max Filippov" <jcmvbkbc@gmail.com>,
	qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH for-8.0 03/19] target/avr: Convert to 3-phase reset
Date: Thu, 24 Nov 2022 11:50:06 +0000	[thread overview]
Message-ID: <20221124115023.2437291-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221124115023.2437291-1-peter.maydell@linaro.org>

Convert the avr CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/avr/cpu-qom.h |  4 ++--
 target/avr/cpu.c     | 13 +++++++++----
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index b5c3507d6d7..01ea5f160b6 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -31,7 +31,7 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
 /**
  *  AVRCPUClass:
  *  @parent_realize: The parent class' realize handler.
- *  @parent_reset: The parent class' reset handler.
+ *  @parent_phases: The parent class' reset phase handlers.
  *
  *  A AVR CPU model.
  */
@@ -40,7 +40,7 @@ struct AVRCPUClass {
     CPUClass parent_class;
     /*< public >*/
     DeviceRealize parent_realize;
-    DeviceReset parent_reset;
+    ResettablePhases parent_phases;
 };
 
 
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index c7295b488d1..d0139804b9f 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -67,14 +67,16 @@ static void avr_restore_state_to_opc(CPUState *cs,
     env->pc_w = data[0];
 }
 
-static void avr_cpu_reset(DeviceState *ds)
+static void avr_cpu_reset_hold(Object *obj)
 {
-    CPUState *cs = CPU(ds);
+    CPUState *cs = CPU(obj);
     AVRCPU *cpu = AVR_CPU(cs);
     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
     CPUAVRState *env = &cpu->env;
 
-    mcc->parent_reset(ds);
+    if (mcc->parent_phases.hold) {
+        mcc->parent_phases.hold(obj);
+    }
 
     env->pc_w = 0;
     env->sregI = 1;
@@ -223,9 +225,12 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
     DeviceClass *dc = DEVICE_CLASS(oc);
     CPUClass *cc = CPU_CLASS(oc);
     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
 
     device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
-    device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
+
+    resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
+                                       &mcc->parent_phases);
 
     cc->class_by_name = avr_cpu_class_by_name;
 
-- 
2.25.1



  parent reply	other threads:[~2022-11-24 11:50 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24 11:50 [PATCH for-8.0 00/19] Convert most CPU classes to 3-phase reset Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 01/19] hw/core/cpu-common: Convert TYPE_CPU class " Peter Maydell
2022-11-27 22:30   ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 02/19] target/arm: Convert " Peter Maydell
2022-11-24 15:15   ` Cédric Le Goater
2022-11-27 22:28   ` Alistair Francis
2022-11-24 11:50 ` Peter Maydell [this message]
2022-11-24 11:50 ` [PATCH for-8.0 04/19] target/cris: " Peter Maydell
2022-11-24 14:44   ` Edgar E. Iglesias
2022-11-24 11:50 ` [PATCH for-8.0 05/19] target/hexagon: " Peter Maydell
2022-11-30  4:38   ` Taylor Simpson
2022-11-24 11:50 ` [PATCH for-8.0 06/19] target/i386: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 07/19] target/loongarch: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 08/19] target/m68k: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 09/19] target/microblaze: " Peter Maydell
2022-11-24 14:44   ` Edgar E. Iglesias
2022-11-24 11:50 ` [PATCH for-8.0 10/19] target/mips: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 11/19] target/nios2: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 12/19] target/openrisc: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 13/19] target/ppc: " Peter Maydell
2022-11-24 15:15   ` Cédric Le Goater
2022-11-24 15:18   ` Greg Kurz
2022-11-24 11:50 ` [PATCH for-8.0 14/19] target/riscv: " Peter Maydell
2022-11-27 22:29   ` Alistair Francis
2022-11-24 11:50 ` [PATCH for-8.0 15/19] target/rx: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 16/19] target/sh4: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 17/19] target/sparc: " Peter Maydell
2022-11-30  9:23   ` Mark Cave-Ayland
2022-11-24 11:50 ` [PATCH for-8.0 18/19] target/tricore: " Peter Maydell
2022-11-24 11:50 ` [PATCH for-8.0 19/19] target/xtensa: " Peter Maydell
2022-11-24 13:46 ` [PATCH for-8.0 00/19] Convert most CPU classes " Philippe Mathieu-Daudé
2022-11-30 10:51   ` Philippe Mathieu-Daudé
2022-11-30 12:38     ` Peter Maydell
2022-11-30 13:22       ` Philippe Mathieu-Daudé
2022-11-26 15:50 ` Richard Henderson
2022-12-16 16:02 ` Peter Maydell

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