* [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:59 ` Philippe Mathieu-Daudé
2022-12-28 12:42 ` [PATCH v2 02/10] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
` (8 subsequent siblings)
9 siblings, 1 reply; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Cleber Rosa, Philippe Mathieu-Daudé
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The riscv32 'spike' machine isn't bootable at this moment, requiring an
Opensbi fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as Opensbi
QEMU rom receives the fix, we're adding a 'skip' test:
(11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike:
SKIP: requires OpenSBI fix to work
[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 tests/avocado/riscv_opensbi.py
diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
new file mode 100644
index 0000000000..64fcf3c774
--- /dev/null
+++ b/tests/avocado/riscv_opensbi.py
@@ -0,0 +1,77 @@
+# opensbi boot test for RISC-V machines
+#
+# Copyright (c) 2022, Ventana Micro
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado import skip
+from avocado_qemu import wait_for_console_pattern
+
+class RiscvOpensbi(QemuSystemTest):
+ """
+ :avocado: tags=accel:tcg
+ """
+ timeout = 5
+
+ def test_riscv64_virt(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv64_spike(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:spike
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv64_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:sifive_u
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv32_virt(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:virt
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ def test_riscv32_sifive_u(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:sifive_u
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+ @skip("requires OpenSBI fix to work")
+ def test_riscv32_spike(self):
+ """
+ :avocado: tags=arch:riscv32
+ :avocado: tags=machine:spike
+ """
+ self.vm.set_console()
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Platform Name')
+ wait_for_console_pattern(self, 'Boot HART MEDELEG')
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test
2022-12-28 12:42 ` [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
@ 2022-12-28 12:59 ` Philippe Mathieu-Daudé
2022-12-28 13:03 ` Daniel Henrique Barboza
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-28 12:59 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng, Cleber Rosa
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
> This test is used to do a quick sanity check to ensure that we're able
> to run the existing QEMU FW image.
>
> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
> RISCV32_BIOS_BIN firmware with minimal options.
>
> The riscv32 'spike' machine isn't bootable at this moment, requiring an
> Opensbi fix [1] and QEMU side changes [2]. We could just leave at that
> or add a 'skip' test to remind us about it. To work as a reminder that
> we have a riscv32 'spike' test that should be enabled as soon as Opensbi
> QEMU rom receives the fix, we're adding a 'skip' test:
>
> (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike:
> SKIP: requires OpenSBI fix to work
>
> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
> [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
>
> Cc: Cleber Rosa <crosa@redhat.com>
> Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 tests/avocado/riscv_opensbi.py
>
> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
> new file mode 100644
> index 0000000000..64fcf3c774
> --- /dev/null
> +++ b/tests/avocado/riscv_opensbi.py
> @@ -0,0 +1,77 @@
> +# opensbi boot test for RISC-V machines
s/opensbi/OpenSBI/
> +#
> +# Copyright (c) 2022, Ventana Micro
> +#
> +# This work is licensed under the terms of the GNU GPL, version 2 or
> +# later. See the COPYING file in the top-level directory.
> +
> +from avocado_qemu import QemuSystemTest
> +from avocado import skip
> +from avocado_qemu import wait_for_console_pattern
> +
> +class RiscvOpensbi(QemuSystemTest):
> + """
> + :avocado: tags=accel:tcg
> + """
> + timeout = 5
Easier to review common code once:
def boot_opensbi(self):
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG')
> +
> + def test_riscv64_virt(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + """
self.boot_opensbi()
> + def test_riscv64_spike(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:spike
> + """
self.boot_opensbi()
[...]
> + @skip("requires OpenSBI fix to work")
> + def test_riscv32_spike(self):
> + """
> + :avocado: tags=arch:riscv32
> + :avocado: tags=machine:spike
> + """
self.boot_opensbi()
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test
2022-12-28 12:59 ` Philippe Mathieu-Daudé
@ 2022-12-28 13:03 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 13:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng, Cleber Rosa
On 12/28/22 09:59, Philippe Mathieu-Daudé wrote:
> On 28/12/22 13:42, Daniel Henrique Barboza wrote:
>> This test is used to do a quick sanity check to ensure that we're able
>> to run the existing QEMU FW image.
>>
>> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
>> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
>> RISCV32_BIOS_BIN firmware with minimal options.
>>
>> The riscv32 'spike' machine isn't bootable at this moment, requiring an
>> Opensbi fix [1] and QEMU side changes [2]. We could just leave at that
>> or add a 'skip' test to remind us about it. To work as a reminder that
>> we have a riscv32 'spike' test that should be enabled as soon as Opensbi
>> QEMU rom receives the fix, we're adding a 'skip' test:
>>
>> (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike:
>> SKIP: requires OpenSBI fix to work
>>
>> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
>> [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
>>
>> Cc: Cleber Rosa <crosa@redhat.com>
>> Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 77 insertions(+)
>> create mode 100644 tests/avocado/riscv_opensbi.py
>>
>> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
>> new file mode 100644
>> index 0000000000..64fcf3c774
>> --- /dev/null
>> +++ b/tests/avocado/riscv_opensbi.py
>> @@ -0,0 +1,77 @@
>> +# opensbi boot test for RISC-V machines
>
> s/opensbi/OpenSBI/
>
>> +#
>> +# Copyright (c) 2022, Ventana Micro
>> +#
>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>> +# later. See the COPYING file in the top-level directory.
>> +
>> +from avocado_qemu import QemuSystemTest
>> +from avocado import skip
>> +from avocado_qemu import wait_for_console_pattern
>> +
>> +class RiscvOpensbi(QemuSystemTest):
>> + """
>> + :avocado: tags=accel:tcg
>> + """
>> + timeout = 5
>
> Easier to review common code once:
>
> def boot_opensbi(self):
> self.vm.set_console()
> self.vm.launch()
> wait_for_console_pattern(self, 'Platform Name')
> wait_for_console_pattern(self, 'Boot HART MEDELEG')
Yeah I mean, here I am, adding duplicated logic in a series that was aimed to
reduce duplicated logic :D
I'll refactor it in v3. Thanks!
Daniel
>
>> +
>> + def test_riscv64_virt(self):
>> + """
>> + :avocado: tags=arch:riscv64
>> + :avocado: tags=machine:virt
>> + """
>
> self.boot_opensbi()
>
>> + def test_riscv64_spike(self):
>> + """
>> + :avocado: tags=arch:riscv64
>> + :avocado: tags=machine:spike
>> + """
>
> self.boot_opensbi()
>
> [...]
>
>> + @skip("requires OpenSBI fix to work")
>> + def test_riscv32_spike(self):
>> + """
>> + :avocado: tags=arch:riscv32
>> + :avocado: tags=machine:spike
>> + """
>
> self.boot_opensbi()
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 02/10] hw/riscv/spike: use 'fdt' from MachineState
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 03/10] hw/riscv/sifive_u: " Daniel Henrique Barboza
` (7 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Philippe Mathieu-Daudé, Bin Meng
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/spike.c | 12 +++++-------
include/hw/riscv/spike.h | 2 --
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 1b747d8f7c..426c383cef 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -53,6 +53,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
bool is_32_bit, bool htif_custom_base)
{
void *fdt;
+ int fdt_size;
uint64_t addr, size;
unsigned long clint_addr;
int cpu, socket;
@@ -65,7 +66,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
"sifive,clint0", "riscv,clint0"
};
- fdt = s->fdt = create_device_tree(&s->fdt_size);
+ fdt = mc->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@@ -322,18 +323,15 @@ static void spike_board_init(MachineState *machine)
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
end);
}
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
- machine->ram_size, s->fdt);
-
- /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
- machine->fdt = s->fdt;
+ machine->ram_size, machine->fdt);
/* load the reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 73d69234de..d13a147942 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -37,8 +37,6 @@ struct SpikeState {
/*< public >*/
RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
- void *fdt;
- int fdt_size;
};
enum {
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 03/10] hw/riscv/sifive_u: use 'fdt' from MachineState
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 02/10] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 04/10] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
` (6 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Philippe Mathieu-Daudé, Bin Meng
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/sifive_u.c | 15 ++++++---------
include/hw/riscv/sifive_u.h | 3 ---
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a58ddb36ac..ddceb750ea 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
{
MachineState *ms = MACHINE(qdev_get_machine());
void *fdt;
- int cpu;
+ int cpu, fdt_size;
uint32_t *cells;
char *nodename;
uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
@@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
};
if (ms->dtb) {
- fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+ fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
if (!fdt) {
error_report("load_device_tree() failed");
exit(1);
}
goto update_bootargs;
} else {
- fdt = s->fdt = create_device_tree(&s->fdt_size);
+ fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
error_report("create_device_tree() failed");
exit(1);
@@ -612,9 +612,9 @@ static void sifive_u_machine_init(MachineState *machine)
hwaddr end = riscv_load_initrd(machine->initrd_filename,
machine->ram_size, kernel_entry,
&start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
"linux,initrd-start", start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
end);
}
} else {
@@ -627,14 +627,11 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
- machine->ram_size, s->fdt);
+ machine->ram_size, machine->fdt);
if (!riscv_is_32bit(&s->soc.u_cpus)) {
start_addr_hi32 = (uint64_t)start_addr >> 32;
}
- /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
- machine->fdt = s->fdt;
-
/* reset vector */
uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e680d61ece..4a8828a30e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -67,9 +67,6 @@ typedef struct SiFiveUState {
/*< public >*/
SiFiveUSoCState soc;
- void *fdt;
- int fdt_size;
-
bool start_in_flash;
uint32_t msel;
uint32_t serial;
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 04/10] hw/riscv/spike.c: load initrd right after riscv_load_kernel()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (2 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 03/10] hw/riscv/sifive_u: " Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 05/10] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
` (5 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Philippe Mathieu-Daudé, Bin Meng
This will make the code more in line with what the other boards are
doing. We'll also avoid an extra check to machine->kernel_filename since
we already checked that before executing riscv_load_kernel().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/spike.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 426c383cef..0d2feea930 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -297,6 +297,10 @@ static void spike_board_init(MachineState *machine)
g_free(firmware_name);
}
+ /* Create device tree */
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+ riscv_is_32bit(&s->soc[0]), htif_custom_base);
+
/* Load kernel */
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
@@ -305,6 +309,17 @@ static void spike_board_init(MachineState *machine)
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr,
htif_symbol_callback);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
@@ -313,22 +328,6 @@ static void spike_board_init(MachineState *machine)
kernel_entry = 0;
}
- /* Create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
- riscv_is_32bit(&s->soc[0]), htif_custom_base);
-
- /* Load initrd */
- if (machine->kernel_filename && machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
- end);
- }
-
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, machine->fdt);
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 05/10] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (3 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 04/10] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 06/10] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
` (4 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Bin Meng
riscv_load_initrd() returns the initrd end addr while also writing a
'start' var to mark the addr start. These informations are being used
just to write the initrd FDT node. Every existing caller of
riscv_load_initrd() is writing the FDT in the same manner.
We can simplify things by writing the FDT inside riscv_load_initrd(),
sparing callers from having to manage start/end addrs to write the FDT
themselves.
An 'if (fdt)' check is already inserted at the end of the function
because we'll end up using it later on with other boards that doesn´t
have a FDT.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/boot.c | 18 ++++++++++++------
hw/riscv/microchip_pfsoc.c | 10 ++--------
hw/riscv/sifive_u.c | 10 ++--------
hw/riscv/spike.c | 10 ++--------
hw/riscv/virt.c | 10 ++--------
include/hw/riscv/boot.h | 4 ++--
6 files changed, 22 insertions(+), 40 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 98b80af51b..d3c71b3f0b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -204,9 +204,10 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
exit(1);
}
-hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, hwaddr *start)
+void riscv_load_initrd(const char *filename, uint64_t mem_size,
+ uint64_t kernel_entry, void *fdt)
{
+ hwaddr start, end;
ssize_t size;
/*
@@ -220,18 +221,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
* halfway into RAM, and for boards with 256MB of RAM or more we put
* the initrd at 128MB.
*/
- *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+ start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
- size = load_ramdisk(filename, *start, mem_size - *start);
+ size = load_ramdisk(filename, start, mem_size - start);
if (size == -1) {
- size = load_image_targphys(filename, *start, mem_size - *start);
+ size = load_image_targphys(filename, start, mem_size - start);
if (size == -1) {
error_report("could not load ramdisk '%s'", filename);
exit(1);
}
}
- return *start + size;
+ /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+ if (fdt) {
+ end = start + size;
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+ }
}
uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index b10321b564..593a799549 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-end", end);
+ riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+ kernel_entry, machine->fdt);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ddceb750ea..37f5087172 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
- end);
+ riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+ kernel_entry, machine->fdt);
}
} else {
/*
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 0d2feea930..360bf83564 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -311,14 +311,8 @@ static void spike_board_init(MachineState *machine)
htif_symbol_callback);
if (machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
- end);
+ riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+ kernel_entry, machine->fdt);
}
} else {
/*
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 408f7a2256..5967b136b4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
- end);
+ riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+ kernel_entry, machine->fdt);
}
} else {
/*
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index b273ab22f7..e37e1d1238 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -46,8 +46,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
target_ulong riscv_load_kernel(const char *kernel_filename,
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
-hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, hwaddr *start);
+void riscv_load_initrd(const char *filename, uint64_t mem_size,
+ uint64_t kernel_entry, void *fdt);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 06/10] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (4 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 05/10] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 07/10] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
` (3 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Bin Meng
The sifive_u, spike and virt machines are writing the 'bootargs' FDT
node during their respective create_fdt().
Given that bootargs is written only when '-append' is used, and this
option is only allowed with the '-kernel' option, which in turn is
already being check before executing riscv_load_kernel(), write
'bootargs' in the same code path as riscv_load_kernel().
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/sifive_u.c | 11 +++++------
hw/riscv/spike.c | 9 +++++----
hw/riscv/virt.c | 11 +++++------
3 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 37f5087172..3e6df87b5b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
error_report("load_device_tree() failed");
exit(1);
}
- goto update_bootargs;
} else {
fdt = ms->fdt = create_device_tree(&fdt_size);
if (!fdt) {
@@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
g_free(nodename);
-
-update_bootargs:
- if (cmdline && *cmdline) {
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
}
static void sifive_u_machine_reset(void *opaque, int n, int level)
@@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *machine)
riscv_load_initrd(machine->initrd_filename, machine->ram_size,
kernel_entry, machine->fdt);
}
+
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+ qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
+ }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 360bf83564..775f910a50 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -179,10 +179,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-
- if (cmdline && *cmdline) {
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
}
static bool spike_test_elf_image(char *filename)
@@ -314,6 +310,11 @@ static void spike_board_init(MachineState *machine)
riscv_load_initrd(machine->initrd_filename, machine->ram_size,
kernel_entry, machine->fdt);
}
+
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+ qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
+ }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5967b136b4..6c946b6def 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
error_report("load_device_tree() failed");
exit(1);
}
- goto update_bootargs;
} else {
mc->fdt = create_device_tree(&s->fdt_size);
if (!mc->fdt) {
@@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
create_fdt_fw_cfg(s, memmap);
create_fdt_pmu(s);
-update_bootargs:
- if (cmdline && *cmdline) {
- qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
- }
-
/* Pass seed to RNG */
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
@@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, void *data)
riscv_load_initrd(machine->initrd_filename, machine->ram_size,
kernel_entry, machine->fdt);
}
+
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+ qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
+ }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 07/10] hw/riscv/boot.c: use MachineState in riscv_load_initrd()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (5 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 06/10] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
` (2 subsequent siblings)
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Philippe Mathieu-Daudé, Bin Meng
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/boot.c | 6 ++++--
hw/riscv/microchip_pfsoc.c | 3 +--
hw/riscv/sifive_u.c | 3 +--
hw/riscv/spike.c | 3 +--
hw/riscv/virt.c | 3 +--
include/hw/riscv/boot.h | 3 +--
6 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index d3c71b3f0b..f7e806143a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -204,9 +204,11 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
exit(1);
}
-void riscv_load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, void *fdt)
+void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
{
+ const char *filename = machine->initrd_filename;
+ uint64_t mem_size = machine->ram_size;
+ void *fdt = machine->fdt;
hwaddr start, end;
ssize_t size;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 593a799549..1e9b0a420e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- riscv_load_initrd(machine->initrd_filename, machine->ram_size,
- kernel_entry, machine->fdt);
+ riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3e6df87b5b..c40885ed5c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- riscv_load_initrd(machine->initrd_filename, machine->ram_size,
- kernel_entry, machine->fdt);
+ riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 775f910a50..0c22978b12 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -307,8 +307,7 @@ static void spike_board_init(MachineState *machine)
htif_symbol_callback);
if (machine->initrd_filename) {
- riscv_load_initrd(machine->initrd_filename, machine->ram_size,
- kernel_entry, machine->fdt);
+ riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6c946b6def..02f1369843 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr, NULL);
if (machine->initrd_filename) {
- riscv_load_initrd(machine->initrd_filename, machine->ram_size,
- kernel_entry, machine->fdt);
+ riscv_load_initrd(machine, kernel_entry);
}
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index e37e1d1238..cfd72ecabf 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -46,8 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
target_ulong riscv_load_kernel(const char *kernel_filename,
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
-void riscv_load_initrd(const char *filename, uint64_t mem_size,
- uint64_t kernel_entry, void *fdt);
+void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (6 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 07/10] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 10/10] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Philippe Mathieu-Daudé, Bin Meng
All callers are using kernel_filename as machine->kernel_filename.
This will also simplify the changes in riscv_load_kernel() that we're
going to do next.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/boot.c | 3 ++-
hw/riscv/microchip_pfsoc.c | 3 +--
hw/riscv/opentitan.c | 3 +--
hw/riscv/sifive_e.c | 3 +--
hw/riscv/sifive_u.c | 3 +--
hw/riscv/spike.c | 3 +--
hw/riscv/virt.c | 3 +--
include/hw/riscv/boot.h | 2 +-
8 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index f7e806143a..cd9c989edb 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -171,10 +171,11 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1);
}
-target_ulong riscv_load_kernel(const char *kernel_filename,
+target_ulong riscv_load_kernel(MachineState *machine,
target_ulong kernel_start_addr,
symbol_fn_t sym_cb)
{
+ const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry;
/*
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 1e9b0a420e..82ae5e7023 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine->kernel_filename,
- kernel_start_addr, NULL);
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 85ffdac5be..64d5d435b9 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine)
}
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename,
- memmap[IBEX_DEV_RAM].base, NULL);
+ riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
}
}
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index d65d2fd869..3e3f4b0088 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename,
- memmap[SIFIVE_E_DEV_DTIM].base, NULL);
+ riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
}
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c40885ed5c..bac394c959 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine->kernel_filename,
- kernel_start_addr, NULL);
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 0c22978b12..0bba5c1640 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -302,8 +302,7 @@ static void spike_board_init(MachineState *machine)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine->kernel_filename,
- kernel_start_addr,
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
htif_symbol_callback);
if (machine->initrd_filename) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 02f1369843..c8e35f861e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
- kernel_entry = riscv_load_kernel(machine->kernel_filename,
- kernel_start_addr, NULL);
+ kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
if (machine->initrd_filename) {
riscv_load_initrd(machine, kernel_entry);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index cfd72ecabf..f94653a09b 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename,
target_ulong riscv_load_firmware(const char *firmware_filename,
hwaddr firmware_load_addr,
symbol_fn_t sym_cb);
-target_ulong riscv_load_kernel(const char *kernel_filename,
+target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (7 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
2022-12-28 12:56 ` Philippe Mathieu-Daudé
2022-12-28 12:42 ` [PATCH v2 10/10] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
9 siblings, 1 reply; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Palmer Dabbelt, Bin Meng
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. Every other board that uses riscv_load_kernel() will have
this same behavior, including boards that doesn't have a valid FDT, so
we need to take care to not do FDT operations without checking it first.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/boot.c | 21 ++++++++++++++++++---
hw/riscv/microchip_pfsoc.c | 9 ---------
hw/riscv/sifive_u.c | 9 ---------
hw/riscv/spike.c | 9 ---------
hw/riscv/virt.c | 9 ---------
5 files changed, 18 insertions(+), 39 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index cd9c989edb..95f780a228 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -177,6 +177,7 @@ target_ulong riscv_load_kernel(MachineState *machine,
{
const char *kernel_filename = machine->kernel_filename;
uint64_t kernel_load_base, kernel_entry;
+ void *fdt = machine->fdt;
/*
* NB: Use low address not ELF entry point to ensure that the fw_dynamic
@@ -188,21 +189,35 @@ target_ulong riscv_load_kernel(MachineState *machine,
if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
NULL, &kernel_load_base, NULL, NULL, 0,
EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
- return kernel_load_base;
+ kernel_entry = kernel_load_base;
+ goto out;
}
if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
NULL, NULL, NULL) > 0) {
- return kernel_entry;
+ goto out;
}
if (load_image_targphys_as(kernel_filename, kernel_start_addr,
current_machine->ram_size, NULL) > 0) {
- return kernel_start_addr;
+ kernel_entry = kernel_start_addr;
+ goto out;
}
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
+
+out:
+ if (machine->initrd_filename) {
+ riscv_load_initrd(machine, kernel_entry);
+ }
+
+ if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
+ machine->kernel_cmdline);
+ }
+
+ return kernel_entry;
}
void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 82ae5e7023..57fd6739a5 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -631,15 +631,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen",
- "bootargs", machine->kernel_cmdline);
- }
-
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
machine->ram_size, machine->fdt);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index bac394c959..0c9bf7fe6a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -599,15 +599,6 @@ static void sifive_u_machine_init(MachineState *machine)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 0bba5c1640..48d004802b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -304,15 +304,6 @@ static void spike_board_init(MachineState *machine)
kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
htif_symbol_callback);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index c8e35f861e..11c903a212 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1282,15 +1282,6 @@ static void virt_machine_done(Notifier *notifier, void *data)
firmware_end_addr);
kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-
- if (machine->initrd_filename) {
- riscv_load_initrd(machine, kernel_entry);
- }
-
- if (machine->kernel_cmdline && *machine->kernel_cmdline) {
- qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
- machine->kernel_cmdline);
- }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
--
2.38.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
2022-12-28 12:42 ` [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
@ 2022-12-28 12:56 ` Philippe Mathieu-Daudé
2022-12-28 13:01 ` Daniel Henrique Barboza
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-12-28 12:56 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng, Palmer Dabbelt, Bin Meng
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
> the same steps when '-kernel' is used:
>
> - execute load_kernel()
> - load init_rd()
> - write kernel_cmdline
>
> Let's fold everything inside riscv_load_kernel() to avoid code
> repetition. Every other board that uses riscv_load_kernel() will have
> this same behavior, including boards that doesn't have a valid FDT, so
> we need to take care to not do FDT operations without checking it first.
>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Bin Meng <bmeng@tinylab.org>
> ---
> hw/riscv/boot.c | 21 ++++++++++++++++++---
> hw/riscv/microchip_pfsoc.c | 9 ---------
> hw/riscv/sifive_u.c | 9 ---------
> hw/riscv/spike.c | 9 ---------
> hw/riscv/virt.c | 9 ---------
> 5 files changed, 18 insertions(+), 39 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index cd9c989edb..95f780a228 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -177,6 +177,7 @@ target_ulong riscv_load_kernel(MachineState *machine,
> {
> const char *kernel_filename = machine->kernel_filename;
> uint64_t kernel_load_base, kernel_entry;
> + void *fdt = machine->fdt;
>
> /*
> * NB: Use low address not ELF entry point to ensure that the fw_dynamic
> @@ -188,21 +189,35 @@ target_ulong riscv_load_kernel(MachineState *machine,
> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
> NULL, &kernel_load_base, NULL, NULL, 0,
> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> - return kernel_load_base;
> + kernel_entry = kernel_load_base;
> + goto out;
> }
>
> if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
> NULL, NULL, NULL) > 0) {
> - return kernel_entry;
> + goto out;
> }
>
> if (load_image_targphys_as(kernel_filename, kernel_start_addr,
> current_machine->ram_size, NULL) > 0) {
> - return kernel_start_addr;
> + kernel_entry = kernel_start_addr;
> + goto out;
> }
>
> error_report("could not load kernel '%s'", kernel_filename);
> exit(1);
> +
> +out:
> + if (machine->initrd_filename) {
> + riscv_load_initrd(machine, kernel_entry);
> + }
> +
> + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
> + machine->kernel_cmdline);
> + }
> +
> + return kernel_entry;
> }
Worth renaming as riscv_load_kernel_and_initrd()?
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
2022-12-28 12:56 ` Philippe Mathieu-Daudé
@ 2022-12-28 13:01 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 13:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, alistair.francis, Bin Meng, Palmer Dabbelt, Bin Meng
On 12/28/22 09:56, Philippe Mathieu-Daudé wrote:
> On 28/12/22 13:42, Daniel Henrique Barboza wrote:
>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
>> the same steps when '-kernel' is used:
>>
>> - execute load_kernel()
>> - load init_rd()
>> - write kernel_cmdline
>>
>> Let's fold everything inside riscv_load_kernel() to avoid code
>> repetition. Every other board that uses riscv_load_kernel() will have
>> this same behavior, including boards that doesn't have a valid FDT, so
>> we need to take care to not do FDT operations without checking it first.
>>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> Reviewed-by: Bin Meng <bmeng@tinylab.org>
>> ---
>> hw/riscv/boot.c | 21 ++++++++++++++++++---
>> hw/riscv/microchip_pfsoc.c | 9 ---------
>> hw/riscv/sifive_u.c | 9 ---------
>> hw/riscv/spike.c | 9 ---------
>> hw/riscv/virt.c | 9 ---------
>> 5 files changed, 18 insertions(+), 39 deletions(-)
>>
>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
>> index cd9c989edb..95f780a228 100644
>> --- a/hw/riscv/boot.c
>> +++ b/hw/riscv/boot.c
>> @@ -177,6 +177,7 @@ target_ulong riscv_load_kernel(MachineState *machine,
>> {
>> const char *kernel_filename = machine->kernel_filename;
>> uint64_t kernel_load_base, kernel_entry;
>> + void *fdt = machine->fdt;
>> /*
>> * NB: Use low address not ELF entry point to ensure that the fw_dynamic
>> @@ -188,21 +189,35 @@ target_ulong riscv_load_kernel(MachineState *machine,
>> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
>> NULL, &kernel_load_base, NULL, NULL, 0,
>> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
>> - return kernel_load_base;
>> + kernel_entry = kernel_load_base;
>> + goto out;
>> }
>> if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
>> NULL, NULL, NULL) > 0) {
>> - return kernel_entry;
>> + goto out;
>> }
>> if (load_image_targphys_as(kernel_filename, kernel_start_addr,
>> current_machine->ram_size, NULL) > 0) {
>> - return kernel_start_addr;
>> + kernel_entry = kernel_start_addr;
>> + goto out;
>> }
>> error_report("could not load kernel '%s'", kernel_filename);
>> exit(1);
>> +
>> +out:
>> + if (machine->initrd_filename) {
>> + riscv_load_initrd(machine, kernel_entry);
>> + }
>> +
>> + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
>> + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
>> + machine->kernel_cmdline);
>> + }
>> +
>> + return kernel_entry;
>> }
>
> Worth renaming as riscv_load_kernel_and_initrd()?
Hmmm, not a bad idea. I'll re-send.
Daniel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 10/10] hw/riscv/boot.c: make riscv_load_initrd() static
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
` (8 preceding siblings ...)
2022-12-28 12:42 ` [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
@ 2022-12-28 12:42 ` Daniel Henrique Barboza
9 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2022-12-28 12:42 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, Daniel Henrique Barboza, Bin Meng,
Philippe Mathieu-Daudé, Bin Meng
The only remaining caller is riscv_load_kernel() which belongs to the
same file.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
---
hw/riscv/boot.c | 76 ++++++++++++++++++++---------------------
include/hw/riscv/boot.h | 1 -
2 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 95f780a228..87c4e5f3a2 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -171,6 +171,44 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
exit(1);
}
+static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+{
+ const char *filename = machine->initrd_filename;
+ uint64_t mem_size = machine->ram_size;
+ void *fdt = machine->fdt;
+ hwaddr start, end;
+ ssize_t size;
+
+ /*
+ * We want to put the initrd far enough into RAM that when the
+ * kernel is uncompressed it will not clobber the initrd. However
+ * on boards without much RAM we must ensure that we still leave
+ * enough room for a decent sized initrd, and on boards with large
+ * amounts of RAM we must avoid the initrd being so far up in RAM
+ * that it is outside lowmem and inaccessible to the kernel.
+ * So for boards with less than 256MB of RAM we put the initrd
+ * halfway into RAM, and for boards with 256MB of RAM or more we put
+ * the initrd at 128MB.
+ */
+ start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size == -1) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size == -1) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+ if (fdt) {
+ end = start + size;
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+ }
+}
+
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong kernel_start_addr,
symbol_fn_t sym_cb)
@@ -220,44 +258,6 @@ out:
return kernel_entry;
}
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-{
- const char *filename = machine->initrd_filename;
- uint64_t mem_size = machine->ram_size;
- void *fdt = machine->fdt;
- hwaddr start, end;
- ssize_t size;
-
- /*
- * We want to put the initrd far enough into RAM that when the
- * kernel is uncompressed it will not clobber the initrd. However
- * on boards without much RAM we must ensure that we still leave
- * enough room for a decent sized initrd, and on boards with large
- * amounts of RAM we must avoid the initrd being so far up in RAM
- * that it is outside lowmem and inaccessible to the kernel.
- * So for boards with less than 256MB of RAM we put the initrd
- * halfway into RAM, and for boards with 256MB of RAM or more we put
- * the initrd at 128MB.
- */
- start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
-
- size = load_ramdisk(filename, start, mem_size - start);
- if (size == -1) {
- size = load_image_targphys(filename, start, mem_size - start);
- if (size == -1) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
-
- /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
- if (fdt) {
- end = start + size;
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
- }
-}
-
uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
{
uint64_t temp, fdt_addr;
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f94653a09b..afebc50830 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -46,7 +46,6 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
target_ulong riscv_load_kernel(MachineState *machine,
target_ulong firmware_end_addr,
symbol_fn_t sym_cb);
-void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr saddr,
--
2.38.1
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