* [PATCH v2 1/2] target/arm: implement DBGCLAIM registers
2023-01-17 15:04 [PATCH v2 0/2] various aarch64 fixes for running Hyper-V on TCG Evgeny Iakovlev
@ 2023-01-17 15:04 ` Evgeny Iakovlev
2023-01-17 15:48 ` Richard Henderson
2023-01-17 15:04 ` [PATCH v2 2/2] target/arm: provide stubs for more external debug registers Evgeny Iakovlev
1 sibling, 1 reply; 5+ messages in thread
From: Evgeny Iakovlev @ 2023-01-17 15:04 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, peter.maydell
The architecture does not define any functionality for the CLAIM tag bits.
So we will just keep the raw bits, as per spec.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 1 +
target/arm/debug_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2b4bd20f9d..eddec155b0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -494,6 +494,7 @@ typedef struct CPUArchState {
uint64_t dbgbcr[16]; /* breakpoint control registers */
uint64_t dbgwvr[16]; /* watchpoint value registers */
uint64_t dbgwcr[16]; /* watchpoint control registers */
+ uint64_t dbgclaim; /* DBGCLAIM bits */
uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */
uint64_t osdlr_el1; /* OS DoubleLock status */
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index c21739242c..6c34c6e27d 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -629,6 +629,29 @@ static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
+static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ env->cp15.dbgclaim |= (value & 0xFF);
+}
+
+static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* CLAIM bits are RAO */
+ return 0xFF;
+}
+
+static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ env->cp15.dbgclaim &= ~(value & 0xFF);
+}
+
+static void dbgclaimclr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ env->cp15.dbgclaim = value;
+}
+
static const ARMCPRegInfo debug_cp_reginfo[] = {
/*
* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
@@ -712,6 +735,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
+ /*
+ * Dummy DBGCLAIM registers.
+ * "The architecture does not define any functionality for the CLAIM tag bits.",
+ * so we only keep the raw bits
+ */
+ { .name = "DBGCLAIMSET_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
+ .type = ARM_CP_ALIAS,
+ .access = PL1_RW, .accessfn = access_tda,
+ .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
+ { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
+ .access = PL1_RW, .accessfn = access_tda,
+ .writefn = dbgclaimclr_write, .raw_writefn = dbgclaimclr_raw_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/2] target/arm: provide stubs for more external debug registers
2023-01-17 15:04 [PATCH v2 0/2] various aarch64 fixes for running Hyper-V on TCG Evgeny Iakovlev
2023-01-17 15:04 ` [PATCH v2 1/2] target/arm: implement DBGCLAIM registers Evgeny Iakovlev
@ 2023-01-17 15:04 ` Evgeny Iakovlev
1 sibling, 0 replies; 5+ messages in thread
From: Evgeny Iakovlev @ 2023-01-17 15:04 UTC (permalink / raw)
To: qemu-arm; +Cc: qemu-devel, peter.maydell
Qemu doesn't implement Debug Communication Channel, as well as the rest
of external debug interface. However, Microsoft Hyper-V tries to access
some of these registers during an EL2 context switch.
Since there is no architectural way to not advertise support for external
debug, provide RAZ/WI stubs for OSDTRRX_EL1, OSDTRTX_EL1 and OSECCR_EL1
registers in the same way the rest of external debug is currently done.
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/debug_helper.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index 6c34c6e27d..bc213ac91e 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -684,6 +684,27 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL0_R, .accessfn = access_tda,
.type = ARM_CP_CONST, .resetvalue = 0 },
+ /*
+ * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
+ * It is a component of the Debug Communications Channel, which is not implemented.
+ */
+ { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
+ /*
+ * OSECCR_EL1 provides a mechanism for an operating system
+ * to access the contents of EDECCR. EDECCR is not implemented though,
+ * as is the rest of external device mechanism.
+ */
+ { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
/*
* DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as
* it is unlikely a guest will care.
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread