From: Shawn Guo <shawnguo@kernel.org>
To: Sean Anderson <sean.anderson@seco.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Camelia Alexandra Groza <camelia.groza@nxp.com>,
Madalin Bucur <madalin.bucur@nxp.com>,
Bagas Sanjaya <bagasdotme@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Yang <leoyang.li@nxp.com>
Subject: Re: [PATCH v9 07/10] arm64: dts: ls1046ardb: Add serdes bindings
Date: Fri, 27 Jan 2023 15:52:49 +0800 [thread overview]
Message-ID: <20230127075248.GL20713@T480> (raw)
In-Reply-To: <8074f0be-8a70-a937-49f2-123e0bfc6218@seco.com>
On Thu, Jan 26, 2023 at 11:48:53AM -0500, Sean Anderson wrote:
> On 1/25/23 18:43, Shawn Guo wrote:
> > On Thu, Dec 29, 2022 at 07:01:36PM -0500, Sean Anderson wrote:
> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> >> no driver for this device (and as far as I know all you can do with the
> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> fixed clock.
> >>
> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> SD1_TX3_P/N.
> >>
> >> Because this will break ethernet if the serdes is not enabled, enable
> >> the serdes driver by default on Layerscape.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> This depends on [1].
> >>
> >> [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/
> >>
> >> Changes in v9:
> >> - Fix name of phy mode node
> >> - phy-type -> fsl,phy
> >>
> >> Changes in v8:
> >> - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
> >> This should help remind readers that the numbering corresponds to the
> >> physical layout of the registers, and not the lane (pin) number.
> >>
> >> Changes in v6:
> >> - XGI.9 -> XFI.9
> >>
> >> Changes in v4:
> >> - Convert to new bindings
> >>
> >> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++
> >> drivers/phy/freescale/Kconfig | 1 +
> >
> > The phy driver Kconfig change shouldn't be part of this patch.
>
> I put it here for bisectability, since this is the point where we need
> to enable it. But I can do this in a separate patch if you want.
From DT ABI perspective, it's already broken anyway if you need to change
kernel and DT atomically.
Shawn
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Sean Anderson <sean.anderson@seco.com>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>,
devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Madalin Bucur <madalin.bucur@nxp.com>,
Li Yang <leoyang.li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Camelia Alexandra Groza <camelia.groza@nxp.com>,
Bagas Sanjaya <bagasdotme@gmail.com>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
linux-phy@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 07/10] arm64: dts: ls1046ardb: Add serdes bindings
Date: Fri, 27 Jan 2023 15:52:49 +0800 [thread overview]
Message-ID: <20230127075248.GL20713@T480> (raw)
In-Reply-To: <8074f0be-8a70-a937-49f2-123e0bfc6218@seco.com>
On Thu, Jan 26, 2023 at 11:48:53AM -0500, Sean Anderson wrote:
> On 1/25/23 18:43, Shawn Guo wrote:
> > On Thu, Dec 29, 2022 at 07:01:36PM -0500, Sean Anderson wrote:
> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> >> no driver for this device (and as far as I know all you can do with the
> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> fixed clock.
> >>
> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> SD1_TX3_P/N.
> >>
> >> Because this will break ethernet if the serdes is not enabled, enable
> >> the serdes driver by default on Layerscape.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> This depends on [1].
> >>
> >> [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/
> >>
> >> Changes in v9:
> >> - Fix name of phy mode node
> >> - phy-type -> fsl,phy
> >>
> >> Changes in v8:
> >> - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
> >> This should help remind readers that the numbering corresponds to the
> >> physical layout of the registers, and not the lane (pin) number.
> >>
> >> Changes in v6:
> >> - XGI.9 -> XFI.9
> >>
> >> Changes in v4:
> >> - Convert to new bindings
> >>
> >> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++
> >> drivers/phy/freescale/Kconfig | 1 +
> >
> > The phy driver Kconfig change shouldn't be part of this patch.
>
> I put it here for bisectability, since this is the point where we need
> to enable it. But I can do this in a separate patch if you want.
From DT ABI perspective, it's already broken anyway if you need to change
kernel and DT atomically.
Shawn
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Sean Anderson <sean.anderson@seco.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Camelia Alexandra Groza <camelia.groza@nxp.com>,
Madalin Bucur <madalin.bucur@nxp.com>,
Bagas Sanjaya <bagasdotme@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Yang <leoyang.li@nxp.com>
Subject: Re: [PATCH v9 07/10] arm64: dts: ls1046ardb: Add serdes bindings
Date: Fri, 27 Jan 2023 15:52:49 +0800 [thread overview]
Message-ID: <20230127075248.GL20713@T480> (raw)
In-Reply-To: <8074f0be-8a70-a937-49f2-123e0bfc6218@seco.com>
On Thu, Jan 26, 2023 at 11:48:53AM -0500, Sean Anderson wrote:
> On 1/25/23 18:43, Shawn Guo wrote:
> > On Thu, Dec 29, 2022 at 07:01:36PM -0500, Sean Anderson wrote:
> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> >> no driver for this device (and as far as I know all you can do with the
> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> fixed clock.
> >>
> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> SD1_TX3_P/N.
> >>
> >> Because this will break ethernet if the serdes is not enabled, enable
> >> the serdes driver by default on Layerscape.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> This depends on [1].
> >>
> >> [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/
> >>
> >> Changes in v9:
> >> - Fix name of phy mode node
> >> - phy-type -> fsl,phy
> >>
> >> Changes in v8:
> >> - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
> >> This should help remind readers that the numbering corresponds to the
> >> physical layout of the registers, and not the lane (pin) number.
> >>
> >> Changes in v6:
> >> - XGI.9 -> XFI.9
> >>
> >> Changes in v4:
> >> - Convert to new bindings
> >>
> >> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++
> >> drivers/phy/freescale/Kconfig | 1 +
> >
> > The phy driver Kconfig change shouldn't be part of this patch.
>
> I put it here for bisectability, since this is the point where we need
> to enable it. But I can do this in a separate patch if you want.
From DT ABI perspective, it's already broken anyway if you need to change
kernel and DT atomically.
Shawn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Sean Anderson <sean.anderson@seco.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Camelia Alexandra Groza <camelia.groza@nxp.com>,
Madalin Bucur <madalin.bucur@nxp.com>,
Bagas Sanjaya <bagasdotme@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Li Yang <leoyang.li@nxp.com>
Subject: Re: [PATCH v9 07/10] arm64: dts: ls1046ardb: Add serdes bindings
Date: Fri, 27 Jan 2023 15:52:49 +0800 [thread overview]
Message-ID: <20230127075248.GL20713@T480> (raw)
In-Reply-To: <8074f0be-8a70-a937-49f2-123e0bfc6218@seco.com>
On Thu, Jan 26, 2023 at 11:48:53AM -0500, Sean Anderson wrote:
> On 1/25/23 18:43, Shawn Guo wrote:
> > On Thu, Dec 29, 2022 at 07:01:36PM -0500, Sean Anderson wrote:
> >> This adds appropriate bindings for the macs which use the SerDes. The
> >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> >> no driver for this device (and as far as I know all you can do with the
> >> 100MHz clocks is gate them), so I have chosen to model it as a single
> >> fixed clock.
> >>
> >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> >> This means that Lane A (what the driver thinks is lane 0) uses pins
> >> SD1_TX3_P/N.
> >>
> >> Because this will break ethernet if the serdes is not enabled, enable
> >> the serdes driver by default on Layerscape.
> >>
> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> >> ---
> >> This depends on [1].
> >>
> >> [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@seco.com/
> >>
> >> Changes in v9:
> >> - Fix name of phy mode node
> >> - phy-type -> fsl,phy
> >>
> >> Changes in v8:
> >> - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
> >> This should help remind readers that the numbering corresponds to the
> >> physical layout of the registers, and not the lane (pin) number.
> >>
> >> Changes in v6:
> >> - XGI.9 -> XFI.9
> >>
> >> Changes in v4:
> >> - Convert to new bindings
> >>
> >> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++
> >> drivers/phy/freescale/Kconfig | 1 +
> >
> > The phy driver Kconfig change shouldn't be part of this patch.
>
> I put it here for bisectability, since this is the point where we need
> to enable it. But I can do this in a separate patch if you want.
From DT ABI perspective, it's already broken anyway if you need to change
kernel and DT atomically.
Shawn
next prev parent reply other threads:[~2023-01-27 7:53 UTC|newest]
Thread overview: 139+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-30 0:01 [PATCH v9 00/10] phy: Add support for Lynx 10G SerDes Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 01/10] dt-bindings: phy: Add 2500BASE-X and 10GBASE-R Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 02/10] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-12 20:37 ` Rob Herring
2023-01-12 20:37 ` Rob Herring
2023-01-12 20:37 ` Rob Herring
2023-01-12 20:37 ` Rob Herring
2022-12-30 0:01 ` [PATCH v9 03/10] dt-bindings: clock: Add ids for Lynx 10g PLLs Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 04/10] clk: Add Lynx 10G SerDes PLL driver Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-27 20:59 ` Stephen Boyd
2023-01-27 20:59 ` Stephen Boyd
2023-01-27 20:59 ` Stephen Boyd
2023-01-27 20:59 ` Stephen Boyd
2023-01-27 21:51 ` Sean Anderson
2023-01-27 21:51 ` Sean Anderson
2023-01-27 21:51 ` Sean Anderson
2023-01-27 21:51 ` Sean Anderson
2023-03-03 17:25 ` Sean Anderson
2023-03-03 17:25 ` Sean Anderson
2023-03-03 17:25 ` Sean Anderson
2023-03-03 17:25 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 05/10] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-03 18:30 ` kernel test robot
2023-01-03 18:30 ` kernel test robot
2023-01-03 18:30 ` kernel test robot
2022-12-30 0:01 ` [PATCH v9 06/10] arm64: dts: ls1046a: Add serdes bindings Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-25 23:46 ` Shawn Guo
2023-01-25 23:46 ` Shawn Guo
2023-01-25 23:46 ` Shawn Guo
2023-01-25 23:46 ` Shawn Guo
2023-01-26 16:43 ` Sean Anderson
2023-01-26 16:43 ` Sean Anderson
2023-01-26 16:43 ` Sean Anderson
2023-01-26 16:43 ` Sean Anderson
2023-01-27 7:53 ` Shawn Guo
2023-01-27 7:53 ` Shawn Guo
2023-01-27 7:53 ` Shawn Guo
2023-01-27 7:53 ` Shawn Guo
2022-12-30 0:01 ` [PATCH v9 07/10] arm64: dts: ls1046ardb: " Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-25 23:43 ` Shawn Guo
2023-01-25 23:43 ` Shawn Guo
2023-01-25 23:43 ` Shawn Guo
2023-01-25 23:43 ` Shawn Guo
2023-01-26 16:48 ` Sean Anderson
2023-01-26 16:48 ` Sean Anderson
2023-01-26 16:48 ` Sean Anderson
2023-01-26 16:48 ` Sean Anderson
2023-01-27 7:52 ` Shawn Guo [this message]
2023-01-27 7:52 ` Shawn Guo
2023-01-27 7:52 ` Shawn Guo
2023-01-27 7:52 ` Shawn Guo
2023-01-27 16:11 ` Sean Anderson
2023-01-27 16:11 ` Sean Anderson
2023-01-27 16:11 ` Sean Anderson
2023-01-27 16:11 ` Sean Anderson
2023-01-27 16:15 ` Krzysztof Kozlowski
2023-01-27 16:15 ` Krzysztof Kozlowski
2023-01-27 16:15 ` Krzysztof Kozlowski
2023-01-27 16:15 ` Krzysztof Kozlowski
2023-01-27 16:22 ` Sean Anderson
2023-01-27 16:22 ` Sean Anderson
2023-01-27 16:22 ` Sean Anderson
2023-01-27 16:22 ` Sean Anderson
2023-01-27 16:41 ` Krzysztof Kozlowski
2023-01-27 16:41 ` Krzysztof Kozlowski
2023-01-27 16:41 ` Krzysztof Kozlowski
2023-01-27 16:41 ` Krzysztof Kozlowski
2023-01-27 16:42 ` Sean Anderson
2023-01-27 16:42 ` Sean Anderson
2023-01-27 16:42 ` Sean Anderson
2023-01-27 16:42 ` Sean Anderson
2023-01-27 16:44 ` Krzysztof Kozlowski
2023-01-27 16:44 ` Krzysztof Kozlowski
2023-01-27 16:44 ` Krzysztof Kozlowski
2023-01-27 16:44 ` Krzysztof Kozlowski
2022-12-30 0:01 ` [PATCH v9 08/10] arm64: dts: ls1088a: " Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-25 23:48 ` Shawn Guo
2023-01-25 23:48 ` Shawn Guo
2023-01-25 23:48 ` Shawn Guo
2023-01-25 23:48 ` Shawn Guo
2023-01-26 17:54 ` Sean Anderson
2023-01-26 17:54 ` Sean Anderson
2023-01-26 17:54 ` Sean Anderson
2023-01-26 17:54 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 09/10] arm64: dts: ls1088a: Prevent PCSs from probing as phys Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` [PATCH v9 10/10] arm64: dts: ls1088ardb: Add serdes bindings Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2022-12-30 0:01 ` Sean Anderson
2023-01-17 16:46 ` [PATCH v9 00/10] phy: Add support for Lynx 10G SerDes Sean Anderson
2023-01-17 16:46 ` Sean Anderson
2023-01-17 16:46 ` Sean Anderson
2023-01-17 16:46 ` Sean Anderson
2023-01-18 16:54 ` Vinod Koul
2023-01-18 16:54 ` Vinod Koul
2023-01-18 16:54 ` Vinod Koul
2023-01-18 16:54 ` Vinod Koul
2023-01-19 16:22 ` Sean Anderson
2023-01-19 16:22 ` Sean Anderson
2023-01-19 16:22 ` Sean Anderson
2023-01-19 16:22 ` Sean Anderson
2023-01-20 8:06 ` Vinod Koul
2023-01-20 8:06 ` Vinod Koul
2023-01-20 8:06 ` Vinod Koul
2023-01-20 8:06 ` Vinod Koul
2023-01-20 16:43 ` Sean Anderson
2023-01-20 16:43 ` Sean Anderson
2023-01-20 16:43 ` Sean Anderson
2023-01-20 16:43 ` Sean Anderson
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