* [PATCH 0/2] Risc-V CPU state by hart ID
@ 2023-03-03 6:50 Mayuresh Chitale
2023-03-03 6:50 ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Mayuresh Chitale
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Mayuresh Chitale @ 2023-03-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis
Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
contiguous logical CPU ID to fetch per CPU state.
This patchset implements cpu_by_arch_id for Risc-V to get the CPU state
by hart ID which may be sparse instead of the contigous logical CPU id.
Mayuresh Chitale (2):
target/riscv: cpu: Implement get_arch_id callback
hw: intc: Use cpu_by_arch_id to fetch CPU state
hw/intc/riscv_aclint.c | 16 ++++++++--------
hw/intc/riscv_aplic.c | 4 ++--
hw/intc/riscv_imsic.c | 6 +++---
target/riscv/cpu.c | 8 ++++++++
4 files changed, 21 insertions(+), 13 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback
2023-03-03 6:50 [PATCH 0/2] Risc-V CPU state by hart ID Mayuresh Chitale
@ 2023-03-03 6:50 ` Mayuresh Chitale
2023-03-03 20:05 ` Daniel Henrique Barboza
2023-03-03 6:50 ` [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Mayuresh Chitale
2023-03-05 23:41 ` [PATCH 0/2] Risc-V CPU state by hart ID Palmer Dabbelt
2 siblings, 1 reply; 6+ messages in thread
From: Mayuresh Chitale @ 2023-03-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis, Anup Patel
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
target/riscv/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..467d8467a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1243,6 +1243,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
}
#ifndef CONFIG_USER_ONLY
+static int64_t riscv_get_arch_id(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ return cpu->env.mhartid;
+}
+
#include "hw/core/sysemu-cpu-ops.h"
static const struct SysemuCPUOps riscv_sysemu_ops = {
@@ -1297,6 +1304,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &riscv_sysemu_ops;
+ cc->get_arch_id = riscv_get_arch_id;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state
2023-03-03 6:50 [PATCH 0/2] Risc-V CPU state by hart ID Mayuresh Chitale
2023-03-03 6:50 ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Mayuresh Chitale
@ 2023-03-03 6:50 ` Mayuresh Chitale
2023-03-03 20:05 ` Daniel Henrique Barboza
2023-03-05 23:41 ` [PATCH 0/2] Risc-V CPU state by hart ID Palmer Dabbelt
2 siblings, 1 reply; 6+ messages in thread
From: Mayuresh Chitale @ 2023-03-03 6:50 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis, Anup Patel
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the
CPU state. However APLIC, IMSIC and ACLINT contain registers and states
which are specific to physical hart Ids. The hart Ids in any given system
might be sparse and hence calls to qemu_get_cpu need to be replaced by
cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
hw/intc/riscv_aclint.c | 16 ++++++++--------
hw/intc/riscv_aplic.c | 4 ++--
hw/intc/riscv_imsic.c | 6 +++---
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index eee04643cb..b466a6abaf 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
size_t hartid = mtimer->hartid_base +
((addr - mtimer->timecmp_base) >> 3);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -231,7 +231,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
/* Check if timer interrupt is triggered for each hart. */
for (i = 0; i < mtimer->num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
continue;
@@ -292,7 +292,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
s->timecmp = g_new0(uint64_t, s->num_harts);
/* Claim timer interrupt bits */
for (i = 0; i < s->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
error_report("MTIP already claimed");
exit(1);
@@ -372,7 +372,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
riscv_aclint_mtimer_callback *cb =
@@ -407,7 +407,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -430,7 +430,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
if (addr < (swi->num_harts << 2)) {
size_t hartid = swi->hartid_base + (addr >> 2);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -545,7 +545,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
RISCVCPU *rvcpu = RISCV_CPU(cpu);
qdev_connect_gpio_out(dev, i,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index cfd007e629..cd7efc4ad4 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -833,7 +833,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
/* Claim the CPU interrupt to be triggered by this APLIC */
for (i = 0; i < aplic->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
if (riscv_cpu_claim_interrupts(cpu,
(aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
error_report("%s already claimed",
@@ -966,7 +966,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
if (!msimode) {
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(hartid_base + i);
+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);
qdev_connect_gpio_out_named(dev, NULL, i,
qdev_get_gpio_in(DEVICE(cpu),
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index 4d4d5b50ca..fea3385b51 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -316,8 +316,8 @@ static const MemoryRegionOps riscv_imsic_ops = {
static void riscv_imsic_realize(DeviceState *dev, Error **errp)
{
RISCVIMSICState *imsic = RISCV_IMSIC(dev);
- RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
- CPUState *cpu = qemu_get_cpu(imsic->hartid);
+ RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));
+ CPUState *cpu = cpu_by_arch_id(imsic->hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
@@ -413,7 +413,7 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
uint32_t num_pages, uint32_t num_ids)
{
DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
- CPUState *cpu = qemu_get_cpu(hartid);
+ CPUState *cpu = cpu_by_arch_id(hartid);
uint32_t i;
assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback
2023-03-03 6:50 ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Mayuresh Chitale
@ 2023-03-03 20:05 ` Daniel Henrique Barboza
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-03 20:05 UTC (permalink / raw)
To: Mayuresh Chitale, qemu-devel, qemu-riscv; +Cc: alistair.francis, Anup Patel
On 3/3/23 03:50, Mayuresh Chitale wrote:
>
> Implement the callback for getting the architecture-dependent CPU ID ie
> mhartid.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dd2f0c753..467d8467a3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1243,6 +1243,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
> }
>
> #ifndef CONFIG_USER_ONLY
> +static int64_t riscv_get_arch_id(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + return cpu->env.mhartid;
> +}
> +
> #include "hw/core/sysemu-cpu-ops.h"
>
> static const struct SysemuCPUOps riscv_sysemu_ops = {
> @@ -1297,6 +1304,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> cc->disas_set_info = riscv_cpu_disas_set_info;
> #ifndef CONFIG_USER_ONLY
> cc->sysemu_ops = &riscv_sysemu_ops;
> + cc->get_arch_id = riscv_get_arch_id;
> #endif
> cc->gdb_arch_name = riscv_gdb_arch_name;
> cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state
2023-03-03 6:50 ` [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Mayuresh Chitale
@ 2023-03-03 20:05 ` Daniel Henrique Barboza
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-03 20:05 UTC (permalink / raw)
To: Mayuresh Chitale, qemu-devel, qemu-riscv; +Cc: alistair.francis, Anup Patel
On 3/3/23 03:50, Mayuresh Chitale wrote:
>
> Qemu_get_cpu uses the logical CPU id assigned during init to fetch the
> CPU state. However APLIC, IMSIC and ACLINT contain registers and states
> which are specific to physical hart Ids. The hart Ids in any given system
> might be sparse and hence calls to qemu_get_cpu need to be replaced by
> cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/intc/riscv_aclint.c | 16 ++++++++--------
> hw/intc/riscv_aplic.c | 4 ++--
> hw/intc/riscv_imsic.c | 6 +++---
> 3 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index eee04643cb..b466a6abaf 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -130,7 +130,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
> addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
> size_t hartid = mtimer->hartid_base +
> ((addr - mtimer->timecmp_base) >> 3);
> - CPUState *cpu = qemu_get_cpu(hartid);
> + CPUState *cpu = cpu_by_arch_id(hartid);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> if (!env) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -173,7 +173,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
> addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
> size_t hartid = mtimer->hartid_base +
> ((addr - mtimer->timecmp_base) >> 3);
> - CPUState *cpu = qemu_get_cpu(hartid);
> + CPUState *cpu = cpu_by_arch_id(hartid);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> if (!env) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -231,7 +231,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
>
> /* Check if timer interrupt is triggered for each hart. */
> for (i = 0; i < mtimer->num_harts; i++) {
> - CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
> + CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> if (!env) {
> continue;
> @@ -292,7 +292,7 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
> s->timecmp = g_new0(uint64_t, s->num_harts);
> /* Claim timer interrupt bits */
> for (i = 0; i < s->num_harts; i++) {
> - RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
> + RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));
> if (riscv_cpu_claim_interrupts(cpu, MIP_MTIP) < 0) {
> error_report("MTIP already claimed");
> exit(1);
> @@ -372,7 +372,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
>
> for (i = 0; i < num_harts; i++) {
> - CPUState *cpu = qemu_get_cpu(hartid_base + i);
> + CPUState *cpu = cpu_by_arch_id(hartid_base + i);
> RISCVCPU *rvcpu = RISCV_CPU(cpu);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> riscv_aclint_mtimer_callback *cb =
> @@ -407,7 +407,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwaddr addr,
>
> if (addr < (swi->num_harts << 2)) {
> size_t hartid = swi->hartid_base + (addr >> 2);
> - CPUState *cpu = qemu_get_cpu(hartid);
> + CPUState *cpu = cpu_by_arch_id(hartid);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> if (!env) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -430,7 +430,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr addr, uint64_t value,
>
> if (addr < (swi->num_harts << 2)) {
> size_t hartid = swi->hartid_base + (addr >> 2);
> - CPUState *cpu = qemu_get_cpu(hartid);
> + CPUState *cpu = cpu_by_arch_id(hartid);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
> if (!env) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -545,7 +545,7 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
> sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
>
> for (i = 0; i < num_harts; i++) {
> - CPUState *cpu = qemu_get_cpu(hartid_base + i);
> + CPUState *cpu = cpu_by_arch_id(hartid_base + i);
> RISCVCPU *rvcpu = RISCV_CPU(cpu);
>
> qdev_connect_gpio_out(dev, i,
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index cfd007e629..cd7efc4ad4 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -833,7 +833,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
>
> /* Claim the CPU interrupt to be triggered by this APLIC */
> for (i = 0; i < aplic->num_harts; i++) {
> - RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(aplic->hartid_base + i));
> + RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));
> if (riscv_cpu_claim_interrupts(cpu,
> (aplic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
> error_report("%s already claimed",
> @@ -966,7 +966,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
>
> if (!msimode) {
> for (i = 0; i < num_harts; i++) {
> - CPUState *cpu = qemu_get_cpu(hartid_base + i);
> + CPUState *cpu = cpu_by_arch_id(hartid_base + i);
>
> qdev_connect_gpio_out_named(dev, NULL, i,
> qdev_get_gpio_in(DEVICE(cpu),
> diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
> index 4d4d5b50ca..fea3385b51 100644
> --- a/hw/intc/riscv_imsic.c
> +++ b/hw/intc/riscv_imsic.c
> @@ -316,8 +316,8 @@ static const MemoryRegionOps riscv_imsic_ops = {
> static void riscv_imsic_realize(DeviceState *dev, Error **errp)
> {
> RISCVIMSICState *imsic = RISCV_IMSIC(dev);
> - RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
> - CPUState *cpu = qemu_get_cpu(imsic->hartid);
> + RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));
> + CPUState *cpu = cpu_by_arch_id(imsic->hartid);
> CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
>
> imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
> @@ -413,7 +413,7 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
> uint32_t num_pages, uint32_t num_ids)
> {
> DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
> - CPUState *cpu = qemu_get_cpu(hartid);
> + CPUState *cpu = cpu_by_arch_id(hartid);
> uint32_t i;
>
> assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Risc-V CPU state by hart ID
2023-03-03 6:50 [PATCH 0/2] Risc-V CPU state by hart ID Mayuresh Chitale
2023-03-03 6:50 ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Mayuresh Chitale
2023-03-03 6:50 ` [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Mayuresh Chitale
@ 2023-03-05 23:41 ` Palmer Dabbelt
2 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-03-05 23:41 UTC (permalink / raw)
To: mchitale; +Cc: qemu-devel, qemu-riscv, mchitale, Alistair Francis
On Thu, 02 Mar 2023 22:50:53 PST (-0800), mchitale@ventanamicro.com wrote:
> Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
> hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
> contiguous logical CPU ID to fetch per CPU state.
>
> This patchset implements cpu_by_arch_id for Risc-V to get the CPU state
> by hart ID which may be sparse instead of the contigous logical CPU id.
>
> Mayuresh Chitale (2):
> target/riscv: cpu: Implement get_arch_id callback
> hw: intc: Use cpu_by_arch_id to fetch CPU state
>
> hw/intc/riscv_aclint.c | 16 ++++++++--------
> hw/intc/riscv_aplic.c | 4 ++--
> hw/intc/riscv_imsic.c | 6 +++---
> target/riscv/cpu.c | 8 ++++++++
> 4 files changed, 21 insertions(+), 13 deletions(-)
Thanks, these are queue up on riscv-to-apply.next.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-03-05 23:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2023-03-03 6:50 [PATCH 0/2] Risc-V CPU state by hart ID Mayuresh Chitale
2023-03-03 6:50 ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Mayuresh Chitale
2023-03-03 20:05 ` Daniel Henrique Barboza
2023-03-03 6:50 ` [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Mayuresh Chitale
2023-03-03 20:05 ` Daniel Henrique Barboza
2023-03-05 23:41 ` [PATCH 0/2] Risc-V CPU state by hart ID Palmer Dabbelt
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