* [PATCH for-8.0] docs/cxl: Fix sentence
@ 2023-04-09 20:18 ` Stefan Weil via
0 siblings, 0 replies; 6+ messages in thread
From: Stefan Weil via @ 2023-04-09 20:18 UTC (permalink / raw)
To: Jonathan Cameron
Cc: qemu-devel, qemu-trivial, Michael S . Tsirkin, Peter Maydell,
Stefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de>
---
If my change is okay I suggest to apply the patch for 8.0
because it fixes documentation.
Regards,
Stefan W.
docs/system/devices/cxl.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f25783a4ec..4c38223069 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -111,7 +111,7 @@ Interfaces provided include:
CXL Root Ports (CXL RP)
~~~~~~~~~~~~~~~~~~~~~~~
-A CXL Root Port servers te same purpose as a PCIe Root Port.
+A CXL Root Port serves the same purpose as a PCIe Root Port.
There are a number of CXL specific Designated Vendor Specific
Extended Capabilities (DVSEC) in PCIe Configuration Space
and associated component register access via PCI bars.
--
2.39.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH for-8.0] docs/cxl: Fix sentence
2023-04-09 20:18 ` Stefan Weil via
(?)
@ 2023-04-11 1:10 ` Richard Henderson
-1 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2023-04-11 1:10 UTC (permalink / raw)
To: Stefan Weil, Jonathan Cameron
Cc: qemu-devel, qemu-trivial, Michael S . Tsirkin, Peter Maydell
On 4/9/23 13:18, Stefan Weil via wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-8.0] docs/cxl: Fix sentence
2023-04-09 20:18 ` Stefan Weil via
(?)
(?)
@ 2023-04-11 7:08 ` Michael S. Tsirkin
-1 siblings, 0 replies; 6+ messages in thread
From: Michael S. Tsirkin @ 2023-04-11 7:08 UTC (permalink / raw)
To: Stefan Weil; +Cc: Jonathan Cameron, qemu-devel, qemu-trivial, Peter Maydell
On Sun, Apr 09, 2023 at 10:18:28PM +0200, Stefan Weil wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
It does but I don't think we should bother for 8.0. Nothing
bad will happen if we defer this, we need to focus on
kicking the release out of the door.
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
> --
> 2.39.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-8.0] docs/cxl: Fix sentence
2023-04-09 20:18 ` Stefan Weil via
@ 2023-04-11 11:43 ` Jonathan Cameron via
-1 siblings, 0 replies; 6+ messages in thread
From: Jonathan Cameron @ 2023-04-11 11:43 UTC (permalink / raw)
To: Stefan Weil; +Cc: qemu-devel, qemu-trivial, Michael S . Tsirkin, Peter Maydell
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil <sw@weilnetz.de> wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH for-8.0] docs/cxl: Fix sentence
@ 2023-04-11 11:43 ` Jonathan Cameron via
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Cameron via @ 2023-04-11 11:43 UTC (permalink / raw)
To: Stefan Weil; +Cc: qemu-devel, qemu-trivial, Michael S . Tsirkin, Peter Maydell
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil <sw@weilnetz.de> wrote:
> Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f25783a4ec..4c38223069 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -111,7 +111,7 @@ Interfaces provided include:
>
> CXL Root Ports (CXL RP)
> ~~~~~~~~~~~~~~~~~~~~~~~
> -A CXL Root Port servers te same purpose as a PCIe Root Port.
> +A CXL Root Port serves the same purpose as a PCIe Root Port.
> There are a number of CXL specific Designated Vendor Specific
> Extended Capabilities (DVSEC) in PCIe Configuration Space
> and associated component register access via PCI bars.
^ permalink raw reply [flat|nested] 6+ messages in thread