From: "Michael S. Tsirkin" <mst@redhat.com>
To: Parav Pandit <parav@nvidia.com>
Cc: virtio-dev@lists.oasis-open.org, cohuck@redhat.com,
david.edmondson@oracle.com, sburla@marvell.com,
jasowang@redhat.com, virtio-comment@lists.oasis-open.org,
shahafs@nvidia.com
Subject: [virtio-comment] Re: [PATCH v1 1/2] transport-pci: Introduce legacy registers access commands
Date: Wed, 3 May 2023 12:49:02 -0400 [thread overview]
Message-ID: <20230503124848-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <36e8746e-9edd-7998-3381-9cee2457f3df@nvidia.com>
On Wed, May 03, 2023 at 10:49:14AM -0400, Parav Pandit wrote:
>
>
> On 5/3/2023 1:50 AM, Michael S. Tsirkin wrote:
> > On Wed, May 03, 2023 at 06:26:58AM +0300, Parav Pandit wrote:
>
> > > +Legacy registers write admin command follows \field{struct virtio_admin_cmd}.
> > > +This command writes legacy registers of a member VF device. Driver should write
> > > +appropriate register \field{size} depending on the width of the legacy
> > > +common registers or device specific registers.
> > > +Driver sets command \field{opcode} to VIRTIO_ADMIN_CMD_LREG_WRITE.
> > > +Driver sets \field{group_type} to 1 for VFs.
> > > +Driver sets \field{group_member_id} to a valid VF number.
> > > +
> > > +The \field{command_specific_data} has following listed structure format:
> > > +
> > > +\begin{lstlisting}
> > > +struct virtio_admin_cmd_lreg_wr_data {
> > > + u8 offset; /* Starting byte offset of the register(s) to write */
> > > + u8 size; /* Number of bytes to write into the register. */
> > > + u8 register[];
> >
> > And maybe add
> > u8 reserved[]; /* structure padding to multiple of 8 bytes */
> >
> > > +};
> Thinking, what do we miss without the padding here?
it's not 100% clear where the padding is.
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WARNING: multiple messages have this Message-ID (diff)
From: "Michael S. Tsirkin" <mst@redhat.com>
To: Parav Pandit <parav@nvidia.com>
Cc: virtio-dev@lists.oasis-open.org, cohuck@redhat.com,
david.edmondson@oracle.com, sburla@marvell.com,
jasowang@redhat.com, virtio-comment@lists.oasis-open.org,
shahafs@nvidia.com
Subject: [virtio-dev] Re: [PATCH v1 1/2] transport-pci: Introduce legacy registers access commands
Date: Wed, 3 May 2023 12:49:02 -0400 [thread overview]
Message-ID: <20230503124848-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <36e8746e-9edd-7998-3381-9cee2457f3df@nvidia.com>
On Wed, May 03, 2023 at 10:49:14AM -0400, Parav Pandit wrote:
>
>
> On 5/3/2023 1:50 AM, Michael S. Tsirkin wrote:
> > On Wed, May 03, 2023 at 06:26:58AM +0300, Parav Pandit wrote:
>
> > > +Legacy registers write admin command follows \field{struct virtio_admin_cmd}.
> > > +This command writes legacy registers of a member VF device. Driver should write
> > > +appropriate register \field{size} depending on the width of the legacy
> > > +common registers or device specific registers.
> > > +Driver sets command \field{opcode} to VIRTIO_ADMIN_CMD_LREG_WRITE.
> > > +Driver sets \field{group_type} to 1 for VFs.
> > > +Driver sets \field{group_member_id} to a valid VF number.
> > > +
> > > +The \field{command_specific_data} has following listed structure format:
> > > +
> > > +\begin{lstlisting}
> > > +struct virtio_admin_cmd_lreg_wr_data {
> > > + u8 offset; /* Starting byte offset of the register(s) to write */
> > > + u8 size; /* Number of bytes to write into the register. */
> > > + u8 register[];
> >
> > And maybe add
> > u8 reserved[]; /* structure padding to multiple of 8 bytes */
> >
> > > +};
> Thinking, what do we miss without the padding here?
it's not 100% clear where the padding is.
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next prev parent reply other threads:[~2023-05-03 16:50 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-03 3:26 [virtio-comment] [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Parav Pandit
2023-05-03 3:26 ` [virtio-dev] " Parav Pandit
2023-05-03 3:26 ` [virtio-comment] [PATCH v1 1/2] transport-pci: Introduce legacy registers access commands Parav Pandit
2023-05-03 3:26 ` [virtio-dev] " Parav Pandit
2023-05-03 5:42 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 5:42 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:47 ` [virtio-comment] " Parav Pandit
2023-05-03 14:47 ` [virtio-dev] " Parav Pandit
2023-05-03 16:48 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 16:48 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 17:21 ` [virtio-comment] " Parav Pandit
2023-05-03 17:21 ` [virtio-dev] " Parav Pandit
2023-05-04 6:30 ` [virtio-comment] " Michael S. Tsirkin
2023-05-04 6:30 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 5:50 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 5:50 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:49 ` [virtio-comment] " Parav Pandit
2023-05-03 14:49 ` [virtio-dev] " Parav Pandit
2023-05-03 16:49 ` Michael S. Tsirkin [this message]
2023-05-03 16:49 ` Michael S. Tsirkin
2023-05-03 17:23 ` [virtio-comment] " Parav Pandit
2023-05-03 17:23 ` [virtio-dev] " Parav Pandit
2023-05-04 6:30 ` [virtio-comment] " Michael S. Tsirkin
2023-05-04 6:30 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 19:21 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 19:21 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 19:38 ` [virtio-comment] " Parav Pandit
2023-05-03 19:38 ` Parav Pandit
2023-05-03 20:08 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 20:08 ` Michael S. Tsirkin
2023-05-03 20:13 ` [virtio-comment] " Parav Pandit
2023-05-03 20:13 ` Parav Pandit
2023-05-05 3:26 ` [virtio-comment] " Jason Wang
2023-05-05 3:26 ` [virtio-dev] " Jason Wang
2023-05-05 12:48 ` [virtio-comment] " Parav Pandit
2023-05-05 12:48 ` [virtio-dev] " Parav Pandit
2023-05-06 2:24 ` [virtio-comment] " Jason Wang
2023-05-06 2:24 ` [virtio-dev] " Jason Wang
2023-05-06 2:25 ` [virtio-comment] " Jason Wang
2023-05-06 2:25 ` [virtio-dev] " Jason Wang
2023-05-03 3:26 ` [virtio-comment] [PATCH v1 2/2] transport-pci: Add legacy register access conformance section Parav Pandit
2023-05-03 3:26 ` [virtio-dev] " Parav Pandit
2023-05-03 5:48 ` [virtio-comment] " Michael S. Tsirkin
2023-05-03 5:48 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:53 ` [virtio-comment] " Parav Pandit
2023-05-03 14:53 ` [virtio-dev] " Parav Pandit
2023-05-03 19:18 ` Michael S. Tsirkin
2023-05-03 19:18 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 19:56 ` Parav Pandit
2023-05-03 19:56 ` [virtio-dev] " Parav Pandit
2023-05-03 10:16 ` [virtio-comment] Re: [PATCH v1 0/2] transport-pci: Introduce legacy registers access using AQ Michael S. Tsirkin
2023-05-03 10:16 ` [virtio-dev] " Michael S. Tsirkin
2023-05-03 14:57 ` [virtio-comment] " Parav Pandit
2023-05-03 14:57 ` [virtio-dev] " Parav Pandit
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