From: Fabio Estevam <festevam@gmail.com>
To: shawnguo@kernel.org
Cc: marex@denx.de, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, conor+dt@kernel.org,
bhelgaas@google.com, Fabio Estevam <festevam@denx.de>
Subject: [PATCH v6 3/5] dt-bindings: soc: Add i.MX6SX General Purpose Register
Date: Mon, 22 May 2023 17:14:02 -0300 [thread overview]
Message-ID: <20230522201404.660242-3-festevam@gmail.com> (raw)
In-Reply-To: <20230522201404.660242-1-festevam@gmail.com>
From: Fabio Estevam <festevam@denx.de>
The i.MX6SX General Purpose Registers is a set of register that serves
various different purposes and in particular, IOMUXC_GPR_GPR6, at
offset 0x18, can be used to configure the LDB block.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v5:
- Dropped "fsl,imx6q-iomuxc-gpr" and "reg-names" (Marek).
.../bindings/soc/imx/fsl,imx6sx-gpr.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
new file mode 100644
index 000000000000..b9752b4c45ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx6sx-gpr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX6SX General Purpose Register
+
+maintainers:
+ - Fabio Estevam <festevam@denx.de>
+
+description:
+ The i.MX6SX General Purpose Registers is a set of register that serves
+ for various purposes and in particular, IOMUXC_GPR_GPR6, at offset 0x18,
+ can be used to configure the LDB block.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx6sx-iomuxc-gpr
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ bridge@18:
+ type: object
+ $ref: /schemas/display/bridge/fsl,ldb.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+
+ syscon@20e4000 {
+ compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bridge@18 {
+ compatible = "fsl,imx6sx-ldb";
+ reg = <0x18 0x4>;
+ clocks = <&clks IMX6SX_CLK_LDB_DI0>;
+ clock-names = "ldb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ldb_from_lcdif1: endpoint {
+ remote-endpoint = <&lcdif1_to_ldb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ldb_lvds_ch0: endpoint {
+ };
+ };
+ };
+ };
+ };
+...
--
2.34.1
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WARNING: multiple messages have this Message-ID (diff)
From: Fabio Estevam <festevam@gmail.com>
To: shawnguo@kernel.org
Cc: marex@denx.de, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, conor+dt@kernel.org,
bhelgaas@google.com, Fabio Estevam <festevam@denx.de>
Subject: [PATCH v6 3/5] dt-bindings: soc: Add i.MX6SX General Purpose Register
Date: Mon, 22 May 2023 17:14:02 -0300 [thread overview]
Message-ID: <20230522201404.660242-3-festevam@gmail.com> (raw)
In-Reply-To: <20230522201404.660242-1-festevam@gmail.com>
From: Fabio Estevam <festevam@denx.de>
The i.MX6SX General Purpose Registers is a set of register that serves
various different purposes and in particular, IOMUXC_GPR_GPR6, at
offset 0x18, can be used to configure the LDB block.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v5:
- Dropped "fsl,imx6q-iomuxc-gpr" and "reg-names" (Marek).
.../bindings/soc/imx/fsl,imx6sx-gpr.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
new file mode 100644
index 000000000000..b9752b4c45ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx6sx-gpr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX6SX General Purpose Register
+
+maintainers:
+ - Fabio Estevam <festevam@denx.de>
+
+description:
+ The i.MX6SX General Purpose Registers is a set of register that serves
+ for various purposes and in particular, IOMUXC_GPR_GPR6, at offset 0x18,
+ can be used to configure the LDB block.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx6sx-iomuxc-gpr
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ bridge@18:
+ type: object
+ $ref: /schemas/display/bridge/fsl,ldb.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+
+ syscon@20e4000 {
+ compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bridge@18 {
+ compatible = "fsl,imx6sx-ldb";
+ reg = <0x18 0x4>;
+ clocks = <&clks IMX6SX_CLK_LDB_DI0>;
+ clock-names = "ldb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ldb_from_lcdif1: endpoint {
+ remote-endpoint = <&lcdif1_to_ldb>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ldb_lvds_ch0: endpoint {
+ };
+ };
+ };
+ };
+ };
+...
--
2.34.1
next prev parent reply other threads:[~2023-05-22 20:15 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-22 20:14 [PATCH v6 1/5] PCI: imx6: Use a more specific i.MX6SX GPR compatible Fabio Estevam
2023-05-22 20:14 ` Fabio Estevam
2023-05-22 20:14 ` [PATCH v6 2/5] dt-bindings: display: bridge: ldb: Adjust imx6sx entries Fabio Estevam
2023-05-22 20:14 ` Fabio Estevam
2023-05-22 22:06 ` Conor Dooley
2023-05-22 22:06 ` Conor Dooley
2023-05-23 2:27 ` Marek Vasut
2023-05-23 2:27 ` Marek Vasut
2023-05-22 20:14 ` Fabio Estevam [this message]
2023-05-22 20:14 ` [PATCH v6 3/5] dt-bindings: soc: Add i.MX6SX General Purpose Register Fabio Estevam
2023-05-22 21:32 ` Rob Herring
2023-05-22 21:32 ` Rob Herring
2023-05-22 21:53 ` Fabio Estevam
2023-05-22 21:53 ` Fabio Estevam
2023-06-07 20:31 ` Rob Herring
2023-06-07 20:31 ` Rob Herring
2023-06-07 21:07 ` Fabio Estevam
2023-06-07 21:07 ` Fabio Estevam
2023-05-22 22:10 ` Conor Dooley
2023-05-22 22:10 ` Conor Dooley
2023-05-23 2:28 ` Marek Vasut
2023-05-23 2:28 ` Marek Vasut
2023-05-22 20:14 ` [PATCH v6 4/5] ARM: dts: imx6sx: Add LDB support Fabio Estevam
2023-05-22 20:14 ` Fabio Estevam
2023-05-23 2:29 ` Marek Vasut
2023-05-23 2:29 ` Marek Vasut
2023-05-23 11:34 ` Fabio Estevam
2023-05-23 11:34 ` Fabio Estevam
2023-05-23 12:56 ` Marek Vasut
2023-05-23 12:56 ` Marek Vasut
2023-05-22 20:14 ` [PATCH v6 5/5] soc: imx: imx6sx-gpr: Introduce a GPR driver Fabio Estevam
2023-05-22 20:14 ` Fabio Estevam
2023-05-23 2:30 ` Marek Vasut
2023-05-23 2:30 ` Marek Vasut
2023-05-23 11:44 ` Fabio Estevam
2023-05-23 11:44 ` Fabio Estevam
2023-05-23 12:57 ` Marek Vasut
2023-05-23 12:57 ` Marek Vasut
2023-05-23 21:13 ` Fabio Estevam
2023-05-23 21:13 ` Fabio Estevam
2023-05-23 23:30 ` Marek Vasut
2023-05-23 23:30 ` Marek Vasut
2023-05-23 23:41 ` Fabio Estevam
2023-05-23 23:41 ` Fabio Estevam
2023-05-23 2:27 ` [PATCH v6 1/5] PCI: imx6: Use a more specific i.MX6SX GPR compatible Marek Vasut
2023-05-23 2:27 ` Marek Vasut
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