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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot
Date: Sat, 27 May 2023 00:59:53 +0800	[thread overview]
Message-ID: <20230526165958.908-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230526165958.908-1-jszhang@kernel.org>

The CBOM size and whether the HW is noncoherent is known and
determined during booting and won't change after that.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/errata/thead/errata.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index c259dc925ec1..be84b14f0118 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
 	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 		return false;
 
-	riscv_cbom_block_size = L1_CACHE_BYTES;
-	riscv_noncoherent_supported();
+	if (stage == RISCV_ALTERNATIVES_BOOT) {
+		riscv_cbom_block_size = L1_CACHE_BYTES;
+		riscv_noncoherent_supported();
+	}
+
 	return true;
 }
 
-- 
2.40.1


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http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot
Date: Sat, 27 May 2023 00:59:53 +0800	[thread overview]
Message-ID: <20230526165958.908-2-jszhang@kernel.org> (raw)
In-Reply-To: <20230526165958.908-1-jszhang@kernel.org>

The CBOM size and whether the HW is noncoherent is known and
determined during booting and won't change after that.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/errata/thead/errata.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index c259dc925ec1..be84b14f0118 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage,
 	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 		return false;
 
-	riscv_cbom_block_size = L1_CACHE_BYTES;
-	riscv_noncoherent_supported();
+	if (stage == RISCV_ALTERNATIVES_BOOT) {
+		riscv_cbom_block_size = L1_CACHE_BYTES;
+		riscv_noncoherent_supported();
+	}
+
 	return true;
 }
 
-- 
2.40.1


  reply	other threads:[~2023-05-26 17:11 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
2023-05-26 16:59 ` Jisheng Zhang
2023-05-26 16:59 ` Jisheng Zhang [this message]
2023-05-26 16:59   ` [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
2023-05-29 10:42   ` Conor Dooley
2023-05-29 10:42     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 10:44   ` Conor Dooley
2023-05-29 10:44     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 10:53   ` Conor Dooley
2023-05-29 10:53     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 11:13   ` Conor Dooley
2023-05-29 11:13     ` Conor Dooley
2023-05-31 15:24     ` Jisheng Zhang
2023-05-31 15:24       ` Jisheng Zhang
2023-05-31 15:28       ` Jisheng Zhang
2023-05-31 15:28         ` Jisheng Zhang
2023-05-31 16:28         ` Conor Dooley
2023-05-31 16:28           ` Conor Dooley
2023-06-01  3:40           ` Jisheng Zhang
2023-06-01  3:40             ` Jisheng Zhang
2023-05-26 16:59 ` [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 11:17   ` Conor Dooley
2023-05-29 11:17     ` Conor Dooley
2023-05-30  9:59     ` Catalin Marinas
2023-05-30  9:59       ` Catalin Marinas
2023-05-30 10:34       ` Conor Dooley
2023-05-30 10:34         ` Conor Dooley
2023-05-30 13:08         ` Catalin Marinas
2023-05-30 13:08           ` Catalin Marinas
2023-05-31 14:52           ` Jisheng Zhang
2023-05-31 14:52             ` Jisheng Zhang
2023-05-26 16:59 ` [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang

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