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From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
Date: Wed, 31 May 2023 23:28:22 +0800	[thread overview]
Message-ID: <ZHdnliDU7ikKaFoX@xhacker> (raw)
In-Reply-To: <ZHdmnfJvF1N5rgvx@xhacker>

On Wed, May 31, 2023 at 11:24:19PM +0800, Jisheng Zhang wrote:
> On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> > Hey Jisheng,
> 
> Hi Conor,
> 
> > 
> > On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > > We will soon take different actions by checking the HW is noncoherent
> > > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/errata/thead/errata.c    | 19 +++++++++++--------
> > >  arch/riscv/include/asm/cacheflush.h |  4 ++--
> > >  arch/riscv/kernel/setup.c           |  6 +++++-
> > >  arch/riscv/mm/dma-noncoherent.c     | 10 ++++++----
> > >  4 files changed, 24 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > index be84b14f0118..c192b80a5166 100644
> > > --- a/arch/riscv/errata/thead/errata.c
> > > +++ b/arch/riscv/errata/thead/errata.c
> > > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > >  static bool errata_probe_cmo(unsigned int stage,
> > >  			     unsigned long arch_id, unsigned long impid)
> > >  {
> > > -	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > > -		return false;
> > > -
> > > -	if (arch_id != 0 || impid != 0)
> > > -		return false;
> > > +	bool cmo;
> > >  
> > >  	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > >  		return false;
> > >  
> > > +	if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > > +	    (arch_id == 0 && impid == 0))
> > > +		cmo = true;
> > > +	else
> > > +		cmo = false;
> > > +
> > >  	if (stage == RISCV_ALTERNATIVES_BOOT) {
> > > -		riscv_cbom_block_size = L1_CACHE_BYTES;
> > > -		riscv_noncoherent_supported();
> > > +		if (cmo)
> > > +			riscv_cbom_block_size = L1_CACHE_BYTES;
> > > +		riscv_noncoherent_supported(cmo);
> > >  	}
> > >  
> > > -	return true;
> > > +	return cmo;
> > 
> > I don't really understand the changes that you are making to this
> > function, so that is tries really hard to call
> > riscv_noncoherent_supported(). Why do we need to always call the function
> > in the erratum's probe function, if the erratum is not detected, given
> 
> In one unified kernel Image, to support both coherent and noncoherent
> platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
> kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.

seems adding three words can make it better:

kmalloc meet both cases at the beginning, specifically ...

> Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
> ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
> to 1. The notice action is done in patch 5:
> 
> +       } else {
> +               dma_cache_alignment = 1;
> 
> 
> > that riscv_noncoherent_supported() is called immediately after
> > apply_boot_alternatives() in setup_arch()?
> > 
> > >  }
> > >  
> > >  static bool errata_probe_pmu(unsigned int stage,
> > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> > > index 8091b8bf4883..9d056c9b625a 100644
> > > --- a/arch/riscv/include/asm/cacheflush.h
> > > +++ b/arch/riscv/include/asm/cacheflush.h
> > > @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
> > >  void riscv_init_cbo_blocksizes(void);
> > >  
> > >  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > > -void riscv_noncoherent_supported(void);
> > > +void riscv_noncoherent_supported(bool cmo);
> > 
> > I think it would "read better" if you renamed this variable to
> > "have_cmo".
> > 
> > >  #else
> > > -static inline void riscv_noncoherent_supported(void) {}
> > > +static inline void riscv_noncoherent_supported(bool cmo) {}
> > >  #endif
> > >  
> > >  /*
> > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > > index 36b026057503..565f3e20169b 100644
> > > --- a/arch/riscv/kernel/setup.c
> > > +++ b/arch/riscv/kernel/setup.c
> > > @@ -264,6 +264,7 @@ static void __init parse_dtb(void)
> > >  
> > >  void __init setup_arch(char **cmdline_p)
> > >  {
> > > +	bool cmo;
> > >  	parse_dtb();
> > >  	setup_initial_init_mm(_stext, _etext, _edata, _end);
> > >  
> > > @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
> > >  	apply_boot_alternatives();
> > >  	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> > >  	    riscv_isa_extension_available(NULL, ZICBOM))
> > > -		riscv_noncoherent_supported();
> > > +		cmo = true;
> > > +	else
> > > +		cmo = false;
> > > +	riscv_noncoherent_supported(cmo);
> > 
> > As a nit, could you put a newline before the call to
> > riscv_noncoherent_supported()?
> > 
> > >  }
> > >  
> > >  static int __init topology_init(void)
> > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > > index d51a75864e53..0e172e2b4751 100644
> > > --- a/arch/riscv/mm/dma-noncoherent.c
> > > +++ b/arch/riscv/mm/dma-noncoherent.c
> > > @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> > >  	dev->dma_coherent = coherent;
> > >  }
> > >  
> > > -void riscv_noncoherent_supported(void)
> > > +void riscv_noncoherent_supported(bool cmo)
> > >  {
> > > -	WARN(!riscv_cbom_block_size,
> > > -	     "Non-coherent DMA support enabled without a block size\n");
> > > -	noncoherent_supported = true;
> > > +	if (cmo) {
> > > +		WARN(!riscv_cbom_block_size,
> > > +		     "Non-coherent DMA support enabled without a block size\n");
> > > +		noncoherent_supported = true;
> > > +	}
> > 
> > The other places that we do a WARN() because of screwed up devicetrees
> > for CMO things, we do a WARN_TAINT(CPU_OUT_OF_SPEC). Should we do the
> > same here too?
> > 
> > Cheers,
> > Conor.
> 
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported()
Date: Wed, 31 May 2023 23:28:22 +0800	[thread overview]
Message-ID: <ZHdnliDU7ikKaFoX@xhacker> (raw)
In-Reply-To: <ZHdmnfJvF1N5rgvx@xhacker>

On Wed, May 31, 2023 at 11:24:19PM +0800, Jisheng Zhang wrote:
> On Mon, May 29, 2023 at 12:13:10PM +0100, Conor Dooley wrote:
> > Hey Jisheng,
> 
> Hi Conor,
> 
> > 
> > On Sat, May 27, 2023 at 12:59:56AM +0800, Jisheng Zhang wrote:
> > > We will soon take different actions by checking the HW is noncoherent
> > > or not, I.E ZICBOM/ERRATA_THEAD_CMO or not.
> > > 
> > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > > ---
> > >  arch/riscv/errata/thead/errata.c    | 19 +++++++++++--------
> > >  arch/riscv/include/asm/cacheflush.h |  4 ++--
> > >  arch/riscv/kernel/setup.c           |  6 +++++-
> > >  arch/riscv/mm/dma-noncoherent.c     | 10 ++++++----
> > >  4 files changed, 24 insertions(+), 15 deletions(-)
> > > 
> > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > > index be84b14f0118..c192b80a5166 100644
> > > --- a/arch/riscv/errata/thead/errata.c
> > > +++ b/arch/riscv/errata/thead/errata.c
> > > @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage,
> > >  static bool errata_probe_cmo(unsigned int stage,
> > >  			     unsigned long arch_id, unsigned long impid)
> > >  {
> > > -	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> > > -		return false;
> > > -
> > > -	if (arch_id != 0 || impid != 0)
> > > -		return false;
> > > +	bool cmo;
> > >  
> > >  	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> > >  		return false;
> > >  
> > > +	if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) &&
> > > +	    (arch_id == 0 && impid == 0))
> > > +		cmo = true;
> > > +	else
> > > +		cmo = false;
> > > +
> > >  	if (stage == RISCV_ALTERNATIVES_BOOT) {
> > > -		riscv_cbom_block_size = L1_CACHE_BYTES;
> > > -		riscv_noncoherent_supported();
> > > +		if (cmo)
> > > +			riscv_cbom_block_size = L1_CACHE_BYTES;
> > > +		riscv_noncoherent_supported(cmo);
> > >  	}
> > >  
> > > -	return true;
> > > +	return cmo;
> > 
> > I don't really understand the changes that you are making to this
> > function, so that is tries really hard to call
> > riscv_noncoherent_supported(). Why do we need to always call the function
> > in the erratum's probe function, if the erratum is not detected, given
> 
> In one unified kernel Image, to support both coherent and noncoherent
> platforms(currently, either T-HEAD CMO or ZICBOM), we need to let the
> kmalloc meet both cases, specifically, ARCH_DMA_MINALIGN aligned.

seems adding three words can make it better:

kmalloc meet both cases at the beginning, specifically ...

> Once we know the underlying HW is coherent, I.E neither T-HEAD CMO nor
> ZICBOM, we need to notice kmalloc we are safe to reduce the alignment
> to 1. The notice action is done in patch 5:
> 
> +       } else {
> +               dma_cache_alignment = 1;
> 
> 
> > that riscv_noncoherent_supported() is called immediately after
> > apply_boot_alternatives() in setup_arch()?
> > 
> > >  }
> > >  
> > >  static bool errata_probe_pmu(unsigned int stage,
> > > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> > > index 8091b8bf4883..9d056c9b625a 100644
> > > --- a/arch/riscv/include/asm/cacheflush.h
> > > +++ b/arch/riscv/include/asm/cacheflush.h
> > > @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size;
> > >  void riscv_init_cbo_blocksizes(void);
> > >  
> > >  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > > -void riscv_noncoherent_supported(void);
> > > +void riscv_noncoherent_supported(bool cmo);
> > 
> > I think it would "read better" if you renamed this variable to
> > "have_cmo".
> > 
> > >  #else
> > > -static inline void riscv_noncoherent_supported(void) {}
> > > +static inline void riscv_noncoherent_supported(bool cmo) {}
> > >  #endif
> > >  
> > >  /*
> > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > > index 36b026057503..565f3e20169b 100644
> > > --- a/arch/riscv/kernel/setup.c
> > > +++ b/arch/riscv/kernel/setup.c
> > > @@ -264,6 +264,7 @@ static void __init parse_dtb(void)
> > >  
> > >  void __init setup_arch(char **cmdline_p)
> > >  {
> > > +	bool cmo;
> > >  	parse_dtb();
> > >  	setup_initial_init_mm(_stext, _etext, _edata, _end);
> > >  
> > > @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p)
> > >  	apply_boot_alternatives();
> > >  	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> > >  	    riscv_isa_extension_available(NULL, ZICBOM))
> > > -		riscv_noncoherent_supported();
> > > +		cmo = true;
> > > +	else
> > > +		cmo = false;
> > > +	riscv_noncoherent_supported(cmo);
> > 
> > As a nit, could you put a newline before the call to
> > riscv_noncoherent_supported()?
> > 
> > >  }
> > >  
> > >  static int __init topology_init(void)
> > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > > index d51a75864e53..0e172e2b4751 100644
> > > --- a/arch/riscv/mm/dma-noncoherent.c
> > > +++ b/arch/riscv/mm/dma-noncoherent.c
> > > @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> > >  	dev->dma_coherent = coherent;
> > >  }
> > >  
> > > -void riscv_noncoherent_supported(void)
> > > +void riscv_noncoherent_supported(bool cmo)
> > >  {
> > > -	WARN(!riscv_cbom_block_size,
> > > -	     "Non-coherent DMA support enabled without a block size\n");
> > > -	noncoherent_supported = true;
> > > +	if (cmo) {
> > > +		WARN(!riscv_cbom_block_size,
> > > +		     "Non-coherent DMA support enabled without a block size\n");
> > > +		noncoherent_supported = true;
> > > +	}
> > 
> > The other places that we do a WARN() because of screwed up devicetrees
> > for CMO things, we do a WARN_TAINT(CPU_OUT_OF_SPEC). Should we do the
> > same here too?
> > 
> > Cheers,
> > Conor.
> 
> 

  reply	other threads:[~2023-05-31 15:39 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-26 16:59 [PATCH 0/6] riscv: Reduce ARCH_KMALLOC_MINALIGN to 8 Jisheng Zhang
2023-05-26 16:59 ` Jisheng Zhang
2023-05-26 16:59 ` [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 10:42   ` Conor Dooley
2023-05-29 10:42     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 10:44   ` Conor Dooley
2023-05-29 10:44     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 10:53   ` Conor Dooley
2023-05-29 10:53     ` Conor Dooley
2023-05-26 16:59 ` [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 11:13   ` Conor Dooley
2023-05-29 11:13     ` Conor Dooley
2023-05-31 15:24     ` Jisheng Zhang
2023-05-31 15:24       ` Jisheng Zhang
2023-05-31 15:28       ` Jisheng Zhang [this message]
2023-05-31 15:28         ` Jisheng Zhang
2023-05-31 16:28         ` Conor Dooley
2023-05-31 16:28           ` Conor Dooley
2023-06-01  3:40           ` Jisheng Zhang
2023-06-01  3:40             ` Jisheng Zhang
2023-05-26 16:59 ` [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang
2023-05-29 11:17   ` Conor Dooley
2023-05-29 11:17     ` Conor Dooley
2023-05-30  9:59     ` Catalin Marinas
2023-05-30  9:59       ` Catalin Marinas
2023-05-30 10:34       ` Conor Dooley
2023-05-30 10:34         ` Conor Dooley
2023-05-30 13:08         ` Catalin Marinas
2023-05-30 13:08           ` Catalin Marinas
2023-05-31 14:52           ` Jisheng Zhang
2023-05-31 14:52             ` Jisheng Zhang
2023-05-26 16:59 ` [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Jisheng Zhang
2023-05-26 16:59   ` Jisheng Zhang

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