From: Conor Dooley <conor@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Prabhakar <prabhakar.csengg@gmail.com>,
Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
Christoph Hellwig <hch@infradead.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support
Date: Wed, 14 Jun 2023 17:43:57 +0100 [thread overview]
Message-ID: <20230614-bundle-greedless-91581fdbdce8@spud> (raw)
In-Reply-To: <CAMuHMdWApGKsS8DU7-=6j6WaRBDZ8Amig2NtA8f8=PbGKoFQjQ@mail.gmail.com>
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On Wed, Jun 14, 2023 at 02:53:26PM +0200, Geert Uytterhoeven wrote:
> Hi Prabhakar,
>
> On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Introduce support for nonstandard noncoherent systems in the RISC-V
> > architecture. It enables function pointer support to handle cache
> > management in such systems.
> >
> > This patch adds a new configuration option called
> > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
> > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
> > support for cache management in nonstandard noncoherent systems.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v8 -> v9
> > * New patch
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/dma-noncoherent.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 Renesas Electronics Corp.
> > + */
> > +
> > +#ifndef __ASM_DMA_NONCOHERENT_H
> > +#define __ASM_DMA_NONCOHERENT_H
> > +
> > +#include <linux/dma-direct.h>
> > +
> > +/*
> > + * struct riscv_cache_ops - Structure for CMO function pointers
> > + *
> > + * @clean: Function pointer for clean cache
> > + * @inval: Function pointer for invalidate cache
> > + * @flush: Function pointer for flushing the cache
> > + */
> > +struct riscv_cache_ops {
> > + void (*clean)(phys_addr_t paddr, unsigned long size);
> > + void (*inval)(phys_addr_t paddr, unsigned long size);
> > + void (*flush)(phys_addr_t paddr, unsigned long size);
> > +};
>
> I guess the naming can be improved?
>
> .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(),
> .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(),
> .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent().
>
> Perhaps .wback(), .inv(), .wback_inv() are more clear?
>
> I understand this is subject to bikeshedding...
> But hey, how many innocent bits of data have already been lost due
> to cache semantic mismatches?
Given this is based on Arnd's stuff, +1 on the bikeshed. The names have
been chosen I guess to match the CBOM extensions naming.
Otherwise, I had it in my head that the next revision of this was going
to take patches 8 & 9 from Arnd's series, to align the semantics. Not
that it really bothers me, just means this will have to wait for the
cross-arch series, when pretty sure Arnd suggested not depending on that
any more... Am I missing something Prabhakar?
Other than the bikeshedding, no objections.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Prabhakar <prabhakar.csengg@gmail.com>,
Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Samuel Holland <samuel@sholland.org>,
linux-riscv@lists.infradead.org,
Christoph Hellwig <hch@infradead.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support
Date: Wed, 14 Jun 2023 17:43:57 +0100 [thread overview]
Message-ID: <20230614-bundle-greedless-91581fdbdce8@spud> (raw)
In-Reply-To: <CAMuHMdWApGKsS8DU7-=6j6WaRBDZ8Amig2NtA8f8=PbGKoFQjQ@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2760 bytes --]
On Wed, Jun 14, 2023 at 02:53:26PM +0200, Geert Uytterhoeven wrote:
> Hi Prabhakar,
>
> On Wed, Jun 14, 2023 at 12:48 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Introduce support for nonstandard noncoherent systems in the RISC-V
> > architecture. It enables function pointer support to handle cache
> > management in such systems.
> >
> > This patch adds a new configuration option called
> > "RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
> > depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
> > support for cache management in nonstandard noncoherent systems.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v8 -> v9
> > * New patch
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/dma-noncoherent.h
> > @@ -0,0 +1,28 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 Renesas Electronics Corp.
> > + */
> > +
> > +#ifndef __ASM_DMA_NONCOHERENT_H
> > +#define __ASM_DMA_NONCOHERENT_H
> > +
> > +#include <linux/dma-direct.h>
> > +
> > +/*
> > + * struct riscv_cache_ops - Structure for CMO function pointers
> > + *
> > + * @clean: Function pointer for clean cache
> > + * @inval: Function pointer for invalidate cache
> > + * @flush: Function pointer for flushing the cache
> > + */
> > +struct riscv_cache_ops {
> > + void (*clean)(phys_addr_t paddr, unsigned long size);
> > + void (*inval)(phys_addr_t paddr, unsigned long size);
> > + void (*flush)(phys_addr_t paddr, unsigned long size);
> > +};
>
> I guess the naming can be improved?
>
> .clean() is used by arch_dma_cache_wback() / arch_wb_cache_pmem(),
> .inval() is used by arch_dma_cache_inv() / arch_invalidate_pmem(),
> .flush() is used by arch_dma_cache_wback_inv() / arch_dma_prep_coherent().
>
> Perhaps .wback(), .inv(), .wback_inv() are more clear?
>
> I understand this is subject to bikeshedding...
> But hey, how many innocent bits of data have already been lost due
> to cache semantic mismatches?
Given this is based on Arnd's stuff, +1 on the bikeshed. The names have
been chosen I guess to match the CBOM extensions naming.
Otherwise, I had it in my head that the next revision of this was going
to take patches 8 & 9 from Arnd's series, to align the semantics. Not
that it really bothers me, just means this will have to wait for the
cross-arch series, when pretty sure Arnd suggested not depending on that
any more... Am I missing something Prabhakar?
Other than the bikeshedding, no objections.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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next prev parent reply other threads:[~2023-06-14 16:44 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 10:47 [PATCH v9 0/6] Add non-coherent DMA support for AX45MP Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 10:47 ` [PATCH v9 1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 10:47 ` [PATCH v9 2/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 10:47 ` [PATCH v9 3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 12:35 ` Arnd Bergmann
2023-06-14 12:35 ` Arnd Bergmann
2023-06-15 6:00 ` Christoph Hellwig
2023-06-15 6:00 ` Christoph Hellwig
2023-06-16 12:13 ` Lad, Prabhakar
2023-06-16 12:13 ` Lad, Prabhakar
2023-06-14 12:53 ` Geert Uytterhoeven
2023-06-14 12:53 ` Geert Uytterhoeven
2023-06-14 16:43 ` Conor Dooley [this message]
2023-06-14 16:43 ` Conor Dooley
2023-06-16 12:23 ` Lad, Prabhakar
2023-06-16 12:23 ` Lad, Prabhakar
2023-06-14 10:47 ` [PATCH v9 4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 10:47 ` [PATCH v9 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 13:10 ` Arnd Bergmann
2023-06-14 13:10 ` Arnd Bergmann
2023-06-28 12:57 ` Lad, Prabhakar
2023-06-28 12:57 ` Lad, Prabhakar
2023-06-14 10:47 ` [PATCH v9 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-06-14 10:47 ` Prabhakar
2023-06-14 16:58 ` [PATCH v9 0/6] Add non-coherent DMA support for AX45MP Conor Dooley
2023-06-14 16:58 ` Conor Dooley
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