Re: [Intel-wired-lan] [RFC PATCH v8 01/10] dpll: documentation on DPLL subsystem interface

From: Jakub Kicinski <kuba@kernel.org>
To: Jiri Pirko <jiri@resnulli.us>
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Subject: Re: [Intel-wired-lan] [RFC PATCH v8 01/10] dpll: documentation on DPLL subsystem interface
Date: Thu, 15 Jun 2023 09:31:11 -0700	[thread overview]
Message-ID: <20230615093111.0ee762e4@kernel.org> (raw)
In-Reply-To: <ZIrldB4ic3zt9nIk@nanopsycho>

On Thu, 15 Jun 2023 12:18:28 +0200 Jiri Pirko wrote:
> Yeah, that is what we had originally. This just pushes out the
> different attr selection from the nest one level up to the actualy
> nesting attribute.

Oh no, no extra nesting. Let me try to fake up the output:

'pin': [{
 {'clock-id': 282574471561216,
  'module-name': 'ice',
  'pin-dpll-caps': 4,
  'pin-id': 13,
  'parent-device': [{'pin-id': 2, 'pin-state': 'connected'},
                    {'pin-id': 3, 'pin-state': 'disconnected'}],
  'parent-pin': [{'id': 0, 'pin-direction': 'input'},
                 {'id': 1, 'pin-direction': 'input'}],
  'pin-type': 'synce-eth-port'}
}]

> One downside of this is you will have 2 arrays of parent objects,
> one per parent type. Current code neatly groups them into a single array.
> 
> I guess this is a matter of personal preference, I'm fine either way.

Yeah, could be.
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