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From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry
Date: Wed, 26 Jul 2023 14:13:47 +0530	[thread overview]
Message-ID: <20230726084352.2136377-3-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230726084352.2136377-1-mchitale@ventanamicro.com>

Add an entry for the Smstateen extension to the riscv,isa-extensions
property.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..36ff6749fbba 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,12 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smstateen
+          description: |
+            The standard Smstateen extension for controlling access to CSRs
+            added by other RISC-V extensions in H/S/VS/U/VU modes and as
+            ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced
-- 
2.34.1



WARNING: multiple messages have this Message-ID (diff)
From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
	Conor Dooley <conor@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry
Date: Wed, 26 Jul 2023 14:13:47 +0530	[thread overview]
Message-ID: <20230726084352.2136377-3-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230726084352.2136377-1-mchitale@ventanamicro.com>

Add an entry for the Smstateen extension to the riscv,isa-extensions
property.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..36ff6749fbba 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,12 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smstateen
+          description: |
+            The standard Smstateen extension for controlling access to CSRs
+            added by other RISC-V extensions in H/S/VS/U/VU modes and as
+            ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced
-- 
2.34.1


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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
	Conor Dooley <conor@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry
Date: Wed, 26 Jul 2023 14:13:47 +0530	[thread overview]
Message-ID: <20230726084352.2136377-3-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230726084352.2136377-1-mchitale@ventanamicro.com>

Add an entry for the Smstateen extension to the riscv,isa-extensions
property.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..36ff6749fbba 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,12 @@ properties:
             changes to interrupts as frozen at commit ccbddab ("Merge pull
             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
 
+        - const: smstateen
+          description: |
+            The standard Smstateen extension for controlling access to CSRs
+            added by other RISC-V extensions in H/S/VS/U/VU modes and as
+            ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+
         - const: ssaia
           description: |
             The standard Ssaia supervisor-level extension for the advanced
-- 
2.34.1


  parent reply	other threads:[~2023-07-26  8:43 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-26  8:43 [PATCH v4 0/7] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-26  8:43 ` Mayuresh Chitale
2023-07-26  8:43 ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 1/7] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-08-03 12:01   ` Conor Dooley
2023-08-03 12:01     ` Conor Dooley
2023-08-03 12:01     ` Conor Dooley
2023-07-26  8:43 ` Mayuresh Chitale [this message]
2023-07-26  8:43   ` [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 3/7] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 4/7] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 5/7] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 6/7] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43 ` [PATCH v4 7/7] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale
2023-07-26  8:43   ` Mayuresh Chitale

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