From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v4 0/7] Risc-V Kvm Smstateen
Date: Wed, 26 Jul 2023 14:13:45 +0530 [thread overview]
Message-ID: <20230726084352.2136377-1-mchitale@ventanamicro.com> (raw)
This series adds support to detect the Smstateen extension for both, the
host and the guest vcpu. It also adds senvcfg and sstateen0 to the ONE_REG
interface and the vcpu context save/restore.
The motivation behind Smstateen from the spec
(https://github.com/riscv/riscv-state-enable):
"The implementation of optional RISC-V extensions has the potential to open
covert channels between separate user threads, or between separate guest OSes
running under a hypervisor. The problem occurs when an extension adds processor
state---usually explicit registers, but possibly other forms of state---that
the main OS or hypervisor is unaware of (and hence won?t context-switch) but
that can be modified/written by one user thread or guest OS and perceived/
examined/read by another."
Changes in v4:
- Update commit description for patch 1
- Rebase to kvm_riscv_queue
- Add reviewed-by tag
Changes in v3:
- Move DT bindings change to a separate patch
- Move senvcfg/sstateen0 save/restore to separate function
Changes in v2:
- Add smstaeen description in riscv/extensions.yaml
- Avoid line wrap at 80 chars
Mayuresh Chitale (7):
RISC-V: Detect Smstateen extension
dt-bindings: riscv: Add smstateen entry
RISC-V: KVM: Add kvm_vcpu_config
RISC-V: KVM: Enable Smstateen accesses
RISCV: KVM: Add senvcfg context save/restore
RISCV: KVM: Add sstateen0 context save/restore
RISCV: KVM: Add sstateen0 to ONE_REG
.../devicetree/bindings/riscv/extensions.yaml | 6 ++
arch/riscv/include/asm/csr.h | 18 +++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 18 +++++
arch/riscv/include/uapi/asm/kvm.h | 11 +++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/vcpu.c | 70 +++++++++++++++----
arch/riscv/kvm/vcpu_onereg.c | 41 +++++++++++
9 files changed, 154 insertions(+), 13 deletions(-)
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
Conor Dooley <conor@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 0/7] Risc-V Kvm Smstateen
Date: Wed, 26 Jul 2023 14:13:45 +0530 [thread overview]
Message-ID: <20230726084352.2136377-1-mchitale@ventanamicro.com> (raw)
This series adds support to detect the Smstateen extension for both, the
host and the guest vcpu. It also adds senvcfg and sstateen0 to the ONE_REG
interface and the vcpu context save/restore.
The motivation behind Smstateen from the spec
(https://github.com/riscv/riscv-state-enable):
"The implementation of optional RISC-V extensions has the potential to open
covert channels between separate user threads, or between separate guest OSes
running under a hypervisor. The problem occurs when an extension adds processor
state---usually explicit registers, but possibly other forms of state---that
the main OS or hypervisor is unaware of (and hence won’t context-switch) but
that can be modified/written by one user thread or guest OS and perceived/
examined/read by another."
Changes in v4:
- Update commit description for patch 1
- Rebase to kvm_riscv_queue
- Add reviewed-by tag
Changes in v3:
- Move DT bindings change to a separate patch
- Move senvcfg/sstateen0 save/restore to separate function
Changes in v2:
- Add smstaeen description in riscv/extensions.yaml
- Avoid line wrap at 80 chars
Mayuresh Chitale (7):
RISC-V: Detect Smstateen extension
dt-bindings: riscv: Add smstateen entry
RISC-V: KVM: Add kvm_vcpu_config
RISC-V: KVM: Enable Smstateen accesses
RISCV: KVM: Add senvcfg context save/restore
RISCV: KVM: Add sstateen0 context save/restore
RISCV: KVM: Add sstateen0 to ONE_REG
.../devicetree/bindings/riscv/extensions.yaml | 6 ++
arch/riscv/include/asm/csr.h | 18 +++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 18 +++++
arch/riscv/include/uapi/asm/kvm.h | 11 +++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/vcpu.c | 70 +++++++++++++++----
arch/riscv/kvm/vcpu_onereg.c | 41 +++++++++++
9 files changed, 154 insertions(+), 13 deletions(-)
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
Conor Dooley <conor@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH v4 0/7] Risc-V Kvm Smstateen
Date: Wed, 26 Jul 2023 14:13:45 +0530 [thread overview]
Message-ID: <20230726084352.2136377-1-mchitale@ventanamicro.com> (raw)
This series adds support to detect the Smstateen extension for both, the
host and the guest vcpu. It also adds senvcfg and sstateen0 to the ONE_REG
interface and the vcpu context save/restore.
The motivation behind Smstateen from the spec
(https://github.com/riscv/riscv-state-enable):
"The implementation of optional RISC-V extensions has the potential to open
covert channels between separate user threads, or between separate guest OSes
running under a hypervisor. The problem occurs when an extension adds processor
state---usually explicit registers, but possibly other forms of state---that
the main OS or hypervisor is unaware of (and hence won’t context-switch) but
that can be modified/written by one user thread or guest OS and perceived/
examined/read by another."
Changes in v4:
- Update commit description for patch 1
- Rebase to kvm_riscv_queue
- Add reviewed-by tag
Changes in v3:
- Move DT bindings change to a separate patch
- Move senvcfg/sstateen0 save/restore to separate function
Changes in v2:
- Add smstaeen description in riscv/extensions.yaml
- Avoid line wrap at 80 chars
Mayuresh Chitale (7):
RISC-V: Detect Smstateen extension
dt-bindings: riscv: Add smstateen entry
RISC-V: KVM: Add kvm_vcpu_config
RISC-V: KVM: Enable Smstateen accesses
RISCV: KVM: Add senvcfg context save/restore
RISCV: KVM: Add sstateen0 context save/restore
RISCV: KVM: Add sstateen0 to ONE_REG
.../devicetree/bindings/riscv/extensions.yaml | 6 ++
arch/riscv/include/asm/csr.h | 18 +++++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 18 +++++
arch/riscv/include/uapi/asm/kvm.h | 11 +++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/vcpu.c | 70 +++++++++++++++----
arch/riscv/kvm/vcpu_onereg.c | 41 +++++++++++
9 files changed, 154 insertions(+), 13 deletions(-)
--
2.34.1
next reply other threads:[~2023-07-26 8:43 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-26 8:43 Mayuresh Chitale [this message]
2023-07-26 8:43 ` [PATCH v4 0/7] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 1/7] RISC-V: Detect Smstateen extension Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-08-03 12:01 ` Conor Dooley
2023-08-03 12:01 ` Conor Dooley
2023-08-03 12:01 ` Conor Dooley
2023-07-26 8:43 ` [PATCH v4 2/7] dt-bindings: riscv: Add smstateen entry Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 3/7] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 4/7] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 5/7] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 6/7] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` [PATCH v4 7/7] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
2023-07-26 8:43 ` Mayuresh Chitale
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230726084352.2136377-1-mchitale@ventanamicro.com \
--to=mchitale@ventanamicro.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.