* [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 7:25 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
` (19 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Add "Message Routing" and "INTx Mechanism Messages" macros to enable
a PCIe driver to send messages for INTx Interrupt Signaling.
The "Message Routing" is from Table 2-17, and the "INTx Mechanism
Messages" is from Table 2-18 on the PCI Express Base Specification,
Rev. 4.0 Version 1.0.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/pci.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index a4c397434057..0b6df6c2c918 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -13,6 +13,24 @@
#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
+/* Message Routing (r[2:0]) */
+#define PCI_MSG_TYPE_R_ROUTING_RC 0
+#define PCI_MSG_TYPE_R_ROUTING_ADDR 1
+#define PCI_MSG_TYPE_R_ROUTING_ID 2
+#define PCI_MSG_TYPE_R_ROUTING_BC 3
+#define PCI_MSG_TYPE_R_ROUTING_LOCAL 4
+#define PCI_MSG_TYPE_R_ROUTING_GATHER 5
+
+/* INTx Mechanism Messages */
+#define PCI_MSG_CODE_ASSERT_INTA 0x20
+#define PCI_MSG_CODE_ASSERT_INTB 0x21
+#define PCI_MSG_CODE_ASSERT_INTC 0x22
+#define PCI_MSG_CODE_ASSERT_INTD 0x23
+#define PCI_MSG_CODE_DEASSERT_INTA 0x24
+#define PCI_MSG_CODE_DEASSERT_INTB 0x25
+#define PCI_MSG_CODE_DEASSERT_INTC 0x26
+#define PCI_MSG_CODE_DEASSERT_INTD 0x27
+
extern const unsigned char pcie_link_speed[];
extern bool pci_early_dump;
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
@ 2023-07-24 7:25 ` Manivannan Sadhasivam
0 siblings, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 7:25 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:33PM +0900, Yoshihiro Shimoda wrote:
> Add "Message Routing" and "INTx Mechanism Messages" macros to enable
> a PCIe driver to send messages for INTx Interrupt Signaling.
>
> The "Message Routing" is from Table 2-17, and the "INTx Mechanism
> Messages" is from Table 2-18 on the PCI Express Base Specification,
> Rev. 4.0 Version 1.0.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/pci.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index a4c397434057..0b6df6c2c918 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -13,6 +13,24 @@
>
> #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
>
> +/* Message Routing (r[2:0]) */
> +#define PCI_MSG_TYPE_R_ROUTING_RC 0
> +#define PCI_MSG_TYPE_R_ROUTING_ADDR 1
> +#define PCI_MSG_TYPE_R_ROUTING_ID 2
> +#define PCI_MSG_TYPE_R_ROUTING_BC 3
> +#define PCI_MSG_TYPE_R_ROUTING_LOCAL 4
> +#define PCI_MSG_TYPE_R_ROUTING_GATHER 5
> +
> +/* INTx Mechanism Messages */
> +#define PCI_MSG_CODE_ASSERT_INTA 0x20
> +#define PCI_MSG_CODE_ASSERT_INTB 0x21
> +#define PCI_MSG_CODE_ASSERT_INTC 0x22
> +#define PCI_MSG_CODE_ASSERT_INTD 0x23
> +#define PCI_MSG_CODE_DEASSERT_INTA 0x24
> +#define PCI_MSG_CODE_DEASSERT_INTB 0x25
> +#define PCI_MSG_CODE_DEASSERT_INTC 0x26
> +#define PCI_MSG_CODE_DEASSERT_INTD 0x27
> +
> extern const unsigned char pcie_link_speed[];
> extern bool pci_early_dump;
>
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 8:10 ` Damien Le Moal
2023-07-21 7:44 ` [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq" Yoshihiro Shimoda
` (18 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Bjorn Helgaas,
Manivannan Sadhasivam, Jesper Nilsson, Tom Joseph,
Vignesh Raghavendra, Richard Zhu, Lucas Stach, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Minghuan Lian, Mingkai Hu, Roy Zang,
Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
Using "INTx" instead of "legacy" is more specific. So, rename
PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
This CC-list is for git send-email.
Cc: Tom Joseph <tjoseph@cadence.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Minghuan Lian <minghuan.Lian@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Srikanth Thokala <srikanth.thokala@intel.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Kishon Vijay Abraham I <kishon@kernel.org>
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +-
drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
drivers/pci/controller/dwc/pci-imx6.c | 2 +-
drivers/pci/controller/dwc/pci-keystone.c | 2 +-
drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
drivers/pci/controller/pcie-rcar-ep.c | 2 +-
drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
drivers/pci/endpoint/functions/pci-epf-test.c | 10 +++++-----
include/linux/pci-epc.h | 4 ++--
15 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index b8b655d4047e..2af8eb4e6d91 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
struct device *dev = pcie->dev;
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
if (vfn > 0) {
dev_err(dev, "Cannot raise legacy interrupts for VF\n");
return -EINVAL;
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index b445ffe95e3f..8767432dda5c 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
dra7xx_pcie_raise_legacy_irq(dra7xx);
break;
case PCI_EPC_IRQ_MSI:
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 235ead4c807f..feadc88782a7 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 49aea6ce3e87..fce300673ea3 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -907,7 +907,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
ks_pcie_am654_raise_legacy_irq(ks_pcie);
break;
case PCI_EPC_IRQ_MSI:
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index de4c1758a6c3..b2e14d64dba2 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -155,7 +155,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index 9b572a2b2c9a..cf92a11ede86 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
return -EINVAL;
case PCI_EPC_IRQ_MSI:
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index b625841e98aa..f72df38dd523 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 289bff99d762..62903fef343c 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -295,7 +295,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
/* Legacy interrupts are not supported in Keem Bay */
dev_err(pci->dev, "Legacy IRQ is not supported\n");
return -EINVAL;
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 267e1247d548..21e2ccc49219 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -660,7 +660,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 383ba71d1e8f..85cc64324efd 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1999,7 +1999,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
case PCI_EPC_IRQ_MSI:
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index cba3c88fcf39..a00301928c38 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return uniphier_pcie_ep_raise_legacy_irq(ep);
case PCI_EPC_IRQ_MSI:
return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
index f9682df1da61..fbdf3d85301c 100644
--- a/drivers/pci/controller/pcie-rcar-ep.c
+++ b/drivers/pci/controller/pcie-rcar-ep.c
@@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return rcar_pcie_ep_assert_intx(ep, fn, 0);
case PCI_EPC_IRQ_MSI:
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index 0af0e965fb57..e856a45d0986 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -413,7 +413,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_EPC_IRQ_INTX:
return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
case PCI_EPC_IRQ_MSI:
return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 1f0d2b84296a..caa30596fadd 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -19,11 +19,11 @@
#include <linux/pci-epf.h>
#include <linux/pci_regs.h>
-#define IRQ_TYPE_LEGACY 0
+#define IRQ_TYPE_INTX 0
#define IRQ_TYPE_MSI 1
#define IRQ_TYPE_MSIX 2
-#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
+#define COMMAND_RAISE_INTX_IRQ BIT(0)
#define COMMAND_RAISE_MSI_IRQ BIT(1)
#define COMMAND_RAISE_MSIX_IRQ BIT(2)
#define COMMAND_READ BIT(3)
@@ -600,9 +600,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
WRITE_ONCE(reg->status, status);
switch (reg->irq_type) {
- case IRQ_TYPE_LEGACY:
+ case IRQ_TYPE_INTX:
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
- PCI_EPC_IRQ_LEGACY, 0);
+ PCI_EPC_IRQ_INTX, 0);
break;
case IRQ_TYPE_MSI:
count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
@@ -659,7 +659,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
}
switch (command) {
- case COMMAND_RAISE_LEGACY_IRQ:
+ case COMMAND_RAISE_INTX_IRQ:
case COMMAND_RAISE_MSI_IRQ:
case COMMAND_RAISE_MSIX_IRQ:
pci_epf_test_raise_irq(epf_test, reg);
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 5cb694031072..c5ada36b6ca0 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -21,7 +21,7 @@ enum pci_epc_interface_type {
enum pci_epc_irq_type {
PCI_EPC_IRQ_UNKNOWN,
- PCI_EPC_IRQ_LEGACY,
+ PCI_EPC_IRQ_INTX,
PCI_EPC_IRQ_MSI,
PCI_EPC_IRQ_MSIX,
};
@@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
* MSI-X capability register
* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
* from the MSI-X capability register
- * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
+ * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt
* @map_msi_irq: ops to map physical address to MSI address and return MSI data
* @start: ops to start the PCI link
* @stop: ops to stop the PCI link
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
@ 2023-07-21 8:10 ` Damien Le Moal
2023-07-24 7:32 ` Manivannan Sadhasivam
0 siblings, 1 reply; 90+ messages in thread
From: Damien Le Moal @ 2023-07-21 8:10 UTC (permalink / raw)
To: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, manivannan.sadhasivam, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Bjorn Helgaas, Manivannan Sadhasivam,
Jesper Nilsson, Tom Joseph, Vignesh Raghavendra, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Minghuan Lian, Mingkai Hu,
Roy Zang, Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
[-- Attachment #1: Type: text/plain, Size: 12662 bytes --]
On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> Using "INTx" instead of "legacy" is more specific. So, rename
> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
>
> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
PCI_IRQ_XXX macros used everywhere. Less definitions :)
See attached patch that I have in my queue (about to send that).
> ---
> This CC-list is for git send-email.
>
> Cc: Tom Joseph <tjoseph@cadence.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Minghuan Lian <minghuan.Lian@nxp.com>
> Cc: Mingkai Hu <mingkai.hu@nxp.com>
> Cc: Roy Zang <roy.zang@nxp.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Srikanth Thokala <srikanth.thokala@intel.com>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Jonathan Hunter <jonathanh@nvidia.com>
> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Shawn Lin <shawn.lin@rock-chips.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> ---
> drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +-
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> drivers/pci/controller/dwc/pci-imx6.c | 2 +-
> drivers/pci/controller/dwc/pci-keystone.c | 2 +-
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
> drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
> drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
> drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
> drivers/pci/controller/pcie-rcar-ep.c | 2 +-
> drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> drivers/pci/endpoint/functions/pci-epf-test.c | 10 +++++-----
> include/linux/pci-epc.h | 4 ++--
> 15 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index b8b655d4047e..2af8eb4e6d91 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> struct device *dev = pcie->dev;
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> if (vfn > 0) {
> dev_err(dev, "Cannot raise legacy interrupts for VF\n");
> return -EINVAL;
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index b445ffe95e3f..8767432dda5c 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> dra7xx_pcie_raise_legacy_irq(dra7xx);
> break;
> case PCI_EPC_IRQ_MSI:
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 235ead4c807f..feadc88782a7 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> case PCI_EPC_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 49aea6ce3e87..fce300673ea3 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -907,7 +907,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> ks_pcie_am654_raise_legacy_irq(ks_pcie);
> break;
> case PCI_EPC_IRQ_MSI:
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index de4c1758a6c3..b2e14d64dba2 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -155,7 +155,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> case PCI_EPC_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index 9b572a2b2c9a..cf92a11ede86 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
> return -EINVAL;
> case PCI_EPC_IRQ_MSI:
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index b625841e98aa..f72df38dd523 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> case PCI_EPC_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 289bff99d762..62903fef343c 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -295,7 +295,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> /* Legacy interrupts are not supported in Keem Bay */
> dev_err(pci->dev, "Legacy IRQ is not supported\n");
> return -EINVAL;
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 267e1247d548..21e2ccc49219 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -660,7 +660,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> case PCI_EPC_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 383ba71d1e8f..85cc64324efd 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1999,7 +1999,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
>
> case PCI_EPC_IRQ_MSI:
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index cba3c88fcf39..a00301928c38 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return uniphier_pcie_ep_raise_legacy_irq(ep);
> case PCI_EPC_IRQ_MSI:
> return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> index f9682df1da61..fbdf3d85301c 100644
> --- a/drivers/pci/controller/pcie-rcar-ep.c
> +++ b/drivers/pci/controller/pcie-rcar-ep.c
> @@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return rcar_pcie_ep_assert_intx(ep, fn, 0);
>
> case PCI_EPC_IRQ_MSI:
> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> index 0af0e965fb57..e856a45d0986 100644
> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -413,7 +413,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_EPC_IRQ_INTX:
> return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
> case PCI_EPC_IRQ_MSI:
> return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> index 1f0d2b84296a..caa30596fadd 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -19,11 +19,11 @@
> #include <linux/pci-epf.h>
> #include <linux/pci_regs.h>
>
> -#define IRQ_TYPE_LEGACY 0
> +#define IRQ_TYPE_INTX 0
> #define IRQ_TYPE_MSI 1
> #define IRQ_TYPE_MSIX 2
>
> -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
> +#define COMMAND_RAISE_INTX_IRQ BIT(0)
> #define COMMAND_RAISE_MSI_IRQ BIT(1)
> #define COMMAND_RAISE_MSIX_IRQ BIT(2)
> #define COMMAND_READ BIT(3)
> @@ -600,9 +600,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> WRITE_ONCE(reg->status, status);
>
> switch (reg->irq_type) {
> - case IRQ_TYPE_LEGACY:
> + case IRQ_TYPE_INTX:
> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> - PCI_EPC_IRQ_LEGACY, 0);
> + PCI_EPC_IRQ_INTX, 0);
> break;
> case IRQ_TYPE_MSI:
> count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
> @@ -659,7 +659,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
> }
>
> switch (command) {
> - case COMMAND_RAISE_LEGACY_IRQ:
> + case COMMAND_RAISE_INTX_IRQ:
> case COMMAND_RAISE_MSI_IRQ:
> case COMMAND_RAISE_MSIX_IRQ:
> pci_epf_test_raise_irq(epf_test, reg);
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index 5cb694031072..c5ada36b6ca0 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -21,7 +21,7 @@ enum pci_epc_interface_type {
>
> enum pci_epc_irq_type {
> PCI_EPC_IRQ_UNKNOWN,
> - PCI_EPC_IRQ_LEGACY,
> + PCI_EPC_IRQ_INTX,
> PCI_EPC_IRQ_MSI,
> PCI_EPC_IRQ_MSIX,
> };
> @@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
> * MSI-X capability register
> * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
> * from the MSI-X capability register
> - * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
> + * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt
> * @map_msi_irq: ops to map physical address to MSI address and return MSI data
> * @start: ops to start the PCI link
> * @stop: ops to stop the PCI link
--
Damien Le Moal
Western Digital Research
[-- Attachment #2: 0001-PCI-endpoint-Drop-PCI_EPC_IRQ_XXX-definitions.patch --]
[-- Type: text/x-patch, Size: 20610 bytes --]
From e2acf8cc92fc3902b355ba3fe4a8c37c9535c7c8 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <dlemoal@kernel.org>
Date: Wed, 12 Apr 2023 19:50:47 +0900
Subject: [PATCH] PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
linux/pci.h defines the IRQ flags PCI_IRQ_LEGACY, PCI_IRQ_MSI and
PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
definitions provided by enum pci_epc_irq_type.
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++++-----
drivers/pci/controller/dwc/pci-dra7xx.c | 6 +++---
drivers/pci/controller/dwc/pci-imx6.c | 9 ++++-----
drivers/pci/controller/dwc/pci-keystone.c | 9 ++++-----
drivers/pci/controller/dwc/pci-layerscape-ep.c | 8 ++++----
drivers/pci/controller/dwc/pcie-artpec6.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-plat.c | 9 ++++-----
drivers/pci/controller/dwc/pcie-designware.h | 2 +-
drivers/pci/controller/dwc/pcie-keembay.c | 9 ++++-----
drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----
drivers/pci/controller/dwc/pcie-uniphier-ep.c | 7 +++----
drivers/pci/controller/pcie-rcar-ep.c | 7 +++----
drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
drivers/pci/endpoint/functions/pci-epf-mhi.c | 2 +-
drivers/pci/endpoint/functions/pci-epf-ntb.c | 4 ++--
drivers/pci/endpoint/functions/pci-epf-test.c | 6 +++---
drivers/pci/endpoint/functions/pci-epf-vntb.c | 7 ++-----
drivers/pci/endpoint/pci-epc-core.c | 2 +-
include/linux/pci-epc.h | 11 ++---------
21 files changed, 59 insertions(+), 78 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index b8b655d4047e..250ad1330ff3 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -531,25 +531,24 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
}
static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
struct cdns_pcie *pcie = &ep->pcie;
struct device *dev = pcie->dev;
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
if (vfn > 0) {
dev_err(dev, "Cannot raise legacy interrupts for VF\n");
return -EINVAL;
}
return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
default:
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 4ae807e7cf79..1203f76b3604 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -404,16 +404,16 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
}
static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
dra7xx_pcie_raise_legacy_irq(dra7xx);
break;
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
break;
default:
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 27aaa2a6bf39..2975f3faca61 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1057,17 +1057,16 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "UNKNOWN IRQ type\n");
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 78818853af9e..e63ea88051c0 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -901,20 +901,19 @@ static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
}
static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
ks_pcie_am654_raise_legacy_irq(ks_pcie);
break;
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
break;
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
break;
default:
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index de4c1758a6c3..794e0bd199b7 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -150,16 +150,16 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
interrupt_num);
default:
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index 98102079e26d..e84748b82fee 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -352,15 +352,15 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
return -EINVAL;
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "UNKNOWN IRQ type\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index f9182f8d552f..ab87ea3b0986 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -426,7 +426,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
}
static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 1fcfb840f238..9871c49b0383 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -42,17 +42,16 @@ static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "UNKNOWN IRQ type\n");
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 615660640801..e039081eb947 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -320,7 +320,7 @@ struct dw_pcie_rp {
struct dw_pcie_ep_ops {
void (*ep_init)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num);
+ unsigned int type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
/*
* Provide a method to implement the different func config space
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index f90f36bac018..c93fd79d400b 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -284,19 +284,18 @@ static void keembay_pcie_ep_init(struct dw_pcie_ep *ep)
}
static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
/* Legacy interrupts are not supported in Keem Bay */
dev_err(pci->dev, "Legacy IRQ is not supported\n");
return -EINVAL;
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "Unknown IRQ type %d\n", type);
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 0fe7f06f2102..3faabc66f07b 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -655,14 +655,14 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
}
static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
default:
dev_err(pci->dev, "Unknown IRQ type\n");
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index e1db909f53ec..cafcef0da223 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1993,20 +1993,19 @@ static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
}
static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
- case PCI_EPC_IRQ_MSIX:
+ case PCI_IRQ_MSIX:
return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
default:
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 4d0a587c0ba5..43c27138c3c5 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -256,15 +256,14 @@ static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
}
static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return uniphier_pcie_ep_raise_legacy_irq(ep);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
interrupt_num);
default:
diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
index f9682df1da61..2172db2343d9 100644
--- a/drivers/pci/controller/pcie-rcar-ep.c
+++ b/drivers/pci/controller/pcie-rcar-ep.c
@@ -402,16 +402,15 @@ static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
}
static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return rcar_pcie_ep_assert_intx(ep, fn, 0);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
default:
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index 0af0e965fb57..397ad551c912 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -407,15 +407,14 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
}
static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
- enum pci_epc_irq_type type,
- u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
switch (type) {
- case PCI_EPC_IRQ_LEGACY:
+ case PCI_IRQ_LEGACY:
return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
- case PCI_EPC_IRQ_MSI:
+ case PCI_IRQ_MSI:
return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
default:
return -EINVAL;
diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
index ddf0bace4e18..f2fcda1c5d4f 100644
--- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
+++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
@@ -177,7 +177,7 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
* MHI supplies 0 based MSI vectors but the API expects the vector
* number to start from 1, so we need to increment the vector by 1.
*/
- pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
+ pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_IRQ_MSI,
vector + 1);
}
diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
index 9aac2c6f3bb9..fad00b1a8335 100644
--- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
@@ -140,9 +140,9 @@ static struct pci_epf_header epf_ntb_header = {
static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
{
enum pci_epc_interface_type type;
- enum pci_epc_irq_type irq_type;
struct epf_ntb_epc *ntb_epc;
struct epf_ntb_ctrl *ctrl;
+ unsigned int irq_type;
struct pci_epc *epc;
u8 func_no, vfunc_no;
bool is_msix;
@@ -159,7 +159,7 @@ static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
ctrl->link_status |= LINK_STATUS_UP;
else
ctrl->link_status &= ~LINK_STATUS_UP;
- irq_type = is_msix ? PCI_EPC_IRQ_MSIX : PCI_EPC_IRQ_MSI;
+ irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
if (ret) {
dev_err(&epc->dev,
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index fa993e71c224..76ddf4c92511 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -602,7 +602,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
switch (reg->irq_type) {
case IRQ_TYPE_LEGACY:
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
- PCI_EPC_IRQ_LEGACY, 0);
+ PCI_IRQ_LEGACY, 0);
break;
case IRQ_TYPE_MSI:
count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
@@ -612,7 +612,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
return;
}
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
- PCI_EPC_IRQ_MSI, reg->irq_number);
+ PCI_IRQ_MSI, reg->irq_number);
break;
case IRQ_TYPE_MSIX:
count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
@@ -622,7 +622,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
return;
}
pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
- PCI_EPC_IRQ_MSIX, reg->irq_number);
+ PCI_IRQ_MSIX, reg->irq_number);
break;
default:
dev_err(dev, "Failed to raise IRQ, unknown type\n");
diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
index c8b423c3c26e..ba2fe0bb400a 100644
--- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
+++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
@@ -1172,11 +1172,8 @@ static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits)
func_no = ntb->epf->func_no;
vfunc_no = ntb->epf->vfunc_no;
- ret = pci_epc_raise_irq(ntb->epf->epc,
- func_no,
- vfunc_no,
- PCI_EPC_IRQ_MSI,
- interrupt_num + 1);
+ ret = pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no,
+ PCI_IRQ_MSI, interrupt_num + 1);
if (ret)
dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 6c54fa5684d2..835d56922cbb 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -218,7 +218,7 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
* Invoke to raise an legacy, MSI or MSI-X interrupt
*/
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
- enum pci_epc_irq_type type, u16 interrupt_num)
+ unsigned int type, u16 interrupt_num)
{
int ret;
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 5cb694031072..f498f9aa2ab0 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -19,13 +19,6 @@ enum pci_epc_interface_type {
SECONDARY_INTERFACE,
};
-enum pci_epc_irq_type {
- PCI_EPC_IRQ_UNKNOWN,
- PCI_EPC_IRQ_LEGACY,
- PCI_EPC_IRQ_MSI,
- PCI_EPC_IRQ_MSIX,
-};
-
static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)
{
@@ -79,7 +72,7 @@ struct pci_epc_ops {
u16 interrupts, enum pci_barno, u32 offset);
int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
- enum pci_epc_irq_type type, u16 interrupt_num);
+ unsigned int type, u16 interrupt_num);
int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr, u8 interrupt_num,
u32 entry_size, u32 *msi_data,
@@ -229,7 +222,7 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
phys_addr_t phys_addr, u8 interrupt_num,
u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
- enum pci_epc_irq_type type, u16 interrupt_num);
+ unsigned int type, u16 interrupt_num);
int pci_epc_start(struct pci_epc *epc);
void pci_epc_stop(struct pci_epc *epc);
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
--
2.41.0
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-21 8:10 ` Damien Le Moal
@ 2023-07-24 7:32 ` Manivannan Sadhasivam
2023-07-29 1:35 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 7:32 UTC (permalink / raw)
To: Damien Le Moal
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Bjorn Helgaas, Manivannan Sadhasivam,
Jesper Nilsson, Tom Joseph, Vignesh Raghavendra, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Minghuan Lian, Mingkai Hu,
Roy Zang, Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> > Using "INTx" instead of "legacy" is more specific. So, rename
> > PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
> >
> > Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
>
> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
> PCI_IRQ_XXX macros used everywhere. Less definitions :)
>
> See attached patch that I have in my queue (about to send that).
>
It looks better! This patch should be dropped.
- Mani
> > ---
> > This CC-list is for git send-email.
> >
> > Cc: Tom Joseph <tjoseph@cadence.com>
> > Cc: Vignesh Raghavendra <vigneshr@ti.com>
> > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> > Cc: Lucas Stach <l.stach@pengutronix.de>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: NXP Linux Team <linux-imx@nxp.com>
> > Cc: Minghuan Lian <minghuan.Lian@nxp.com>
> > Cc: Mingkai Hu <mingkai.hu@nxp.com>
> > Cc: Roy Zang <roy.zang@nxp.com>
> > Cc: Jingoo Han <jingoohan1@gmail.com>
> > Cc: Srikanth Thokala <srikanth.thokala@intel.com>
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Jonathan Hunter <jonathanh@nvidia.com>
> > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> > Cc: Masami Hiramatsu <mhiramat@kernel.org>
> > Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
> > Cc: Shawn Lin <shawn.lin@rock-chips.com>
> > Cc: Heiko Stuebner <heiko@sntech.de>
> > Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> > ---
> > drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +-
> > drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> > drivers/pci/controller/dwc/pci-imx6.c | 2 +-
> > drivers/pci/controller/dwc/pci-keystone.c | 2 +-
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
> > drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
> > drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
> > drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> > drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
> > drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> > drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
> > drivers/pci/controller/pcie-rcar-ep.c | 2 +-
> > drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> > drivers/pci/endpoint/functions/pci-epf-test.c | 10 +++++-----
> > include/linux/pci-epc.h | 4 ++--
> > 15 files changed, 20 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > index b8b655d4047e..2af8eb4e6d91 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > @@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > struct device *dev = pcie->dev;
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > if (vfn > 0) {
> > dev_err(dev, "Cannot raise legacy interrupts for VF\n");
> > return -EINVAL;
> > diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> > index b445ffe95e3f..8767432dda5c 100644
> > --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> > +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> > @@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > dra7xx_pcie_raise_legacy_irq(dra7xx);
> > break;
> > case PCI_EPC_IRQ_MSI:
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 235ead4c807f..feadc88782a7 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > case PCI_EPC_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> > index 49aea6ce3e87..fce300673ea3 100644
> > --- a/drivers/pci/controller/dwc/pci-keystone.c
> > +++ b/drivers/pci/controller/dwc/pci-keystone.c
> > @@ -907,7 +907,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > ks_pcie_am654_raise_legacy_irq(ks_pcie);
> > break;
> > case PCI_EPC_IRQ_MSI:
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index de4c1758a6c3..b2e14d64dba2 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -155,7 +155,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > case PCI_EPC_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> > index 9b572a2b2c9a..cf92a11ede86 100644
> > --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> > @@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
> > return -EINVAL;
> > case PCI_EPC_IRQ_MSI:
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > index b625841e98aa..f72df38dd523 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > @@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > case PCI_EPC_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> > index 289bff99d762..62903fef343c 100644
> > --- a/drivers/pci/controller/dwc/pcie-keembay.c
> > +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> > @@ -295,7 +295,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > /* Legacy interrupts are not supported in Keem Bay */
> > dev_err(pci->dev, "Legacy IRQ is not supported\n");
> > return -EINVAL;
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > index 267e1247d548..21e2ccc49219 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > @@ -660,7 +660,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > case PCI_EPC_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > index 383ba71d1e8f..85cc64324efd 100644
> > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > @@ -1999,7 +1999,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
> >
> > case PCI_EPC_IRQ_MSI:
> > diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > index cba3c88fcf39..a00301928c38 100644
> > --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > @@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return uniphier_pcie_ep_raise_legacy_irq(ep);
> > case PCI_EPC_IRQ_MSI:
> > return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
> > diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> > index f9682df1da61..fbdf3d85301c 100644
> > --- a/drivers/pci/controller/pcie-rcar-ep.c
> > +++ b/drivers/pci/controller/pcie-rcar-ep.c
> > @@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return rcar_pcie_ep_assert_intx(ep, fn, 0);
> >
> > case PCI_EPC_IRQ_MSI:
> > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> > index 0af0e965fb57..e856a45d0986 100644
> > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > @@ -413,7 +413,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_EPC_IRQ_INTX:
> > return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
> > case PCI_EPC_IRQ_MSI:
> > return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> > index 1f0d2b84296a..caa30596fadd 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> > @@ -19,11 +19,11 @@
> > #include <linux/pci-epf.h>
> > #include <linux/pci_regs.h>
> >
> > -#define IRQ_TYPE_LEGACY 0
> > +#define IRQ_TYPE_INTX 0
> > #define IRQ_TYPE_MSI 1
> > #define IRQ_TYPE_MSIX 2
> >
> > -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
> > +#define COMMAND_RAISE_INTX_IRQ BIT(0)
> > #define COMMAND_RAISE_MSI_IRQ BIT(1)
> > #define COMMAND_RAISE_MSIX_IRQ BIT(2)
> > #define COMMAND_READ BIT(3)
> > @@ -600,9 +600,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> > WRITE_ONCE(reg->status, status);
> >
> > switch (reg->irq_type) {
> > - case IRQ_TYPE_LEGACY:
> > + case IRQ_TYPE_INTX:
> > pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> > - PCI_EPC_IRQ_LEGACY, 0);
> > + PCI_EPC_IRQ_INTX, 0);
> > break;
> > case IRQ_TYPE_MSI:
> > count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
> > @@ -659,7 +659,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
> > }
> >
> > switch (command) {
> > - case COMMAND_RAISE_LEGACY_IRQ:
> > + case COMMAND_RAISE_INTX_IRQ:
> > case COMMAND_RAISE_MSI_IRQ:
> > case COMMAND_RAISE_MSIX_IRQ:
> > pci_epf_test_raise_irq(epf_test, reg);
> > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> > index 5cb694031072..c5ada36b6ca0 100644
> > --- a/include/linux/pci-epc.h
> > +++ b/include/linux/pci-epc.h
> > @@ -21,7 +21,7 @@ enum pci_epc_interface_type {
> >
> > enum pci_epc_irq_type {
> > PCI_EPC_IRQ_UNKNOWN,
> > - PCI_EPC_IRQ_LEGACY,
> > + PCI_EPC_IRQ_INTX,
> > PCI_EPC_IRQ_MSI,
> > PCI_EPC_IRQ_MSIX,
> > };
> > @@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
> > * MSI-X capability register
> > * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
> > * from the MSI-X capability register
> > - * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
> > + * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt
> > * @map_msi_irq: ops to map physical address to MSI address and return MSI data
> > * @start: ops to start the PCI link
> > * @stop: ops to stop the PCI link
>
> --
> Damien Le Moal
> Western Digital Research
> From e2acf8cc92fc3902b355ba3fe4a8c37c9535c7c8 Mon Sep 17 00:00:00 2001
> From: Damien Le Moal <dlemoal@kernel.org>
> Date: Wed, 12 Apr 2023 19:50:47 +0900
> Subject: [PATCH] PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
>
> linux/pci.h defines the IRQ flags PCI_IRQ_LEGACY, PCI_IRQ_MSI and
> PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
> definitions provided by enum pci_epc_irq_type.
>
> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
> ---
> drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++++-----
> drivers/pci/controller/dwc/pci-dra7xx.c | 6 +++---
> drivers/pci/controller/dwc/pci-imx6.c | 9 ++++-----
> drivers/pci/controller/dwc/pci-keystone.c | 9 ++++-----
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 8 ++++----
> drivers/pci/controller/dwc/pcie-artpec6.c | 6 +++---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> drivers/pci/controller/dwc/pcie-designware-plat.c | 9 ++++-----
> drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> drivers/pci/controller/dwc/pcie-keembay.c | 9 ++++-----
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++---
> drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 7 +++----
> drivers/pci/controller/pcie-rcar-ep.c | 7 +++----
> drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
> drivers/pci/endpoint/functions/pci-epf-mhi.c | 2 +-
> drivers/pci/endpoint/functions/pci-epf-ntb.c | 4 ++--
> drivers/pci/endpoint/functions/pci-epf-test.c | 6 +++---
> drivers/pci/endpoint/functions/pci-epf-vntb.c | 7 ++-----
> drivers/pci/endpoint/pci-epc-core.c | 2 +-
> include/linux/pci-epc.h | 11 ++---------
> 21 files changed, 59 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> index b8b655d4047e..250ad1330ff3 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> @@ -531,25 +531,24 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
> }
>
> static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
> struct cdns_pcie *pcie = &ep->pcie;
> struct device *dev = pcie->dev;
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> if (vfn > 0) {
> dev_err(dev, "Cannot raise legacy interrupts for VF\n");
> return -EINVAL;
> }
> return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
>
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
>
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
>
> default:
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index 4ae807e7cf79..1203f76b3604 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -404,16 +404,16 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
> }
>
> static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> dra7xx_pcie_raise_legacy_irq(dra7xx);
> break;
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
> break;
> default:
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 27aaa2a6bf39..2975f3faca61 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1057,17 +1057,16 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
> }
>
> static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> default:
> dev_err(pci->dev, "UNKNOWN IRQ type\n");
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 78818853af9e..e63ea88051c0 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -901,20 +901,19 @@ static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
> }
>
> static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> ks_pcie_am654_raise_legacy_irq(ks_pcie);
> break;
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> break;
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> break;
> default:
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index de4c1758a6c3..794e0bd199b7 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -150,16 +150,16 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
> }
>
> static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
> interrupt_num);
> default:
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index 98102079e26d..e84748b82fee 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -352,15 +352,15 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
> }
>
> static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
> return -EINVAL;
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> default:
> dev_err(pci->dev, "UNKNOWN IRQ type\n");
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index f9182f8d552f..ab87ea3b0986 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -426,7 +426,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> }
>
> static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index 1fcfb840f238..9871c49b0383 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -42,17 +42,16 @@ static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
> }
>
> static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> default:
> dev_err(pci->dev, "UNKNOWN IRQ type\n");
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 615660640801..e039081eb947 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -320,7 +320,7 @@ struct dw_pcie_rp {
> struct dw_pcie_ep_ops {
> void (*ep_init)(struct dw_pcie_ep *ep);
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type, u16 interrupt_num);
> + unsigned int type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> /*
> * Provide a method to implement the different func config space
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index f90f36bac018..c93fd79d400b 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -284,19 +284,18 @@ static void keembay_pcie_ep_init(struct dw_pcie_ep *ep)
> }
>
> static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> /* Legacy interrupts are not supported in Keem Bay */
> dev_err(pci->dev, "Legacy IRQ is not supported\n");
> return -EINVAL;
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> default:
> dev_err(pci->dev, "Unknown IRQ type %d\n", type);
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 0fe7f06f2102..3faabc66f07b 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -655,14 +655,14 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
> }
>
> static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> default:
> dev_err(pci->dev, "Unknown IRQ type\n");
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index e1db909f53ec..cafcef0da223 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1993,20 +1993,19 @@ static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
> }
>
> static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
>
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
>
> - case PCI_EPC_IRQ_MSIX:
> + case PCI_IRQ_MSIX:
> return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
>
> default:
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index 4d0a587c0ba5..43c27138c3c5 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -256,15 +256,14 @@ static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
> }
>
> static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return uniphier_pcie_ep_raise_legacy_irq(ep);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
> interrupt_num);
> default:
> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> index f9682df1da61..2172db2343d9 100644
> --- a/drivers/pci/controller/pcie-rcar-ep.c
> +++ b/drivers/pci/controller/pcie-rcar-ep.c
> @@ -402,16 +402,15 @@ static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
> }
>
> static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return rcar_pcie_ep_assert_intx(ep, fn, 0);
>
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
>
> default:
> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> index 0af0e965fb57..397ad551c912 100644
> --- a/drivers/pci/controller/pcie-rockchip-ep.c
> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> @@ -407,15 +407,14 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
> }
>
> static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> - enum pci_epc_irq_type type,
> - u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
>
> switch (type) {
> - case PCI_EPC_IRQ_LEGACY:
> + case PCI_IRQ_LEGACY:
> return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
> - case PCI_EPC_IRQ_MSI:
> + case PCI_IRQ_MSI:
> return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
> default:
> return -EINVAL;
> diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> index ddf0bace4e18..f2fcda1c5d4f 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> @@ -177,7 +177,7 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
> * MHI supplies 0 based MSI vectors but the API expects the vector
> * number to start from 1, so we need to increment the vector by 1.
> */
> - pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
> + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_IRQ_MSI,
> vector + 1);
> }
>
> diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
> index 9aac2c6f3bb9..fad00b1a8335 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
> @@ -140,9 +140,9 @@ static struct pci_epf_header epf_ntb_header = {
> static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
> {
> enum pci_epc_interface_type type;
> - enum pci_epc_irq_type irq_type;
> struct epf_ntb_epc *ntb_epc;
> struct epf_ntb_ctrl *ctrl;
> + unsigned int irq_type;
> struct pci_epc *epc;
> u8 func_no, vfunc_no;
> bool is_msix;
> @@ -159,7 +159,7 @@ static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
> ctrl->link_status |= LINK_STATUS_UP;
> else
> ctrl->link_status &= ~LINK_STATUS_UP;
> - irq_type = is_msix ? PCI_EPC_IRQ_MSIX : PCI_EPC_IRQ_MSI;
> + irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
> ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
> if (ret) {
> dev_err(&epc->dev,
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> index fa993e71c224..76ddf4c92511 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -602,7 +602,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> switch (reg->irq_type) {
> case IRQ_TYPE_LEGACY:
> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> - PCI_EPC_IRQ_LEGACY, 0);
> + PCI_IRQ_LEGACY, 0);
> break;
> case IRQ_TYPE_MSI:
> count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
> @@ -612,7 +612,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> return;
> }
> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> - PCI_EPC_IRQ_MSI, reg->irq_number);
> + PCI_IRQ_MSI, reg->irq_number);
> break;
> case IRQ_TYPE_MSIX:
> count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
> @@ -622,7 +622,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> return;
> }
> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> - PCI_EPC_IRQ_MSIX, reg->irq_number);
> + PCI_IRQ_MSIX, reg->irq_number);
> break;
> default:
> dev_err(dev, "Failed to raise IRQ, unknown type\n");
> diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
> index c8b423c3c26e..ba2fe0bb400a 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
> @@ -1172,11 +1172,8 @@ static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits)
> func_no = ntb->epf->func_no;
> vfunc_no = ntb->epf->vfunc_no;
>
> - ret = pci_epc_raise_irq(ntb->epf->epc,
> - func_no,
> - vfunc_no,
> - PCI_EPC_IRQ_MSI,
> - interrupt_num + 1);
> + ret = pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no,
> + PCI_IRQ_MSI, interrupt_num + 1);
> if (ret)
> dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
>
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> index 6c54fa5684d2..835d56922cbb 100644
> --- a/drivers/pci/endpoint/pci-epc-core.c
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -218,7 +218,7 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
> * Invoke to raise an legacy, MSI or MSI-X interrupt
> */
> int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> - enum pci_epc_irq_type type, u16 interrupt_num)
> + unsigned int type, u16 interrupt_num)
> {
> int ret;
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index 5cb694031072..f498f9aa2ab0 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -19,13 +19,6 @@ enum pci_epc_interface_type {
> SECONDARY_INTERFACE,
> };
>
> -enum pci_epc_irq_type {
> - PCI_EPC_IRQ_UNKNOWN,
> - PCI_EPC_IRQ_LEGACY,
> - PCI_EPC_IRQ_MSI,
> - PCI_EPC_IRQ_MSIX,
> -};
> -
> static inline const char *
> pci_epc_interface_string(enum pci_epc_interface_type type)
> {
> @@ -79,7 +72,7 @@ struct pci_epc_ops {
> u16 interrupts, enum pci_barno, u32 offset);
> int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
> int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> - enum pci_epc_irq_type type, u16 interrupt_num);
> + unsigned int type, u16 interrupt_num);
> int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> phys_addr_t phys_addr, u8 interrupt_num,
> u32 entry_size, u32 *msi_data,
> @@ -229,7 +222,7 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> phys_addr_t phys_addr, u8 interrupt_num,
> u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
> int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> - enum pci_epc_irq_type type, u16 interrupt_num);
> + unsigned int type, u16 interrupt_num);
> int pci_epc_start(struct pci_epc *epc);
> void pci_epc_stop(struct pci_epc *epc);
> const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
> --
> 2.41.0
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-24 7:32 ` Manivannan Sadhasivam
@ 2023-07-29 1:35 ` Serge Semin
2023-07-29 1:55 ` Damien Le Moal
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-29 1:35 UTC (permalink / raw)
To: Manivannan Sadhasivam, Damien Le Moal, Bjorn Helgaas
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Manivannan Sadhasivam, Jesper Nilsson, Tom Joseph,
Vignesh Raghavendra, Richard Zhu, Lucas Stach, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Minghuan Lian, Mingkai Hu, Roy Zang,
Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
> > On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> > > Using "INTx" instead of "legacy" is more specific. So, rename
> > > PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
> > >
> > > Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > > Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> >
> > I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
> > PCI_IRQ_XXX macros used everywhere. Less definitions :)
> >
> > See attached patch that I have in my queue (about to send that).
> >
>
> It looks better! This patch should be dropped.
Back then Bjorn specifically asked to change the names suffix in a
preparation patch before adding the INTx support to the DW PCIe core
driver (see the Sb tag in the patch log). Damien, seeing you cleanup
the names anyway what about fixing the macro suffix too: INTx instead
of LEGACY)?
Mani, Damien, what do you suggest to Yoshihiro to do with the
LEGACY/INTx names in the following up patches of this series?
-Serge(y)
>
> - Mani
>
> > > ---
> > > This CC-list is for git send-email.
> > >
> > > Cc: Tom Joseph <tjoseph@cadence.com>
> > > Cc: Vignesh Raghavendra <vigneshr@ti.com>
> > > Cc: Richard Zhu <hongxing.zhu@nxp.com>
> > > Cc: Lucas Stach <l.stach@pengutronix.de>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <s.hauer@pengutronix.de>
> > > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <festevam@gmail.com>
> > > Cc: NXP Linux Team <linux-imx@nxp.com>
> > > Cc: Minghuan Lian <minghuan.Lian@nxp.com>
> > > Cc: Mingkai Hu <mingkai.hu@nxp.com>
> > > Cc: Roy Zang <roy.zang@nxp.com>
> > > Cc: Jingoo Han <jingoohan1@gmail.com>
> > > Cc: Srikanth Thokala <srikanth.thokala@intel.com>
> > > Cc: Thierry Reding <thierry.reding@gmail.com>
> > > Cc: Jonathan Hunter <jonathanh@nvidia.com>
> > > Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> > > Cc: Masami Hiramatsu <mhiramat@kernel.org>
> > > Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
> > > Cc: Shawn Lin <shawn.lin@rock-chips.com>
> > > Cc: Heiko Stuebner <heiko@sntech.de>
> > > Cc: Kishon Vijay Abraham I <kishon@kernel.org>
> > > ---
> > > drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +-
> > > drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> > > drivers/pci/controller/dwc/pci-imx6.c | 2 +-
> > > drivers/pci/controller/dwc/pci-keystone.c | 2 +-
> > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
> > > drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
> > > drivers/pci/controller/pcie-rcar-ep.c | 2 +-
> > > drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> > > drivers/pci/endpoint/functions/pci-epf-test.c | 10 +++++-----
> > > include/linux/pci-epc.h | 4 ++--
> > > 15 files changed, 20 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > > index b8b655d4047e..2af8eb4e6d91 100644
> > > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > > @@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > > struct device *dev = pcie->dev;
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > if (vfn > 0) {
> > > dev_err(dev, "Cannot raise legacy interrupts for VF\n");
> > > return -EINVAL;
> > > diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> > > index b445ffe95e3f..8767432dda5c 100644
> > > --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> > > +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> > > @@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > dra7xx_pcie_raise_legacy_irq(dra7xx);
> > > break;
> > > case PCI_EPC_IRQ_MSI:
> > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > > index 235ead4c807f..feadc88782a7 100644
> > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > @@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > > case PCI_EPC_IRQ_MSI:
> > > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> > > index 49aea6ce3e87..fce300673ea3 100644
> > > --- a/drivers/pci/controller/dwc/pci-keystone.c
> > > +++ b/drivers/pci/controller/dwc/pci-keystone.c
> > > @@ -907,7 +907,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > ks_pcie_am654_raise_legacy_irq(ks_pcie);
> > > break;
> > > case PCI_EPC_IRQ_MSI:
> > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > index de4c1758a6c3..b2e14d64dba2 100644
> > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > @@ -155,7 +155,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > > case PCI_EPC_IRQ_MSI:
> > > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> > > index 9b572a2b2c9a..cf92a11ede86 100644
> > > --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> > > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> > > @@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
> > > return -EINVAL;
> > > case PCI_EPC_IRQ_MSI:
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > > index b625841e98aa..f72df38dd523 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > > @@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > > case PCI_EPC_IRQ_MSI:
> > > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > > diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> > > index 289bff99d762..62903fef343c 100644
> > > --- a/drivers/pci/controller/dwc/pcie-keembay.c
> > > +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> > > @@ -295,7 +295,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > /* Legacy interrupts are not supported in Keem Bay */
> > > dev_err(pci->dev, "Legacy IRQ is not supported\n");
> > > return -EINVAL;
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > index 267e1247d548..21e2ccc49219 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > > @@ -660,7 +660,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > > case PCI_EPC_IRQ_MSI:
> > > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > index 383ba71d1e8f..85cc64324efd 100644
> > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > @@ -1999,7 +1999,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
> > >
> > > case PCI_EPC_IRQ_MSI:
> > > diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > > index cba3c88fcf39..a00301928c38 100644
> > > --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > > @@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return uniphier_pcie_ep_raise_legacy_irq(ep);
> > > case PCI_EPC_IRQ_MSI:
> > > return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
> > > diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> > > index f9682df1da61..fbdf3d85301c 100644
> > > --- a/drivers/pci/controller/pcie-rcar-ep.c
> > > +++ b/drivers/pci/controller/pcie-rcar-ep.c
> > > @@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > > struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return rcar_pcie_ep_assert_intx(ep, fn, 0);
> > >
> > > case PCI_EPC_IRQ_MSI:
> > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> > > index 0af0e965fb57..e856a45d0986 100644
> > > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > > @@ -413,7 +413,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
> > >
> > > switch (type) {
> > > - case PCI_EPC_IRQ_LEGACY:
> > > + case PCI_EPC_IRQ_INTX:
> > > return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
> > > case PCI_EPC_IRQ_MSI:
> > > return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
> > > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> > > index 1f0d2b84296a..caa30596fadd 100644
> > > --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> > > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> > > @@ -19,11 +19,11 @@
> > > #include <linux/pci-epf.h>
> > > #include <linux/pci_regs.h>
> > >
> > > -#define IRQ_TYPE_LEGACY 0
> > > +#define IRQ_TYPE_INTX 0
> > > #define IRQ_TYPE_MSI 1
> > > #define IRQ_TYPE_MSIX 2
> > >
> > > -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
> > > +#define COMMAND_RAISE_INTX_IRQ BIT(0)
> > > #define COMMAND_RAISE_MSI_IRQ BIT(1)
> > > #define COMMAND_RAISE_MSIX_IRQ BIT(2)
> > > #define COMMAND_READ BIT(3)
> > > @@ -600,9 +600,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> > > WRITE_ONCE(reg->status, status);
> > >
> > > switch (reg->irq_type) {
> > > - case IRQ_TYPE_LEGACY:
> > > + case IRQ_TYPE_INTX:
> > > pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> > > - PCI_EPC_IRQ_LEGACY, 0);
> > > + PCI_EPC_IRQ_INTX, 0);
> > > break;
> > > case IRQ_TYPE_MSI:
> > > count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
> > > @@ -659,7 +659,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
> > > }
> > >
> > > switch (command) {
> > > - case COMMAND_RAISE_LEGACY_IRQ:
> > > + case COMMAND_RAISE_INTX_IRQ:
> > > case COMMAND_RAISE_MSI_IRQ:
> > > case COMMAND_RAISE_MSIX_IRQ:
> > > pci_epf_test_raise_irq(epf_test, reg);
> > > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> > > index 5cb694031072..c5ada36b6ca0 100644
> > > --- a/include/linux/pci-epc.h
> > > +++ b/include/linux/pci-epc.h
> > > @@ -21,7 +21,7 @@ enum pci_epc_interface_type {
> > >
> > > enum pci_epc_irq_type {
> > > PCI_EPC_IRQ_UNKNOWN,
> > > - PCI_EPC_IRQ_LEGACY,
> > > + PCI_EPC_IRQ_INTX,
> > > PCI_EPC_IRQ_MSI,
> > > PCI_EPC_IRQ_MSIX,
> > > };
> > > @@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
> > > * MSI-X capability register
> > > * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
> > > * from the MSI-X capability register
> > > - * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
> > > + * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt
> > > * @map_msi_irq: ops to map physical address to MSI address and return MSI data
> > > * @start: ops to start the PCI link
> > > * @stop: ops to stop the PCI link
> >
> > --
> > Damien Le Moal
> > Western Digital Research
>
> > From e2acf8cc92fc3902b355ba3fe4a8c37c9535c7c8 Mon Sep 17 00:00:00 2001
> > From: Damien Le Moal <dlemoal@kernel.org>
> > Date: Wed, 12 Apr 2023 19:50:47 +0900
> > Subject: [PATCH] PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
> >
> > linux/pci.h defines the IRQ flags PCI_IRQ_LEGACY, PCI_IRQ_MSI and
> > PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
> > definitions provided by enum pci_epc_irq_type.
> >
> > Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
> > ---
> > drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++++-----
> > drivers/pci/controller/dwc/pci-dra7xx.c | 6 +++---
> > drivers/pci/controller/dwc/pci-imx6.c | 9 ++++-----
> > drivers/pci/controller/dwc/pci-keystone.c | 9 ++++-----
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 8 ++++----
> > drivers/pci/controller/dwc/pcie-artpec6.c | 6 +++---
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> > drivers/pci/controller/dwc/pcie-designware-plat.c | 9 ++++-----
> > drivers/pci/controller/dwc/pcie-designware.h | 2 +-
> > drivers/pci/controller/dwc/pcie-keembay.c | 9 ++++-----
> > drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++---
> > drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----
> > drivers/pci/controller/dwc/pcie-uniphier-ep.c | 7 +++----
> > drivers/pci/controller/pcie-rcar-ep.c | 7 +++----
> > drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
> > drivers/pci/endpoint/functions/pci-epf-mhi.c | 2 +-
> > drivers/pci/endpoint/functions/pci-epf-ntb.c | 4 ++--
> > drivers/pci/endpoint/functions/pci-epf-test.c | 6 +++---
> > drivers/pci/endpoint/functions/pci-epf-vntb.c | 7 ++-----
> > drivers/pci/endpoint/pci-epc-core.c | 2 +-
> > include/linux/pci-epc.h | 11 ++---------
> > 21 files changed, 59 insertions(+), 78 deletions(-)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > index b8b655d4047e..250ad1330ff3 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
> > @@ -531,25 +531,24 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
> > }
> >
> > static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
> > struct cdns_pcie *pcie = &ep->pcie;
> > struct device *dev = pcie->dev;
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > if (vfn > 0) {
> > dev_err(dev, "Cannot raise legacy interrupts for VF\n");
> > return -EINVAL;
> > }
> > return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
> >
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
> >
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
> >
> > default:
> > diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> > index 4ae807e7cf79..1203f76b3604 100644
> > --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> > +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> > @@ -404,16 +404,16 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
> > }
> >
> > static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > dra7xx_pcie_raise_legacy_irq(dra7xx);
> > break;
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
> > break;
> > default:
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> > index 27aaa2a6bf39..2975f3faca61 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -1057,17 +1057,16 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
> > }
> >
> > static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > default:
> > dev_err(pci->dev, "UNKNOWN IRQ type\n");
> > diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> > index 78818853af9e..e63ea88051c0 100644
> > --- a/drivers/pci/controller/dwc/pci-keystone.c
> > +++ b/drivers/pci/controller/dwc/pci-keystone.c
> > @@ -901,20 +901,19 @@ static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
> > }
> >
> > static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > ks_pcie_am654_raise_legacy_irq(ks_pcie);
> > break;
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > break;
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > break;
> > default:
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > index de4c1758a6c3..794e0bd199b7 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -150,16 +150,16 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
> > }
> >
> > static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
> > interrupt_num);
> > default:
> > diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> > index 98102079e26d..e84748b82fee 100644
> > --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> > +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> > @@ -352,15 +352,15 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
> > }
> >
> > static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
> > return -EINVAL;
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > default:
> > dev_err(pci->dev, "UNKNOWN IRQ type\n");
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index f9182f8d552f..ab87ea3b0986 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -426,7 +426,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > }
> >
> > static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > index 1fcfb840f238..9871c49b0383 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> > @@ -42,17 +42,16 @@ static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
> > }
> >
> > static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > default:
> > dev_err(pci->dev, "UNKNOWN IRQ type\n");
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 615660640801..e039081eb947 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -320,7 +320,7 @@ struct dw_pcie_rp {
> > struct dw_pcie_ep_ops {
> > void (*ep_init)(struct dw_pcie_ep *ep);
> > int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num);
> > + unsigned int type, u16 interrupt_num);
> > const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> > /*
> > * Provide a method to implement the different func config space
> > diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> > index f90f36bac018..c93fd79d400b 100644
> > --- a/drivers/pci/controller/dwc/pcie-keembay.c
> > +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> > @@ -284,19 +284,18 @@ static void keembay_pcie_ep_init(struct dw_pcie_ep *ep)
> > }
> >
> > static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > /* Legacy interrupts are not supported in Keem Bay */
> > dev_err(pci->dev, "Legacy IRQ is not supported\n");
> > return -EINVAL;
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > default:
> > dev_err(pci->dev, "Unknown IRQ type %d\n", type);
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > index 0fe7f06f2102..3faabc66f07b 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> > @@ -655,14 +655,14 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
> > }
> >
> > static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > default:
> > dev_err(pci->dev, "Unknown IRQ type\n");
> > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > index e1db909f53ec..cafcef0da223 100644
> > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > @@ -1993,20 +1993,19 @@ static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
> > }
> >
> > static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
> >
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
> >
> > - case PCI_EPC_IRQ_MSIX:
> > + case PCI_IRQ_MSIX:
> > return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
> >
> > default:
> > diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > index 4d0a587c0ba5..43c27138c3c5 100644
> > --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> > @@ -256,15 +256,14 @@ static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
> > }
> >
> > static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return uniphier_pcie_ep_raise_legacy_irq(ep);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
> > interrupt_num);
> > default:
> > diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> > index f9682df1da61..2172db2343d9 100644
> > --- a/drivers/pci/controller/pcie-rcar-ep.c
> > +++ b/drivers/pci/controller/pcie-rcar-ep.c
> > @@ -402,16 +402,15 @@ static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
> > }
> >
> > static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return rcar_pcie_ep_assert_intx(ep, fn, 0);
> >
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
> >
> > default:
> > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
> > index 0af0e965fb57..397ad551c912 100644
> > --- a/drivers/pci/controller/pcie-rockchip-ep.c
> > +++ b/drivers/pci/controller/pcie-rockchip-ep.c
> > @@ -407,15 +407,14 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
> > }
> >
> > static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
> > - enum pci_epc_irq_type type,
> > - u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
> >
> > switch (type) {
> > - case PCI_EPC_IRQ_LEGACY:
> > + case PCI_IRQ_LEGACY:
> > return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
> > - case PCI_EPC_IRQ_MSI:
> > + case PCI_IRQ_MSI:
> > return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
> > default:
> > return -EINVAL;
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> > index ddf0bace4e18..f2fcda1c5d4f 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
> > @@ -177,7 +177,7 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
> > * MHI supplies 0 based MSI vectors but the API expects the vector
> > * number to start from 1, so we need to increment the vector by 1.
> > */
> > - pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
> > + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_IRQ_MSI,
> > vector + 1);
> > }
> >
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
> > index 9aac2c6f3bb9..fad00b1a8335 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
> > @@ -140,9 +140,9 @@ static struct pci_epf_header epf_ntb_header = {
> > static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
> > {
> > enum pci_epc_interface_type type;
> > - enum pci_epc_irq_type irq_type;
> > struct epf_ntb_epc *ntb_epc;
> > struct epf_ntb_ctrl *ctrl;
> > + unsigned int irq_type;
> > struct pci_epc *epc;
> > u8 func_no, vfunc_no;
> > bool is_msix;
> > @@ -159,7 +159,7 @@ static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
> > ctrl->link_status |= LINK_STATUS_UP;
> > else
> > ctrl->link_status &= ~LINK_STATUS_UP;
> > - irq_type = is_msix ? PCI_EPC_IRQ_MSIX : PCI_EPC_IRQ_MSI;
> > + irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
> > ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
> > if (ret) {
> > dev_err(&epc->dev,
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> > index fa993e71c224..76ddf4c92511 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> > @@ -602,7 +602,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> > switch (reg->irq_type) {
> > case IRQ_TYPE_LEGACY:
> > pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> > - PCI_EPC_IRQ_LEGACY, 0);
> > + PCI_IRQ_LEGACY, 0);
> > break;
> > case IRQ_TYPE_MSI:
> > count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
> > @@ -612,7 +612,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> > return;
> > }
> > pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> > - PCI_EPC_IRQ_MSI, reg->irq_number);
> > + PCI_IRQ_MSI, reg->irq_number);
> > break;
> > case IRQ_TYPE_MSIX:
> > count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
> > @@ -622,7 +622,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
> > return;
> > }
> > pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
> > - PCI_EPC_IRQ_MSIX, reg->irq_number);
> > + PCI_IRQ_MSIX, reg->irq_number);
> > break;
> > default:
> > dev_err(dev, "Failed to raise IRQ, unknown type\n");
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
> > index c8b423c3c26e..ba2fe0bb400a 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
> > @@ -1172,11 +1172,8 @@ static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits)
> > func_no = ntb->epf->func_no;
> > vfunc_no = ntb->epf->vfunc_no;
> >
> > - ret = pci_epc_raise_irq(ntb->epf->epc,
> > - func_no,
> > - vfunc_no,
> > - PCI_EPC_IRQ_MSI,
> > - interrupt_num + 1);
> > + ret = pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no,
> > + PCI_IRQ_MSI, interrupt_num + 1);
> > if (ret)
> > dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
> >
> > diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> > index 6c54fa5684d2..835d56922cbb 100644
> > --- a/drivers/pci/endpoint/pci-epc-core.c
> > +++ b/drivers/pci/endpoint/pci-epc-core.c
> > @@ -218,7 +218,7 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
> > * Invoke to raise an legacy, MSI or MSI-X interrupt
> > */
> > int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num)
> > + unsigned int type, u16 interrupt_num)
> > {
> > int ret;
> >
> > diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> > index 5cb694031072..f498f9aa2ab0 100644
> > --- a/include/linux/pci-epc.h
> > +++ b/include/linux/pci-epc.h
> > @@ -19,13 +19,6 @@ enum pci_epc_interface_type {
> > SECONDARY_INTERFACE,
> > };
> >
> > -enum pci_epc_irq_type {
> > - PCI_EPC_IRQ_UNKNOWN,
> > - PCI_EPC_IRQ_LEGACY,
> > - PCI_EPC_IRQ_MSI,
> > - PCI_EPC_IRQ_MSIX,
> > -};
> > -
> > static inline const char *
> > pci_epc_interface_string(enum pci_epc_interface_type type)
> > {
> > @@ -79,7 +72,7 @@ struct pci_epc_ops {
> > u16 interrupts, enum pci_barno, u32 offset);
> > int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
> > int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num);
> > + unsigned int type, u16 interrupt_num);
> > int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > phys_addr_t phys_addr, u8 interrupt_num,
> > u32 entry_size, u32 *msi_data,
> > @@ -229,7 +222,7 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > phys_addr_t phys_addr, u8 interrupt_num,
> > u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
> > int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > - enum pci_epc_irq_type type, u16 interrupt_num);
> > + unsigned int type, u16 interrupt_num);
> > int pci_epc_start(struct pci_epc *epc);
> > void pci_epc_stop(struct pci_epc *epc);
> > const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
> > --
> > 2.41.0
> >
>
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-29 1:35 ` Serge Semin
@ 2023-07-29 1:55 ` Damien Le Moal
2023-07-29 1:58 ` Damien Le Moal
0 siblings, 1 reply; 90+ messages in thread
From: Damien Le Moal @ 2023-07-29 1:55 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Manivannan Sadhasivam, Jesper Nilsson, Tom Joseph,
Vignesh Raghavendra, Richard Zhu, Lucas Stach, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Minghuan Lian, Mingkai Hu, Roy Zang,
Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On 7/29/23 10:35, Serge Semin wrote:
> On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
>> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
>>> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
>>>> Using "INTx" instead of "legacy" is more specific. So, rename
>>>> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
>>>>
>>>> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
>>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>>>> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
>>>> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
>>>
>
>>> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
>>> PCI_IRQ_XXX macros used everywhere. Less definitions :)
>>>
>>> See attached patch that I have in my queue (about to send that).
>>>
>>
>> It looks better! This patch should be dropped.
>
> Back then Bjorn specifically asked to change the names suffix in a
> preparation patch before adding the INTx support to the DW PCIe core
> driver (see the Sb tag in the patch log). Damien, seeing you cleanup
> the names anyway what about fixing the macro suffix too: INTx instead
> of LEGACY)?
Sure, I can do that. That is going to be a gigantic patch though given that
PCI_IRQ_LEGACY is used well beyond the ep/pcie controller drivers.
While I agree it would be nice to do, not sure it is worth such code churn.
> Mani, Damien, what do you suggest to Yoshihiro to do with the
> LEGACY/INTx names in the following up patches of this series?
If everyone is OK with the patch I proposed (the PCI_IRQ_LEGACY -> PCI_IRQ_INTx
change can go on top), then I can rebase it and send it next week (the remaining
of my EP cleanup series needs some more testing & rebasing). Yoshihiro can
either include it in his series or rebase on it if the patch is added to
pci-next quickly.
>
> -Serge(y)
>
>>
>> - Mani
>>
>>>> ---
>>>> This CC-list is for git send-email.
>>>>
>>>> Cc: Tom Joseph <tjoseph@cadence.com>
>>>> Cc: Vignesh Raghavendra <vigneshr@ti.com>
>>>> Cc: Richard Zhu <hongxing.zhu@nxp.com>
>>>> Cc: Lucas Stach <l.stach@pengutronix.de>
>>>> Cc: Shawn Guo <shawnguo@kernel.org>
>>>> Cc: Sascha Hauer <s.hauer@pengutronix.de>
>>>> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>>>> Cc: Fabio Estevam <festevam@gmail.com>
>>>> Cc: NXP Linux Team <linux-imx@nxp.com>
>>>> Cc: Minghuan Lian <minghuan.Lian@nxp.com>
>>>> Cc: Mingkai Hu <mingkai.hu@nxp.com>
>>>> Cc: Roy Zang <roy.zang@nxp.com>
>>>> Cc: Jingoo Han <jingoohan1@gmail.com>
>>>> Cc: Srikanth Thokala <srikanth.thokala@intel.com>
>>>> Cc: Thierry Reding <thierry.reding@gmail.com>
>>>> Cc: Jonathan Hunter <jonathanh@nvidia.com>
>>>> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
>>>> Cc: Masami Hiramatsu <mhiramat@kernel.org>
>>>> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
>>>> Cc: Shawn Lin <shawn.lin@rock-chips.com>
>>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>>> Cc: Kishon Vijay Abraham I <kishon@kernel.org>
>>>> ---
>>>> drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +-
>>>> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
>>>> drivers/pci/controller/dwc/pci-imx6.c | 2 +-
>>>> drivers/pci/controller/dwc/pci-keystone.c | 2 +-
>>>> drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
>>>> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
>>>> drivers/pci/controller/pcie-rcar-ep.c | 2 +-
>>>> drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
>>>> drivers/pci/endpoint/functions/pci-epf-test.c | 10 +++++-----
>>>> include/linux/pci-epc.h | 4 ++--
>>>> 15 files changed, 20 insertions(+), 20 deletions(-)
>>>>
>>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>>> index b8b655d4047e..2af8eb4e6d91 100644
>>>> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>>> @@ -539,7 +539,7 @@ static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>>> struct device *dev = pcie->dev;
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> if (vfn > 0) {
>>>> dev_err(dev, "Cannot raise legacy interrupts for VF\n");
>>>> return -EINVAL;
>>>> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
>>>> index b445ffe95e3f..8767432dda5c 100644
>>>> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
>>>> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
>>>> @@ -410,7 +410,7 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> dra7xx_pcie_raise_legacy_irq(dra7xx);
>>>> break;
>>>> case PCI_EPC_IRQ_MSI:
>>>> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
>>>> index 235ead4c807f..feadc88782a7 100644
>>>> --- a/drivers/pci/controller/dwc/pci-imx6.c
>>>> +++ b/drivers/pci/controller/dwc/pci-imx6.c
>>>> @@ -1063,7 +1063,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>>> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
>>>> index 49aea6ce3e87..fce300673ea3 100644
>>>> --- a/drivers/pci/controller/dwc/pci-keystone.c
>>>> +++ b/drivers/pci/controller/dwc/pci-keystone.c
>>>> @@ -907,7 +907,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> ks_pcie_am654_raise_legacy_irq(ks_pcie);
>>>> break;
>>>> case PCI_EPC_IRQ_MSI:
>>>> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> index de4c1758a6c3..b2e14d64dba2 100644
>>>> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>>> @@ -155,7 +155,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>>> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
>>>> index 9b572a2b2c9a..cf92a11ede86 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
>>>> @@ -357,7 +357,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
>>>> return -EINVAL;
>>>> case PCI_EPC_IRQ_MSI:
>>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
>>>> index b625841e98aa..f72df38dd523 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
>>>> @@ -48,7 +48,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>>> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
>>>> index 289bff99d762..62903fef343c 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-keembay.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
>>>> @@ -295,7 +295,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> /* Legacy interrupts are not supported in Keem Bay */
>>>> dev_err(pci->dev, "Legacy IRQ is not supported\n");
>>>> return -EINVAL;
>>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>>> index 267e1247d548..21e2ccc49219 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>>> @@ -660,7 +660,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>>>> index 383ba71d1e8f..85cc64324efd 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>>>> @@ -1999,7 +1999,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
>>>>
>>>> case PCI_EPC_IRQ_MSI:
>>>> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>>> index cba3c88fcf39..a00301928c38 100644
>>>> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>>> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>>> @@ -262,7 +262,7 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return uniphier_pcie_ep_raise_legacy_irq(ep);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
>>>> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
>>>> index f9682df1da61..fbdf3d85301c 100644
>>>> --- a/drivers/pci/controller/pcie-rcar-ep.c
>>>> +++ b/drivers/pci/controller/pcie-rcar-ep.c
>>>> @@ -408,7 +408,7 @@ static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>>> struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return rcar_pcie_ep_assert_intx(ep, fn, 0);
>>>>
>>>> case PCI_EPC_IRQ_MSI:
>>>> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
>>>> index 0af0e965fb57..e856a45d0986 100644
>>>> --- a/drivers/pci/controller/pcie-rockchip-ep.c
>>>> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
>>>> @@ -413,7 +413,7 @@ static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>>> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
>>>>
>>>> switch (type) {
>>>> - case PCI_EPC_IRQ_LEGACY:
>>>> + case PCI_EPC_IRQ_INTX:
>>>> return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
>>>> case PCI_EPC_IRQ_MSI:
>>>> return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
>>>> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
>>>> index 1f0d2b84296a..caa30596fadd 100644
>>>> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
>>>> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
>>>> @@ -19,11 +19,11 @@
>>>> #include <linux/pci-epf.h>
>>>> #include <linux/pci_regs.h>
>>>>
>>>> -#define IRQ_TYPE_LEGACY 0
>>>> +#define IRQ_TYPE_INTX 0
>>>> #define IRQ_TYPE_MSI 1
>>>> #define IRQ_TYPE_MSIX 2
>>>>
>>>> -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
>>>> +#define COMMAND_RAISE_INTX_IRQ BIT(0)
>>>> #define COMMAND_RAISE_MSI_IRQ BIT(1)
>>>> #define COMMAND_RAISE_MSIX_IRQ BIT(2)
>>>> #define COMMAND_READ BIT(3)
>>>> @@ -600,9 +600,9 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
>>>> WRITE_ONCE(reg->status, status);
>>>>
>>>> switch (reg->irq_type) {
>>>> - case IRQ_TYPE_LEGACY:
>>>> + case IRQ_TYPE_INTX:
>>>> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
>>>> - PCI_EPC_IRQ_LEGACY, 0);
>>>> + PCI_EPC_IRQ_INTX, 0);
>>>> break;
>>>> case IRQ_TYPE_MSI:
>>>> count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
>>>> @@ -659,7 +659,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
>>>> }
>>>>
>>>> switch (command) {
>>>> - case COMMAND_RAISE_LEGACY_IRQ:
>>>> + case COMMAND_RAISE_INTX_IRQ:
>>>> case COMMAND_RAISE_MSI_IRQ:
>>>> case COMMAND_RAISE_MSIX_IRQ:
>>>> pci_epf_test_raise_irq(epf_test, reg);
>>>> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
>>>> index 5cb694031072..c5ada36b6ca0 100644
>>>> --- a/include/linux/pci-epc.h
>>>> +++ b/include/linux/pci-epc.h
>>>> @@ -21,7 +21,7 @@ enum pci_epc_interface_type {
>>>>
>>>> enum pci_epc_irq_type {
>>>> PCI_EPC_IRQ_UNKNOWN,
>>>> - PCI_EPC_IRQ_LEGACY,
>>>> + PCI_EPC_IRQ_INTX,
>>>> PCI_EPC_IRQ_MSI,
>>>> PCI_EPC_IRQ_MSIX,
>>>> };
>>>> @@ -54,7 +54,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type)
>>>> * MSI-X capability register
>>>> * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
>>>> * from the MSI-X capability register
>>>> - * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
>>>> + * @raise_irq: ops to raise an INTx, MSI or MSI-X interrupt
>>>> * @map_msi_irq: ops to map physical address to MSI address and return MSI data
>>>> * @start: ops to start the PCI link
>>>> * @stop: ops to stop the PCI link
>>>
>>> --
>>> Damien Le Moal
>>> Western Digital Research
>>
>>> From e2acf8cc92fc3902b355ba3fe4a8c37c9535c7c8 Mon Sep 17 00:00:00 2001
>>> From: Damien Le Moal <dlemoal@kernel.org>
>>> Date: Wed, 12 Apr 2023 19:50:47 +0900
>>> Subject: [PATCH] PCI: endpoint: Drop PCI_EPC_IRQ_XXX definitions
>>>
>>> linux/pci.h defines the IRQ flags PCI_IRQ_LEGACY, PCI_IRQ_MSI and
>>> PCI_IRQ_MSIX. Let's use these flags directly instead of the endpoint
>>> definitions provided by enum pci_epc_irq_type.
>>>
>>> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
>>> ---
>>> drivers/pci/controller/cadence/pcie-cadence-ep.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pci-dra7xx.c | 6 +++---
>>> drivers/pci/controller/dwc/pci-imx6.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pci-keystone.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pci-layerscape-ep.c | 8 ++++----
>>> drivers/pci/controller/dwc/pcie-artpec6.c | 6 +++---
>>> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
>>> drivers/pci/controller/dwc/pcie-designware-plat.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pcie-designware.h | 2 +-
>>> drivers/pci/controller/dwc/pcie-keembay.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +++---
>>> drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----
>>> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 7 +++----
>>> drivers/pci/controller/pcie-rcar-ep.c | 7 +++----
>>> drivers/pci/controller/pcie-rockchip-ep.c | 7 +++----
>>> drivers/pci/endpoint/functions/pci-epf-mhi.c | 2 +-
>>> drivers/pci/endpoint/functions/pci-epf-ntb.c | 4 ++--
>>> drivers/pci/endpoint/functions/pci-epf-test.c | 6 +++---
>>> drivers/pci/endpoint/functions/pci-epf-vntb.c | 7 ++-----
>>> drivers/pci/endpoint/pci-epc-core.c | 2 +-
>>> include/linux/pci-epc.h | 11 ++---------
>>> 21 files changed, 59 insertions(+), 78 deletions(-)
>>>
>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>> index b8b655d4047e..250ad1330ff3 100644
>>> --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
>>> @@ -531,25 +531,24 @@ static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn,
>>> }
>>>
>>> static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
>>> struct cdns_pcie *pcie = &ep->pcie;
>>> struct device *dev = pcie->dev;
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> if (vfn > 0) {
>>> dev_err(dev, "Cannot raise legacy interrupts for VF\n");
>>> return -EINVAL;
>>> }
>>> return cdns_pcie_ep_send_legacy_irq(ep, fn, vfn, 0);
>>>
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return cdns_pcie_ep_send_msi_irq(ep, fn, vfn, interrupt_num);
>>>
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return cdns_pcie_ep_send_msix_irq(ep, fn, vfn, interrupt_num);
>>>
>>> default:
>>> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
>>> index 4ae807e7cf79..1203f76b3604 100644
>>> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
>>> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
>>> @@ -404,16 +404,16 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
>>> }
>>>
>>> static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>> struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> dra7xx_pcie_raise_legacy_irq(dra7xx);
>>> break;
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
>>> break;
>>> default:
>>> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
>>> index 27aaa2a6bf39..2975f3faca61 100644
>>> --- a/drivers/pci/controller/dwc/pci-imx6.c
>>> +++ b/drivers/pci/controller/dwc/pci-imx6.c
>>> @@ -1057,17 +1057,16 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
>>> }
>>>
>>> static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
>>> default:
>>> dev_err(pci->dev, "UNKNOWN IRQ type\n");
>>> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
>>> index 78818853af9e..e63ea88051c0 100644
>>> --- a/drivers/pci/controller/dwc/pci-keystone.c
>>> +++ b/drivers/pci/controller/dwc/pci-keystone.c
>>> @@ -901,20 +901,19 @@ static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie)
>>> }
>>>
>>> static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>> struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> ks_pcie_am654_raise_legacy_irq(ks_pcie);
>>> break;
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> break;
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
>>> break;
>>> default:
>>> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>> index de4c1758a6c3..794e0bd199b7 100644
>>> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
>>> @@ -150,16 +150,16 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
>>> }
>>>
>>> static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
>>> interrupt_num);
>>> default:
>>> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
>>> index 98102079e26d..e84748b82fee 100644
>>> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
>>> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
>>> @@ -352,15 +352,15 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
>>> }
>>>
>>> static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
>>> return -EINVAL;
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> default:
>>> dev_err(pci->dev, "UNKNOWN IRQ type\n");
>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
>>> index f9182f8d552f..ab87ea3b0986 100644
>>> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
>>> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
>>> @@ -426,7 +426,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> }
>>>
>>> static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
>>> index 1fcfb840f238..9871c49b0383 100644
>>> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
>>> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
>>> @@ -42,17 +42,16 @@ static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
>>> }
>>>
>>> static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
>>> default:
>>> dev_err(pci->dev, "UNKNOWN IRQ type\n");
>>> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
>>> index 615660640801..e039081eb947 100644
>>> --- a/drivers/pci/controller/dwc/pcie-designware.h
>>> +++ b/drivers/pci/controller/dwc/pcie-designware.h
>>> @@ -320,7 +320,7 @@ struct dw_pcie_rp {
>>> struct dw_pcie_ep_ops {
>>> void (*ep_init)(struct dw_pcie_ep *ep);
>>> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num);
>>> + unsigned int type, u16 interrupt_num);
>>> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
>>> /*
>>> * Provide a method to implement the different func config space
>>> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
>>> index f90f36bac018..c93fd79d400b 100644
>>> --- a/drivers/pci/controller/dwc/pcie-keembay.c
>>> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
>>> @@ -284,19 +284,18 @@ static void keembay_pcie_ep_init(struct dw_pcie_ep *ep)
>>> }
>>>
>>> static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> /* Legacy interrupts are not supported in Keem Bay */
>>> dev_err(pci->dev, "Legacy IRQ is not supported\n");
>>> return -EINVAL;
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
>>> default:
>>> dev_err(pci->dev, "Unknown IRQ type %d\n", type);
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> index 0fe7f06f2102..3faabc66f07b 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
>>> @@ -655,14 +655,14 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
>>> }
>>>
>>> static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return dw_pcie_ep_raise_legacy_irq(ep, func_no);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
>>> default:
>>> dev_err(pci->dev, "Unknown IRQ type\n");
>>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>>> index e1db909f53ec..cafcef0da223 100644
>>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>>> @@ -1993,20 +1993,19 @@ static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
>>> }
>>>
>>> static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>> struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
>>>
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
>>>
>>> - case PCI_EPC_IRQ_MSIX:
>>> + case PCI_IRQ_MSIX:
>>> return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
>>>
>>> default:
>>> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>> index 4d0a587c0ba5..43c27138c3c5 100644
>>> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>>> @@ -256,15 +256,14 @@ static int uniphier_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
>>> }
>>>
>>> static int uniphier_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return uniphier_pcie_ep_raise_legacy_irq(ep);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return uniphier_pcie_ep_raise_msi_irq(ep, func_no,
>>> interrupt_num);
>>> default:
>>> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
>>> index f9682df1da61..2172db2343d9 100644
>>> --- a/drivers/pci/controller/pcie-rcar-ep.c
>>> +++ b/drivers/pci/controller/pcie-rcar-ep.c
>>> @@ -402,16 +402,15 @@ static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
>>> }
>>>
>>> static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return rcar_pcie_ep_assert_intx(ep, fn, 0);
>>>
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
>>>
>>> default:
>>> diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
>>> index 0af0e965fb57..397ad551c912 100644
>>> --- a/drivers/pci/controller/pcie-rockchip-ep.c
>>> +++ b/drivers/pci/controller/pcie-rockchip-ep.c
>>> @@ -407,15 +407,14 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
>>> }
>>>
>>> static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
>>> - enum pci_epc_irq_type type,
>>> - u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
>>>
>>> switch (type) {
>>> - case PCI_EPC_IRQ_LEGACY:
>>> + case PCI_IRQ_LEGACY:
>>> return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
>>> - case PCI_EPC_IRQ_MSI:
>>> + case PCI_IRQ_MSI:
>>> return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
>>> default:
>>> return -EINVAL;
>>> diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c
>>> index ddf0bace4e18..f2fcda1c5d4f 100644
>>> --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c
>>> +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c
>>> @@ -177,7 +177,7 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector)
>>> * MHI supplies 0 based MSI vectors but the API expects the vector
>>> * number to start from 1, so we need to increment the vector by 1.
>>> */
>>> - pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI,
>>> + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_IRQ_MSI,
>>> vector + 1);
>>> }
>>>
>>> diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/endpoint/functions/pci-epf-ntb.c
>>> index 9aac2c6f3bb9..fad00b1a8335 100644
>>> --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c
>>> +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c
>>> @@ -140,9 +140,9 @@ static struct pci_epf_header epf_ntb_header = {
>>> static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
>>> {
>>> enum pci_epc_interface_type type;
>>> - enum pci_epc_irq_type irq_type;
>>> struct epf_ntb_epc *ntb_epc;
>>> struct epf_ntb_ctrl *ctrl;
>>> + unsigned int irq_type;
>>> struct pci_epc *epc;
>>> u8 func_no, vfunc_no;
>>> bool is_msix;
>>> @@ -159,7 +159,7 @@ static int epf_ntb_link_up(struct epf_ntb *ntb, bool link_up)
>>> ctrl->link_status |= LINK_STATUS_UP;
>>> else
>>> ctrl->link_status &= ~LINK_STATUS_UP;
>>> - irq_type = is_msix ? PCI_EPC_IRQ_MSIX : PCI_EPC_IRQ_MSI;
>>> + irq_type = is_msix ? PCI_IRQ_MSIX : PCI_IRQ_MSI;
>>> ret = pci_epc_raise_irq(epc, func_no, vfunc_no, irq_type, 1);
>>> if (ret) {
>>> dev_err(&epc->dev,
>>> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
>>> index fa993e71c224..76ddf4c92511 100644
>>> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
>>> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
>>> @@ -602,7 +602,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
>>> switch (reg->irq_type) {
>>> case IRQ_TYPE_LEGACY:
>>> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
>>> - PCI_EPC_IRQ_LEGACY, 0);
>>> + PCI_IRQ_LEGACY, 0);
>>> break;
>>> case IRQ_TYPE_MSI:
>>> count = pci_epc_get_msi(epc, epf->func_no, epf->vfunc_no);
>>> @@ -612,7 +612,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
>>> return;
>>> }
>>> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
>>> - PCI_EPC_IRQ_MSI, reg->irq_number);
>>> + PCI_IRQ_MSI, reg->irq_number);
>>> break;
>>> case IRQ_TYPE_MSIX:
>>> count = pci_epc_get_msix(epc, epf->func_no, epf->vfunc_no);
>>> @@ -622,7 +622,7 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test,
>>> return;
>>> }
>>> pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no,
>>> - PCI_EPC_IRQ_MSIX, reg->irq_number);
>>> + PCI_IRQ_MSIX, reg->irq_number);
>>> break;
>>> default:
>>> dev_err(dev, "Failed to raise IRQ, unknown type\n");
>>> diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c
>>> index c8b423c3c26e..ba2fe0bb400a 100644
>>> --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c
>>> +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c
>>> @@ -1172,11 +1172,8 @@ static int vntb_epf_peer_db_set(struct ntb_dev *ndev, u64 db_bits)
>>> func_no = ntb->epf->func_no;
>>> vfunc_no = ntb->epf->vfunc_no;
>>>
>>> - ret = pci_epc_raise_irq(ntb->epf->epc,
>>> - func_no,
>>> - vfunc_no,
>>> - PCI_EPC_IRQ_MSI,
>>> - interrupt_num + 1);
>>> + ret = pci_epc_raise_irq(ntb->epf->epc, func_no, vfunc_no,
>>> + PCI_IRQ_MSI, interrupt_num + 1);
>>> if (ret)
>>> dev_err(&ntb->ntb.dev, "Failed to raise IRQ\n");
>>>
>>> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
>>> index 6c54fa5684d2..835d56922cbb 100644
>>> --- a/drivers/pci/endpoint/pci-epc-core.c
>>> +++ b/drivers/pci/endpoint/pci-epc-core.c
>>> @@ -218,7 +218,7 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
>>> * Invoke to raise an legacy, MSI or MSI-X interrupt
>>> */
>>> int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num)
>>> + unsigned int type, u16 interrupt_num)
>>> {
>>> int ret;
>>>
>>> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
>>> index 5cb694031072..f498f9aa2ab0 100644
>>> --- a/include/linux/pci-epc.h
>>> +++ b/include/linux/pci-epc.h
>>> @@ -19,13 +19,6 @@ enum pci_epc_interface_type {
>>> SECONDARY_INTERFACE,
>>> };
>>>
>>> -enum pci_epc_irq_type {
>>> - PCI_EPC_IRQ_UNKNOWN,
>>> - PCI_EPC_IRQ_LEGACY,
>>> - PCI_EPC_IRQ_MSI,
>>> - PCI_EPC_IRQ_MSIX,
>>> -};
>>> -
>>> static inline const char *
>>> pci_epc_interface_string(enum pci_epc_interface_type type)
>>> {
>>> @@ -79,7 +72,7 @@ struct pci_epc_ops {
>>> u16 interrupts, enum pci_barno, u32 offset);
>>> int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
>>> int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num);
>>> + unsigned int type, u16 interrupt_num);
>>> int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> phys_addr_t phys_addr, u8 interrupt_num,
>>> u32 entry_size, u32 *msi_data,
>>> @@ -229,7 +222,7 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> phys_addr_t phys_addr, u8 interrupt_num,
>>> u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
>>> int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>>> - enum pci_epc_irq_type type, u16 interrupt_num);
>>> + unsigned int type, u16 interrupt_num);
>>> int pci_epc_start(struct pci_epc *epc);
>>> void pci_epc_stop(struct pci_epc *epc);
>>> const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
>>> --
>>> 2.41.0
>>>
>>
>>
>> --
>> மணிவண்ணன் சதாசிவம்
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-29 1:55 ` Damien Le Moal
@ 2023-07-29 1:58 ` Damien Le Moal
2023-07-29 2:02 ` Serge Semin
2023-07-29 15:32 ` Bjorn Helgaas
0 siblings, 2 replies; 90+ messages in thread
From: Damien Le Moal @ 2023-07-29 1:58 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam, Bjorn Helgaas
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Manivannan Sadhasivam, Jesper Nilsson, Tom Joseph,
Vignesh Raghavendra, Richard Zhu, Lucas Stach, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Minghuan Lian, Mingkai Hu, Roy Zang,
Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On 7/29/23 10:55, Damien Le Moal wrote:
> On 7/29/23 10:35, Serge Semin wrote:
>> On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
>>> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
>>>> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
>>>>> Using "INTx" instead of "legacy" is more specific. So, rename
>>>>> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
>>>>>
>>>>> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
>>>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>>>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>>>>> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
>>>>> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
>>>>
>>
>>>> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
>>>> PCI_IRQ_XXX macros used everywhere. Less definitions :)
>>>>
>>>> See attached patch that I have in my queue (about to send that).
>>>>
>>>
>>> It looks better! This patch should be dropped.
>>
>> Back then Bjorn specifically asked to change the names suffix in a
>> preparation patch before adding the INTx support to the DW PCIe core
>> driver (see the Sb tag in the patch log). Damien, seeing you cleanup
>> the names anyway what about fixing the macro suffix too: INTx instead
>> of LEGACY)?
>
> Sure, I can do that. That is going to be a gigantic patch though given that
> PCI_IRQ_LEGACY is used well beyond the ep/pcie controller drivers.
> While I agree it would be nice to do, not sure it is worth such code churn.
>
>> Mani, Damien, what do you suggest to Yoshihiro to do with the
>> LEGACY/INTx names in the following up patches of this series?
>
> If everyone is OK with the patch I proposed (the PCI_IRQ_LEGACY -> PCI_IRQ_INTx
> change can go on top), then I can rebase it and send it next week (the remaining
> of my EP cleanup series needs some more testing & rebasing). Yoshihiro can
> either include it in his series or rebase on it if the patch is added to
> pci-next quickly.
Note that we could start by simply defining an alias:
#define PCI_IRQ_INTx PCI_IRQ_LEGACY
and gradually convert all drivers using it until we can get rid of PCI_IRQ_LEGACY.
That probably would be simpler than a treewide patch that would likely create
lots of conflicts.
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-29 1:58 ` Damien Le Moal
@ 2023-07-29 2:02 ` Serge Semin
2023-07-29 15:32 ` Bjorn Helgaas
1 sibling, 0 replies; 90+ messages in thread
From: Serge Semin @ 2023-07-29 2:02 UTC (permalink / raw)
To: Damien Le Moal
Cc: Manivannan Sadhasivam, Bjorn Helgaas, Yoshihiro Shimoda,
jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
linux-pci, devicetree, linux-renesas-soc, Manivannan Sadhasivam,
Jesper Nilsson, Tom Joseph, Vignesh Raghavendra, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Minghuan Lian, Mingkai Hu,
Roy Zang, Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On Sat, Jul 29, 2023 at 10:58:46AM +0900, Damien Le Moal wrote:
> On 7/29/23 10:55, Damien Le Moal wrote:
> > On 7/29/23 10:35, Serge Semin wrote:
> >> On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
> >>> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
> >>>> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> >>>>> Using "INTx" instead of "legacy" is more specific. So, rename
> >>>>> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
> >>>>>
> >>>>> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> >>>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >>>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> >>>>> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> >>>>> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> >>>>
> >>
> >>>> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
> >>>> PCI_IRQ_XXX macros used everywhere. Less definitions :)
> >>>>
> >>>> See attached patch that I have in my queue (about to send that).
> >>>>
> >>>
> >>> It looks better! This patch should be dropped.
> >>
> >> Back then Bjorn specifically asked to change the names suffix in a
> >> preparation patch before adding the INTx support to the DW PCIe core
> >> driver (see the Sb tag in the patch log). Damien, seeing you cleanup
> >> the names anyway what about fixing the macro suffix too: INTx instead
> >> of LEGACY)?
> >
> > Sure, I can do that. That is going to be a gigantic patch though given that
> > PCI_IRQ_LEGACY is used well beyond the ep/pcie controller drivers.
> > While I agree it would be nice to do, not sure it is worth such code churn.
> >
> >> Mani, Damien, what do you suggest to Yoshihiro to do with the
> >> LEGACY/INTx names in the following up patches of this series?
> >
> > If everyone is OK with the patch I proposed (the PCI_IRQ_LEGACY -> PCI_IRQ_INTx
> > change can go on top), then I can rebase it and send it next week (the remaining
> > of my EP cleanup series needs some more testing & rebasing). Yoshihiro can
> > either include it in his series or rebase on it if the patch is added to
> > pci-next quickly.
>
> Note that we could start by simply defining an alias:
>
> #define PCI_IRQ_INTx PCI_IRQ_LEGACY
>
> and gradually convert all drivers using it until we can get rid of PCI_IRQ_LEGACY.
>
> That probably would be simpler than a treewide patch that would likely create
> lots of conflicts.
Sounds good to me. Though it's better to wait for the Bjorn opinion
about that before moving forward with the implementation.
-Serge(y)
>
> --
> Damien Le Moal
> Western Digital Research
>
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-29 1:58 ` Damien Le Moal
2023-07-29 2:02 ` Serge Semin
@ 2023-07-29 15:32 ` Bjorn Helgaas
2023-07-30 4:58 ` Manivannan Sadhasivam
1 sibling, 1 reply; 90+ messages in thread
From: Bjorn Helgaas @ 2023-07-29 15:32 UTC (permalink / raw)
To: Damien Le Moal
Cc: Serge Semin, Manivannan Sadhasivam, Yoshihiro Shimoda, jingoohan1,
gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Manivannan Sadhasivam,
Jesper Nilsson, Tom Joseph, Vignesh Raghavendra, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Minghuan Lian, Mingkai Hu,
Roy Zang, Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On Sat, Jul 29, 2023 at 10:58:46AM +0900, Damien Le Moal wrote:
> On 7/29/23 10:55, Damien Le Moal wrote:
> > On 7/29/23 10:35, Serge Semin wrote:
> >> On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
> >>> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
> >>>> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> >>>>> Using "INTx" instead of "legacy" is more specific. So, rename
> >>>>> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
> >>>>>
> >>>>> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> >>>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >>>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> >>>>> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> >>>>> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> >>>>
> >>
> >>>> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
> >>>> PCI_IRQ_XXX macros used everywhere. Less definitions :)
> >>>>
> >>>> See attached patch that I have in my queue (about to send that).
> >>>>
> >>>
> >>> It looks better! This patch should be dropped.
> >>
> >> Back then Bjorn specifically asked to change the names suffix in a
> >> preparation patch before adding the INTx support to the DW PCIe core
> >> driver (see the Sb tag in the patch log). Damien, seeing you cleanup
> >> the names anyway what about fixing the macro suffix too: INTx instead
> >> of LEGACY)?
> >
> > Sure, I can do that. That is going to be a gigantic patch though given that
> > PCI_IRQ_LEGACY is used well beyond the ep/pcie controller drivers.
> > While I agree it would be nice to do, not sure it is worth such code churn.
> >
> >> Mani, Damien, what do you suggest to Yoshihiro to do with the
> >> LEGACY/INTx names in the following up patches of this series?
> >
> > If everyone is OK with the patch I proposed (the PCI_IRQ_LEGACY -> PCI_IRQ_INTx
> > change can go on top), then I can rebase it and send it next week (the remaining
> > of my EP cleanup series needs some more testing & rebasing). Yoshihiro can
> > either include it in his series or rebase on it if the patch is added to
> > pci-next quickly.
>
> Note that we could start by simply defining an alias:
>
> #define PCI_IRQ_INTx PCI_IRQ_LEGACY
>
> and gradually convert all drivers using it until we can get rid of PCI_IRQ_LEGACY.
I try to catch additions of "legacy," e.g., in new drivers, but I
agree this patch looks like it might be more churn than it's worth.
But I like your idea of an alias, Damien. Maybe something like the
below to make it more obvious that the preferred usage is the "INTX"
form.
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 5cb694031072..6c0bb4c5d12e 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -21,11 +21,13 @@ enum pci_epc_interface_type {
enum pci_epc_irq_type {
PCI_EPC_IRQ_UNKNOWN,
- PCI_EPC_IRQ_LEGACY,
+ PCI_EPC_IRQ_INTX,
PCI_EPC_IRQ_MSI,
PCI_EPC_IRQ_MSIX,
};
+#define PCI_EPC_IRQ_LEGACY PCI_EPC_IRQ_INTX
+
static inline const char *
pci_epc_interface_string(enum pci_epc_interface_type type)
{
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c69a2cc1f412..6638e0cd487f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1048,11 +1048,13 @@ enum {
PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
};
-#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
+#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
+#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* prefer PCI_IRQ_INTX */
+
/* These external functions are only available when PCI support is enabled */
#ifdef CONFIG_PCI
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
2023-07-29 15:32 ` Bjorn Helgaas
@ 2023-07-30 4:58 ` Manivannan Sadhasivam
0 siblings, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-30 4:58 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Damien Le Moal, Serge Semin, Manivannan Sadhasivam,
Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Jesper Nilsson, Tom Joseph, Vignesh Raghavendra, Richard Zhu,
Lucas Stach, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Minghuan Lian, Mingkai Hu,
Roy Zang, Srikanth Thokala, Thierry Reding, Jonathan Hunter,
Kunihiko Hayashi, Masami Hiramatsu, Shawn Lin, Heiko Stuebner
On Sat, Jul 29, 2023 at 10:32:01AM -0500, Bjorn Helgaas wrote:
> On Sat, Jul 29, 2023 at 10:58:46AM +0900, Damien Le Moal wrote:
> > On 7/29/23 10:55, Damien Le Moal wrote:
> > > On 7/29/23 10:35, Serge Semin wrote:
> > >> On Mon, Jul 24, 2023 at 01:02:11PM +0530, Manivannan Sadhasivam wrote:
> > >>> On Fri, Jul 21, 2023 at 05:10:27PM +0900, Damien Le Moal wrote:
> > >>>> On 7/21/23 16:44, Yoshihiro Shimoda wrote:
> > >>>>> Using "INTx" instead of "legacy" is more specific. So, rename
> > >>>>> PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX.
> > >>>>>
> > >>>>> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> > >>>>> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >>>>> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > >>>>> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> # ARTPEC
> > >>>>> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > >>>>
> > >>
> > >>>> I would rather drop completely the PCI_EPC_IRQ_XXX enum and simply use the
> > >>>> PCI_IRQ_XXX macros used everywhere. Less definitions :)
> > >>>>
> > >>>> See attached patch that I have in my queue (about to send that).
> > >>>>
> > >>>
> > >>> It looks better! This patch should be dropped.
> > >>
> > >> Back then Bjorn specifically asked to change the names suffix in a
> > >> preparation patch before adding the INTx support to the DW PCIe core
> > >> driver (see the Sb tag in the patch log). Damien, seeing you cleanup
> > >> the names anyway what about fixing the macro suffix too: INTx instead
> > >> of LEGACY)?
> > >
> > > Sure, I can do that. That is going to be a gigantic patch though given that
> > > PCI_IRQ_LEGACY is used well beyond the ep/pcie controller drivers.
> > > While I agree it would be nice to do, not sure it is worth such code churn.
> > >
> > >> Mani, Damien, what do you suggest to Yoshihiro to do with the
> > >> LEGACY/INTx names in the following up patches of this series?
> > >
> > > If everyone is OK with the patch I proposed (the PCI_IRQ_LEGACY -> PCI_IRQ_INTx
> > > change can go on top), then I can rebase it and send it next week (the remaining
> > > of my EP cleanup series needs some more testing & rebasing). Yoshihiro can
> > > either include it in his series or rebase on it if the patch is added to
> > > pci-next quickly.
> >
> > Note that we could start by simply defining an alias:
> >
> > #define PCI_IRQ_INTx PCI_IRQ_LEGACY
> >
> > and gradually convert all drivers using it until we can get rid of PCI_IRQ_LEGACY.
>
> I try to catch additions of "legacy," e.g., in new drivers, but I
> agree this patch looks like it might be more churn than it's worth.
>
> But I like your idea of an alias, Damien. Maybe something like the
> below to make it more obvious that the preferred usage is the "INTX"
> form.
Looks good to me. I'd prefer to merge these (Damien's) patches first and let
Yoshihiro rebase on top of pci-next instead of clubbing everything in a single
series.
- Mani
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index 5cb694031072..6c0bb4c5d12e 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -21,11 +21,13 @@ enum pci_epc_interface_type {
>
> enum pci_epc_irq_type {
> PCI_EPC_IRQ_UNKNOWN,
> - PCI_EPC_IRQ_LEGACY,
> + PCI_EPC_IRQ_INTX,
> PCI_EPC_IRQ_MSI,
> PCI_EPC_IRQ_MSIX,
> };
>
> +#define PCI_EPC_IRQ_LEGACY PCI_EPC_IRQ_INTX
> +
> static inline const char *
> pci_epc_interface_string(enum pci_epc_interface_type type)
> {
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index c69a2cc1f412..6638e0cd487f 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -1048,11 +1048,13 @@ enum {
> PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
> };
>
> -#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
> +#define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */
> #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
> #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
> #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
>
> +#define PCI_IRQ_LEGACY PCI_IRQ_INTX /* prefer PCI_IRQ_INTX */
> +
> /* These external functions are only available when PCI support is enabled */
> #ifdef CONFIG_PCI
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq"
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 01/20] PCI: Add INTx Mechanism Messages macros Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 02/20] PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
` (17 subsequent siblings)
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Bjorn Helgaas,
Manivannan Sadhasivam
Using "INTx" instead of "legacy" is more specific. So, rename
dw_pcie_ep_raise_legacy_irq() to dw_pcie_ep_raise_intx_irq().
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 2 +-
drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +-
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
drivers/pci/controller/dwc/pcie-qcom-ep.c | 2 +-
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index feadc88782a7..326b8eb9a424 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1064,7 +1064,7 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
switch (type) {
case PCI_EPC_IRQ_INTX:
- return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
case PCI_EPC_IRQ_MSIX:
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index b2e14d64dba2..5e00f0be4f95 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -156,7 +156,7 @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
switch (type) {
case PCI_EPC_IRQ_INTX:
- return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
case PCI_EPC_IRQ_MSIX:
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index f9182f8d552f..27278010ecec 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -479,16 +479,16 @@ static const struct pci_epc_ops epc_ops = {
.get_features = dw_pcie_ep_get_features,
};
-int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
+int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct device *dev = pci->dev;
- dev_err(dev, "EP cannot trigger legacy IRQs\n");
+ dev_err(dev, "EP cannot trigger INTx IRQs\n");
return -EINVAL;
}
-EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
+EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index f72df38dd523..c311f42ff7ca 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -49,7 +49,7 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
switch (type) {
case PCI_EPC_IRQ_INTX:
- return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
case PCI_EPC_IRQ_MSIX:
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 615660640801..3c06e025c905 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -548,7 +548,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep);
int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
-int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
+int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num);
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -581,7 +581,7 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
{
}
-static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
+static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
{
return 0;
}
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 21e2ccc49219..4b43357b1c6c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -661,7 +661,7 @@ static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
switch (type) {
case PCI_EPC_IRQ_INTX:
- return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
case PCI_EPC_IRQ_MSI:
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (2 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 03/20] PCI: dwc: Rename "legacy_irq" to "INTx_irq" Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 7:45 ` Manivannan Sadhasivam
2023-07-29 2:06 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
` (16 subsequent siblings)
20 siblings, 2 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
To support INTx IRQs in the future, it requires an additional 2
arguments. For improved code readability, introduce the struct
dw_pcie_ob_atu_cfg and update the arguments of
dw_pcie_prog_outbound_atu().
Consequently, remove __dw_pcie_prog_outbound_atu() and
dw_pcie_prog_ep_outbound_atu() because there is no longer
a need.
No behavior changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
.../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
.../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
4 files changed, 77 insertions(+), 60 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 27278010ecec..fe2e0d765be9 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
return 0;
}
-static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
- phys_addr_t phys_addr,
- u64 pci_addr, size_t size)
+static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
+ struct dw_pcie_ob_atu_cfg *atu)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
u32 free_win;
@@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
return -EINVAL;
}
- ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
- phys_addr, pci_addr, size);
+ atu->index = free_win;
+ ret = dw_pcie_prog_outbound_atu(pci, atu);
if (ret)
return ret;
set_bit(free_win, ep->ob_window_map);
- ep->outbound_addr[free_win] = phys_addr;
+ ep->outbound_addr[free_win] = atu->cpu_addr;
return 0;
}
@@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
int ret;
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
- ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
+
+ atu.func_no = func_no;
+ atu.type = PCIE_ATU_TYPE_MEM;
+ atu.cpu_addr = addr;
+ atu.pci_addr = pci_addr;
+ atu.size = size;
+ ret = dw_pcie_ep_outbound_atu(ep, &atu);
if (ret) {
dev_err(pci->dev, "Failed to enable address\n");
return ret;
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index cf61733bf78d..7419185721f2 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int type, ret;
u32 busdev;
@@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
else
type = PCIE_ATU_TYPE_CFG1;
- ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
- pp->cfg0_size);
+ atu.type = type;
+ atu.cpu_addr = pp->cfg0_base;
+ atu.pci_addr = busdev;
+ atu.size = pp->cfg0_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return NULL;
@@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int ret;
ret = pci_generic_config_read(bus, devfn, where, size, val);
@@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
return ret;
if (pp->cfg0_io_shared) {
- ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
- pp->io_base, pp->io_bus_addr,
- pp->io_size);
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return PCIBIOS_SET_FAILED;
}
@@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
{
struct dw_pcie_rp *pp = bus->sysdata;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
int ret;
ret = pci_generic_config_write(bus, devfn, where, size, val);
@@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
return ret;
if (pp->cfg0_io_shared) {
- ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
- pp->io_base, pp->io_bus_addr,
- pp->io_size);
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret)
return PCIBIOS_SET_FAILED;
}
@@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
struct resource_entry *entry;
int i, ret;
@@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
if (pci->num_ob_windows <= ++i)
break;
- ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
- entry->res->start,
- entry->res->start - entry->offset,
- resource_size(entry->res));
+ atu.index = i;
+ atu.type = PCIE_ATU_TYPE_MEM;
+ atu.cpu_addr = entry->res->start;
+ atu.pci_addr = entry->res->start - entry->offset;
+ atu.size = resource_size(entry->res);
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret) {
dev_err(pci->dev, "Failed to set MEM range %pr\n",
entry->res);
@@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
if (pp->io_size) {
if (pci->num_ob_windows > ++i) {
- ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
- pp->io_base,
- pp->io_bus_addr,
- pp->io_size);
+ atu.index = i;
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
+
+ ret = dw_pcie_prog_outbound_atu(pci, &atu);
if (ret) {
dev_err(pci->dev, "Failed to set IO range %pr\n",
entry->res);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2459f2a61b9b..49b785509576 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
return val | PCIE_ATU_TD;
}
-static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
- int index, int type, u64 cpu_addr,
- u64 pci_addr, u64 size)
+int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
+ const struct dw_pcie_ob_atu_cfg *atu)
{
+ u64 cpu_addr = atu->cpu_addr;
u32 retries, val;
u64 limit_addr;
if (pci->ops && pci->ops->cpu_addr_fixup)
cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
- limit_addr = cpu_addr + size - 1;
+ limit_addr = cpu_addr + atu->size - 1;
if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
!IS_ALIGNED(cpu_addr, pci->region_align) ||
- !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
+ !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
return -EINVAL;
}
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
lower_32_bits(cpu_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
upper_32_bits(cpu_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
lower_32_bits(limit_addr));
if (dw_pcie_ver_is_ge(pci, 460A))
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
upper_32_bits(limit_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
- lower_32_bits(pci_addr));
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
- upper_32_bits(pci_addr));
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
+ lower_32_bits(atu->pci_addr));
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
+ upper_32_bits(atu->pci_addr));
- val = type | PCIE_ATU_FUNC_NUM(func_no);
+ val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
dw_pcie_ver_is_ge(pci, 460A))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
if (dw_pcie_ver_is(pci, 490A))
val = dw_pcie_enable_ecrc(val);
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
- dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
/*
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
- val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
+ val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
if (val & PCIE_ATU_ENABLE)
return 0;
@@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
return -ETIMEDOUT;
}
-int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u64 size)
-{
- return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
- cpu_addr, pci_addr, size);
-}
-
-int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
- int type, u64 cpu_addr, u64 pci_addr,
- u64 size)
-{
- return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
- cpu_addr, pci_addr, size);
-}
-
static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
{
return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 3c06e025c905..85de0d8346fa 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
DW_PCIE_NUM_CORE_RSTS
};
+struct dw_pcie_ob_atu_cfg {
+ int index;
+ int type;
+ u8 func_no;
+ u64 cpu_addr;
+ u64 pci_addr;
+ u64 size;
+};
+
struct dw_pcie_host_ops {
int (*host_init)(struct dw_pcie_rp *pp);
void (*host_deinit)(struct dw_pcie_rp *pp);
@@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
void dw_pcie_upconfig_setup(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
-int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u64 size);
-int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
- int type, u64 cpu_addr, u64 pci_addr, u64 size);
+int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
+ const struct dw_pcie_ob_atu_cfg *atu);
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
u64 cpu_addr, u64 pci_addr, u64 size);
int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
@ 2023-07-24 7:45 ` Manivannan Sadhasivam
2023-07-26 5:02 ` Serge Semin
2023-07-29 2:06 ` Serge Semin
1 sibling, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 7:45 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, fancer.lancer, linux-pci,
devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> To support INTx IRQs in the future, it requires an additional 2
> arguments. For improved code readability, introduce the struct
> dw_pcie_ob_atu_cfg and update the arguments of
> dw_pcie_prog_outbound_atu().
>
> Consequently, remove __dw_pcie_prog_outbound_atu() and
> dw_pcie_prog_ep_outbound_atu() because there is no longer
> a need.
>
> No behavior changes.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
One nit below. With that,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> 4 files changed, 77 insertions(+), 60 deletions(-)
>
[...]
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 3c06e025c905..85de0d8346fa 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> DW_PCIE_NUM_CORE_RSTS
> };
>
> +struct dw_pcie_ob_atu_cfg {
> + int index;
> + int type;
> + u8 func_no;
> + u64 cpu_addr;
> + u64 pci_addr;
> + u64 size;
Reorder the members in below order to avoid holes:
u64
int
u8
- Mani
> +};
> +
> struct dw_pcie_host_ops {
> int (*host_init)(struct dw_pcie_rp *pp);
> void (*host_deinit)(struct dw_pcie_rp *pp);
> @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> int dw_pcie_link_up(struct dw_pcie *pci);
> void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u64 size);
> -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> + const struct dw_pcie_ob_atu_cfg *atu);
> int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> u64 cpu_addr, u64 pci_addr, u64 size);
> int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-24 7:45 ` Manivannan Sadhasivam
@ 2023-07-26 5:02 ` Serge Semin
2023-07-26 13:00 ` Manivannan Sadhasivam
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-26 5:02 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, manivannan.sadhasivam, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > To support INTx IRQs in the future, it requires an additional 2
> > arguments. For improved code readability, introduce the struct
> > dw_pcie_ob_atu_cfg and update the arguments of
> > dw_pcie_prog_outbound_atu().
> >
> > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > a need.
> >
> > No behavior changes.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> One nit below. With that,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > 4 files changed, 77 insertions(+), 60 deletions(-)
> >
>
> [...]
>
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 3c06e025c905..85de0d8346fa 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > DW_PCIE_NUM_CORE_RSTS
> > };
> >
> > +struct dw_pcie_ob_atu_cfg {
> > + int index;
> > + int type;
> > + u8 func_no;
> > + u64 cpu_addr;
> > + u64 pci_addr;
> > + u64 size;
>
> Reorder the members in below order to avoid holes:
>
> u64
> int
> u8
One more time. Your suggestion won't prevent the compiler from adding
the pads. (If by "holes" you meant the padding. Otherwise please
elaborate what you meant?). The structure will have the same size of
40 bytes in both cases. So your suggestion will just worsen the
structure readability from having a more natural parameters order (MW
index, type, function, and then the mapping parameters) to a redundant
type-based order.
-Serge(y)
>
> - Mani
>
> > +};
> > +
> > struct dw_pcie_host_ops {
> > int (*host_init)(struct dw_pcie_rp *pp);
> > void (*host_deinit)(struct dw_pcie_rp *pp);
> > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > int dw_pcie_link_up(struct dw_pcie *pci);
> > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > - u64 cpu_addr, u64 pci_addr, u64 size);
> > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > + const struct dw_pcie_ob_atu_cfg *atu);
> > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > u64 cpu_addr, u64 pci_addr, u64 size);
> > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-26 5:02 ` Serge Semin
@ 2023-07-26 13:00 ` Manivannan Sadhasivam
2023-07-26 23:38 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-26 13:00 UTC (permalink / raw)
To: Serge Semin
Cc: Manivannan Sadhasivam, Yoshihiro Shimoda, jingoohan1,
gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Wed, Jul 26, 2023 at 08:02:24AM +0300, Serge Semin wrote:
> On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > To support INTx IRQs in the future, it requires an additional 2
> > > arguments. For improved code readability, introduce the struct
> > > dw_pcie_ob_atu_cfg and update the arguments of
> > > dw_pcie_prog_outbound_atu().
> > >
> > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > a need.
> > >
> > > No behavior changes.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > One nit below. With that,
> >
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > ---
> > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > >
> >
> > [...]
> >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 3c06e025c905..85de0d8346fa 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > DW_PCIE_NUM_CORE_RSTS
> > > };
> > >
> > > +struct dw_pcie_ob_atu_cfg {
> > > + int index;
> > > + int type;
> > > + u8 func_no;
> > > + u64 cpu_addr;
> > > + u64 pci_addr;
> > > + u64 size;
> >
>
> > Reorder the members in below order to avoid holes:
> >
> > u64
> > int
> > u8
>
> One more time. Your suggestion won't prevent the compiler from adding
> the pads. (If by "holes" you meant the padding. Otherwise please
> elaborate what you meant?).
Struct padding is often referred as struct holes. So yes, I'm referring the
same.
> The structure will have the same size of
> 40 bytes in both cases. So your suggestion will just worsen the
> structure readability from having a more natural parameters order (MW
> index, type, function, and then the mapping parameters) to a redundant
> type-based order.
>
This is a common comment I provide for all structures. Even though the current
result (reordering) doesn't save any space, when the structure grows big (who
knows), we often see more holes/padding being inserted by the compiler if the
members are not ordered in the descending order w.r.t their size.
I agree that it makes more clear if the members are grouped based on their
function etc... but for large structures this would often add more padding/hole.
- Mani
> -Serge(y)
>
> >
> > - Mani
> >
> > > +};
> > > +
> > > struct dw_pcie_host_ops {
> > > int (*host_init)(struct dw_pcie_rp *pp);
> > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-26 13:00 ` Manivannan Sadhasivam
@ 2023-07-26 23:38 ` Serge Semin
2023-07-27 1:06 ` Yoshihiro Shimoda
2023-07-27 11:03 ` Manivannan Sadhasivam
0 siblings, 2 replies; 90+ messages in thread
From: Serge Semin @ 2023-07-26 23:38 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Manivannan Sadhasivam, Yoshihiro Shimoda, jingoohan1,
gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Wed, Jul 26, 2023 at 06:30:15PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jul 26, 2023 at 08:02:24AM +0300, Serge Semin wrote:
> > On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > To support INTx IRQs in the future, it requires an additional 2
> > > > arguments. For improved code readability, introduce the struct
> > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > dw_pcie_prog_outbound_atu().
> > > >
> > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > a need.
> > > >
> > > > No behavior changes.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> > > One nit below. With that,
> > >
> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > >
> > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > ---
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > >
> > >
> > > [...]
> > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > index 3c06e025c905..85de0d8346fa 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > DW_PCIE_NUM_CORE_RSTS
> > > > };
> > > >
> > > > +struct dw_pcie_ob_atu_cfg {
> > > > + int index;
> > > > + int type;
> > > > + u8 func_no;
> > > > + u64 cpu_addr;
> > > > + u64 pci_addr;
> > > > + u64 size;
> > >
> >
> > > Reorder the members in below order to avoid holes:
> > >
> > > u64
> > > int
> > > u8
> >
> > One more time. Your suggestion won't prevent the compiler from adding
> > the pads. (If by "holes" you meant the padding. Otherwise please
> > elaborate what you meant?).
>
> Struct padding is often referred as struct holes. So yes, I'm referring the
> same.
>
> > The structure will have the same size of
> > 40 bytes in both cases. So your suggestion will just worsen the
> > structure readability from having a more natural parameters order (MW
> > index, type, function, and then the mapping parameters) to a redundant
> > type-based order.
> >
>
> This is a common comment I provide for all structures. Even though the current
> result (reordering) doesn't save any space, when the structure grows big (who
> knows), we often see more holes/padding being inserted by the compiler if the
> members are not ordered in the descending order w.r.t their size.
>
> I agree that it makes more clear if the members are grouped based on their
> function etc... but for large structures this would often add more padding/hole.
This structure will never be big enough to be considered for such
strange optimization. Moreover practicality almost always beats some
theoretical considerations. In this case there is no any reason to
reorder the fields as you say.
Speaking in general I very much doubt that saving a few bytes of
memory can be considered as a better option than having a more
readable structure especially these days. Moreover for all these years
I never met anybody asking to set the descending order of
the members or maintaining such limitation in the commonly used kernel
structures. What is normally done:
1. Move an embedded object to the head of the structure for the
container_of-macro optimization.
2. Group up the commonly used fields to optimize the system cache
utilization.
3. Logical grouping the members, which naturally may lead to the more
optimal cache utilization.
4. Move a field to a certain place of the structure to fill in the
pads.
Even if the "descending alignment" requirement minimizes the number of
the pads it isn't the only possible way to do so in the particular
cases and it looks too harsh to be blindly applied all the time. If a
few bytes is so important why not do the same for instance for the
local variables too? They are also normally size-aligned in the stack
memory, which is much more precious in kernel.
Anyway in this case changing the fields order is absolutely redundant.
Even a provided afterwards update doesn't cause the structure size
change. So for the sake of readability it's better to leave its fields
ordered as is.
-Serge(y)
>
> - Mani
>
> > -Serge(y)
> >
> > >
> > > - Mani
> > >
> > > > +};
> > > > +
> > > > struct dw_pcie_host_ops {
> > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-26 23:38 ` Serge Semin
@ 2023-07-27 1:06 ` Yoshihiro Shimoda
2023-07-27 11:03 ` Manivannan Sadhasivam
1 sibling, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-27 1:06 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Thursday, July 27, 2023 8:39 AM
> On Wed, Jul 26, 2023 at 06:30:15PM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Jul 26, 2023 at 08:02:24AM +0300, Serge Semin wrote:
> > > On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> > > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > > To support INTx IRQs in the future, it requires an additional 2
> > > > > arguments. For improved code readability, introduce the struct
> > > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > > dw_pcie_prog_outbound_atu().
> > > > >
> > > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > > a need.
> > > > >
> > > > > No behavior changes.
> > > > >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > >
> > > > One nit below. With that,
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > >
> > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > ---
> > > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > > >
> > > >
> > > > [...]
> > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > index 3c06e025c905..85de0d8346fa 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > > DW_PCIE_NUM_CORE_RSTS
> > > > > };
> > > > >
> > > > > +struct dw_pcie_ob_atu_cfg {
> > > > > + int index;
> > > > > + int type;
> > > > > + u8 func_no;
> > > > > + u64 cpu_addr;
> > > > > + u64 pci_addr;
> > > > > + u64 size;
> > > >
> > >
> > > > Reorder the members in below order to avoid holes:
> > > >
> > > > u64
> > > > int
> > > > u8
> > >
> > > One more time. Your suggestion won't prevent the compiler from adding
> > > the pads. (If by "holes" you meant the padding. Otherwise please
> > > elaborate what you meant?).
> >
> > Struct padding is often referred as struct holes. So yes, I'm referring the
> > same.
> >
> > > The structure will have the same size of
> > > 40 bytes in both cases. So your suggestion will just worsen the
> > > structure readability from having a more natural parameters order (MW
> > > index, type, function, and then the mapping parameters) to a redundant
> > > type-based order.
> > >
> >
>
> > This is a common comment I provide for all structures. Even though the current
> > result (reordering) doesn't save any space, when the structure grows big (who
> > knows), we often see more holes/padding being inserted by the compiler if the
> > members are not ordered in the descending order w.r.t their size.
> >
> > I agree that it makes more clear if the members are grouped based on their
> > function etc... but for large structures this would often add more padding/hole.
>
> This structure will never be big enough to be considered for such
> strange optimization. Moreover practicality almost always beats some
> theoretical considerations. In this case there is no any reason to
> reorder the fields as you say.
>
> Speaking in general I very much doubt that saving a few bytes of
> memory can be considered as a better option than having a more
> readable structure especially these days. Moreover for all these years
> I never met anybody asking to set the descending order of
> the members or maintaining such limitation in the commonly used kernel
> structures. What is normally done:
> 1. Move an embedded object to the head of the structure for the
> container_of-macro optimization.
> 2. Group up the commonly used fields to optimize the system cache
> utilization.
> 3. Logical grouping the members, which naturally may lead to the more
> optimal cache utilization.
> 4. Move a field to a certain place of the structure to fill in the
> pads.
>
> Even if the "descending alignment" requirement minimizes the number of
> the pads it isn't the only possible way to do so in the particular
> cases and it looks too harsh to be blindly applied all the time. If a
> few bytes is so important why not do the same for instance for the
> local variables too? They are also normally size-aligned in the stack
> memory, which is much more precious in kernel.
I found some patches to save memory by avoiding padding/hole in 2023:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=86c6bb0edffa9fc02b4e3801b48c8e82114f1352
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=48cd6bc5b22d68b8bbc8601f3c7ddeed99541a0b
> Anyway in this case changing the fields order is absolutely redundant.
> Even a provided afterwards update doesn't cause the structure size
> change. So for the sake of readability it's better to leave its fields
> ordered as is.
I should have asked you before you suggested this ordering [1], but
I don't know why the current ordering is good readability.
-----
struct dw_pcie_ob_atu_cfg {
int index;
int type;
u8 func_no;
u64 cpu_addr;
u64 pci_addr;
u64 size;
};
-----
The ordering of struct dw_pcie_ob_atu_cfg seems to related to the arguments
of original functions which are dw_pcie_prog_{ep}_outbound_atu().
-----
int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
u64 cpu_addr, u64 pci_addr, u64 size);
int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
int type, u64 cpu_addr, u64 pci_addr, u64 size);
-----
About the patch, I relied on the arguments order in the code like below:
-----
- ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
- pp->io_base, pp->io_bus_addr,
- pp->io_size);
+ atu.type = PCIE_ATU_TYPE_IO;
+ atu.cpu_addr = pp->io_base;
+ atu.pci_addr = pp->io_bus_addr;
+ atu.size = pp->io_size;
-----
For reviewing the patch, I believe this is good ordering. However,
about ordering of the struct dw_pcie_ob_atu_cfg members, I think
that both ordering is the same readability. Perhaps, we should add
comments in the struct like below?
-----
struct dw_pcie_ob_atu_cfg {
/* The following members are required on both host and endpoint */
u64 cpu_addr;
u64 pci_addr;
u64 size;
int index;
int type;
/* The following member is required on endpoint */
u8 func_no;
};
-----
# Each "The following member(s) is/are" can be dropped?
And then, we add new members like below:
-----
struct dw_pcie_ob_atu_cfg {
/* The following members are required on both host and endpoint */
u64 cpu_addr;
u64 pci_addr;
u64 size;
int index;
int type;
/* The following member is required on endpoint */
u8 func_no;
/* The following members are optional for endpoint */
u8 routing;
u8 code;
};
-----
There is the good ordering for padding/hole unexpectedly :)
But, what do you think?
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > - Mani
> >
> > > -Serge(y)
> > >
> > > >
> > > > - Mani
> > > >
> > > > > +};
> > > > > +
> > > > > struct dw_pcie_host_ops {
> > > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > --
> > > > > 2.25.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> >
> > --
> > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-26 23:38 ` Serge Semin
2023-07-27 1:06 ` Yoshihiro Shimoda
@ 2023-07-27 11:03 ` Manivannan Sadhasivam
2023-07-27 12:21 ` Serge Semin
1 sibling, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-27 11:03 UTC (permalink / raw)
To: Serge Semin
Cc: Manivannan Sadhasivam, Yoshihiro Shimoda, jingoohan1,
gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Thu, Jul 27, 2023 at 02:38:44AM +0300, Serge Semin wrote:
> On Wed, Jul 26, 2023 at 06:30:15PM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Jul 26, 2023 at 08:02:24AM +0300, Serge Semin wrote:
> > > On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> > > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > > To support INTx IRQs in the future, it requires an additional 2
> > > > > arguments. For improved code readability, introduce the struct
> > > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > > dw_pcie_prog_outbound_atu().
> > > > >
> > > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > > a need.
> > > > >
> > > > > No behavior changes.
> > > > >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > >
> > > > One nit below. With that,
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > >
> > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > ---
> > > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > > >
> > > >
> > > > [...]
> > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > index 3c06e025c905..85de0d8346fa 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > > DW_PCIE_NUM_CORE_RSTS
> > > > > };
> > > > >
> > > > > +struct dw_pcie_ob_atu_cfg {
> > > > > + int index;
> > > > > + int type;
> > > > > + u8 func_no;
> > > > > + u64 cpu_addr;
> > > > > + u64 pci_addr;
> > > > > + u64 size;
> > > >
> > >
> > > > Reorder the members in below order to avoid holes:
> > > >
> > > > u64
> > > > int
> > > > u8
> > >
> > > One more time. Your suggestion won't prevent the compiler from adding
> > > the pads. (If by "holes" you meant the padding. Otherwise please
> > > elaborate what you meant?).
> >
> > Struct padding is often referred as struct holes. So yes, I'm referring the
> > same.
> >
> > > The structure will have the same size of
> > > 40 bytes in both cases. So your suggestion will just worsen the
> > > structure readability from having a more natural parameters order (MW
> > > index, type, function, and then the mapping parameters) to a redundant
> > > type-based order.
> > >
> >
>
> > This is a common comment I provide for all structures. Even though the current
> > result (reordering) doesn't save any space, when the structure grows big (who
> > knows), we often see more holes/padding being inserted by the compiler if the
> > members are not ordered in the descending order w.r.t their size.
> >
> > I agree that it makes more clear if the members are grouped based on their
> > function etc... but for large structures this would often add more padding/hole.
>
> This structure will never be big enough to be considered for such
> strange optimization. Moreover practicality almost always beats some
> theoretical considerations. In this case there is no any reason to
> reorder the fields as you say.
>
> Speaking in general I very much doubt that saving a few bytes of
> memory can be considered as a better option than having a more
> readable structure especially these days. Moreover for all these years
> I never met anybody asking to set the descending order of
> the members or maintaining such limitation in the commonly used kernel
> structures. What is normally done:
> 1. Move an embedded object to the head of the structure for the
> container_of-macro optimization.
> 2. Group up the commonly used fields to optimize the system cache
> utilization.
> 3. Logical grouping the members, which naturally may lead to the more
> optimal cache utilization.
Indeed.
> 4. Move a field to a certain place of the structure to fill in the
> pads.
>
This is what I try to avoid by grouping the members. If you move a field to
a certain place, wouldn't it affect readability?
But I do not want to argue more on this. Please see below.
> Even if the "descending alignment" requirement minimizes the number of
> the pads it isn't the only possible way to do so in the particular
> cases and it looks too harsh to be blindly applied all the time. If a
> few bytes is so important why not do the same for instance for the
> local variables too? They are also normally size-aligned in the stack
> memory, which is much more precious in kernel.
>
Well, for local variables I prefer reverse Xmas tree order which is what widely
used throughout the kernel. But we do not care about their ordering because, it
won't grow too much like a structure (not talking about recursive case).
> Anyway in this case changing the fields order is absolutely redundant.
> Even a provided afterwards update doesn't cause the structure size
> change. So for the sake of readability it's better to leave its fields
> ordered as is.
>
I certainly agree that reordering wouldn't save any space for this structure.
As a maintainer, I prefer to keep this pattern so that I don't have to worry
about the padding issues in the future and hence the suggestion.
But feel free to drop it as I don't have a strong objection to this specific
case.
- Mani
> -Serge(y)
>
> >
> > - Mani
> >
> > > -Serge(y)
> > >
> > > >
> > > > - Mani
> > > >
> > > > > +};
> > > > > +
> > > > > struct dw_pcie_host_ops {
> > > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > --
> > > > > 2.25.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-27 11:03 ` Manivannan Sadhasivam
@ 2023-07-27 12:21 ` Serge Semin
0 siblings, 0 replies; 90+ messages in thread
From: Serge Semin @ 2023-07-27 12:21 UTC (permalink / raw)
To: Manivannan Sadhasivam, Yoshihiro Shimoda
Cc: Manivannan Sadhasivam, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc
On Thu, Jul 27, 2023 at 04:33:43PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Jul 27, 2023 at 02:38:44AM +0300, Serge Semin wrote:
> > On Wed, Jul 26, 2023 at 06:30:15PM +0530, Manivannan Sadhasivam wrote:
> > > On Wed, Jul 26, 2023 at 08:02:24AM +0300, Serge Semin wrote:
> > > > On Mon, Jul 24, 2023 at 01:15:56PM +0530, Manivannan Sadhasivam wrote:
> > > > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > > > To support INTx IRQs in the future, it requires an additional 2
> > > > > > arguments. For improved code readability, introduce the struct
> > > > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > > > dw_pcie_prog_outbound_atu().
> > > > > >
> > > > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > > > a need.
> > > > > >
> > > > > > No behavior changes.
> > > > > >
> > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > >
> > > > > One nit below. With that,
> > > > >
> > > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > >
> > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > ---
> > > > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > > > >
> > > > >
> > > > > [...]
> > > > >
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > index 3c06e025c905..85de0d8346fa 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > > > DW_PCIE_NUM_CORE_RSTS
> > > > > > };
> > > > > >
> > > > > > +struct dw_pcie_ob_atu_cfg {
> > > > > > + int index;
> > > > > > + int type;
> > > > > > + u8 func_no;
> > > > > > + u64 cpu_addr;
> > > > > > + u64 pci_addr;
> > > > > > + u64 size;
> > > > >
> > > >
> > > > > Reorder the members in below order to avoid holes:
> > > > >
> > > > > u64
> > > > > int
> > > > > u8
> > > >
> > > > One more time. Your suggestion won't prevent the compiler from adding
> > > > the pads. (If by "holes" you meant the padding. Otherwise please
> > > > elaborate what you meant?).
> > >
> > > Struct padding is often referred as struct holes. So yes, I'm referring the
> > > same.
> > >
> > > > The structure will have the same size of
> > > > 40 bytes in both cases. So your suggestion will just worsen the
> > > > structure readability from having a more natural parameters order (MW
> > > > index, type, function, and then the mapping parameters) to a redundant
> > > > type-based order.
> > > >
> > >
> >
> > > This is a common comment I provide for all structures. Even though the current
> > > result (reordering) doesn't save any space, when the structure grows big (who
> > > knows), we often see more holes/padding being inserted by the compiler if the
> > > members are not ordered in the descending order w.r.t their size.
> > >
> > > I agree that it makes more clear if the members are grouped based on their
> > > function etc... but for large structures this would often add more padding/hole.
> >
> > This structure will never be big enough to be considered for such
> > strange optimization. Moreover practicality almost always beats some
> > theoretical considerations. In this case there is no any reason to
> > reorder the fields as you say.
> >
> > Speaking in general I very much doubt that saving a few bytes of
> > memory can be considered as a better option than having a more
> > readable structure especially these days. Moreover for all these years
> > I never met anybody asking to set the descending order of
> > the members or maintaining such limitation in the commonly used kernel
> > structures. What is normally done:
> > 1. Move an embedded object to the head of the structure for the
> > container_of-macro optimization.
> > 2. Group up the commonly used fields to optimize the system cache
> > utilization.
> > 3. Logical grouping the members, which naturally may lead to the more
> > optimal cache utilization.
>
> Indeed.
>
> > 4. Move a field to a certain place of the structure to fill in the
> > pads.
> >
>
> This is what I try to avoid by grouping the members. If you move a field to
> a certain place, wouldn't it affect readability?
>
> But I do not want to argue more on this. Please see below.
>
> > Even if the "descending alignment" requirement minimizes the number of
> > the pads it isn't the only possible way to do so in the particular
> > cases and it looks too harsh to be blindly applied all the time. If a
> > few bytes is so important why not do the same for instance for the
> > local variables too? They are also normally size-aligned in the stack
> > memory, which is much more precious in kernel.
> >
>
> Well, for local variables I prefer reverse Xmas tree order which is what widely
> used throughout the kernel. But we do not care about their ordering because, it
> won't grow too much like a structure (not talking about recursive case).
>
> > Anyway in this case changing the fields order is absolutely redundant.
> > Even a provided afterwards update doesn't cause the structure size
> > change. So for the sake of readability it's better to leave its fields
> > ordered as is.
> >
>
> I certainly agree that reordering wouldn't save any space for this structure.
> As a maintainer, I prefer to keep this pattern so that I don't have to worry
> about the padding issues in the future and hence the suggestion.
>
> But feel free to drop it as I don't have a strong objection to this specific
> case.
Agreed then.
Yoshihiro, could you please ignore the Mani' comment regarding the
"descending alignment" order and retain the fields order is in your
current patch?
I'll get back to the series review tomorrow. Please no rush with
resubmitting.
-Serge(y)
>
> - Mani
>
> > -Serge(y)
> >
> > >
> > > - Mani
> > >
> > > > -Serge(y)
> > > >
> > > > >
> > > > > - Mani
> > > > >
> > > > > > +};
> > > > > > +
> > > > > > struct dw_pcie_host_ops {
> > > > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > > --
> > > > > > 2.25.1
> > > > > >
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
2023-07-24 7:45 ` Manivannan Sadhasivam
@ 2023-07-29 2:06 ` Serge Semin
2023-07-31 1:24 ` Yoshihiro Shimoda
1 sibling, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-29 2:06 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> To support INTx IRQs in the future, it requires an additional 2
> arguments. For improved code readability, introduce the struct
> dw_pcie_ob_atu_cfg and update the arguments of
> dw_pcie_prog_outbound_atu().
>
> Consequently, remove __dw_pcie_prog_outbound_atu() and
> dw_pcie_prog_ep_outbound_atu() because there is no longer
> a need.
>
> No behavior changes.
So you decided not to use a suggested by me in v17 more detailed patch
log? C&P it here just in case if you change your mind:
This is a preparation before adding the Msg-type outbound iATU
mapping. The respective update will require two more arguments added
to __dw_pcie_prog_outbound_atu(). That will make the already
complicated function prototype even more hard to comprehend accepting
_eight_ arguments. In order to prevent that and keep the code
more-or-less readable all the outbound iATU-related arguments are
moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
is supposed to be locally defined and populated with the outbound iATU
settings implied by the caller context.
As a result of the denoted change there is no longer need in having
the two distinctive methods for the Host and End-point outbound iATU
setups since the corresponding code can directly call the
dw_pcie_prog_outbound_atu() method with the config-structure
populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
-Serge(y)
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> 4 files changed, 77 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 27278010ecec..fe2e0d765be9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> return 0;
> }
>
> -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> - phys_addr_t phys_addr,
> - u64 pci_addr, size_t size)
> +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> + struct dw_pcie_ob_atu_cfg *atu)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> u32 free_win;
> @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> return -EINVAL;
> }
>
> - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> - phys_addr, pci_addr, size);
> + atu->index = free_win;
> + ret = dw_pcie_prog_outbound_atu(pci, atu);
> if (ret)
> return ret;
>
> set_bit(free_win, ep->ob_window_map);
> - ep->outbound_addr[free_win] = phys_addr;
> + ep->outbound_addr[free_win] = atu->cpu_addr;
>
> return 0;
> }
> @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> int ret;
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -
> - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> +
> + atu.func_no = func_no;
> + atu.type = PCIE_ATU_TYPE_MEM;
> + atu.cpu_addr = addr;
> + atu.pci_addr = pci_addr;
> + atu.size = size;
> + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to enable address\n");
> return ret;
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index cf61733bf78d..7419185721f2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int type, ret;
> u32 busdev;
>
> @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> else
> type = PCIE_ATU_TYPE_CFG1;
>
> - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> - pp->cfg0_size);
> + atu.type = type;
> + atu.cpu_addr = pp->cfg0_base;
> + atu.pci_addr = busdev;
> + atu.size = pp->cfg0_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return NULL;
>
> @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int ret;
>
> ret = pci_generic_config_read(bus, devfn, where, size, val);
> @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> return ret;
>
> if (pp->cfg0_io_shared) {
> - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> - pp->io_base, pp->io_bus_addr,
> - pp->io_size);
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return PCIBIOS_SET_FAILED;
> }
> @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> {
> struct dw_pcie_rp *pp = bus->sysdata;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> int ret;
>
> ret = pci_generic_config_write(bus, devfn, where, size, val);
> @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> return ret;
>
> if (pp->cfg0_io_shared) {
> - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> - pp->io_base, pp->io_bus_addr,
> - pp->io_size);
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret)
> return PCIBIOS_SET_FAILED;
> }
> @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> struct resource_entry *entry;
> int i, ret;
>
> @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> if (pci->num_ob_windows <= ++i)
> break;
>
> - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> - entry->res->start,
> - entry->res->start - entry->offset,
> - resource_size(entry->res));
> + atu.index = i;
> + atu.type = PCIE_ATU_TYPE_MEM;
> + atu.cpu_addr = entry->res->start;
> + atu.pci_addr = entry->res->start - entry->offset;
> + atu.size = resource_size(entry->res);
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to set MEM range %pr\n",
> entry->res);
> @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>
> if (pp->io_size) {
> if (pci->num_ob_windows > ++i) {
> - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> - pp->io_base,
> - pp->io_bus_addr,
> - pp->io_size);
> + atu.index = i;
> + atu.type = PCIE_ATU_TYPE_IO;
> + atu.cpu_addr = pp->io_base;
> + atu.pci_addr = pp->io_bus_addr;
> + atu.size = pp->io_size;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret) {
> dev_err(pci->dev, "Failed to set IO range %pr\n",
> entry->res);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2459f2a61b9b..49b785509576 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> return val | PCIE_ATU_TD;
> }
>
> -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> - int index, int type, u64 cpu_addr,
> - u64 pci_addr, u64 size)
> +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> + const struct dw_pcie_ob_atu_cfg *atu)
> {
> + u64 cpu_addr = atu->cpu_addr;
> u32 retries, val;
> u64 limit_addr;
>
> if (pci->ops && pci->ops->cpu_addr_fixup)
> cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
>
> - limit_addr = cpu_addr + size - 1;
> + limit_addr = cpu_addr + atu->size - 1;
>
> if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> !IS_ALIGNED(cpu_addr, pci->region_align) ||
> - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> return -EINVAL;
> }
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> lower_32_bits(cpu_addr));
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> upper_32_bits(cpu_addr));
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> lower_32_bits(limit_addr));
> if (dw_pcie_ver_is_ge(pci, 460A))
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> upper_32_bits(limit_addr));
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> - lower_32_bits(pci_addr));
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> - upper_32_bits(pci_addr));
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> + lower_32_bits(atu->pci_addr));
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> + upper_32_bits(atu->pci_addr));
>
> - val = type | PCIE_ATU_FUNC_NUM(func_no);
> + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> dw_pcie_ver_is_ge(pci, 460A))
> val |= PCIE_ATU_INCREASE_REGION_SIZE;
> if (dw_pcie_ver_is(pci, 490A))
> val = dw_pcie_enable_ecrc(val);
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>
> - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
>
> /*
> * Make sure ATU enable takes effect before any subsequent config
> * and I/O accesses.
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> if (val & PCIE_ATU_ENABLE)
> return 0;
>
> @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> return -ETIMEDOUT;
> }
>
> -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u64 size)
> -{
> - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> - cpu_addr, pci_addr, size);
> -}
> -
> -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> - int type, u64 cpu_addr, u64 pci_addr,
> - u64 size)
> -{
> - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> - cpu_addr, pci_addr, size);
> -}
> -
> static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> {
> return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 3c06e025c905..85de0d8346fa 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> DW_PCIE_NUM_CORE_RSTS
> };
>
> +struct dw_pcie_ob_atu_cfg {
> + int index;
> + int type;
> + u8 func_no;
> + u64 cpu_addr;
> + u64 pci_addr;
> + u64 size;
> +};
> +
> struct dw_pcie_host_ops {
> int (*host_init)(struct dw_pcie_rp *pp);
> void (*host_deinit)(struct dw_pcie_rp *pp);
> @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> int dw_pcie_link_up(struct dw_pcie *pci);
> void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u64 size);
> -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> + const struct dw_pcie_ob_atu_cfg *atu);
> int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> u64 cpu_addr, u64 pci_addr, u64 size);
> int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-29 2:06 ` Serge Semin
@ 2023-07-31 1:24 ` Yoshihiro Shimoda
2023-07-31 21:33 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-31 1:24 UTC (permalink / raw)
To: Serge Semin
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Saturday, July 29, 2023 11:07 AM
>
> On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > To support INTx IRQs in the future, it requires an additional 2
> > arguments. For improved code readability, introduce the struct
> > dw_pcie_ob_atu_cfg and update the arguments of
> > dw_pcie_prog_outbound_atu().
> >
> > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > a need.
> >
> > No behavior changes.
>
> So you decided not to use a suggested by me in v17 more detailed patch
> log?
You're correct. I thought your suggested comments was too detailed.
Best regards,
Yoshihiro Shimoda
> C&P it here just in case if you change your mind:
>
> This is a preparation before adding the Msg-type outbound iATU
> mapping. The respective update will require two more arguments added
> to __dw_pcie_prog_outbound_atu(). That will make the already
> complicated function prototype even more hard to comprehend accepting
> _eight_ arguments. In order to prevent that and keep the code
> more-or-less readable all the outbound iATU-related arguments are
> moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> is supposed to be locally defined and populated with the outbound iATU
> settings implied by the caller context.
>
> As a result of the denoted change there is no longer need in having
> the two distinctive methods for the Host and End-point outbound iATU
> setups since the corresponding code can directly call the
> dw_pcie_prog_outbound_atu() method with the config-structure
> populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
>
> -Serge(y)
>
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > 4 files changed, 77 insertions(+), 60 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 27278010ecec..fe2e0d765be9 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> > return 0;
> > }
> >
> > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > - phys_addr_t phys_addr,
> > - u64 pci_addr, size_t size)
> > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > + struct dw_pcie_ob_atu_cfg *atu)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > u32 free_win;
> > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > return -EINVAL;
> > }
> >
> > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> > - phys_addr, pci_addr, size);
> > + atu->index = free_win;
> > + ret = dw_pcie_prog_outbound_atu(pci, atu);
> > if (ret)
> > return ret;
> >
> > set_bit(free_win, ep->ob_window_map);
> > - ep->outbound_addr[free_win] = phys_addr;
> > + ep->outbound_addr[free_win] = atu->cpu_addr;
> >
> > return 0;
> > }
> > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > int ret;
> > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > -
> > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > +
> > + atu.func_no = func_no;
> > + atu.type = PCIE_ATU_TYPE_MEM;
> > + atu.cpu_addr = addr;
> > + atu.pci_addr = pci_addr;
> > + atu.size = size;
> > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > if (ret) {
> > dev_err(pci->dev, "Failed to enable address\n");
> > return ret;
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index cf61733bf78d..7419185721f2 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > {
> > struct dw_pcie_rp *pp = bus->sysdata;
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > int type, ret;
> > u32 busdev;
> >
> > @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > else
> > type = PCIE_ATU_TYPE_CFG1;
> >
> > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> > - pp->cfg0_size);
> > + atu.type = type;
> > + atu.cpu_addr = pp->cfg0_base;
> > + atu.pci_addr = busdev;
> > + atu.size = pp->cfg0_size;
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret)
> > return NULL;
> >
> > @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > {
> > struct dw_pcie_rp *pp = bus->sysdata;
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > int ret;
> >
> > ret = pci_generic_config_read(bus, devfn, where, size, val);
> > @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > return ret;
> >
> > if (pp->cfg0_io_shared) {
> > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > - pp->io_base, pp->io_bus_addr,
> > - pp->io_size);
> > + atu.type = PCIE_ATU_TYPE_IO;
> > + atu.cpu_addr = pp->io_base;
> > + atu.pci_addr = pp->io_bus_addr;
> > + atu.size = pp->io_size;
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret)
> > return PCIBIOS_SET_FAILED;
> > }
> > @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > {
> > struct dw_pcie_rp *pp = bus->sysdata;
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > int ret;
> >
> > ret = pci_generic_config_write(bus, devfn, where, size, val);
> > @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > return ret;
> >
> > if (pp->cfg0_io_shared) {
> > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > - pp->io_base, pp->io_bus_addr,
> > - pp->io_size);
> > + atu.type = PCIE_ATU_TYPE_IO;
> > + atu.cpu_addr = pp->io_base;
> > + atu.pci_addr = pp->io_bus_addr;
> > + atu.size = pp->io_size;
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret)
> > return PCIBIOS_SET_FAILED;
> > }
> > @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > struct resource_entry *entry;
> > int i, ret;
> >
> > @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > if (pci->num_ob_windows <= ++i)
> > break;
> >
> > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> > - entry->res->start,
> > - entry->res->start - entry->offset,
> > - resource_size(entry->res));
> > + atu.index = i;
> > + atu.type = PCIE_ATU_TYPE_MEM;
> > + atu.cpu_addr = entry->res->start;
> > + atu.pci_addr = entry->res->start - entry->offset;
> > + atu.size = resource_size(entry->res);
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret) {
> > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > entry->res);
> > @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> >
> > if (pp->io_size) {
> > if (pci->num_ob_windows > ++i) {
> > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> > - pp->io_base,
> > - pp->io_bus_addr,
> > - pp->io_size);
> > + atu.index = i;
> > + atu.type = PCIE_ATU_TYPE_IO;
> > + atu.cpu_addr = pp->io_base;
> > + atu.pci_addr = pp->io_bus_addr;
> > + atu.size = pp->io_size;
> > +
> > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > if (ret) {
> > dev_err(pci->dev, "Failed to set IO range %pr\n",
> > entry->res);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 2459f2a61b9b..49b785509576 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > return val | PCIE_ATU_TD;
> > }
> >
> > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > - int index, int type, u64 cpu_addr,
> > - u64 pci_addr, u64 size)
> > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > + const struct dw_pcie_ob_atu_cfg *atu)
> > {
> > + u64 cpu_addr = atu->cpu_addr;
> > u32 retries, val;
> > u64 limit_addr;
> >
> > if (pci->ops && pci->ops->cpu_addr_fixup)
> > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> >
> > - limit_addr = cpu_addr + size - 1;
> > + limit_addr = cpu_addr + atu->size - 1;
> >
> > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > return -EINVAL;
> > }
> >
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > lower_32_bits(cpu_addr));
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > upper_32_bits(cpu_addr));
> >
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > lower_32_bits(limit_addr));
> > if (dw_pcie_ver_is_ge(pci, 460A))
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > upper_32_bits(limit_addr));
> >
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > - lower_32_bits(pci_addr));
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > - upper_32_bits(pci_addr));
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > + lower_32_bits(atu->pci_addr));
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > + upper_32_bits(atu->pci_addr));
> >
> > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > dw_pcie_ver_is_ge(pci, 460A))
> > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > if (dw_pcie_ver_is(pci, 490A))
> > val = dw_pcie_enable_ecrc(val);
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> >
> > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> >
> > /*
> > * Make sure ATU enable takes effect before any subsequent config
> > * and I/O accesses.
> > */
> > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > if (val & PCIE_ATU_ENABLE)
> > return 0;
> >
> > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > return -ETIMEDOUT;
> > }
> >
> > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > - u64 cpu_addr, u64 pci_addr, u64 size)
> > -{
> > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > - cpu_addr, pci_addr, size);
> > -}
> > -
> > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > - int type, u64 cpu_addr, u64 pci_addr,
> > - u64 size)
> > -{
> > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > - cpu_addr, pci_addr, size);
> > -}
> > -
> > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > {
> > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 3c06e025c905..85de0d8346fa 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > DW_PCIE_NUM_CORE_RSTS
> > };
> >
> > +struct dw_pcie_ob_atu_cfg {
> > + int index;
> > + int type;
> > + u8 func_no;
> > + u64 cpu_addr;
> > + u64 pci_addr;
> > + u64 size;
> > +};
> > +
> > struct dw_pcie_host_ops {
> > int (*host_init)(struct dw_pcie_rp *pp);
> > void (*host_deinit)(struct dw_pcie_rp *pp);
> > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > int dw_pcie_link_up(struct dw_pcie *pci);
> > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > - u64 cpu_addr, u64 pci_addr, u64 size);
> > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > + const struct dw_pcie_ob_atu_cfg *atu);
> > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > u64 cpu_addr, u64 pci_addr, u64 size);
> > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-31 1:24 ` Yoshihiro Shimoda
@ 2023-07-31 21:33 ` Serge Semin
2023-08-01 1:29 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-31 21:33 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Mon, Jul 31, 2023 at 01:24:27AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Saturday, July 29, 2023 11:07 AM
> >
> > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > To support INTx IRQs in the future, it requires an additional 2
> > > arguments. For improved code readability, introduce the struct
> > > dw_pcie_ob_atu_cfg and update the arguments of
> > > dw_pcie_prog_outbound_atu().
> > >
> > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > a need.
> > >
> > > No behavior changes.
> >
> > So you decided not to use a suggested by me in v17 more detailed patch
> > log?
>
> You're correct. I thought your suggested comments was too detailed.
I strongly recommend for you to use mine instead. It gives more
details about the change and the patch context. Moreover it much more
clearer justifies the change implemented in the patch.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > C&P it here just in case if you change your mind:
> >
> > This is a preparation before adding the Msg-type outbound iATU
> > mapping. The respective update will require two more arguments added
> > to __dw_pcie_prog_outbound_atu(). That will make the already
> > complicated function prototype even more hard to comprehend accepting
> > _eight_ arguments. In order to prevent that and keep the code
> > more-or-less readable all the outbound iATU-related arguments are
> > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> > is supposed to be locally defined and populated with the outbound iATU
> > settings implied by the caller context.
> >
> > As a result of the denoted change there is no longer need in having
> > the two distinctive methods for the Host and End-point outbound iATU
> > setups since the corresponding code can directly call the
> > dw_pcie_prog_outbound_atu() method with the config-structure
> > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
> >
> > -Serge(y)
> >
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > ---
> > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > index 27278010ecec..fe2e0d765be9 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> > > return 0;
> > > }
> > >
> > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > - phys_addr_t phys_addr,
> > > - u64 pci_addr, size_t size)
> > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > > + struct dw_pcie_ob_atu_cfg *atu)
> > > {
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > u32 free_win;
> > > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > return -EINVAL;
> > > }
> > >
> > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> > > - phys_addr, pci_addr, size);
> > > + atu->index = free_win;
> > > + ret = dw_pcie_prog_outbound_atu(pci, atu);
> > > if (ret)
> > > return ret;
> > >
> > > set_bit(free_win, ep->ob_window_map);
> > > - ep->outbound_addr[free_win] = phys_addr;
> > > + ep->outbound_addr[free_win] = atu->cpu_addr;
> > >
> > > return 0;
> > > }
> > > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > int ret;
> > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > -
> > > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > +
> > > + atu.func_no = func_no;
> > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > + atu.cpu_addr = addr;
> > > + atu.pci_addr = pci_addr;
> > > + atu.size = size;
> > > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > > if (ret) {
> > > dev_err(pci->dev, "Failed to enable address\n");
> > > return ret;
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > index cf61733bf78d..7419185721f2 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > {
> > > struct dw_pcie_rp *pp = bus->sysdata;
> > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > int type, ret;
> > > u32 busdev;
> > >
> > > @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > else
> > > type = PCIE_ATU_TYPE_CFG1;
> > >
> > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> > > - pp->cfg0_size);
> > > + atu.type = type;
> > > + atu.cpu_addr = pp->cfg0_base;
> > > + atu.pci_addr = busdev;
> > > + atu.size = pp->cfg0_size;
> > > +
> > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > if (ret)
> > > return NULL;
> > >
> > > @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > {
> > > struct dw_pcie_rp *pp = bus->sysdata;
> > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > int ret;
> > >
> > > ret = pci_generic_config_read(bus, devfn, where, size, val);
> > > @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > return ret;
> > >
> > > if (pp->cfg0_io_shared) {
> > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > - pp->io_base, pp->io_bus_addr,
> > > - pp->io_size);
> > > + atu.type = PCIE_ATU_TYPE_IO;
> > > + atu.cpu_addr = pp->io_base;
> > > + atu.pci_addr = pp->io_bus_addr;
> > > + atu.size = pp->io_size;
> > > +
> > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > if (ret)
> > > return PCIBIOS_SET_FAILED;
> > > }
> > > @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > {
> > > struct dw_pcie_rp *pp = bus->sysdata;
> > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > int ret;
> > >
> > > ret = pci_generic_config_write(bus, devfn, where, size, val);
> > > @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > return ret;
> > >
> > > if (pp->cfg0_io_shared) {
> > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > - pp->io_base, pp->io_bus_addr,
> > > - pp->io_size);
> > > + atu.type = PCIE_ATU_TYPE_IO;
> > > + atu.cpu_addr = pp->io_base;
> > > + atu.pci_addr = pp->io_bus_addr;
> > > + atu.size = pp->io_size;
> > > +
> > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > if (ret)
> > > return PCIBIOS_SET_FAILED;
> > > }
> > > @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> > > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > {
> > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > struct resource_entry *entry;
> > > int i, ret;
> > >
> > > @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > if (pci->num_ob_windows <= ++i)
> > > break;
> > >
> > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> > > - entry->res->start,
> > > - entry->res->start - entry->offset,
> > > - resource_size(entry->res));
> > > + atu.index = i;
> > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > + atu.cpu_addr = entry->res->start;
> > > + atu.pci_addr = entry->res->start - entry->offset;
> > > + atu.size = resource_size(entry->res);
> > > +
> > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > if (ret) {
> > > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > > entry->res);
> > > @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > >
> > > if (pp->io_size) {
> > > if (pci->num_ob_windows > ++i) {
> > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> > > - pp->io_base,
> > > - pp->io_bus_addr,
> > > - pp->io_size);
> > > + atu.index = i;
> > > + atu.type = PCIE_ATU_TYPE_IO;
> > > + atu.cpu_addr = pp->io_base;
> > > + atu.pci_addr = pp->io_bus_addr;
> > > + atu.size = pp->io_size;
> > > +
> > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > if (ret) {
> > > dev_err(pci->dev, "Failed to set IO range %pr\n",
> > > entry->res);
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > index 2459f2a61b9b..49b785509576 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > > return val | PCIE_ATU_TD;
> > > }
> > >
> > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > - int index, int type, u64 cpu_addr,
> > > - u64 pci_addr, u64 size)
> > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > + const struct dw_pcie_ob_atu_cfg *atu)
> > > {
> > > + u64 cpu_addr = atu->cpu_addr;
> > > u32 retries, val;
> > > u64 limit_addr;
> > >
> > > if (pci->ops && pci->ops->cpu_addr_fixup)
> > > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > >
> > > - limit_addr = cpu_addr + size - 1;
> > > + limit_addr = cpu_addr + atu->size - 1;
> > >
> > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > > !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > > return -EINVAL;
> > > }
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > > lower_32_bits(cpu_addr));
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > > upper_32_bits(cpu_addr));
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > > lower_32_bits(limit_addr));
> > > if (dw_pcie_ver_is_ge(pci, 460A))
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > > upper_32_bits(limit_addr));
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > > - lower_32_bits(pci_addr));
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > > - upper_32_bits(pci_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > > + lower_32_bits(atu->pci_addr));
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > + upper_32_bits(atu->pci_addr));
> > >
> > > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > dw_pcie_ver_is_ge(pci, 460A))
> > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > if (dw_pcie_ver_is(pci, 490A))
> > > val = dw_pcie_enable_ecrc(val);
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > >
> > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > >
> > > /*
> > > * Make sure ATU enable takes effect before any subsequent config
> > > * and I/O accesses.
> > > */
> > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > > if (val & PCIE_ATU_ENABLE)
> > > return 0;
> > >
> > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > return -ETIMEDOUT;
> > > }
> > >
> > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > - u64 cpu_addr, u64 pci_addr, u64 size)
> > > -{
> > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > > - cpu_addr, pci_addr, size);
> > > -}
> > > -
> > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > - int type, u64 cpu_addr, u64 pci_addr,
> > > - u64 size)
> > > -{
> > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > > - cpu_addr, pci_addr, size);
> > > -}
> > > -
> > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > > {
> > > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 3c06e025c905..85de0d8346fa 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > DW_PCIE_NUM_CORE_RSTS
> > > };
> > >
> > > +struct dw_pcie_ob_atu_cfg {
> > > + int index;
> > > + int type;
> > > + u8 func_no;
> > > + u64 cpu_addr;
> > > + u64 pci_addr;
> > > + u64 size;
> > > +};
> > > +
> > > struct dw_pcie_host_ops {
> > > int (*host_init)(struct dw_pcie_rp *pp);
> > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-07-31 21:33 ` Serge Semin
@ 2023-08-01 1:29 ` Yoshihiro Shimoda
2023-08-01 1:44 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 1:29 UTC (permalink / raw)
To: Serge Semin
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 6:33 AM
>
> On Mon, Jul 31, 2023 at 01:24:27AM +0000, Yoshihiro Shimoda wrote:
> > Hi Serge,
> >
> > > From: Serge Semin, Sent: Saturday, July 29, 2023 11:07 AM
> > >
> > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > To support INTx IRQs in the future, it requires an additional 2
> > > > arguments. For improved code readability, introduce the struct
> > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > dw_pcie_prog_outbound_atu().
> > > >
> > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > a need.
> > > >
> > > > No behavior changes.
> > >
> > > So you decided not to use a suggested by me in v17 more detailed patch
> > > log?
> >
> > You're correct. I thought your suggested comments was too detailed.
>
> I strongly recommend for you to use mine instead. It gives more
> details about the change and the patch context. Moreover it much more
> clearer justifies the change implemented in the patch.
I didn't realize that you have a strong recommendation about the comments
you suggested. I'll replace the commit description and add your Suggested-by
tag on v19.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > C&P it here just in case if you change your mind:
> > >
> > > This is a preparation before adding the Msg-type outbound iATU
> > > mapping. The respective update will require two more arguments added
> > > to __dw_pcie_prog_outbound_atu(). That will make the already
> > > complicated function prototype even more hard to comprehend accepting
> > > _eight_ arguments. In order to prevent that and keep the code
> > > more-or-less readable all the outbound iATU-related arguments are
> > > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> > > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> > > is supposed to be locally defined and populated with the outbound iATU
> > > settings implied by the caller context.
> > >
> > > As a result of the denoted change there is no longer need in having
> > > the two distinctive methods for the Host and End-point outbound iATU
> > > setups since the corresponding code can directly call the
> > > dw_pcie_prog_outbound_atu() method with the config-structure
> > > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
> > >
> > > -Serge(y)
> > >
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > ---
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > index 27278010ecec..fe2e0d765be9 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> > > > return 0;
> > > > }
> > > >
> > > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > - phys_addr_t phys_addr,
> > > > - u64 pci_addr, size_t size)
> > > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > > > + struct dw_pcie_ob_atu_cfg *atu)
> > > > {
> > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > u32 free_win;
> > > > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > return -EINVAL;
> > > > }
> > > >
> > > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> > > > - phys_addr, pci_addr, size);
> > > > + atu->index = free_win;
> > > > + ret = dw_pcie_prog_outbound_atu(pci, atu);
> > > > if (ret)
> > > > return ret;
> > > >
> > > > set_bit(free_win, ep->ob_window_map);
> > > > - ep->outbound_addr[free_win] = phys_addr;
> > > > + ep->outbound_addr[free_win] = atu->cpu_addr;
> > > >
> > > > return 0;
> > > > }
> > > > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > > int ret;
> > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > -
> > > > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > +
> > > > + atu.func_no = func_no;
> > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > + atu.cpu_addr = addr;
> > > > + atu.pci_addr = pci_addr;
> > > > + atu.size = size;
> > > > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > > > if (ret) {
> > > > dev_err(pci->dev, "Failed to enable address\n");
> > > > return ret;
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > index cf61733bf78d..7419185721f2 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > {
> > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > int type, ret;
> > > > u32 busdev;
> > > >
> > > > @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > else
> > > > type = PCIE_ATU_TYPE_CFG1;
> > > >
> > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> > > > - pp->cfg0_size);
> > > > + atu.type = type;
> > > > + atu.cpu_addr = pp->cfg0_base;
> > > > + atu.pci_addr = busdev;
> > > > + atu.size = pp->cfg0_size;
> > > > +
> > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > if (ret)
> > > > return NULL;
> > > >
> > > > @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > {
> > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > int ret;
> > > >
> > > > ret = pci_generic_config_read(bus, devfn, where, size, val);
> > > > @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > return ret;
> > > >
> > > > if (pp->cfg0_io_shared) {
> > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > - pp->io_base, pp->io_bus_addr,
> > > > - pp->io_size);
> > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > + atu.cpu_addr = pp->io_base;
> > > > + atu.pci_addr = pp->io_bus_addr;
> > > > + atu.size = pp->io_size;
> > > > +
> > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > if (ret)
> > > > return PCIBIOS_SET_FAILED;
> > > > }
> > > > @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > {
> > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > int ret;
> > > >
> > > > ret = pci_generic_config_write(bus, devfn, where, size, val);
> > > > @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > return ret;
> > > >
> > > > if (pp->cfg0_io_shared) {
> > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > - pp->io_base, pp->io_bus_addr,
> > > > - pp->io_size);
> > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > + atu.cpu_addr = pp->io_base;
> > > > + atu.pci_addr = pp->io_bus_addr;
> > > > + atu.size = pp->io_size;
> > > > +
> > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > if (ret)
> > > > return PCIBIOS_SET_FAILED;
> > > > }
> > > > @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> > > > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > {
> > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > struct resource_entry *entry;
> > > > int i, ret;
> > > >
> > > > @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > if (pci->num_ob_windows <= ++i)
> > > > break;
> > > >
> > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> > > > - entry->res->start,
> > > > - entry->res->start - entry->offset,
> > > > - resource_size(entry->res));
> > > > + atu.index = i;
> > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > + atu.cpu_addr = entry->res->start;
> > > > + atu.pci_addr = entry->res->start - entry->offset;
> > > > + atu.size = resource_size(entry->res);
> > > > +
> > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > if (ret) {
> > > > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > > > entry->res);
> > > > @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > >
> > > > if (pp->io_size) {
> > > > if (pci->num_ob_windows > ++i) {
> > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> > > > - pp->io_base,
> > > > - pp->io_bus_addr,
> > > > - pp->io_size);
> > > > + atu.index = i;
> > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > + atu.cpu_addr = pp->io_base;
> > > > + atu.pci_addr = pp->io_bus_addr;
> > > > + atu.size = pp->io_size;
> > > > +
> > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > if (ret) {
> > > > dev_err(pci->dev, "Failed to set IO range %pr\n",
> > > > entry->res);
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > index 2459f2a61b9b..49b785509576 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > > > return val | PCIE_ATU_TD;
> > > > }
> > > >
> > > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > - int index, int type, u64 cpu_addr,
> > > > - u64 pci_addr, u64 size)
> > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > + const struct dw_pcie_ob_atu_cfg *atu)
> > > > {
> > > > + u64 cpu_addr = atu->cpu_addr;
> > > > u32 retries, val;
> > > > u64 limit_addr;
> > > >
> > > > if (pci->ops && pci->ops->cpu_addr_fixup)
> > > > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > > >
> > > > - limit_addr = cpu_addr + size - 1;
> > > > + limit_addr = cpu_addr + atu->size - 1;
> > > >
> > > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > > > !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > > > return -EINVAL;
> > > > }
> > > >
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > > > lower_32_bits(cpu_addr));
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > > > upper_32_bits(cpu_addr));
> > > >
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > > > lower_32_bits(limit_addr));
> > > > if (dw_pcie_ver_is_ge(pci, 460A))
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > > > upper_32_bits(limit_addr));
> > > >
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > > > - lower_32_bits(pci_addr));
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > > > - upper_32_bits(pci_addr));
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > > > + lower_32_bits(atu->pci_addr));
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > > + upper_32_bits(atu->pci_addr));
> > > >
> > > > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > > dw_pcie_ver_is_ge(pci, 460A))
> > > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > > if (dw_pcie_ver_is(pci, 490A))
> > > > val = dw_pcie_enable_ecrc(val);
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > > >
> > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > >
> > > > /*
> > > > * Make sure ATU enable takes effect before any subsequent config
> > > > * and I/O accesses.
> > > > */
> > > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > > > if (val & PCIE_ATU_ENABLE)
> > > > return 0;
> > > >
> > > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > return -ETIMEDOUT;
> > > > }
> > > >
> > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > - u64 cpu_addr, u64 pci_addr, u64 size)
> > > > -{
> > > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > > > - cpu_addr, pci_addr, size);
> > > > -}
> > > > -
> > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > - int type, u64 cpu_addr, u64 pci_addr,
> > > > - u64 size)
> > > > -{
> > > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > > > - cpu_addr, pci_addr, size);
> > > > -}
> > > > -
> > > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > > > {
> > > > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > index 3c06e025c905..85de0d8346fa 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > DW_PCIE_NUM_CORE_RSTS
> > > > };
> > > >
> > > > +struct dw_pcie_ob_atu_cfg {
> > > > + int index;
> > > > + int type;
> > > > + u8 func_no;
> > > > + u64 cpu_addr;
> > > > + u64 pci_addr;
> > > > + u64 size;
> > > > +};
> > > > +
> > > > struct dw_pcie_host_ops {
> > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > --
> > > > 2.25.1
> > > >
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-08-01 1:29 ` Yoshihiro Shimoda
@ 2023-08-01 1:44 ` Serge Semin
2023-08-01 7:02 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-01 1:44 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Tue, Aug 01, 2023 at 01:29:10AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Tuesday, August 1, 2023 6:33 AM
> >
> > On Mon, Jul 31, 2023 at 01:24:27AM +0000, Yoshihiro Shimoda wrote:
> > > Hi Serge,
> > >
> > > > From: Serge Semin, Sent: Saturday, July 29, 2023 11:07 AM
> > > >
> > > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > > To support INTx IRQs in the future, it requires an additional 2
> > > > > arguments. For improved code readability, introduce the struct
> > > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > > dw_pcie_prog_outbound_atu().
> > > > >
> > > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > > a need.
> > > > >
> > > > > No behavior changes.
> > > >
> > > > So you decided not to use a suggested by me in v17 more detailed patch
> > > > log?
> > >
> > > You're correct. I thought your suggested comments was too detailed.
> >
> > I strongly recommend for you to use mine instead. It gives more
> > details about the change and the patch context. Moreover it much more
> > clearer justifies the change implemented in the patch.
>
> I didn't realize that you have a strong recommendation about the comments
> you suggested. I'll replace the commit description and add your Suggested-by
> tag on v19.
Just to note if there is a misunderstanding on your side. Suggested-by tag is
relevant to the patch idea in general.
See Documentation/process/submitting-patches.rst:559 for details.
So you don't need to add the tag if somebody just suggested an
alternative patch description.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > -Serge(y)
> >
> > >
> > > Best regards,
> > > Yoshihiro Shimoda
> > >
> > > > C&P it here just in case if you change your mind:
> > > >
> > > > This is a preparation before adding the Msg-type outbound iATU
> > > > mapping. The respective update will require two more arguments added
> > > > to __dw_pcie_prog_outbound_atu(). That will make the already
> > > > complicated function prototype even more hard to comprehend accepting
> > > > _eight_ arguments. In order to prevent that and keep the code
> > > > more-or-less readable all the outbound iATU-related arguments are
> > > > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> > > > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> > > > is supposed to be locally defined and populated with the outbound iATU
> > > > settings implied by the caller context.
> > > >
> > > > As a result of the denoted change there is no longer need in having
> > > > the two distinctive methods for the Host and End-point outbound iATU
> > > > setups since the corresponding code can directly call the
> > > > dw_pcie_prog_outbound_atu() method with the config-structure
> > > > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
> > > >
> > > > -Serge(y)
> > > >
> > > > >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > ---
> > > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > index 27278010ecec..fe2e0d765be9 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > > - phys_addr_t phys_addr,
> > > > > - u64 pci_addr, size_t size)
> > > > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > > > > + struct dw_pcie_ob_atu_cfg *atu)
> > > > > {
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > u32 free_win;
> > > > > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> > > > > - phys_addr, pci_addr, size);
> > > > > + atu->index = free_win;
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, atu);
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > set_bit(free_win, ep->ob_window_map);
> > > > > - ep->outbound_addr[free_win] = phys_addr;
> > > > > + ep->outbound_addr[free_win] = atu->cpu_addr;
> > > > >
> > > > > return 0;
> > > > > }
> > > > > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > > > int ret;
> > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > -
> > > > > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > +
> > > > > + atu.func_no = func_no;
> > > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > > + atu.cpu_addr = addr;
> > > > > + atu.pci_addr = pci_addr;
> > > > > + atu.size = size;
> > > > > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > > > > if (ret) {
> > > > > dev_err(pci->dev, "Failed to enable address\n");
> > > > > return ret;
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > index cf61733bf78d..7419185721f2 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > > {
> > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > int type, ret;
> > > > > u32 busdev;
> > > > >
> > > > > @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > > else
> > > > > type = PCIE_ATU_TYPE_CFG1;
> > > > >
> > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> > > > > - pp->cfg0_size);
> > > > > + atu.type = type;
> > > > > + atu.cpu_addr = pp->cfg0_base;
> > > > > + atu.pci_addr = busdev;
> > > > > + atu.size = pp->cfg0_size;
> > > > > +
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > if (ret)
> > > > > return NULL;
> > > > >
> > > > > @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > {
> > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > int ret;
> > > > >
> > > > > ret = pci_generic_config_read(bus, devfn, where, size, val);
> > > > > @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > return ret;
> > > > >
> > > > > if (pp->cfg0_io_shared) {
> > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > > - pp->io_base, pp->io_bus_addr,
> > > > > - pp->io_size);
> > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > + atu.cpu_addr = pp->io_base;
> > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > + atu.size = pp->io_size;
> > > > > +
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > if (ret)
> > > > > return PCIBIOS_SET_FAILED;
> > > > > }
> > > > > @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > {
> > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > int ret;
> > > > >
> > > > > ret = pci_generic_config_write(bus, devfn, where, size, val);
> > > > > @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > return ret;
> > > > >
> > > > > if (pp->cfg0_io_shared) {
> > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > > - pp->io_base, pp->io_bus_addr,
> > > > > - pp->io_size);
> > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > + atu.cpu_addr = pp->io_base;
> > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > + atu.size = pp->io_size;
> > > > > +
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > if (ret)
> > > > > return PCIBIOS_SET_FAILED;
> > > > > }
> > > > > @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> > > > > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > > {
> > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > struct resource_entry *entry;
> > > > > int i, ret;
> > > > >
> > > > > @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > > if (pci->num_ob_windows <= ++i)
> > > > > break;
> > > > >
> > > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> > > > > - entry->res->start,
> > > > > - entry->res->start - entry->offset,
> > > > > - resource_size(entry->res));
> > > > > + atu.index = i;
> > > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > > + atu.cpu_addr = entry->res->start;
> > > > > + atu.pci_addr = entry->res->start - entry->offset;
> > > > > + atu.size = resource_size(entry->res);
> > > > > +
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > if (ret) {
> > > > > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > > > > entry->res);
> > > > > @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > >
> > > > > if (pp->io_size) {
> > > > > if (pci->num_ob_windows > ++i) {
> > > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> > > > > - pp->io_base,
> > > > > - pp->io_bus_addr,
> > > > > - pp->io_size);
> > > > > + atu.index = i;
> > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > + atu.cpu_addr = pp->io_base;
> > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > + atu.size = pp->io_size;
> > > > > +
> > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > if (ret) {
> > > > > dev_err(pci->dev, "Failed to set IO range %pr\n",
> > > > > entry->res);
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > index 2459f2a61b9b..49b785509576 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > > > > return val | PCIE_ATU_TD;
> > > > > }
> > > > >
> > > > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > > - int index, int type, u64 cpu_addr,
> > > > > - u64 pci_addr, u64 size)
> > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > + const struct dw_pcie_ob_atu_cfg *atu)
> > > > > {
> > > > > + u64 cpu_addr = atu->cpu_addr;
> > > > > u32 retries, val;
> > > > > u64 limit_addr;
> > > > >
> > > > > if (pci->ops && pci->ops->cpu_addr_fixup)
> > > > > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > > > >
> > > > > - limit_addr = cpu_addr + size - 1;
> > > > > + limit_addr = cpu_addr + atu->size - 1;
> > > > >
> > > > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > > > > !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > > > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > > > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > > > > return -EINVAL;
> > > > > }
> > > > >
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > > > > lower_32_bits(cpu_addr));
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > > > > upper_32_bits(cpu_addr));
> > > > >
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > > > > lower_32_bits(limit_addr));
> > > > > if (dw_pcie_ver_is_ge(pci, 460A))
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > > > > upper_32_bits(limit_addr));
> > > > >
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > > > > - lower_32_bits(pci_addr));
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > > > > - upper_32_bits(pci_addr));
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > > > > + lower_32_bits(atu->pci_addr));
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > > > + upper_32_bits(atu->pci_addr));
> > > > >
> > > > > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > > > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > > > dw_pcie_ver_is_ge(pci, 460A))
> > > > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > > > if (dw_pcie_ver_is(pci, 490A))
> > > > > val = dw_pcie_enable_ecrc(val);
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > > > >
> > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > >
> > > > > /*
> > > > > * Make sure ATU enable takes effect before any subsequent config
> > > > > * and I/O accesses.
> > > > > */
> > > > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > > > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > > > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > > > > if (val & PCIE_ATU_ENABLE)
> > > > > return 0;
> > > > >
> > > > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > > return -ETIMEDOUT;
> > > > > }
> > > > >
> > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > - u64 cpu_addr, u64 pci_addr, u64 size)
> > > > > -{
> > > > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > > > > - cpu_addr, pci_addr, size);
> > > > > -}
> > > > > -
> > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > - int type, u64 cpu_addr, u64 pci_addr,
> > > > > - u64 size)
> > > > > -{
> > > > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > > > > - cpu_addr, pci_addr, size);
> > > > > -}
> > > > > -
> > > > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > > > > {
> > > > > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > index 3c06e025c905..85de0d8346fa 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > > DW_PCIE_NUM_CORE_RSTS
> > > > > };
> > > > >
> > > > > +struct dw_pcie_ob_atu_cfg {
> > > > > + int index;
> > > > > + int type;
> > > > > + u8 func_no;
> > > > > + u64 cpu_addr;
> > > > > + u64 pci_addr;
> > > > > + u64 size;
> > > > > +};
> > > > > +
> > > > > struct dw_pcie_host_ops {
> > > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > --
> > > > > 2.25.1
> > > > >
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
2023-08-01 1:44 ` Serge Semin
@ 2023-08-01 7:02 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 7:02 UTC (permalink / raw)
To: Serge Semin
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 10:45 AM
>
> On Tue, Aug 01, 2023 at 01:29:10AM +0000, Yoshihiro Shimoda wrote:
> > Hi Serge,
> >
> > > From: Serge Semin, Sent: Tuesday, August 1, 2023 6:33 AM
> > >
> > > On Mon, Jul 31, 2023 at 01:24:27AM +0000, Yoshihiro Shimoda wrote:
> > > > Hi Serge,
> > > >
> > > > > From: Serge Semin, Sent: Saturday, July 29, 2023 11:07 AM
> > > > >
> > > > > On Fri, Jul 21, 2023 at 04:44:36PM +0900, Yoshihiro Shimoda wrote:
> > > > > > The __dw_pcie_prog_outbound_atu() currently has 6 arguments.
> > > > > > To support INTx IRQs in the future, it requires an additional 2
> > > > > > arguments. For improved code readability, introduce the struct
> > > > > > dw_pcie_ob_atu_cfg and update the arguments of
> > > > > > dw_pcie_prog_outbound_atu().
> > > > > >
> > > > > > Consequently, remove __dw_pcie_prog_outbound_atu() and
> > > > > > dw_pcie_prog_ep_outbound_atu() because there is no longer
> > > > > > a need.
> > > > > >
> > > > > > No behavior changes.
> > > > >
> > > > > So you decided not to use a suggested by me in v17 more detailed patch
> > > > > log?
> > > >
> > > > You're correct. I thought your suggested comments was too detailed.
> > >
> > > I strongly recommend for you to use mine instead. It gives more
> > > details about the change and the patch context. Moreover it much more
> > > clearer justifies the change implemented in the patch.
> >
>
> > I didn't realize that you have a strong recommendation about the comments
> > you suggested. I'll replace the commit description and add your Suggested-by
> > tag on v19.
>
> Just to note if there is a misunderstanding on your side. Suggested-by tag is
> relevant to the patch idea in general.
> See Documentation/process/submitting-patches.rst:559 for details.
> So you don't need to add the tag if somebody just suggested an
> alternative patch description.
Thank you for your comments. So, I will not add Suggested-by tag.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > -Serge(y)
> > >
> > > >
> > > > Best regards,
> > > > Yoshihiro Shimoda
> > > >
> > > > > C&P it here just in case if you change your mind:
> > > > >
> > > > > This is a preparation before adding the Msg-type outbound iATU
> > > > > mapping. The respective update will require two more arguments added
> > > > > to __dw_pcie_prog_outbound_atu(). That will make the already
> > > > > complicated function prototype even more hard to comprehend accepting
> > > > > _eight_ arguments. In order to prevent that and keep the code
> > > > > more-or-less readable all the outbound iATU-related arguments are
> > > > > moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer
> > > > > to which shall be passed to dw_pcie_prog_outbound_atu(). The structure
> > > > > is supposed to be locally defined and populated with the outbound iATU
> > > > > settings implied by the caller context.
> > > > >
> > > > > As a result of the denoted change there is no longer need in having
> > > > > the two distinctive methods for the Host and End-point outbound iATU
> > > > > setups since the corresponding code can directly call the
> > > > > dw_pcie_prog_outbound_atu() method with the config-structure
> > > > > populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped.
> > > > >
> > > > > -Serge(y)
> > > > >
> > > > > >
> > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > ---
> > > > > > .../pci/controller/dwc/pcie-designware-ep.c | 21 +++++---
> > > > > > .../pci/controller/dwc/pcie-designware-host.c | 52 +++++++++++++------
> > > > > > drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++-----------
> > > > > > drivers/pci/controller/dwc/pcie-designware.h | 15 ++++--
> > > > > > 4 files changed, 77 insertions(+), 60 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > > index 27278010ecec..fe2e0d765be9 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > > > @@ -182,9 +182,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type,
> > > > > > return 0;
> > > > > > }
> > > > > >
> > > > > > -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > > > - phys_addr_t phys_addr,
> > > > > > - u64 pci_addr, size_t size)
> > > > > > +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep,
> > > > > > + struct dw_pcie_ob_atu_cfg *atu)
> > > > > > {
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > > u32 free_win;
> > > > > > @@ -196,13 +195,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no,
> > > > > > return -EINVAL;
> > > > > > }
> > > > > >
> > > > > > - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM,
> > > > > > - phys_addr, pci_addr, size);
> > > > > > + atu->index = free_win;
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, atu);
> > > > > > if (ret)
> > > > > > return ret;
> > > > > >
> > > > > > set_bit(free_win, ep->ob_window_map);
> > > > > > - ep->outbound_addr[free_win] = phys_addr;
> > > > > > + ep->outbound_addr[free_win] = atu->cpu_addr;
> > > > > >
> > > > > > return 0;
> > > > > > }
> > > > > > @@ -305,8 +304,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > > > > int ret;
> > > > > > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > > > -
> > > > > > - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size);
> > > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > > +
> > > > > > + atu.func_no = func_no;
> > > > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > > > + atu.cpu_addr = addr;
> > > > > > + atu.pci_addr = pci_addr;
> > > > > > + atu.size = size;
> > > > > > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > > > > > if (ret) {
> > > > > > dev_err(pci->dev, "Failed to enable address\n");
> > > > > > return ret;
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > index cf61733bf78d..7419185721f2 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > > > > > @@ -549,6 +549,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > > > {
> > > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > > int type, ret;
> > > > > > u32 busdev;
> > > > > >
> > > > > > @@ -571,8 +572,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
> > > > > > else
> > > > > > type = PCIE_ATU_TYPE_CFG1;
> > > > > >
> > > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev,
> > > > > > - pp->cfg0_size);
> > > > > > + atu.type = type;
> > > > > > + atu.cpu_addr = pp->cfg0_base;
> > > > > > + atu.pci_addr = busdev;
> > > > > > + atu.size = pp->cfg0_size;
> > > > > > +
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > > if (ret)
> > > > > > return NULL;
> > > > > >
> > > > > > @@ -584,6 +589,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > > {
> > > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > > int ret;
> > > > > >
> > > > > > ret = pci_generic_config_read(bus, devfn, where, size, val);
> > > > > > @@ -591,9 +597,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > > return ret;
> > > > > >
> > > > > > if (pp->cfg0_io_shared) {
> > > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > > > - pp->io_base, pp->io_bus_addr,
> > > > > > - pp->io_size);
> > > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > > + atu.cpu_addr = pp->io_base;
> > > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > > + atu.size = pp->io_size;
> > > > > > +
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > > if (ret)
> > > > > > return PCIBIOS_SET_FAILED;
> > > > > > }
> > > > > > @@ -606,6 +615,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > > {
> > > > > > struct dw_pcie_rp *pp = bus->sysdata;
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > > int ret;
> > > > > >
> > > > > > ret = pci_generic_config_write(bus, devfn, where, size, val);
> > > > > > @@ -613,9 +623,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
> > > > > > return ret;
> > > > > >
> > > > > > if (pp->cfg0_io_shared) {
> > > > > > - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO,
> > > > > > - pp->io_base, pp->io_bus_addr,
> > > > > > - pp->io_size);
> > > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > > + atu.cpu_addr = pp->io_base;
> > > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > > + atu.size = pp->io_size;
> > > > > > +
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > > if (ret)
> > > > > > return PCIBIOS_SET_FAILED;
> > > > > > }
> > > > > > @@ -650,6 +663,7 @@ static struct pci_ops dw_pcie_ops = {
> > > > > > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > > > {
> > > > > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > > > > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > > > > > struct resource_entry *entry;
> > > > > > int i, ret;
> > > > > >
> > > > > > @@ -677,10 +691,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > > > if (pci->num_ob_windows <= ++i)
> > > > > > break;
> > > > > >
> > > > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM,
> > > > > > - entry->res->start,
> > > > > > - entry->res->start - entry->offset,
> > > > > > - resource_size(entry->res));
> > > > > > + atu.index = i;
> > > > > > + atu.type = PCIE_ATU_TYPE_MEM;
> > > > > > + atu.cpu_addr = entry->res->start;
> > > > > > + atu.pci_addr = entry->res->start - entry->offset;
> > > > > > + atu.size = resource_size(entry->res);
> > > > > > +
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > > if (ret) {
> > > > > > dev_err(pci->dev, "Failed to set MEM range %pr\n",
> > > > > > entry->res);
> > > > > > @@ -690,10 +707,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> > > > > >
> > > > > > if (pp->io_size) {
> > > > > > if (pci->num_ob_windows > ++i) {
> > > > > > - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO,
> > > > > > - pp->io_base,
> > > > > > - pp->io_bus_addr,
> > > > > > - pp->io_size);
> > > > > > + atu.index = i;
> > > > > > + atu.type = PCIE_ATU_TYPE_IO;
> > > > > > + atu.cpu_addr = pp->io_base;
> > > > > > + atu.pci_addr = pp->io_bus_addr;
> > > > > > + atu.size = pp->io_size;
> > > > > > +
> > > > > > + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> > > > > > if (ret) {
> > > > > > dev_err(pci->dev, "Failed to set IO range %pr\n",
> > > > > > entry->res);
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > index 2459f2a61b9b..49b785509576 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > @@ -464,56 +464,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val)
> > > > > > return val | PCIE_ATU_TD;
> > > > > > }
> > > > > >
> > > > > > -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > > > - int index, int type, u64 cpu_addr,
> > > > > > - u64 pci_addr, u64 size)
> > > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > > + const struct dw_pcie_ob_atu_cfg *atu)
> > > > > > {
> > > > > > + u64 cpu_addr = atu->cpu_addr;
> > > > > > u32 retries, val;
> > > > > > u64 limit_addr;
> > > > > >
> > > > > > if (pci->ops && pci->ops->cpu_addr_fixup)
> > > > > > cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
> > > > > >
> > > > > > - limit_addr = cpu_addr + size - 1;
> > > > > > + limit_addr = cpu_addr + atu->size - 1;
> > > > > >
> > > > > > if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) ||
> > > > > > !IS_ALIGNED(cpu_addr, pci->region_align) ||
> > > > > > - !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> > > > > > + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) {
> > > > > > return -EINVAL;
> > > > > > }
> > > > > >
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE,
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE,
> > > > > > lower_32_bits(cpu_addr));
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE,
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE,
> > > > > > upper_32_bits(cpu_addr));
> > > > > >
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT,
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT,
> > > > > > lower_32_bits(limit_addr));
> > > > > > if (dw_pcie_ver_is_ge(pci, 460A))
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT,
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT,
> > > > > > upper_32_bits(limit_addr));
> > > > > >
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET,
> > > > > > - lower_32_bits(pci_addr));
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET,
> > > > > > - upper_32_bits(pci_addr));
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET,
> > > > > > + lower_32_bits(atu->pci_addr));
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > > > > + upper_32_bits(atu->pci_addr));
> > > > > >
> > > > > > - val = type | PCIE_ATU_FUNC_NUM(func_no);
> > > > > > + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > > > > dw_pcie_ver_is_ge(pci, 460A))
> > > > > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > > > > if (dw_pcie_ver_is(pci, 490A))
> > > > > > val = dw_pcie_enable_ecrc(val);
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val);
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > > > > >
> > > > > > - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > > >
> > > > > > /*
> > > > > > * Make sure ATU enable takes effect before any subsequent config
> > > > > > * and I/O accesses.
> > > > > > */
> > > > > > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> > > > > > - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2);
> > > > > > + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2);
> > > > > > if (val & PCIE_ATU_ENABLE)
> > > > > > return 0;
> > > > > >
> > > > > > @@ -525,21 +525,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> > > > > > return -ETIMEDOUT;
> > > > > > }
> > > > > >
> > > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > > - u64 cpu_addr, u64 pci_addr, u64 size)
> > > > > > -{
> > > > > > - return __dw_pcie_prog_outbound_atu(pci, 0, index, type,
> > > > > > - cpu_addr, pci_addr, size);
> > > > > > -}
> > > > > > -
> > > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > > - int type, u64 cpu_addr, u64 pci_addr,
> > > > > > - u64 size)
> > > > > > -{
> > > > > > - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
> > > > > > - cpu_addr, pci_addr, size);
> > > > > > -}
> > > > > > -
> > > > > > static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg)
> > > > > > {
> > > > > > return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg);
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > index 3c06e025c905..85de0d8346fa 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > > @@ -288,6 +288,15 @@ enum dw_pcie_core_rst {
> > > > > > DW_PCIE_NUM_CORE_RSTS
> > > > > > };
> > > > > >
> > > > > > +struct dw_pcie_ob_atu_cfg {
> > > > > > + int index;
> > > > > > + int type;
> > > > > > + u8 func_no;
> > > > > > + u64 cpu_addr;
> > > > > > + u64 pci_addr;
> > > > > > + u64 size;
> > > > > > +};
> > > > > > +
> > > > > > struct dw_pcie_host_ops {
> > > > > > int (*host_init)(struct dw_pcie_rp *pp);
> > > > > > void (*host_deinit)(struct dw_pcie_rp *pp);
> > > > > > @@ -416,10 +425,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
> > > > > > int dw_pcie_link_up(struct dw_pcie *pci);
> > > > > > void dw_pcie_upconfig_setup(struct dw_pcie *pci);
> > > > > > int dw_pcie_wait_for_link(struct dw_pcie *pci);
> > > > > > -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > > - u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > > - int type, u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > > + const struct dw_pcie_ob_atu_cfg *atu);
> > > > > > int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
> > > > > > u64 cpu_addr, u64 pci_addr, u64 size);
> > > > > > int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
> > > > > > --
> > > > > > 2.25.1
> > > > > >
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (3 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 04/20] PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu() Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 8:12 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
` (15 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
MSG by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 49b785509576..2d0f816fa0ab 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
upper_32_bits(atu->pci_addr));
- val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+ val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
dw_pcie_ver_is_ge(pci, 460A))
val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
val = dw_pcie_enable_ecrc(val);
dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
- dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+ val = PCIE_ATU_ENABLE;
+ if (atu->type == PCIE_ATU_TYPE_MSG) {
+ /* The data-less messages only for now */
+ val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+ }
+ dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
/*
* Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 85de0d8346fa..c626d21243b0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -147,11 +147,13 @@
#define PCIE_ATU_TYPE_IO 0x2
#define PCIE_ATU_TYPE_CFG0 0x4
#define PCIE_ATU_TYPE_CFG1 0x5
+#define PCIE_ATU_TYPE_MSG 0x10
#define PCIE_ATU_TD BIT(8)
#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
#define PCIE_ATU_REGION_CTRL2 0x004
#define PCIE_ATU_ENABLE BIT(31)
#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
#define PCIE_ATU_LOWER_BASE 0x008
#define PCIE_ATU_UPPER_BASE 0x00C
@@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
int index;
int type;
u8 func_no;
+ u8 code;
+ u8 routing;
u64 cpu_addr;
u64 pci_addr;
u64 size;
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
@ 2023-07-24 8:12 ` Manivannan Sadhasivam
2023-07-29 1:40 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 8:12 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, fancer.lancer, linux-pci,
devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:37PM +0900, Yoshihiro Shimoda wrote:
> Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
> MSG by iATU in the PCIe endpoint mode in near the future.
It's better to specify the exact requirement here "triggering INTx IRQs"
instead of implying.
> PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> MsgD. So, this implementation supports the data-less messages only
> for now.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Same comment for patch 4/20 applies here also. With that fixed,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 49b785509576..2d0f816fa0ab 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> upper_32_bits(atu->pci_addr));
>
> - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> dw_pcie_ver_is_ge(pci, 460A))
> val |= PCIE_ATU_INCREASE_REGION_SIZE;
> @@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> val = dw_pcie_enable_ecrc(val);
> dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
>
> - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> + val = PCIE_ATU_ENABLE;
> + if (atu->type == PCIE_ATU_TYPE_MSG) {
> + /* The data-less messages only for now */
> + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> + }
> + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
>
> /*
> * Make sure ATU enable takes effect before any subsequent config
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 85de0d8346fa..c626d21243b0 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -147,11 +147,13 @@
> #define PCIE_ATU_TYPE_IO 0x2
> #define PCIE_ATU_TYPE_CFG0 0x4
> #define PCIE_ATU_TYPE_CFG1 0x5
> +#define PCIE_ATU_TYPE_MSG 0x10
> #define PCIE_ATU_TD BIT(8)
> #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> #define PCIE_ATU_REGION_CTRL2 0x004
> #define PCIE_ATU_ENABLE BIT(31)
> #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> #define PCIE_ATU_LOWER_BASE 0x008
> #define PCIE_ATU_UPPER_BASE 0x00C
> @@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
> int index;
> int type;
> u8 func_no;
> + u8 code;
> + u8 routing;
> u64 cpu_addr;
> u64 pci_addr;
> u64 size;
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-24 8:12 ` Manivannan Sadhasivam
@ 2023-07-29 1:40 ` Serge Semin
2023-07-31 1:18 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-29 1:40 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, manivannan.sadhasivam, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Mon, Jul 24, 2023 at 01:42:50PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jul 21, 2023 at 04:44:37PM +0900, Yoshihiro Shimoda wrote:
> > Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
> > MSG by iATU in the PCIe endpoint mode in near the future.
>
> It's better to specify the exact requirement here "triggering INTx IRQs"
> instead of implying.
>
> > PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> > MsgD. So, this implementation supports the data-less messages only
> > for now.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Same comment for patch 4/20 applies here also. With that fixed,
Yoshihiro, as we greed with Mani in the PATCH 4/20 discussion please
ignore this request.
-Serge(y)
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> - Mani
>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > 2 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 49b785509576..2d0f816fa0ab 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > upper_32_bits(atu->pci_addr));
> >
> > - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > dw_pcie_ver_is_ge(pci, 460A))
> > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > @@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > val = dw_pcie_enable_ecrc(val);
> > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> >
> > - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > + val = PCIE_ATU_ENABLE;
> > + if (atu->type == PCIE_ATU_TYPE_MSG) {
> > + /* The data-less messages only for now */
> > + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> > + }
> > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
> >
> > /*
> > * Make sure ATU enable takes effect before any subsequent config
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 85de0d8346fa..c626d21243b0 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -147,11 +147,13 @@
> > #define PCIE_ATU_TYPE_IO 0x2
> > #define PCIE_ATU_TYPE_CFG0 0x4
> > #define PCIE_ATU_TYPE_CFG1 0x5
> > +#define PCIE_ATU_TYPE_MSG 0x10
> > #define PCIE_ATU_TD BIT(8)
> > #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> > #define PCIE_ATU_REGION_CTRL2 0x004
> > #define PCIE_ATU_ENABLE BIT(31)
> > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> > #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > #define PCIE_ATU_LOWER_BASE 0x008
> > #define PCIE_ATU_UPPER_BASE 0x00C
> > @@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
> > int index;
> > int type;
> > u8 func_no;
> > + u8 code;
> > + u8 routing;
> > u64 cpu_addr;
> > u64 pci_addr;
> > u64 size;
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-29 1:40 ` Serge Semin
@ 2023-07-31 1:18 ` Yoshihiro Shimoda
2023-07-31 22:11 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-31 1:18 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Saturday, July 29, 2023 10:41 AM
>
> On Mon, Jul 24, 2023 at 01:42:50PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Jul 21, 2023 at 04:44:37PM +0900, Yoshihiro Shimoda wrote:
> > > Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
> > > MSG by iATU in the PCIe endpoint mode in near the future.
> >
> > It's better to specify the exact requirement here "triggering INTx IRQs"
> > instead of implying.
> >
> > > PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> > > MsgD. So, this implementation supports the data-less messages only
> > > for now.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
>
> > Same comment for patch 4/20 applies here also. With that fixed,
>
> Yoshihiro, as we greed with Mani in the PATCH 4/20 discussion please
> ignore this request.
By the way, do you have any comment about my suggestion? [1]
[1]
https://lore.kernel.org/linux-pci/TYBPR01MB5341407DC508F0B390B84090D801A@TYBPR01MB5341.jpnprd01.prod.outlook.com/
If you don't agree my suggestion, I'll ignore this request.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> >
> > - Mani
> >
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> > > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > > 2 files changed, 11 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > index 49b785509576..2d0f816fa0ab 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > @@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > upper_32_bits(atu->pci_addr));
> > >
> > > - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > dw_pcie_ver_is_ge(pci, 460A))
> > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > @@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > val = dw_pcie_enable_ecrc(val);
> > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > >
> > > - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > + val = PCIE_ATU_ENABLE;
> > > + if (atu->type == PCIE_ATU_TYPE_MSG) {
> > > + /* The data-less messages only for now */
> > > + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> > > + }
> > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
> > >
> > > /*
> > > * Make sure ATU enable takes effect before any subsequent config
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 85de0d8346fa..c626d21243b0 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -147,11 +147,13 @@
> > > #define PCIE_ATU_TYPE_IO 0x2
> > > #define PCIE_ATU_TYPE_CFG0 0x4
> > > #define PCIE_ATU_TYPE_CFG1 0x5
> > > +#define PCIE_ATU_TYPE_MSG 0x10
> > > #define PCIE_ATU_TD BIT(8)
> > > #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> > > #define PCIE_ATU_REGION_CTRL2 0x004
> > > #define PCIE_ATU_ENABLE BIT(31)
> > > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > > +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> > > #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > > #define PCIE_ATU_LOWER_BASE 0x008
> > > #define PCIE_ATU_UPPER_BASE 0x00C
> > > @@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
> > > int index;
> > > int type;
> > > u8 func_no;
> > > + u8 code;
> > > + u8 routing;
> > > u64 cpu_addr;
> > > u64 pci_addr;
> > > u64 size;
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-31 1:18 ` Yoshihiro Shimoda
@ 2023-07-31 22:11 ` Serge Semin
2023-08-01 1:31 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-31 22:11 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Mon, Jul 31, 2023 at 01:18:30AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Saturday, July 29, 2023 10:41 AM
> >
> > On Mon, Jul 24, 2023 at 01:42:50PM +0530, Manivannan Sadhasivam wrote:
> > > On Fri, Jul 21, 2023 at 04:44:37PM +0900, Yoshihiro Shimoda wrote:
> > > > Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
> > > > MSG by iATU in the PCIe endpoint mode in near the future.
> > >
> > > It's better to specify the exact requirement here "triggering INTx IRQs"
> > > instead of implying.
> > >
> > > > PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> > > > MsgD. So, this implementation supports the data-less messages only
> > > > for now.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> >
> > > Same comment for patch 4/20 applies here also. With that fixed,
> >
> > Yoshihiro, as we greed with Mani in the PATCH 4/20 discussion please
> > ignore this request.
>
> By the way, do you have any comment about my suggestion? [1]
>
> [1]
> https://lore.kernel.org/linux-pci/TYBPR01MB5341407DC508F0B390B84090D801A@TYBPR01MB5341.jpnprd01.prod.outlook.com/
>
> If you don't agree my suggestion, I'll ignore this request.
Your suggested is not good for several reasons:
1. You suggest to add the function caller context-wise comments to the
structure. It will cause the maintainers to keep the comments and the
callers semantics in sync which is almost always gets to be diverged
at some point.
2. dw_pcie_prog_outbound_atu() doesn't know whether it is called for
an End-point or a Root Port controller. It just maps the CPU->PCIe
spaces by means of the outbound iATU engine with the specified mapping
parameters. This makes the comments you suggest misleading. Moreover
depending on the application the low-level drivers or even the DW PCIe
core driver may decided to map them in any way. In that case the
respective change will need to update the comments too, otherwise
they'll get to be wrong which gets us to the reason 1.
3. The current arguments/fields order more-or-less preserves the
natural settings setup: first you specifies the entity index, then you
specify the mapping settings, then you specified the mapping itself
(addresses and size). Ideally the "func_no" field should be moved to
the head of the structure since it also represents the mapping entity
index but it will cause having the pads (so called "holes") if we
didn't change it type. Anyway inverting the order so the mapping
itself goes first will break that, the structure will look as if, for
instance, the device-managed function taking the device pointer
somewhere in the middle or at the tail of the arguments lists. The
most important settings which are normally initialized first will be
defined at some random place in the structure.
So to speak, it's better to keep the structure fields as is for
now.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > -Serge(y)
> >
> > >
> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > >
> > > - Mani
> > >
> > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> > > > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > > > 2 files changed, 11 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > index 49b785509576..2d0f816fa0ab 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > @@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > > upper_32_bits(atu->pci_addr));
> > > >
> > > > - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > > dw_pcie_ver_is_ge(pci, 460A))
> > > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > > @@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > val = dw_pcie_enable_ecrc(val);
> > > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > > >
> > > > - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > + val = PCIE_ATU_ENABLE;
> > > > + if (atu->type == PCIE_ATU_TYPE_MSG) {
> > > > + /* The data-less messages only for now */
> > > > + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> > > > + }
> > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
> > > >
> > > > /*
> > > > * Make sure ATU enable takes effect before any subsequent config
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > index 85de0d8346fa..c626d21243b0 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > @@ -147,11 +147,13 @@
> > > > #define PCIE_ATU_TYPE_IO 0x2
> > > > #define PCIE_ATU_TYPE_CFG0 0x4
> > > > #define PCIE_ATU_TYPE_CFG1 0x5
> > > > +#define PCIE_ATU_TYPE_MSG 0x10
> > > > #define PCIE_ATU_TD BIT(8)
> > > > #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> > > > #define PCIE_ATU_REGION_CTRL2 0x004
> > > > #define PCIE_ATU_ENABLE BIT(31)
> > > > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > > > +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> > > > #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > > > #define PCIE_ATU_LOWER_BASE 0x008
> > > > #define PCIE_ATU_UPPER_BASE 0x00C
> > > > @@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
> > > > int index;
> > > > int type;
> > > > u8 func_no;
> > > > + u8 code;
> > > > + u8 routing;
> > > > u64 cpu_addr;
> > > > u64 pci_addr;
> > > > u64 size;
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support
2023-07-31 22:11 ` Serge Semin
@ 2023-08-01 1:31 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 1:31 UTC (permalink / raw)
To: Serge Semin
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 7:12 AM
>
> On Mon, Jul 31, 2023 at 01:18:30AM +0000, Yoshihiro Shimoda wrote:
> > Hi Serge,
> >
> > > From: Serge Semin, Sent: Saturday, July 29, 2023 10:41 AM
> > >
> > > On Mon, Jul 24, 2023 at 01:42:50PM +0530, Manivannan Sadhasivam wrote:
> > > > On Fri, Jul 21, 2023 at 04:44:37PM +0900, Yoshihiro Shimoda wrote:
> > > > > Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for sending
> > > > > MSG by iATU in the PCIe endpoint mode in near the future.
> > > >
> > > > It's better to specify the exact requirement here "triggering INTx IRQs"
> > > > instead of implying.
> > > >
> > > > > PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
> > > > > MsgD. So, this implementation supports the data-less messages only
> > > > > for now.
> > > > >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > >
> > >
> > > > Same comment for patch 4/20 applies here also. With that fixed,
> > >
> > > Yoshihiro, as we greed with Mani in the PATCH 4/20 discussion please
> > > ignore this request.
> >
>
> > By the way, do you have any comment about my suggestion? [1]
> >
> > [1]
> >
<snip URL>
> >
> > If you don't agree my suggestion, I'll ignore this request.
>
> Your suggested is not good for several reasons:
>
> 1. You suggest to add the function caller context-wise comments to the
> structure. It will cause the maintainers to keep the comments and the
> callers semantics in sync which is almost always gets to be diverged
> at some point.
>
> 2. dw_pcie_prog_outbound_atu() doesn't know whether it is called for
> an End-point or a Root Port controller. It just maps the CPU->PCIe
> spaces by means of the outbound iATU engine with the specified mapping
> parameters. This makes the comments you suggest misleading. Moreover
> depending on the application the low-level drivers or even the DW PCIe
> core driver may decided to map them in any way. In that case the
> respective change will need to update the comments too, otherwise
> they'll get to be wrong which gets us to the reason 1.
>
> 3. The current arguments/fields order more-or-less preserves the
> natural settings setup: first you specifies the entity index, then you
> specify the mapping settings, then you specified the mapping itself
> (addresses and size). Ideally the "func_no" field should be moved to
> the head of the structure since it also represents the mapping entity
> index but it will cause having the pads (so called "holes") if we
> didn't change it type. Anyway inverting the order so the mapping
> itself goes first will break that, the structure will look as if, for
> instance, the device-managed function taking the device pointer
> somewhere in the middle or at the tail of the arguments lists. The
> most important settings which are normally initialized first will be
> defined at some random place in the structure.
>
> So to speak, it's better to keep the structure fields as is for
> now.
Thank you for your reply. I understood that my suggestion is not good.
I'll keep the order as-is on v19.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > -Serge(y)
> > >
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > >
> > > > - Mani
> > > >
> > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > ---
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> > > > > drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> > > > > 2 files changed, 11 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > index 49b785509576..2d0f816fa0ab 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > @@ -498,7 +498,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
> > > > > upper_32_bits(atu->pci_addr));
> > > > >
> > > > > - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > > + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
> > > > > if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
> > > > > dw_pcie_ver_is_ge(pci, 460A))
> > > > > val |= PCIE_ATU_INCREASE_REGION_SIZE;
> > > > > @@ -506,7 +506,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> > > > > val = dw_pcie_enable_ecrc(val);
> > > > > dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
> > > > >
> > > > > - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
> > > > > + val = PCIE_ATU_ENABLE;
> > > > > + if (atu->type == PCIE_ATU_TYPE_MSG) {
> > > > > + /* The data-less messages only for now */
> > > > > + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
> > > > > + }
> > > > > + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
> > > > >
> > > > > /*
> > > > > * Make sure ATU enable takes effect before any subsequent config
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > index 85de0d8346fa..c626d21243b0 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > > @@ -147,11 +147,13 @@
> > > > > #define PCIE_ATU_TYPE_IO 0x2
> > > > > #define PCIE_ATU_TYPE_CFG0 0x4
> > > > > #define PCIE_ATU_TYPE_CFG1 0x5
> > > > > +#define PCIE_ATU_TYPE_MSG 0x10
> > > > > #define PCIE_ATU_TD BIT(8)
> > > > > #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
> > > > > #define PCIE_ATU_REGION_CTRL2 0x004
> > > > > #define PCIE_ATU_ENABLE BIT(31)
> > > > > #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
> > > > > +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)
> > > > > #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
> > > > > #define PCIE_ATU_LOWER_BASE 0x008
> > > > > #define PCIE_ATU_UPPER_BASE 0x00C
> > > > > @@ -292,6 +294,8 @@ struct dw_pcie_ob_atu_cfg {
> > > > > int index;
> > > > > int type;
> > > > > u8 func_no;
> > > > > + u8 code;
> > > > > + u8 routing;
> > > > > u64 cpu_addr;
> > > > > u64 pci_addr;
> > > > > u64 size;
> > > > > --
> > > > > 2.25.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (4 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 05/20] PCI: dwc: Add outbound MSG TLPs support Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 8:34 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
` (14 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Add support for triggering INTx IRQs by using outbound iATU.
Outbound iATU is utilized to send assert and de-assert INTx TLPs.
The message is generated based on the payloadless Msg TLP with type
0x14, where 0x4 is the routing code implying the Terminate at
Receiver message. The message code is specified as b1000xx for
the INTx assertion and b1001xx for the INTx de-assertion.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
.../pci/controller/dwc/pcie-designware-ep.c | 69 +++++++++++++++++--
drivers/pci/controller/dwc/pcie-designware.h | 2 +
2 files changed, 67 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index fe2e0d765be9..1d24ebf9686f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -6,9 +6,11 @@
* Author: Kishon Vijay Abraham I <kishon@ti.com>
*/
+#include <linux/delay.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#include <linux/pci-epc.h>
#include <linux/pci-epf.h>
@@ -484,14 +486,60 @@ static const struct pci_epc_ops epc_ops = {
.get_features = dw_pcie_ep_get_features,
};
+static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code,
+ u8 routing)
+{
+ struct dw_pcie_ob_atu_cfg atu = { 0 };
+ struct pci_epc *epc = ep->epc;
+ int ret;
+
+ atu.func_no = func_no;
+ atu.code = code;
+ atu.routing = routing;
+ atu.type = PCIE_ATU_TYPE_MSG;
+ atu.cpu_addr = ep->intx_mem_phys;
+ atu.size = epc->mem->window.page_size;
+
+ ret = dw_pcie_ep_outbound_atu(ep, &atu);
+ if (ret)
+ return ret;
+
+ writel(0, ep->intx_mem);
+
+ dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys);
+
+ return 0;
+}
+
int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct device *dev = pci->dev;
+ int ret;
- dev_err(dev, "EP cannot trigger INTx IRQs\n");
+ if (!ep->intx_mem) {
+ dev_err(dev, "INTx not supported\n");
+ return -EOPNOTSUPP;
+ }
- return -EINVAL;
+ /*
+ * Even though the PCI bus specification implies the level-triggered
+ * INTx interrupts the kernel PCIe endpoint framework has a single
+ * PCI_EPC_IRQ_INTx flag defined for the legacy IRQs simulation. Thus
+ * this function sends the Deassert_INTx PCIe TLP after the Assert_INTx
+ * message with the 50 usec duration basically implementing the
+ * rising-edge triggering IRQ. Hopefully the interrupt controller will
+ * still be able to register the incoming IRQ event...
+ */
+ ret = dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_ASSERT_INTA,
+ PCI_MSG_TYPE_R_ROUTING_LOCAL);
+ if (ret)
+ return ret;
+
+ usleep_range(50, 100);
+
+ return dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_DEASSERT_INTA,
+ PCI_MSG_TYPE_R_ROUTING_LOCAL);
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
@@ -622,6 +670,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
dw_pcie_edma_remove(pci);
+ if (ep->intx_mem)
+ pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
+ epc->mem->window.page_size);
+
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
epc->mem->window.page_size);
@@ -793,9 +845,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
goto err_exit_epc_mem;
}
+ ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys,
+ epc->mem->window.page_size);
+ if (!ep->intx_mem)
+ dev_warn(dev, "Failed to reserve memory for INTx\n");
+
ret = dw_pcie_edma_detect(pci);
if (ret)
- goto err_free_epc_mem;
+ goto err_free_epc_mem_intx;
if (ep->ops->get_features) {
epc_features = ep->ops->get_features(ep);
@@ -812,7 +869,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
err_remove_edma:
dw_pcie_edma_remove(pci);
-err_free_epc_mem:
+err_free_epc_mem_intx:
+ if (ep->intx_mem)
+ pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
+ epc->mem->window.page_size);
+
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
epc->mem->window.page_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index c626d21243b0..812c221b3f7c 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -365,6 +365,8 @@ struct dw_pcie_ep {
unsigned long *ob_window_map;
void __iomem *msi_mem;
phys_addr_t msi_mem_phys;
+ void __iomem *intx_mem;
+ phys_addr_t intx_mem_phys;
struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
};
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
@ 2023-07-24 8:34 ` Manivannan Sadhasivam
2023-07-26 3:03 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 8:34 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, fancer.lancer, linux-pci,
devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:38PM +0900, Yoshihiro Shimoda wrote:
> Add support for triggering INTx IRQs by using outbound iATU.
> Outbound iATU is utilized to send assert and de-assert INTx TLPs.
> The message is generated based on the payloadless Msg TLP with type
> 0x14, where 0x4 is the routing code implying the Terminate at
> Receiver message. The message code is specified as b1000xx for
> the INTx assertion and b1001xx for the INTx de-assertion.
>
Commit message is missing a few important points:
1. EDGE IRQ is simulated for INTx
2. Only INTA is asserted
3. INTx support is optional (if there is no memory for INTx, probe will not
fail)
Above points should be included in the commit message to properly describe the
change.
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 69 +++++++++++++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 2 +
> 2 files changed, 67 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index fe2e0d765be9..1d24ebf9686f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -6,9 +6,11 @@
> * Author: Kishon Vijay Abraham I <kishon@ti.com>
> */
>
> +#include <linux/delay.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
>
> +#include "../../pci.h"
> #include "pcie-designware.h"
> #include <linux/pci-epc.h>
> #include <linux/pci-epf.h>
> @@ -484,14 +486,60 @@ static const struct pci_epc_ops epc_ops = {
> .get_features = dw_pcie_ep_get_features,
> };
>
> +static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code,
> + u8 routing)
> +{
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> + struct pci_epc *epc = ep->epc;
> + int ret;
> +
> + atu.func_no = func_no;
> + atu.code = code;
> + atu.routing = routing;
> + atu.type = PCIE_ATU_TYPE_MSG;
> + atu.cpu_addr = ep->intx_mem_phys;
> + atu.size = epc->mem->window.page_size;
> +
> + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> + if (ret)
> + return ret;
> +
> + writel(0, ep->intx_mem);
> +
This write is not described anywhere.
- Mani
> + dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys);
> +
> + return 0;
> +}
> +
> int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
> {
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct device *dev = pci->dev;
> + int ret;
>
> - dev_err(dev, "EP cannot trigger INTx IRQs\n");
> + if (!ep->intx_mem) {
> + dev_err(dev, "INTx not supported\n");
> + return -EOPNOTSUPP;
> + }
>
> - return -EINVAL;
> + /*
> + * Even though the PCI bus specification implies the level-triggered
> + * INTx interrupts the kernel PCIe endpoint framework has a single
> + * PCI_EPC_IRQ_INTx flag defined for the legacy IRQs simulation. Thus
> + * this function sends the Deassert_INTx PCIe TLP after the Assert_INTx
> + * message with the 50 usec duration basically implementing the
> + * rising-edge triggering IRQ. Hopefully the interrupt controller will
> + * still be able to register the incoming IRQ event...
> + */
> + ret = dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_ASSERT_INTA,
> + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> + if (ret)
> + return ret;
> +
> + usleep_range(50, 100);
> +
> + return dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_DEASSERT_INTA,
> + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> }
> EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
>
> @@ -622,6 +670,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>
> dw_pcie_edma_remove(pci);
>
> + if (ep->intx_mem)
> + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> + epc->mem->window.page_size);
> +
> pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> epc->mem->window.page_size);
>
> @@ -793,9 +845,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> goto err_exit_epc_mem;
> }
>
> + ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys,
> + epc->mem->window.page_size);
> + if (!ep->intx_mem)
> + dev_warn(dev, "Failed to reserve memory for INTx\n");
> +
> ret = dw_pcie_edma_detect(pci);
> if (ret)
> - goto err_free_epc_mem;
> + goto err_free_epc_mem_intx;
>
> if (ep->ops->get_features) {
> epc_features = ep->ops->get_features(ep);
> @@ -812,7 +869,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> err_remove_edma:
> dw_pcie_edma_remove(pci);
>
> -err_free_epc_mem:
> +err_free_epc_mem_intx:
> + if (ep->intx_mem)
> + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> + epc->mem->window.page_size);
> +
> pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> epc->mem->window.page_size);
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index c626d21243b0..812c221b3f7c 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -365,6 +365,8 @@ struct dw_pcie_ep {
> unsigned long *ob_window_map;
> void __iomem *msi_mem;
> phys_addr_t msi_mem_phys;
> + void __iomem *intx_mem;
> + phys_addr_t intx_mem_phys;
> struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
> };
>
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support
2023-07-24 8:34 ` Manivannan Sadhasivam
@ 2023-07-26 3:03 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-26 3:03 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 5:34 PM
>
> On Fri, Jul 21, 2023 at 04:44:38PM +0900, Yoshihiro Shimoda wrote:
> > Add support for triggering INTx IRQs by using outbound iATU.
> > Outbound iATU is utilized to send assert and de-assert INTx TLPs.
> > The message is generated based on the payloadless Msg TLP with type
> > 0x14, where 0x4 is the routing code implying the Terminate at
> > Receiver message. The message code is specified as b1000xx for
> > the INTx assertion and b1001xx for the INTx de-assertion.
> >
>
> Commit message is missing a few important points:
>
> 1. EDGE IRQ is simulated for INTx
> 2. Only INTA is asserted
> 3. INTx support is optional (if there is no memory for INTx, probe will not
> fail)
>
> Above points should be included in the commit message to properly describe the
> change.
I'll add such information.
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 69 +++++++++++++++++--
> > drivers/pci/controller/dwc/pcie-designware.h | 2 +
> > 2 files changed, 67 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index fe2e0d765be9..1d24ebf9686f 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -6,9 +6,11 @@
> > * Author: Kishon Vijay Abraham I <kishon@ti.com>
> > */
> >
> > +#include <linux/delay.h>
> > #include <linux/of.h>
> > #include <linux/platform_device.h>
> >
> > +#include "../../pci.h"
> > #include "pcie-designware.h"
> > #include <linux/pci-epc.h>
> > #include <linux/pci-epf.h>
> > @@ -484,14 +486,60 @@ static const struct pci_epc_ops epc_ops = {
> > .get_features = dw_pcie_ep_get_features,
> > };
> >
> > +static int dw_pcie_ep_send_msg(struct dw_pcie_ep *ep, u8 func_no, u8 code,
> > + u8 routing)
> > +{
> > + struct dw_pcie_ob_atu_cfg atu = { 0 };
> > + struct pci_epc *epc = ep->epc;
> > + int ret;
> > +
> > + atu.func_no = func_no;
> > + atu.code = code;
> > + atu.routing = routing;
> > + atu.type = PCIE_ATU_TYPE_MSG;
> > + atu.cpu_addr = ep->intx_mem_phys;
> > + atu.size = epc->mem->window.page_size;
> > +
> > + ret = dw_pcie_ep_outbound_atu(ep, &atu);
> > + if (ret)
> > + return ret;
> > +
> > + writel(0, ep->intx_mem);
> > +
>
> This write is not described anywhere.
I'll add a comment before the writel.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > + dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->intx_mem_phys);
> > +
> > + return 0;
> > +}
> > +
> > int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)
> > {
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct device *dev = pci->dev;
> > + int ret;
> >
> > - dev_err(dev, "EP cannot trigger INTx IRQs\n");
> > + if (!ep->intx_mem) {
> > + dev_err(dev, "INTx not supported\n");
> > + return -EOPNOTSUPP;
> > + }
> >
> > - return -EINVAL;
> > + /*
> > + * Even though the PCI bus specification implies the level-triggered
> > + * INTx interrupts the kernel PCIe endpoint framework has a single
> > + * PCI_EPC_IRQ_INTx flag defined for the legacy IRQs simulation. Thus
> > + * this function sends the Deassert_INTx PCIe TLP after the Assert_INTx
> > + * message with the 50 usec duration basically implementing the
> > + * rising-edge triggering IRQ. Hopefully the interrupt controller will
> > + * still be able to register the incoming IRQ event...
> > + */
> > + ret = dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_ASSERT_INTA,
> > + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> > + if (ret)
> > + return ret;
> > +
> > + usleep_range(50, 100);
> > +
> > + return dw_pcie_ep_send_msg(ep, func_no, PCI_MSG_CODE_DEASSERT_INTA,
> > + PCI_MSG_TYPE_R_ROUTING_LOCAL);
> > }
> > EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_intx_irq);
> >
> > @@ -622,6 +670,10 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> >
> > dw_pcie_edma_remove(pci);
> >
> > + if (ep->intx_mem)
> > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> > + epc->mem->window.page_size);
> > +
> > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> > epc->mem->window.page_size);
> >
> > @@ -793,9 +845,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > goto err_exit_epc_mem;
> > }
> >
> > + ep->intx_mem = pci_epc_mem_alloc_addr(epc, &ep->intx_mem_phys,
> > + epc->mem->window.page_size);
> > + if (!ep->intx_mem)
> > + dev_warn(dev, "Failed to reserve memory for INTx\n");
> > +
> > ret = dw_pcie_edma_detect(pci);
> > if (ret)
> > - goto err_free_epc_mem;
> > + goto err_free_epc_mem_intx;
> >
> > if (ep->ops->get_features) {
> > epc_features = ep->ops->get_features(ep);
> > @@ -812,7 +869,11 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > err_remove_edma:
> > dw_pcie_edma_remove(pci);
> >
> > -err_free_epc_mem:
> > +err_free_epc_mem_intx:
> > + if (ep->intx_mem)
> > + pci_epc_mem_free_addr(epc, ep->intx_mem_phys, ep->intx_mem,
> > + epc->mem->window.page_size);
> > +
> > pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
> > epc->mem->window.page_size);
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index c626d21243b0..812c221b3f7c 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -365,6 +365,8 @@ struct dw_pcie_ep {
> > unsigned long *ob_window_map;
> > void __iomem *msi_mem;
> > phys_addr_t msi_mem_phys;
> > + void __iomem *intx_mem;
> > + phys_addr_t intx_mem_phys;
> > struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
> > };
> >
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (5 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 06/20] PCI: designware-ep: Add INTx IRQs support Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 9:24 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
` (13 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
for DWC") added .func_conf_select() to get the configuration space of
different PFs and assumed that the offsets between dbi and dbi2 would
be the same. However, Renesas R-Car Gen4 PCIe controllers have different
offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
the offset for dbi2, add .func_conf_select2() and
dw_pcie_ep_func_select2().
Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
if .func_conf_select2() doesn't exist for backward compatibility.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
drivers/pci/controller/dwc/pcie-designware.h | 3 +-
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 1d24ebf9686f..bd57516d5313 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
return func_offset;
}
+static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
+{
+ unsigned int func_offset = 0;
+
+ if (ep->ops->func_conf_select2)
+ func_offset = ep->ops->func_conf_select2(ep, func_no);
+ else if (ep->ops->func_conf_select) /* for backward compatibility */
+ func_offset = ep->ops->func_conf_select(ep, func_no);
+
+ return func_offset;
+}
+
static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
enum pci_barno bar, int flags)
{
- u32 reg;
- unsigned int func_offset = 0;
+ u32 reg, reg_dbi2;
+ unsigned int func_offset, func_offset_dbi2;
struct dw_pcie_ep *ep = &pci->ep;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
+ reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
dw_pcie_writel_dbi(pci, reg, 0x0);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
dw_pcie_writel_dbi(pci, reg + 4, 0x0);
}
dw_pcie_dbi_ro_wr_dis(pci);
@@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
enum pci_barno bar = epf_bar->barno;
size_t size = epf_bar->size;
int flags = epf_bar->flags;
- unsigned int func_offset = 0;
+ unsigned int func_offset, func_offset_dbi2;
int ret, type;
- u32 reg;
+ u32 reg, reg_dbi2;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
+ reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
if (!(flags & PCI_BASE_ADDRESS_SPACE))
type = PCIE_ATU_TYPE_MEM;
@@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg, flags);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg + 4, 0);
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 812c221b3f7c..94bc20f5f600 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
* access for different platform, if different func have different
* offset, return the offset of func. if use write a register way
* return a 0, and implement code in callback function of platform
- * driver.
+ * driver. The func_conf_select2 is for dbi2.
*/
unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
+ unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
};
struct dw_pcie_ep_func {
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
@ 2023-07-24 9:24 ` Manivannan Sadhasivam
2023-07-25 11:57 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 9:24 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, fancer.lancer, linux-pci,
devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:39PM +0900, Yoshihiro Shimoda wrote:
> The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> for DWC") added .func_conf_select() to get the configuration space of
> different PFs and assumed that the offsets between dbi and dbi2 would
> be the same. However, Renesas R-Car Gen4 PCIe controllers have different
> offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
> the offset for dbi2, add .func_conf_select2() and
> dw_pcie_ep_func_select2().
>
How about,
.get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset()?
This would've been much simpler if dw_pcie_writeX_{dbi/dbi2} APIs accepted the
func_no argument, so that these offset calculations are contained in the API
definitions itself as it should. Then the APIs could just do "func_offset *
func_no" to get DBI base and "(func_offset * func_no) + dbi2_offset" to get DBI2
base, provided these offsets are passed by the vendor drivers.
It can be done in a separate cleanup series later.
> Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
s/Notes/Note
> if .func_conf_select2() doesn't exist for backward compatibility.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> drivers/pci/controller/dwc/pcie-designware.h | 3 +-
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 1d24ebf9686f..bd57516d5313 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> return func_offset;
> }
>
> +static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
> +{
> + unsigned int func_offset = 0;
> +
> + if (ep->ops->func_conf_select2)
> + func_offset = ep->ops->func_conf_select2(ep, func_no);
> + else if (ep->ops->func_conf_select) /* for backward compatibility */
> + func_offset = ep->ops->func_conf_select(ep, func_no);
> +
> + return func_offset;
> +}
> +
> static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> enum pci_barno bar, int flags)
> {
> - u32 reg;
> - unsigned int func_offset = 0;
> + u32 reg, reg_dbi2;
> + unsigned int func_offset, func_offset_dbi2;
Please maitain reverse Xmas tree order.
- Mani
> struct dw_pcie_ep *ep = &pci->ep;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
>
> reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> + reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
> dw_pcie_dbi_ro_wr_en(pci);
> - dw_pcie_writel_dbi2(pci, reg, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> dw_pcie_writel_dbi(pci, reg, 0x0);
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> }
> dw_pcie_dbi_ro_wr_dis(pci);
> @@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> enum pci_barno bar = epf_bar->barno;
> size_t size = epf_bar->size;
> int flags = epf_bar->flags;
> - unsigned int func_offset = 0;
> + unsigned int func_offset, func_offset_dbi2;
> int ret, type;
> - u32 reg;
> + u32 reg, reg_dbi2;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
>
> reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
>
> if (!(flags & PCI_BASE_ADDRESS_SPACE))
> type = PCIE_ATU_TYPE_MEM;
> @@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>
> dw_pcie_dbi_ro_wr_en(pci);
>
> - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg, flags);
>
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg + 4, 0);
> }
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 812c221b3f7c..94bc20f5f600 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
> * access for different platform, if different func have different
> * offset, return the offset of func. if use write a register way
> * return a 0, and implement code in callback function of platform
> - * driver.
> + * driver. The func_conf_select2 is for dbi2.
> */
> unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> + unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
> };
>
> struct dw_pcie_ep_func {
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-07-24 9:24 ` Manivannan Sadhasivam
@ 2023-07-25 11:57 ` Yoshihiro Shimoda
2023-07-28 2:34 ` Manivannan Sadhasivam
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-25 11:57 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 6:25 PM
>
> On Fri, Jul 21, 2023 at 04:44:39PM +0900, Yoshihiro Shimoda wrote:
> > The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> > for DWC") added .func_conf_select() to get the configuration space of
> > different PFs and assumed that the offsets between dbi and dbi2 would
> > be the same. However, Renesas R-Car Gen4 PCIe controllers have different
> > offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
> > the offset for dbi2, add .func_conf_select2() and
> > dw_pcie_ep_func_select2().
> >
>
> How about,
>
> .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset()?
Thank you for your suggestion. I should have shared the following information
in the commit log, but dbi2_offset is not depended on the DBI on my environment:
+0x0000 : dbi Function 0
+0x1000 : dbi Function 1
+0x2000 : dbi2 Function 0
+0x2800 : dbi2 Function 1
So, on my environment:
- the dbi_base is set to +0x0000..
-- And func_offset of func_no = 1 was 0x1000.
- the dbi_base2 is set to +0x2000.
-- And func_offset2 of function = 1 was 0x0800, not 0x1800.
Perhaps, the name of new API should be .func_conf_select_dbi2 instead?
~~~~~
> This would've been much simpler if dw_pcie_writeX_{dbi/dbi2} APIs accepted the
> func_no argument, so that these offset calculations are contained in the API
> definitions itself as it should. Then the APIs could just do "func_offset *
> func_no" to get DBI base and "(func_offset * func_no) + dbi2_offset" to get DBI2
> base, provided these offsets are passed by the vendor drivers.
Serge suggested such implementation before [1]
[1]
https://lore.kernel.org/linux-pci/j4g4ijnxd7qyacszlwyi3tdztkw2nmnjwyhdqf2l2yj3h2mvje@iqsrqiodqbhq/
> It can be done in a separate cleanup series later.
>
> > Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
>
> s/Notes/Note
I'll fix it.
> > if .func_conf_select2() doesn't exist for backward compatibility.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> > drivers/pci/controller/dwc/pcie-designware.h | 3 +-
> > 2 files changed, 26 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 1d24ebf9686f..bd57516d5313 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> > return func_offset;
> > }
> >
> > +static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
> > +{
> > + unsigned int func_offset = 0;
> > +
> > + if (ep->ops->func_conf_select2)
> > + func_offset = ep->ops->func_conf_select2(ep, func_no);
> > + else if (ep->ops->func_conf_select) /* for backward compatibility */
> > + func_offset = ep->ops->func_conf_select(ep, func_no);
> > +
> > + return func_offset;
> > +}
> > +
> > static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> > enum pci_barno bar, int flags)
> > {
> > - u32 reg;
> > - unsigned int func_offset = 0;
> > + u32 reg, reg_dbi2;
> > + unsigned int func_offset, func_offset_dbi2;
>
> Please maitain reverse Xmas tree order.
I got it.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > struct dw_pcie_ep *ep = &pci->ep;
> >
> > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> >
> > reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> > + reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
> > dw_pcie_dbi_ro_wr_en(pci);
> > - dw_pcie_writel_dbi2(pci, reg, 0x0);
> > + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> > dw_pcie_writel_dbi(pci, reg, 0x0);
> > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> > dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> > }
> > dw_pcie_dbi_ro_wr_dis(pci);
> > @@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > enum pci_barno bar = epf_bar->barno;
> > size_t size = epf_bar->size;
> > int flags = epf_bar->flags;
> > - unsigned int func_offset = 0;
> > + unsigned int func_offset, func_offset_dbi2;
> > int ret, type;
> > - u32 reg;
> > + u32 reg, reg_dbi2;
> >
> > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> >
> > reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> > + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
> >
> > if (!(flags & PCI_BASE_ADDRESS_SPACE))
> > type = PCIE_ATU_TYPE_MEM;
> > @@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> >
> > dw_pcie_dbi_ro_wr_en(pci);
> >
> > - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> > dw_pcie_writel_dbi(pci, reg, flags);
> >
> > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> > dw_pcie_writel_dbi(pci, reg + 4, 0);
> > }
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 812c221b3f7c..94bc20f5f600 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
> > * access for different platform, if different func have different
> > * offset, return the offset of func. if use write a register way
> > * return a 0, and implement code in callback function of platform
> > - * driver.
> > + * driver. The func_conf_select2 is for dbi2.
> > */
> > unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> > + unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
> > };
> >
> > struct dw_pcie_ep_func {
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-07-25 11:57 ` Yoshihiro Shimoda
@ 2023-07-28 2:34 ` Manivannan Sadhasivam
2023-07-28 4:18 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-28 2:34 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
On Tue, Jul 25, 2023 at 11:57:34AM +0000, Yoshihiro Shimoda wrote:
> Hi Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 6:25 PM
> >
> > On Fri, Jul 21, 2023 at 04:44:39PM +0900, Yoshihiro Shimoda wrote:
> > > The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> > > for DWC") added .func_conf_select() to get the configuration space of
> > > different PFs and assumed that the offsets between dbi and dbi2 would
> > > be the same. However, Renesas R-Car Gen4 PCIe controllers have different
> > > offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
> > > the offset for dbi2, add .func_conf_select2() and
> > > dw_pcie_ep_func_select2().
> > >
> >
> > How about,
> >
> > .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset()?
>
> Thank you for your suggestion. I should have shared the following information
> in the commit log, but dbi2_offset is not depended on the DBI on my environment:
>
> +0x0000 : dbi Function 0
> +0x1000 : dbi Function 1
> +0x2000 : dbi2 Function 0
> +0x2800 : dbi2 Function 1
>
> So, on my environment:
> - the dbi_base is set to +0x0000..
> -- And func_offset of func_no = 1 was 0x1000.
> - the dbi_base2 is set to +0x2000.
> -- And func_offset2 of function = 1 was 0x0800, not 0x1800.
>
> Perhaps, the name of new API should be .func_conf_select_dbi2 instead?
> ~~~~~
"func_conf_select" doesn't look intuitive to me atleast. The idea behind this
callback is to get the funcion offset based on the supplied function no. So this
should've been something like, "get_func_offset" and the API should've been
dw_pcie_ep_get_func_offset().
Since I do not want you to change the existing naming in this series, I
suggested to get the next API naming right.
>
> > This would've been much simpler if dw_pcie_writeX_{dbi/dbi2} APIs accepted the
> > func_no argument, so that these offset calculations are contained in the API
> > definitions itself as it should. Then the APIs could just do "func_offset *
> > func_no" to get DBI base and "(func_offset * func_no) + dbi2_offset" to get DBI2
> > base, provided these offsets are passed by the vendor drivers.
>
> Serge suggested such implementation before [1]
>
> [1]
> https://lore.kernel.org/linux-pci/j4g4ijnxd7qyacszlwyi3tdztkw2nmnjwyhdqf2l2yj3h2mvje@iqsrqiodqbhq/
>
Thanks for the link. I missed Serge's suggestion before. But I completely agree
with him as you can see from my above suggestion. In addition, I also want to
fix the "func_conf_select" naming as well.
However, I do not want you to implement the suggestion in this series itself.
It should be done as a separate cleanup series later. (I think you both agree to
that as well).
- Mani
> > It can be done in a separate cleanup series later.
> >
> > > Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
> >
> > s/Notes/Note
>
> I'll fix it.
>
> > > if .func_conf_select2() doesn't exist for backward compatibility.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > ---
> > > .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> > > drivers/pci/controller/dwc/pcie-designware.h | 3 +-
> > > 2 files changed, 26 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > index 1d24ebf9686f..bd57516d5313 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > @@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> > > return func_offset;
> > > }
> > >
> > > +static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
> > > +{
> > > + unsigned int func_offset = 0;
> > > +
> > > + if (ep->ops->func_conf_select2)
> > > + func_offset = ep->ops->func_conf_select2(ep, func_no);
> > > + else if (ep->ops->func_conf_select) /* for backward compatibility */
> > > + func_offset = ep->ops->func_conf_select(ep, func_no);
> > > +
> > > + return func_offset;
> > > +}
> > > +
> > > static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> > > enum pci_barno bar, int flags)
> > > {
> > > - u32 reg;
> > > - unsigned int func_offset = 0;
> > > + u32 reg, reg_dbi2;
> > > + unsigned int func_offset, func_offset_dbi2;
> >
> > Please maitain reverse Xmas tree order.
>
> I got it.
>
> Best regards,
> Yoshihiro Shimoda
>
> > - Mani
> >
> > > struct dw_pcie_ep *ep = &pci->ep;
> > >
> > > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> > >
> > > reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> > > + reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
> > > dw_pcie_dbi_ro_wr_en(pci);
> > > - dw_pcie_writel_dbi2(pci, reg, 0x0);
> > > + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> > > dw_pcie_writel_dbi(pci, reg, 0x0);
> > > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> > > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> > > dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> > > }
> > > dw_pcie_dbi_ro_wr_dis(pci);
> > > @@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > enum pci_barno bar = epf_bar->barno;
> > > size_t size = epf_bar->size;
> > > int flags = epf_bar->flags;
> > > - unsigned int func_offset = 0;
> > > + unsigned int func_offset, func_offset_dbi2;
> > > int ret, type;
> > > - u32 reg;
> > > + u32 reg, reg_dbi2;
> > >
> > > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> > >
> > > reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> > > + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
> > >
> > > if (!(flags & PCI_BASE_ADDRESS_SPACE))
> > > type = PCIE_ATU_TYPE_MEM;
> > > @@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > >
> > > dw_pcie_dbi_ro_wr_en(pci);
> > >
> > > - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > > + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> > > dw_pcie_writel_dbi(pci, reg, flags);
> > >
> > > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> > > dw_pcie_writel_dbi(pci, reg + 4, 0);
> > > }
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 812c221b3f7c..94bc20f5f600 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
> > > * access for different platform, if different func have different
> > > * offset, return the offset of func. if use write a register way
> > > * return a 0, and implement code in callback function of platform
> > > - * driver.
> > > + * driver. The func_conf_select2 is for dbi2.
> > > */
> > > unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> > > + unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
> > > };
> > >
> > > struct dw_pcie_ep_func {
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-07-28 2:34 ` Manivannan Sadhasivam
@ 2023-07-28 4:18 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-28 4:18 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
fancer.lancer@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:35 AM
>
> On Tue, Jul 25, 2023 at 11:57:34AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 6:25 PM
> > >
> > > On Fri, Jul 21, 2023 at 04:44:39PM +0900, Yoshihiro Shimoda wrote:
> > > > The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> > > > for DWC") added .func_conf_select() to get the configuration space of
> > > > different PFs and assumed that the offsets between dbi and dbi2 would
> > > > be the same. However, Renesas R-Car Gen4 PCIe controllers have different
> > > > offsets of function 1: dbi (+0x1000) and dbi2 (+0x800). To get
> > > > the offset for dbi2, add .func_conf_select2() and
> > > > dw_pcie_ep_func_select2().
> > > >
> > >
> > > How about,
> > >
> > > .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset()?
> >
> > Thank you for your suggestion. I should have shared the following information
> > in the commit log, but dbi2_offset is not depended on the DBI on my environment:
> >
> > +0x0000 : dbi Function 0
> > +0x1000 : dbi Function 1
> > +0x2000 : dbi2 Function 0
> > +0x2800 : dbi2 Function 1
> >
> > So, on my environment:
> > - the dbi_base is set to +0x0000..
> > -- And func_offset of func_no = 1 was 0x1000.
> > - the dbi_base2 is set to +0x2000.
> > -- And func_offset2 of function = 1 was 0x0800, not 0x1800.
> >
> > Perhaps, the name of new API should be .func_conf_select_dbi2 instead?
> > ~~~~~
>
> "func_conf_select" doesn't look intuitive to me atleast. The idea behind this
> callback is to get the funcion offset based on the supplied function no. So this
> should've been something like, "get_func_offset" and the API should've been
> dw_pcie_ep_get_func_offset().
>
> Since I do not want you to change the existing naming in this series, I
> suggested to get the next API naming right.
I got it.
> >
> > > This would've been much simpler if dw_pcie_writeX_{dbi/dbi2} APIs accepted the
> > > func_no argument, so that these offset calculations are contained in the API
> > > definitions itself as it should. Then the APIs could just do "func_offset *
> > > func_no" to get DBI base and "(func_offset * func_no) + dbi2_offset" to get DBI2
> > > base, provided these offsets are passed by the vendor drivers.
> >
> > Serge suggested such implementation before [1]
> >
> > [1]
> >
<snip URL>
> >
>
> Thanks for the link. I missed Serge's suggestion before. But I completely agree
> with him as you can see from my above suggestion. In addition, I also want to
> fix the "func_conf_select" naming as well.
>
> However, I do not want you to implement the suggestion in this series itself.
> It should be done as a separate cleanup series later.
I got it.
> (I think you both agree to
> that as well).
Yes, I both agree to that.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > > It can be done in a separate cleanup series later.
> > >
> > > > Notes that dw_pcie_ep_func_select2() will call .func_conf_select()
> > >
> > > s/Notes/Note
> >
> > I'll fix it.
> >
> > > > if .func_conf_select2() doesn't exist for backward compatibility.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > ---
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> > > > drivers/pci/controller/dwc/pcie-designware.h | 3 +-
> > > > 2 files changed, 26 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > index 1d24ebf9686f..bd57516d5313 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > @@ -54,21 +54,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> > > > return func_offset;
> > > > }
> > > >
> > > > +static unsigned int dw_pcie_ep_func_select2(struct dw_pcie_ep *ep, u8 func_no)
> > > > +{
> > > > + unsigned int func_offset = 0;
> > > > +
> > > > + if (ep->ops->func_conf_select2)
> > > > + func_offset = ep->ops->func_conf_select2(ep, func_no);
> > > > + else if (ep->ops->func_conf_select) /* for backward compatibility */
> > > > + func_offset = ep->ops->func_conf_select(ep, func_no);
> > > > +
> > > > + return func_offset;
> > > > +}
> > > > +
> > > > static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> > > > enum pci_barno bar, int flags)
> > > > {
> > > > - u32 reg;
> > > > - unsigned int func_offset = 0;
> > > > + u32 reg, reg_dbi2;
> > > > + unsigned int func_offset, func_offset_dbi2;
> > >
> > > Please maitain reverse Xmas tree order.
> >
> > I got it.
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > - Mani
> > >
> > > > struct dw_pcie_ep *ep = &pci->ep;
> > > >
> > > > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > > > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> > > >
> > > > reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> > > > + reg_dbi2 = func_offset_dbi2 + PCI_BASE_ADDRESS_0 + (4 * bar);
> > > > dw_pcie_dbi_ro_wr_en(pci);
> > > > - dw_pcie_writel_dbi2(pci, reg, 0x0);
> > > > + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> > > > dw_pcie_writel_dbi(pci, reg, 0x0);
> > > > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > > - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> > > > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> > > > dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> > > > }
> > > > dw_pcie_dbi_ro_wr_dis(pci);
> > > > @@ -232,13 +246,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > > enum pci_barno bar = epf_bar->barno;
> > > > size_t size = epf_bar->size;
> > > > int flags = epf_bar->flags;
> > > > - unsigned int func_offset = 0;
> > > > + unsigned int func_offset, func_offset_dbi2;
> > > > int ret, type;
> > > > - u32 reg;
> > > > + u32 reg, reg_dbi2;
> > > >
> > > > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > > > + func_offset_dbi2 = dw_pcie_ep_func_select2(ep, func_no);
> > > >
> > > > reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> > > > + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset_dbi2;
> > > >
> > > > if (!(flags & PCI_BASE_ADDRESS_SPACE))
> > > > type = PCIE_ATU_TYPE_MEM;
> > > > @@ -254,11 +270,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > > >
> > > > dw_pcie_dbi_ro_wr_en(pci);
> > > >
> > > > - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > > > + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> > > > dw_pcie_writel_dbi(pci, reg, flags);
> > > >
> > > > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > > > - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > > > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> > > > dw_pcie_writel_dbi(pci, reg + 4, 0);
> > > > }
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > index 812c221b3f7c..94bc20f5f600 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > @@ -340,9 +340,10 @@ struct dw_pcie_ep_ops {
> > > > * access for different platform, if different func have different
> > > > * offset, return the offset of func. if use write a register way
> > > > * return a 0, and implement code in callback function of platform
> > > > - * driver.
> > > > + * driver. The func_conf_select2 is for dbi2.
> > > > */
> > > > unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> > > > + unsigned int (*func_conf_select2)(struct dw_pcie_ep *ep, u8 func_no);
> > > > };
> > > >
> > > > struct dw_pcie_ep_func {
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (6 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 07/20] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-31 23:53 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
` (12 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Manivannan Sadhasivam
To improve code readability, add dw_pcie_link_set_max_link_width().
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
1 file changed, 41 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2d0f816fa0ab..5cca34140d2a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -728,6 +728,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
}
+static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
+{
+ u32 lwsc, plc;
+
+ if (!num_lanes)
+ return;
+
+ /* Set the number of lanes */
+ plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
+ plc &= ~PORT_LINK_FAST_LINK_MODE;
+ plc &= ~PORT_LINK_MODE_MASK;
+
+ /* Set link width speed control register */
+ lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+ switch (num_lanes) {
+ case 1:
+ plc |= PORT_LINK_MODE_1_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+ break;
+ case 2:
+ plc |= PORT_LINK_MODE_2_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+ break;
+ case 4:
+ plc |= PORT_LINK_MODE_4_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+ break;
+ case 8:
+ plc |= PORT_LINK_MODE_8_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+ break;
+ default:
+ dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
+ return;
+ }
+ dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+}
+
void dw_pcie_iatu_detect(struct dw_pcie *pci)
{
int max_region, ob, ib;
@@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LINK_DLL_LINK_EN;
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
- if (!pci->num_lanes) {
- dev_dbg(pci->dev, "Using h/w default number of lanes\n");
- return;
- }
-
- /* Set the number of lanes */
- val &= ~PORT_LINK_FAST_LINK_MODE;
- val &= ~PORT_LINK_MODE_MASK;
- switch (pci->num_lanes) {
- case 1:
- val |= PORT_LINK_MODE_1_LANES;
- break;
- case 2:
- val |= PORT_LINK_MODE_2_LANES;
- break;
- case 4:
- val |= PORT_LINK_MODE_4_LANES;
- break;
- case 8:
- val |= PORT_LINK_MODE_8_LANES;
- break;
- default:
- dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
- return;
- }
- dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
-
- /* Set link width speed control register */
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
- val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
- switch (pci->num_lanes) {
- case 1:
- val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
- break;
- case 2:
- val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
- break;
- case 4:
- val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
- break;
- case 8:
- val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
- break;
- }
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
@ 2023-07-31 23:53 ` Serge Semin
2023-08-01 1:50 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-07-31 23:53 UTC (permalink / raw)
To: Yoshihiro Shimoda, bhelgaas, Bjorn Helgaas
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc, Manivannan Sadhasivam
On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> To improve code readability, add dw_pcie_link_set_max_link_width().
You completely ignored all my comments regarding this patch again.
It's getting to be annoying really.
Once again: "This patch is a preparation before adding the
Max-Link-width capability setup which would in its turn complete the
max-link-width setup procedure defined by Synopsys in the HW-manual.
Seeing there is a max-link-speed setup method defined in the DW PCIe
core driver it would be good to have a similar function for the link
width setup. That's why we need to define a dedicated function first
from already implemented but incomplete link-width setting up
code." This is what should have been described in the commit log.
If you were a side-reader of the patch could you guess that from your
commit log and the patch content? I bet you couldn't. That's why a
very thorough description is important.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
> 1 file changed, 41 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2d0f816fa0ab..5cca34140d2a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -728,6 +728,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
>
> }
>
> +static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> +{
> + u32 lwsc, plc;
> +
> + if (!num_lanes)
> + return;
> +
> + /* Set the number of lanes */
> + plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> + plc &= ~PORT_LINK_FAST_LINK_MODE;
Once again: this masking is unrelated to the link width setup.
Moreover it's completely redundant in here and in the original code.
See further for details.
> + plc &= ~PORT_LINK_MODE_MASK;
> +
> + /* Set link width speed control register */
> + lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> + switch (num_lanes) {
> + case 1:
> + plc |= PORT_LINK_MODE_1_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> + break;
> + case 2:
> + plc |= PORT_LINK_MODE_2_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> + break;
> + case 4:
> + plc |= PORT_LINK_MODE_4_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> + break;
> + case 8:
> + plc |= PORT_LINK_MODE_8_LANES;
> + lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> + break;
> + default:
> + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> + return;
> + }
> + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> +}
> +
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> {
> int max_region, ob, ib;
> @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> val |= PORT_LINK_DLL_LINK_EN;
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
>
> - if (!pci->num_lanes) {
> - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> - return;
> - }
> -
> - /* Set the number of lanes */
> - val &= ~PORT_LINK_FAST_LINK_MODE;
My series contains the patch which drops this line:
https://patchwork.kernel.org/project/linux-pci/patch/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
So either pick my patch up and add it to your series or still pick it up
but with changing the authorship and adding me under the Suggested-by
tag with the email-address I am using to review your series. Bjorn,
what approach would you prefer? Perhaps alternative?
Note the patch I am talking about doesn't contain anything what
couldn't be merged in. The problem with my series is in completely
another dimension.
Bjorn
> - val &= ~PORT_LINK_MODE_MASK;
> - switch (pci->num_lanes) {
> - case 1:
> - val |= PORT_LINK_MODE_1_LANES;
> - break;
> - case 2:
> - val |= PORT_LINK_MODE_2_LANES;
> - break;
> - case 4:
> - val |= PORT_LINK_MODE_4_LANES;
> - break;
> - case 8:
> - val |= PORT_LINK_MODE_8_LANES;
> - break;
> - default:
> - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
> - return;
> - }
> - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> -
> - /* Set link width speed control register */
> - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> - val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> - switch (pci->num_lanes) {
> - case 1:
> - val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> - break;
> - case 2:
> - val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> - break;
> - case 4:
> - val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> - break;
> - case 8:
> - val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> - break;
> - }
> - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> + dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-07-31 23:53 ` Serge Semin
@ 2023-08-01 1:50 ` Yoshihiro Shimoda
2023-08-07 22:53 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 1:50 UTC (permalink / raw)
To: Serge Semin, bhelgaas@google.com, Bjorn Helgaas
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Manivannan Sadhasivam
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
>
> On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > To improve code readability, add dw_pcie_link_set_max_link_width().
>
> You completely ignored all my comments regarding this patch again.
> It's getting to be annoying really.
I'm sorry for that. I completely forgot to add description even though
I said so on the v17 [1].
[1] https://lore.kernel.org/linux-pci/TYBPR01MB5341BE7E22A0721672A0FFAFD834A@TYBPR01MB5341.jpnprd01.prod.outlook.com/
> Once again: "This patch is a preparation before adding the
> Max-Link-width capability setup which would in its turn complete the
> max-link-width setup procedure defined by Synopsys in the HW-manual.
> Seeing there is a max-link-speed setup method defined in the DW PCIe
> core driver it would be good to have a similar function for the link
> width setup. That's why we need to define a dedicated function first
> from already implemented but incomplete link-width setting up
> code." This is what should have been described in the commit log.
> If you were a side-reader of the patch could you guess that from your
> commit log and the patch content? I bet you couldn't. That's why a
> very thorough description is important.
Thank you for your suggestion. I have never read the description before.
About the [1] above, you said just "This patch is a preparation".
So, perhaps, some trouble happened when I sent an email?
Anyway, I will replace the commit description to your suggestion and
add your Suggested-by tag.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
> > 1 file changed, 41 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 2d0f816fa0ab..5cca34140d2a 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -728,6 +728,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> >
> > }
> >
> > +static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > +{
> > + u32 lwsc, plc;
> > +
> > + if (!num_lanes)
> > + return;
> > +
> > + /* Set the number of lanes */
> > + plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
>
> > + plc &= ~PORT_LINK_FAST_LINK_MODE;
>
> Once again: this masking is unrelated to the link width setup.
> Moreover it's completely redundant in here and in the original code.
> See further for details.
I got it.
> > + plc &= ~PORT_LINK_MODE_MASK;
> > +
> > + /* Set link width speed control register */
> > + lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> > + switch (num_lanes) {
> > + case 1:
> > + plc |= PORT_LINK_MODE_1_LANES;
> > + lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> > + break;
> > + case 2:
> > + plc |= PORT_LINK_MODE_2_LANES;
> > + lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> > + break;
> > + case 4:
> > + plc |= PORT_LINK_MODE_4_LANES;
> > + lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> > + break;
> > + case 8:
> > + plc |= PORT_LINK_MODE_8_LANES;
> > + lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> > + break;
> > + default:
> > + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> > + return;
> > + }
> > + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > +}
> > +
> > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > {
> > int max_region, ob, ib;
> > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > val |= PORT_LINK_DLL_LINK_EN;
> > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> >
> > - if (!pci->num_lanes) {
> > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > - return;
> > - }
> > -
> > - /* Set the number of lanes */
>
> > - val &= ~PORT_LINK_FAST_LINK_MODE;
>
> My series contains the patch which drops this line:
<snip URL>
> So either pick my patch up and add it to your series or still pick it up
> but with changing the authorship and adding me under the Suggested-by
> tag with the email-address I am using to review your series. Bjorn,
> what approach would you prefer? Perhaps alternative?
I'll wait for Bjorn's opinion.
Best regards,
Yoshihiro Shimoda
> Note the patch I am talking about doesn't contain anything what
> couldn't be merged in. The problem with my series is in completely
> another dimension.
>
> Bjorn
>
> > - val &= ~PORT_LINK_MODE_MASK;
> > - switch (pci->num_lanes) {
> > - case 1:
> > - val |= PORT_LINK_MODE_1_LANES;
> > - break;
> > - case 2:
> > - val |= PORT_LINK_MODE_2_LANES;
> > - break;
> > - case 4:
> > - val |= PORT_LINK_MODE_4_LANES;
> > - break;
> > - case 8:
> > - val |= PORT_LINK_MODE_8_LANES;
> > - break;
> > - default:
> > - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
> > - return;
> > - }
> > - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > -
> > - /* Set link width speed control register */
> > - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > - val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> > - switch (pci->num_lanes) {
> > - case 1:
> > - val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> > - break;
> > - case 2:
> > - val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> > - break;
> > - case 4:
> > - val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> > - break;
> > - case 8:
> > - val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> > - break;
> > - }
> > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > + dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> > }
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-08-01 1:50 ` Yoshihiro Shimoda
@ 2023-08-07 22:53 ` Serge Semin
2023-08-07 23:40 ` Bjorn Helgaas
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-07 22:53 UTC (permalink / raw)
To: Bjorn Helgaas, Bjorn Helgaas
Cc: Yoshihiro Shimoda, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam
Hi Bjorn,
Your attention is required in this thread. Could you please give us
your resolution regarding the issue denoted in my last comment?
-Serge(y)
On Tue, Aug 01, 2023 at 01:50:59AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
> >
> > On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > > To improve code readability, add dw_pcie_link_set_max_link_width().
> >
> > You completely ignored all my comments regarding this patch again.
> > It's getting to be annoying really.
>
> I'm sorry for that. I completely forgot to add description even though
> I said so on the v17 [1].
>
> [1] https://lore.kernel.org/linux-pci/TYBPR01MB5341BE7E22A0721672A0FFAFD834A@TYBPR01MB5341.jpnprd01.prod.outlook.com/
>
> > Once again: "This patch is a preparation before adding the
> > Max-Link-width capability setup which would in its turn complete the
> > max-link-width setup procedure defined by Synopsys in the HW-manual.
> > Seeing there is a max-link-speed setup method defined in the DW PCIe
> > core driver it would be good to have a similar function for the link
> > width setup. That's why we need to define a dedicated function first
> > from already implemented but incomplete link-width setting up
> > code." This is what should have been described in the commit log.
> > If you were a side-reader of the patch could you guess that from your
> > commit log and the patch content? I bet you couldn't. That's why a
> > very thorough description is important.
>
> Thank you for your suggestion. I have never read the description before.
> About the [1] above, you said just "This patch is a preparation".
> So, perhaps, some trouble happened when I sent an email?
> Anyway, I will replace the commit description to your suggestion and
> add your Suggested-by tag.
>
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
> > > 1 file changed, 41 insertions(+), 45 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > index 2d0f816fa0ab..5cca34140d2a 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > @@ -728,6 +728,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > >
> > > }
> > >
> > > +static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > +{
> > > + u32 lwsc, plc;
> > > +
> > > + if (!num_lanes)
> > > + return;
> > > +
> > > + /* Set the number of lanes */
> > > + plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> >
> > > + plc &= ~PORT_LINK_FAST_LINK_MODE;
> >
> > Once again: this masking is unrelated to the link width setup.
> > Moreover it's completely redundant in here and in the original code.
> > See further for details.
>
> I got it.
>
> > > + plc &= ~PORT_LINK_MODE_MASK;
> > > +
> > > + /* Set link width speed control register */
> > > + lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > + lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> > > + switch (num_lanes) {
> > > + case 1:
> > > + plc |= PORT_LINK_MODE_1_LANES;
> > > + lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> > > + break;
> > > + case 2:
> > > + plc |= PORT_LINK_MODE_2_LANES;
> > > + lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> > > + break;
> > > + case 4:
> > > + plc |= PORT_LINK_MODE_4_LANES;
> > > + lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> > > + break;
> > > + case 8:
> > > + plc |= PORT_LINK_MODE_8_LANES;
> > > + lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> > > + break;
> > > + default:
> > > + dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
> > > + return;
> > > + }
> > > + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > +}
> > > +
> > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > {
> > > int max_region, ob, ib;
> > > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > > val |= PORT_LINK_DLL_LINK_EN;
> > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > >
> > > - if (!pci->num_lanes) {
> > > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > > - return;
> > > - }
> > > -
> > > - /* Set the number of lanes */
> >
> > > - val &= ~PORT_LINK_FAST_LINK_MODE;
> >
> > My series contains the patch which drops this line:
> <snip URL>
> > So either pick my patch up and add it to your series or still pick it up
> > but with changing the authorship and adding me under the Suggested-by
> > tag with the email-address I am using to review your series. Bjorn,
> > what approach would you prefer? Perhaps alternative?
>
> I'll wait for Bjorn's opinion.
>
> Best regards,
> Yoshihiro Shimoda
>
> > Note the patch I am talking about doesn't contain anything what
> > couldn't be merged in. The problem with my series is in completely
> > another dimension.
> >
> > Bjorn
> >
> > > - val &= ~PORT_LINK_MODE_MASK;
> > > - switch (pci->num_lanes) {
> > > - case 1:
> > > - val |= PORT_LINK_MODE_1_LANES;
> > > - break;
> > > - case 2:
> > > - val |= PORT_LINK_MODE_2_LANES;
> > > - break;
> > > - case 4:
> > > - val |= PORT_LINK_MODE_4_LANES;
> > > - break;
> > > - case 8:
> > > - val |= PORT_LINK_MODE_8_LANES;
> > > - break;
> > > - default:
> > > - dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
> > > - return;
> > > - }
> > > - dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > > -
> > > - /* Set link width speed control register */
> > > - val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > - val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> > > - switch (pci->num_lanes) {
> > > - case 1:
> > > - val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
> > > - break;
> > > - case 2:
> > > - val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
> > > - break;
> > > - case 4:
> > > - val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
> > > - break;
> > > - case 8:
> > > - val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
> > > - break;
> > > - }
> > > - dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > > + dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> > > }
> > > --
> > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-08-07 22:53 ` Serge Semin
@ 2023-08-07 23:40 ` Bjorn Helgaas
2023-08-08 0:15 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Bjorn Helgaas @ 2023-08-07 23:40 UTC (permalink / raw)
To: Serge Semin
Cc: Bjorn Helgaas, Yoshihiro Shimoda, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam
On Tue, Aug 08, 2023 at 01:53:11AM +0300, Serge Semin wrote:
> Your attention is required in this thread. Could you please give us
> your resolution regarding the issue denoted in my last comment?
Sorry I missed this and thanks for pinging me. Lorenzo and Krzysztof
take care of the native controller drivers so I don't pay close
attention.
> On Tue, Aug 01, 2023 at 01:50:59AM +0000, Yoshihiro Shimoda wrote:
> > > From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
> > > On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > > > To improve code readability, add dw_pcie_link_set_max_link_width().
> > > > ...
> > > > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > > > val |= PORT_LINK_DLL_LINK_EN;
> > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > > >
> > > > - if (!pci->num_lanes) {
> > > > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > > > - return;
> > > > - }
> > > > -
> > > > - /* Set the number of lanes */
> > >
> > > > - val &= ~PORT_LINK_FAST_LINK_MODE;
> > >
> > > My series contains the patch which drops this line:
> > <snip URL>
> > > So either pick my patch up and add it to your series or still pick it up
> > > but with changing the authorship and adding me under the Suggested-by
> > > tag with the email-address I am using to review your series. Bjorn,
> > > what approach would you prefer? Perhaps alternative?
I don't really see the argument here. AFAICT, Yoshihiro's patch
(https://lore.kernel.org/r/20230721074452.65545-9-yoshihiro.shimoda.uh@renesas.com)
is a trivial refactoring to make dw_pcie_link_set_max_link_width(),
which might be reused elsewhere later, which seems perfectly fine.
It'd be fine with me to add a little detail in the commit log to
reference the Synopsys manual, which I don't have. But doesn't seem
like a big deal to me.
Dropping the PORT_LINK_FAST_LINK_MODE mask seems like a separate
question that should be in a separate patch.
https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
says it's redundant, so it sounds more like a cleanup than a fix.
> > > Note the patch I am talking about doesn't contain anything what
> > > couldn't be merged in. The problem with my series is in completely
> > > another dimension.
> > >
> > > Bjorn
Despite the "Bjorn" that looks like a signature, I did not write the
"Note the patch ..." paragraph above.
Bjorn
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-08-07 23:40 ` Bjorn Helgaas
@ 2023-08-08 0:15 ` Serge Semin
2023-08-08 15:08 ` Bjorn Helgaas
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-08 0:15 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Bjorn Helgaas, Yoshihiro Shimoda, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam
On Mon, Aug 07, 2023 at 06:40:34PM -0500, Bjorn Helgaas wrote:
> On Tue, Aug 08, 2023 at 01:53:11AM +0300, Serge Semin wrote:
> > Your attention is required in this thread. Could you please give us
> > your resolution regarding the issue denoted in my last comment?
>
> Sorry I missed this and thanks for pinging me. Lorenzo and Krzysztof
> take care of the native controller drivers so I don't pay close
> attention.
>
> > On Tue, Aug 01, 2023 at 01:50:59AM +0000, Yoshihiro Shimoda wrote:
> > > > From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
> > > > On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > > > > To improve code readability, add dw_pcie_link_set_max_link_width().
> > > > > ...
>
> > > > > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > > > > val |= PORT_LINK_DLL_LINK_EN;
> > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > > > >
> > > > > - if (!pci->num_lanes) {
> > > > > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > > > > - return;
> > > > > - }
> > > > > -
> > > > > - /* Set the number of lanes */
> > > >
> > > > > - val &= ~PORT_LINK_FAST_LINK_MODE;
> > > >
> > > > My series contains the patch which drops this line:
> > > <snip URL>
> > > > So either pick my patch up and add it to your series or still pick it up
> > > > but with changing the authorship and adding me under the Suggested-by
> > > > tag with the email-address I am using to review your series. Bjorn,
> > > > what approach would you prefer? Perhaps alternative?
>
> I don't really see the argument here. AFAICT, Yoshihiro's patch
> (https://lore.kernel.org/r/20230721074452.65545-9-yoshihiro.shimoda.uh@renesas.com)
> is a trivial refactoring to make dw_pcie_link_set_max_link_width(),
> which might be reused elsewhere later, which seems perfectly fine.
>
> It'd be fine with me to add a little detail in the commit log to
> reference the Synopsys manual, which I don't have. But doesn't seem
> like a big deal to me.
More details are in one of my earlier comments to this patch which
Yoshihiro promised to add to the patch log on the next patchset
revision. You can read it here:
https://lore.kernel.org/linux-pci/20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com/T/#m8ac364249f40c726da88316b67f11a6d55068ef0
>
> Dropping the PORT_LINK_FAST_LINK_MODE mask seems like a separate
> question that should be in a separate patch.
> https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
> says it's redundant, so it sounds more like a cleanup than a fix.
That's the point of my comment. There is no need in copying that mask
to the dw_pcie_link_set_max_link_width() method because first it's
unrelated to the link-width setting, second it's redundant. There is
my patch dropping the mask with the proper justification:
https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
It would be good to either merge it in before the Yoshihiro' series or
add my patch to the Yoshihiro' patchset. But it's in the patchwork
limbo now, neither you nor Lorenzo or Krzysztof were willing to merge
it in. That's why I suggested to move the patch here with the denoted
alterations. Could you give your resolution whether the suggested
movement is ok or perhaps you or Lorenzo or Krzysztof consider merge
it in as is?
Note this and the next Yoshihiro' patches aren't considered as fixes
for now.
>
> > > > Note the patch I am talking about doesn't contain anything what
> > > > couldn't be merged in. The problem with my series is in completely
> > > > another dimension.
> > > >
> > > > Bjorn
>
> Despite the "Bjorn" that looks like a signature, I did not write the
> "Note the patch ..." paragraph above.
>
> Bjorn
Ah, sorry. It was my incomplete text. Part of it somehow was dropped from the
message so it turned out to look as a signature. My message was in
response to the Yoshihiro' worry regarding your email:
https://lore.kernel.org/linux-pci/20230612154127.GA1335023@bhelgaas/
What I was saying is that my patch didn't contain anything which could prevent
it from being merged in. So at least the patch content could be easily
copied to his series.
-Serge(y)
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-08-08 0:15 ` Serge Semin
@ 2023-08-08 15:08 ` Bjorn Helgaas
2023-08-08 21:16 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Bjorn Helgaas @ 2023-08-08 15:08 UTC (permalink / raw)
To: Serge Semin
Cc: Bjorn Helgaas, Yoshihiro Shimoda, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam
On Tue, Aug 08, 2023 at 03:15:33AM +0300, Serge Semin wrote:
> On Mon, Aug 07, 2023 at 06:40:34PM -0500, Bjorn Helgaas wrote:
> > On Tue, Aug 08, 2023 at 01:53:11AM +0300, Serge Semin wrote:
> > > On Tue, Aug 01, 2023 at 01:50:59AM +0000, Yoshihiro Shimoda wrote:
> > > > > From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
> > > > > On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > > > > > To improve code readability, add dw_pcie_link_set_max_link_width().
> > > > > > ...
> >
> > > > > > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > > > > > val |= PORT_LINK_DLL_LINK_EN;
> > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > > > > >
> > > > > > - if (!pci->num_lanes) {
> > > > > > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > > > > > - return;
> > > > > > - }
> > > > > > -
> > > > > > - /* Set the number of lanes */
> > > > >
> > > > > > - val &= ~PORT_LINK_FAST_LINK_MODE;
> > > > >
> > > > > My series contains the patch which drops this line:
> > > > <snip URL>
> > > > > So either pick my patch up and add it to your series or still pick it up
> > > > > but with changing the authorship and adding me under the Suggested-by
> > > > > tag with the email-address I am using to review your series. Bjorn,
> > > > > what approach would you prefer? Perhaps alternative?
>
> > I don't really see the argument here. AFAICT, Yoshihiro's patch
> > (https://lore.kernel.org/r/20230721074452.65545-9-yoshihiro.shimoda.uh@renesas.com)
> > is a trivial refactoring to make dw_pcie_link_set_max_link_width(),
> > which might be reused elsewhere later, which seems perfectly fine.
> >
> > It'd be fine with me to add a little detail in the commit log to
> > reference the Synopsys manual, which I don't have. But doesn't seem
> > like a big deal to me.
>
> More details are in one of my earlier comments to this patch which
> Yoshihiro promised to add to the patch log on the next patchset
> revision. You can read it here:
> https://lore.kernel.org/linux-pci/20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com/T/#m8ac364249f40c726da88316b67f11a6d55068ef0
>
> > Dropping the PORT_LINK_FAST_LINK_MODE mask seems like a separate
> > question that should be in a separate patch.
> > https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
> > says it's redundant, so it sounds more like a cleanup than a fix.
>
> That's the point of my comment. There is no need in copying that mask
> to the dw_pcie_link_set_max_link_width() method because first it's
> unrelated to the link-width setting, second it's redundant. There is
> my patch dropping the mask with the proper justification:
> https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
> It would be good to either merge it in before the Yoshihiro' series or
> add my patch to the Yoshihiro' patchset. But it's in the patchwork
> limbo now, neither you nor Lorenzo or Krzysztof were willing to merge
> it in. That's why I suggested to move the patch here with the denoted
> alterations. Could you give your resolution whether the suggested
> movement is ok or perhaps you or Lorenzo or Krzysztof consider merge
> it in as is?
If I understand Yoshihiro's patch, it pulls code out into
dw_pcie_link_set_max_link_width() without changing that code. That
seems like the best approach to me because it's very easy to review.
If we want to remove a little redundant code later in a separate
patch, that's fine too but doesn't seem urgent. I don't think they
need to be tied together.
Bjorn
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-08-08 15:08 ` Bjorn Helgaas
@ 2023-08-08 21:16 ` Serge Semin
0 siblings, 0 replies; 90+ messages in thread
From: Serge Semin @ 2023-08-08 21:16 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Bjorn Helgaas, Yoshihiro Shimoda, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Manivannan Sadhasivam
On Tue, Aug 08, 2023 at 10:08:54AM -0500, Bjorn Helgaas wrote:
> On Tue, Aug 08, 2023 at 03:15:33AM +0300, Serge Semin wrote:
> > On Mon, Aug 07, 2023 at 06:40:34PM -0500, Bjorn Helgaas wrote:
> > > On Tue, Aug 08, 2023 at 01:53:11AM +0300, Serge Semin wrote:
> > > > On Tue, Aug 01, 2023 at 01:50:59AM +0000, Yoshihiro Shimoda wrote:
> > > > > > From: Serge Semin, Sent: Tuesday, August 1, 2023 8:54 AM
> > > > > > On Fri, Jul 21, 2023 at 04:44:40PM +0900, Yoshihiro Shimoda wrote:
> > > > > > > To improve code readability, add dw_pcie_link_set_max_link_width().
> > > > > > > ...
> > >
> > > > > > > @@ -1009,49 +1049,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
> > > > > > > val |= PORT_LINK_DLL_LINK_EN;
> > > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
> > > > > > >
> > > > > > > - if (!pci->num_lanes) {
> > > > > > > - dev_dbg(pci->dev, "Using h/w default number of lanes\n");
> > > > > > > - return;
> > > > > > > - }
> > > > > > > -
> > > > > > > - /* Set the number of lanes */
> > > > > >
> > > > > > > - val &= ~PORT_LINK_FAST_LINK_MODE;
> > > > > >
> > > > > > My series contains the patch which drops this line:
> > > > > <snip URL>
> > > > > > So either pick my patch up and add it to your series or still pick it up
> > > > > > but with changing the authorship and adding me under the Suggested-by
> > > > > > tag with the email-address I am using to review your series. Bjorn,
> > > > > > what approach would you prefer? Perhaps alternative?
> >
> > > I don't really see the argument here. AFAICT, Yoshihiro's patch
> > > (https://lore.kernel.org/r/20230721074452.65545-9-yoshihiro.shimoda.uh@renesas.com)
> > > is a trivial refactoring to make dw_pcie_link_set_max_link_width(),
> > > which might be reused elsewhere later, which seems perfectly fine.
> > >
> > > It'd be fine with me to add a little detail in the commit log to
> > > reference the Synopsys manual, which I don't have. But doesn't seem
> > > like a big deal to me.
> >
> > More details are in one of my earlier comments to this patch which
> > Yoshihiro promised to add to the patch log on the next patchset
> > revision. You can read it here:
> > https://lore.kernel.org/linux-pci/20230721074452.65545-1-yoshihiro.shimoda.uh@renesas.com/T/#m8ac364249f40c726da88316b67f11a6d55068ef0
> >
> > > Dropping the PORT_LINK_FAST_LINK_MODE mask seems like a separate
> > > question that should be in a separate patch.
> > > https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
> > > says it's redundant, so it sounds more like a cleanup than a fix.
> >
> > That's the point of my comment. There is no need in copying that mask
> > to the dw_pcie_link_set_max_link_width() method because first it's
> > unrelated to the link-width setting, second it's redundant. There is
> > my patch dropping the mask with the proper justification:
> > https://lore.kernel.org/linux-pci/20230611192005.25636-6-Sergey.Semin@baikalelectronics.ru/
> > It would be good to either merge it in before the Yoshihiro' series or
> > add my patch to the Yoshihiro' patchset. But it's in the patchwork
> > limbo now, neither you nor Lorenzo or Krzysztof were willing to merge
> > it in. That's why I suggested to move the patch here with the denoted
> > alterations. Could you give your resolution whether the suggested
> > movement is ok or perhaps you or Lorenzo or Krzysztof consider merge
> > it in as is?
>
> If I understand Yoshihiro's patch, it pulls code out into
> dw_pcie_link_set_max_link_width() without changing that code. That
> seems like the best approach to me because it's very easy to review.
>
> If we want to remove a little redundant code later in a separate
> patch, that's fine too but doesn't seem urgent. I don't think they
> need to be tied together.
Well, my point was the opposite: why would we need to maintain a dead,
redundant code which also unrelated to the function it's being copied
to, meanwhile there is already available patch which drops that code
and Yoshihiro needs to resubmit a new revision of his series anyway?
It would have been much better to just merge in my patch/change
somehow (with another authorship if that's the problem) and forget
about that from now on. If you get to merge in the Yoshohiro patchset
first, my patch won't be cleanly applicable after that.
-Serge(y)
>
> Bjorn
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (7 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 11:03 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
` (11 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
field there is another one which needs to be updated. It's
LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
the very least the maximum link-width capability CSR won't expose
the actual maximum capability.
[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.60a, March 2015, p.1032
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.70a, March 2016, p.1065
[3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.90a, March 2016, p.1057
...
[X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
Version 5.40a, March 2019, p.1396
[X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 5.40a, March 2019, p.1266
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 5cca34140d2a..c4998194fe74 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
{
- u32 lwsc, plc;
+ u32 lnkcap, lwsc, plc;
+ u8 cap;
if (!num_lanes)
return;
@@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
}
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+
+ cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
+ lnkcap &= ~PCI_EXP_LNKCAP_MLW;
+ lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
+ dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
}
void dw_pcie_iatu_detect(struct dw_pcie *pci)
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
@ 2023-07-24 11:03 ` Manivannan Sadhasivam
2023-07-26 2:12 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 11:03 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
handling".
On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> field there is another one which needs to be updated. It's
> LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> the very least the maximum link-width capability CSR won't expose
> the actual maximum capability.
>
> [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.60a, March 2015, p.1032
> [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.70a, March 2016, p.1065
> [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.90a, March 2016, p.1057
> ...
> [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> Version 5.40a, March 2019, p.1396
> [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 5.40a, March 2019, p.1266
>
> Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Add Reported-by also?
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This looks like a potential bug fix to me. So please move this change before the
previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
CC stable list for backporting.
- Mani
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 5cca34140d2a..c4998194fe74 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
>
> static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> {
> - u32 lwsc, plc;
> + u32 lnkcap, lwsc, plc;
> + u8 cap;
>
> if (!num_lanes)
> return;
> @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> }
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> +
> + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> }
>
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-24 11:03 ` Manivannan Sadhasivam
@ 2023-07-26 2:12 ` Yoshihiro Shimoda
2023-07-28 2:51 ` Manivannan Sadhasivam
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-26 2:12 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
>
> Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> handling".
I got it.
> On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > field there is another one which needs to be updated. It's
> > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > the very least the maximum link-width capability CSR won't expose
> > the actual maximum capability.
> >
> > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.60a, March 2015, p.1032
> > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.70a, March 2016, p.1065
> > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 4.90a, March 2016, p.1057
> > ...
> > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > Version 5.40a, March 2019, p.1396
> > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > Version 5.40a, March 2019, p.1266
> >
> > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
>
> Add Reported-by also?
I don't think so because Serge suggested the commit description from my submitted patch [1].
[1]
https://lore.kernel.org/linux-pci/20230322065701.po7owyzwisntalyz@mobilestation/
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> This looks like a potential bug fix to me. So please move this change before the
> previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> CC stable list for backporting.
I think that this patch should be a next branch because this is possible to
cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
without this setting.
Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
Additionally, I could not determine which old kernel versions should have this patch
applied as backporting.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 5cca34140d2a..c4998194fe74 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> >
> > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > {
> > - u32 lwsc, plc;
> > + u32 lnkcap, lwsc, plc;
> > + u8 cap;
> >
> > if (!num_lanes)
> > return;
> > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > }
> > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > +
> > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > }
> >
> > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-26 2:12 ` Yoshihiro Shimoda
@ 2023-07-28 2:51 ` Manivannan Sadhasivam
2023-07-28 4:19 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-28 2:51 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> Hi Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> >
> > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > handling".
>
> I got it.
>
> > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > field there is another one which needs to be updated. It's
> > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > the very least the maximum link-width capability CSR won't expose
> > > the actual maximum capability.
> > >
> > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > Version 4.60a, March 2015, p.1032
> > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > Version 4.70a, March 2016, p.1065
> > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > Version 4.90a, March 2016, p.1057
> > > ...
> > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > Version 5.40a, March 2019, p.1396
> > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > Version 5.40a, March 2019, p.1266
> > >
> > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> >
> > Add Reported-by also?
>
> I don't think so because Serge suggested the commit description from my submitted patch [1].
>
> [1]
> https://lore.kernel.org/linux-pci/20230322065701.po7owyzwisntalyz@mobilestation/
>
Fine then.
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > This looks like a potential bug fix to me. So please move this change before the
> > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > CC stable list for backporting.
>
> I think that this patch should be a next branch because this is possible to
> cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> without this setting.
>
> Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> Additionally, I could not determine which old kernel versions should have this patch
> applied as backporting.
>
Ok. But you can still move this patch as I suggested. If we happen to hit any
issue with this setting, then we can easily revert it.
- Mani
> Best regards,
> Yoshihiro Shimoda
>
> > - Mani
> >
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > index 5cca34140d2a..c4998194fe74 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > >
> > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > {
> > > - u32 lwsc, plc;
> > > + u32 lnkcap, lwsc, plc;
> > > + u8 cap;
> > >
> > > if (!num_lanes)
> > > return;
> > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > }
> > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > +
> > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > }
> > >
> > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-28 2:51 ` Manivannan Sadhasivam
@ 2023-07-28 4:19 ` Yoshihiro Shimoda
2023-07-28 16:07 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-28 4:19 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
>
> On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > >
> > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > handling".
> >
> > I got it.
> >
> > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > field there is another one which needs to be updated. It's
> > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > the very least the maximum link-width capability CSR won't expose
> > > > the actual maximum capability.
> > > >
> > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > Version 4.60a, March 2015, p.1032
> > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > Version 4.70a, March 2016, p.1065
> > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > Version 4.90a, March 2016, p.1057
> > > > ...
> > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > Version 5.40a, March 2019, p.1396
> > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > Version 5.40a, March 2019, p.1266
> > > >
> > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > >
> > > Add Reported-by also?
> >
> > I don't think so because Serge suggested the commit description from my submitted patch [1].
> >
> > [1]
> >
<snip URL>
> >
>
> Fine then.
>
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> > > This looks like a potential bug fix to me. So please move this change before the
> > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > CC stable list for backporting.
> >
> > I think that this patch should be a next branch because this is possible to
> > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > without this setting.
> >
> > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > Additionally, I could not determine which old kernel versions should have this patch
> > applied as backporting.
> >
>
> Ok. But you can still move this patch as I suggested. If we happen to hit any
> issue with this setting, then we can easily revert it.
I got it. I'll move this patch as you suggested.
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > - Mani
> > >
> > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > index 5cca34140d2a..c4998194fe74 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > >
> > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > {
> > > > - u32 lwsc, plc;
> > > > + u32 lnkcap, lwsc, plc;
> > > > + u8 cap;
> > > >
> > > > if (!num_lanes)
> > > > return;
> > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > }
> > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > +
> > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > }
> > > >
> > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-28 4:19 ` Yoshihiro Shimoda
@ 2023-07-28 16:07 ` Serge Semin
2023-07-31 1:15 ` Yoshihiro Shimoda
2023-08-02 10:46 ` Manivannan Sadhasivam
0 siblings, 2 replies; 90+ messages in thread
From: Serge Semin @ 2023-07-28 16:07 UTC (permalink / raw)
To: Yoshihiro Shimoda, Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
On Fri, Jul 28, 2023 at 04:19:38AM +0000, Yoshihiro Shimoda wrote:
> Hi Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
> >
> > On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > > Hi Manivannan,
> > >
> > > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > > >
> > > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > > handling".
> > >
> > > I got it.
> > >
> > > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > > field there is another one which needs to be updated. It's
> > > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > > the very least the maximum link-width capability CSR won't expose
> > > > > the actual maximum capability.
> > > > >
> > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > Version 4.60a, March 2015, p.1032
> > > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > Version 4.70a, March 2016, p.1065
> > > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > Version 4.90a, March 2016, p.1057
> > > > > ...
> > > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > > Version 5.40a, March 2019, p.1396
> > > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > Version 5.40a, March 2019, p.1266
> > > > >
> > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > > >
> > > > Add Reported-by also?
> > >
> > > I don't think so because Serge suggested the commit description from my submitted patch [1].
> > >
> > > [1]
> > >
> <snip URL>
> > >
> >
> > Fine then.
> >
> > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > >
> > > > This looks like a potential bug fix to me. So please move this change before the
> > > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > > CC stable list for backporting.
> > >
> > > I think that this patch should be a next branch because this is possible to
> > > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > > without this setting.
> > >
> > > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > > Additionally, I could not determine which old kernel versions should have this patch
> > > applied as backporting.
> > >
> >
> > Ok. But you can still move this patch as I suggested. If we happen to hit any
> > issue with this setting, then we can easily revert it.
>
> I got it. I'll move this patch as you suggested.
No. By moving this patch to be implemented before the patch:
[PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
you won't be able to easily revert it afterwards because the patch #8
will move the code added by the patch #9 to the
dw_pcie_link_set_max_link_width() function. Basically you suggest to
switch the preparation and functional patches order which doesn't look
right.
Basically the Link-width-related part of this series currently implies
the next logic:
1. Prepare the DW PCIe core driver to implementing a comprehensive
Max-link-width setup methods (aka as it's done in
dw_pcie_link_set_max_speed()) by moving the Link-width related code to
a dedicated method:
[PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2. Add the PCI_EXP_LNKCAP_MLW field update, which
dw_pcie_link_set_max_link_width() lacks to be comprehensive:
[PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
3. Drop the duplicating code from the Tegra194 PCIe driver:
[PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
In case if the patch #9 appears to be a bug fix, then it will need to
be backported together with patch #8 which isn't a problem at all
(though it's doubtfully to happen since nobody reported any problem
with that so far). But if patch #9 turns out to break something in
current circumstances we'll be able to either easily revert it (since
it's applied after the preparation patch) or fix somehow. If you
switch patch #8 and #9 order, the reversion will require to be
performed for both these patches to avoid the conflicts. Thus I'd
suggest to leave the patches order as is which looks more natural and
won't cause any problems to revert the functional change or to
backport it.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > - Mani
> >
> > > Best regards,
> > > Yoshihiro Shimoda
> > >
> > > > - Mani
> > > >
> > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > ---
> > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > index 5cca34140d2a..c4998194fe74 100644
> > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > > >
> > > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > {
> > > > > - u32 lwsc, plc;
> > > > > + u32 lnkcap, lwsc, plc;
> > > > > + u8 cap;
> > > > >
> > > > > if (!num_lanes)
> > > > > return;
> > > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > }
> > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > > +
> > > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > > }
> > > > >
> > > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > > --
> > > > > 2.25.1
> > > > >
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
> >
> > --
> > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-28 16:07 ` Serge Semin
@ 2023-07-31 1:15 ` Yoshihiro Shimoda
2023-08-01 0:00 ` Serge Semin
2023-08-02 10:46 ` Manivannan Sadhasivam
1 sibling, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-31 1:15 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Saturday, July 29, 2023 1:07 AM
>
> On Fri, Jul 28, 2023 at 04:19:38AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
> > >
> > > On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > > > Hi Manivannan,
> > > >
> > > > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > > > >
> > > > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > > > handling".
> > > >
> > > > I got it.
> > > >
> > > > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > > > field there is another one which needs to be updated. It's
> > > > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > > > the very least the maximum link-width capability CSR won't expose
> > > > > > the actual maximum capability.
> > > > > >
> > > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.60a, March 2015, p.1032
> > > > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.70a, March 2016, p.1065
> > > > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.90a, March 2016, p.1057
> > > > > > ...
> > > > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > > > Version 5.40a, March 2019, p.1396
> > > > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 5.40a, March 2019, p.1266
> > > > > >
> > > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > > > >
> > > > > Add Reported-by also?
> > > >
> > > > I don't think so because Serge suggested the commit description from my submitted patch [1].
> > > >
> > > > [1]
> > > >
> > <snip URL>
> > > >
> > >
> > > Fine then.
> > >
> > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > >
> > > > > This looks like a potential bug fix to me. So please move this change before the
> > > > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > > > CC stable list for backporting.
> > > >
> > > > I think that this patch should be a next branch because this is possible to
> > > > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > > > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > > > without this setting.
> > > >
> > > > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > > > Additionally, I could not determine which old kernel versions should have this patch
> > > > applied as backporting.
> > > >
> > >
>
> > > Ok. But you can still move this patch as I suggested. If we happen to hit any
> > > issue with this setting, then we can easily revert it.
> >
> > I got it. I'll move this patch as you suggested.
>
> No. By moving this patch to be implemented before the patch:
> [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> you won't be able to easily revert it afterwards because the patch #8
> will move the code added by the patch #9 to the
> dw_pcie_link_set_max_link_width() function. Basically you suggest to
> switch the preparation and functional patches order which doesn't look
> right.
You're correct. If moving this patch to the top of this series and then
still apply the original #8, it's difficult to revert this patch.
> Basically the Link-width-related part of this series currently implies
> the next logic:
>
> 1. Prepare the DW PCIe core driver to implementing a comprehensive
> Max-link-width setup methods (aka as it's done in
> dw_pcie_link_set_max_speed()) by moving the Link-width related code to
> a dedicated method:
> [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
>
> 2. Add the PCI_EXP_LNKCAP_MLW field update, which
> dw_pcie_link_set_max_link_width() lacks to be comprehensive:
> [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
>
> 3. Drop the duplicating code from the Tegra194 PCIe driver:
> [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
Yes.
> In case if the patch #9 appears to be a bug fix, then it will need to
> be backported together with patch #8 which isn't a problem at all
> (though it's doubtfully to happen since nobody reported any problem
> with that so far).
Basically, I don't think that backporting #8 is good as backport because
the #8 patch is a clean up code for readability.
> But if patch #9 turns out to break something in
> current circumstances we'll be able to either easily revert it (since
> it's applied after the preparation patch) or fix somehow. If you
> switch patch #8 and #9 order, the reversion will require to be
> performed for both these patches to avoid the conflicts. Thus I'd
> suggest to leave the patches order as is which looks more natural and
> won't cause any problems to revert the functional change or to
> backport it.
To follow Manivannan's suggestion and your comments, I'm thinking that
- drop the #8 because this is just clean up code for readability.
-- After this patch series is merged and worked correctly without any
regression on other platforms, we can apply the #8.
- move the #9 to the top of this series as Manivannan suggested.
-- This mean adding this code into dw_pcie_setup().
But, what do you think?
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > - Mani
> > >
> > > > Best regards,
> > > > Yoshihiro Shimoda
> > > >
> > > > > - Mani
> > > > >
> > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > ---
> > > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > index 5cca34140d2a..c4998194fe74 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > > > >
> > > > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > {
> > > > > > - u32 lwsc, plc;
> > > > > > + u32 lnkcap, lwsc, plc;
> > > > > > + u8 cap;
> > > > > >
> > > > > > if (!num_lanes)
> > > > > > return;
> > > > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > }
> > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > > > +
> > > > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > > > }
> > > > > >
> > > > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > > > --
> > > > > > 2.25.1
> > > > > >
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-31 1:15 ` Yoshihiro Shimoda
@ 2023-08-01 0:00 ` Serge Semin
2023-08-01 6:26 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-01 0:00 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Mon, Jul 31, 2023 at 01:15:02AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Saturday, July 29, 2023 1:07 AM
> >
> > On Fri, Jul 28, 2023 at 04:19:38AM +0000, Yoshihiro Shimoda wrote:
> > > Hi Manivannan,
> > >
> > > > From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
> > > >
> > > > On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > > > > Hi Manivannan,
> > > > >
> > > > > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > > > > >
> > > > > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > > > > handling".
> > > > >
> > > > > I got it.
> > > > >
> > > > > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > > > > field there is another one which needs to be updated. It's
> > > > > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > > > > the very least the maximum link-width capability CSR won't expose
> > > > > > > the actual maximum capability.
> > > > > > >
> > > > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > Version 4.60a, March 2015, p.1032
> > > > > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > Version 4.70a, March 2016, p.1065
> > > > > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > Version 4.90a, March 2016, p.1057
> > > > > > > ...
> > > > > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > > > > Version 5.40a, March 2019, p.1396
> > > > > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > Version 5.40a, March 2019, p.1266
> > > > > > >
> > > > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > >
> > > > > > Add Reported-by also?
> > > > >
> > > > > I don't think so because Serge suggested the commit description from my submitted patch [1].
> > > > >
> > > > > [1]
> > > > >
> > > <snip URL>
> > > > >
> > > >
> > > > Fine then.
> > > >
> > > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > > >
> > > > > > This looks like a potential bug fix to me. So please move this change before the
> > > > > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > > > > CC stable list for backporting.
> > > > >
> > > > > I think that this patch should be a next branch because this is possible to
> > > > > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > > > > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > > > > without this setting.
> > > > >
> > > > > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > > > > Additionally, I could not determine which old kernel versions should have this patch
> > > > > applied as backporting.
> > > > >
> > > >
> >
> > > > Ok. But you can still move this patch as I suggested. If we happen to hit any
> > > > issue with this setting, then we can easily revert it.
> > >
> > > I got it. I'll move this patch as you suggested.
> >
> > No. By moving this patch to be implemented before the patch:
> > [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> > you won't be able to easily revert it afterwards because the patch #8
> > will move the code added by the patch #9 to the
> > dw_pcie_link_set_max_link_width() function. Basically you suggest to
> > switch the preparation and functional patches order which doesn't look
> > right.
>
> You're correct. If moving this patch to the top of this series and then
> still apply the original #8, it's difficult to revert this patch.
>
> > Basically the Link-width-related part of this series currently implies
> > the next logic:
> >
> > 1. Prepare the DW PCIe core driver to implementing a comprehensive
> > Max-link-width setup methods (aka as it's done in
> > dw_pcie_link_set_max_speed()) by moving the Link-width related code to
> > a dedicated method:
> > [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> >
> > 2. Add the PCI_EXP_LNKCAP_MLW field update, which
> > dw_pcie_link_set_max_link_width() lacks to be comprehensive:
> > [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
> >
> > 3. Drop the duplicating code from the Tegra194 PCIe driver:
> > [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
>
> Yes.
>
> > In case if the patch #9 appears to be a bug fix, then it will need to
> > be backported together with patch #8 which isn't a problem at all
> > (though it's doubtfully to happen since nobody reported any problem
> > with that so far).
>
> Basically, I don't think that backporting #8 is good as backport because
> the #8 patch is a clean up code for readability.
>
> > But if patch #9 turns out to break something in
> > current circumstances we'll be able to either easily revert it (since
> > it's applied after the preparation patch) or fix somehow. If you
> > switch patch #8 and #9 order, the reversion will require to be
> > performed for both these patches to avoid the conflicts. Thus I'd
> > suggest to leave the patches order as is which looks more natural and
> > won't cause any problems to revert the functional change or to
> > backport it.
>
> To follow Manivannan's suggestion and your comments, I'm thinking that
> - drop the #8 because this is just clean up code for readability.
> -- After this patch series is merged and worked correctly without any
> regression on other platforms, we can apply the #8.
> - move the #9 to the top of this series as Manivannan suggested.
> -- This mean adding this code into dw_pcie_setup().
>
> But, what do you think?
No. It's better to leave the preparation patch and the order as is.
Once again this patch doesn't look as a bug-fix since nobody reported
any related problem so far. If anyone decides to back it port there
won't a problem with porting both #8 and #9. It's a common practice.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > -Serge(y)
> >
> > >
> > > Best regards,
> > > Yoshihiro Shimoda
> > >
> > > > - Mani
> > > >
> > > > > Best regards,
> > > > > Yoshihiro Shimoda
> > > > >
> > > > > > - Mani
> > > > > >
> > > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > > ---
> > > > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > index 5cca34140d2a..c4998194fe74 100644
> > > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > > > > >
> > > > > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > > {
> > > > > > > - u32 lwsc, plc;
> > > > > > > + u32 lnkcap, lwsc, plc;
> > > > > > > + u8 cap;
> > > > > > >
> > > > > > > if (!num_lanes)
> > > > > > > return;
> > > > > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > > }
> > > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > > > > +
> > > > > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > > > > }
> > > > > > >
> > > > > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > > > > --
> > > > > > > 2.25.1
> > > > > > >
> > > > > >
> > > > > > --
> > > > > > மணிவண்ணன் சதாசிவம்
> > > >
> > > > --
> > > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-08-01 0:00 ` Serge Semin
@ 2023-08-01 6:26 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 6:26 UTC (permalink / raw)
To: Serge Semin
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 9:01 AM
>
> On Mon, Jul 31, 2023 at 01:15:02AM +0000, Yoshihiro Shimoda wrote:
> > Hi Serge,
> >
> > > From: Serge Semin, Sent: Saturday, July 29, 2023 1:07 AM
> > >
> > > On Fri, Jul 28, 2023 at 04:19:38AM +0000, Yoshihiro Shimoda wrote:
> > > > Hi Manivannan,
> > > >
> > > > > From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
> > > > >
> > > > > On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > > > > > Hi Manivannan,
> > > > > >
> > > > > > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > > > > > >
> > > > > > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > > > > > handling".
> > > > > >
> > > > > > I got it.
> > > > > >
> > > > > > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > > > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > > > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > > > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > > > > > field there is another one which needs to be updated. It's
> > > > > > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > > > > > the very least the maximum link-width capability CSR won't expose
> > > > > > > > the actual maximum capability.
> > > > > > > >
> > > > > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > > Version 4.60a, March 2015, p.1032
> > > > > > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > > Version 4.70a, March 2016, p.1065
> > > > > > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > > Version 4.90a, March 2016, p.1057
> > > > > > > > ...
> > > > > > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > > > > > Version 5.40a, March 2019, p.1396
> > > > > > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > > > Version 5.40a, March 2019, p.1266
> > > > > > > >
> > > > > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > >
> > > > > > > Add Reported-by also?
> > > > > >
> > > > > > I don't think so because Serge suggested the commit description from my submitted patch [1].
> > > > > >
> > > > > > [1]
> > > > > >
> > > > <snip URL>
> > > > > >
> > > > >
> > > > > Fine then.
> > > > >
> > > > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > > > >
> > > > > > > This looks like a potential bug fix to me. So please move this change before the
> > > > > > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > > > > > CC stable list for backporting.
> > > > > >
> > > > > > I think that this patch should be a next branch because this is possible to
> > > > > > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > > > > > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > > > > > without this setting.
> > > > > >
> > > > > > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > > > > > Additionally, I could not determine which old kernel versions should have this patch
> > > > > > applied as backporting.
> > > > > >
> > > > >
> > >
> > > > > Ok. But you can still move this patch as I suggested. If we happen to hit any
> > > > > issue with this setting, then we can easily revert it.
> > > >
> > > > I got it. I'll move this patch as you suggested.
> > >
> > > No. By moving this patch to be implemented before the patch:
> > > [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> > > you won't be able to easily revert it afterwards because the patch #8
> > > will move the code added by the patch #9 to the
> > > dw_pcie_link_set_max_link_width() function. Basically you suggest to
> > > switch the preparation and functional patches order which doesn't look
> > > right.
> >
> > You're correct. If moving this patch to the top of this series and then
> > still apply the original #8, it's difficult to revert this patch.
> >
> > > Basically the Link-width-related part of this series currently implies
> > > the next logic:
> > >
> > > 1. Prepare the DW PCIe core driver to implementing a comprehensive
> > > Max-link-width setup methods (aka as it's done in
> > > dw_pcie_link_set_max_speed()) by moving the Link-width related code to
> > > a dedicated method:
> > > [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> > >
> > > 2. Add the PCI_EXP_LNKCAP_MLW field update, which
> > > dw_pcie_link_set_max_link_width() lacks to be comprehensive:
> > > [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
> > >
> > > 3. Drop the duplicating code from the Tegra194 PCIe driver:
> > > [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
> >
> > Yes.
> >
> > > In case if the patch #9 appears to be a bug fix, then it will need to
> > > be backported together with patch #8 which isn't a problem at all
> > > (though it's doubtfully to happen since nobody reported any problem
> > > with that so far).
> >
> > Basically, I don't think that backporting #8 is good as backport because
> > the #8 patch is a clean up code for readability.
> >
> > > But if patch #9 turns out to break something in
> > > current circumstances we'll be able to either easily revert it (since
> > > it's applied after the preparation patch) or fix somehow. If you
> > > switch patch #8 and #9 order, the reversion will require to be
> > > performed for both these patches to avoid the conflicts. Thus I'd
> > > suggest to leave the patches order as is which looks more natural and
> > > won't cause any problems to revert the functional change or to
> > > backport it.
> >
> > To follow Manivannan's suggestion and your comments, I'm thinking that
> > - drop the #8 because this is just clean up code for readability.
> > -- After this patch series is merged and worked correctly without any
> > regression on other platforms, we can apply the #8.
> > - move the #9 to the top of this series as Manivannan suggested.
> > -- This mean adding this code into dw_pcie_setup().
> >
> > But, what do you think?
>
> No. It's better to leave the preparation patch and the order as is.
> Once again this patch doesn't look as a bug-fix since nobody reported
> any related problem so far. If anyone decides to back it port there
> won't a problem with porting both #8 and #9. It's a common practice.
I got it. I'll keep the order #8 and #9 as-is, because the #9 is not a
bug-fix patch.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > -Serge(y)
> > >
> > > >
> > > > Best regards,
> > > > Yoshihiro Shimoda
> > > >
> > > > > - Mani
> > > > >
> > > > > > Best regards,
> > > > > > Yoshihiro Shimoda
> > > > > >
> > > > > > > - Mani
> > > > > > >
> > > > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > > > ---
> > > > > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > > > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > > index 5cca34140d2a..c4998194fe74 100644
> > > > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > > > > > >
> > > > > > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > > > {
> > > > > > > > - u32 lwsc, plc;
> > > > > > > > + u32 lnkcap, lwsc, plc;
> > > > > > > > + u8 cap;
> > > > > > > >
> > > > > > > > if (!num_lanes)
> > > > > > > > return;
> > > > > > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > > > }
> > > > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > > > > > +
> > > > > > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > > > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > > > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > > > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > > > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > > > > > }
> > > > > > > >
> > > > > > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > > > > > --
> > > > > > > > 2.25.1
> > > > > > > >
> > > > > > >
> > > > > > > --
> > > > > > > மணிவண்ணன் சதாசிவம்
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
2023-07-28 16:07 ` Serge Semin
2023-07-31 1:15 ` Yoshihiro Shimoda
@ 2023-08-02 10:46 ` Manivannan Sadhasivam
1 sibling, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-08-02 10:46 UTC (permalink / raw)
To: Serge Semin
Cc: Yoshihiro Shimoda, Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Fri, Jul 28, 2023 at 07:07:03PM +0300, Serge Semin wrote:
> On Fri, Jul 28, 2023 at 04:19:38AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Friday, July 28, 2023 11:51 AM
> > >
> > > On Wed, Jul 26, 2023 at 02:12:15AM +0000, Yoshihiro Shimoda wrote:
> > > > Hi Manivannan,
> > > >
> > > > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:04 PM
> > > > >
> > > > > Subject should contain the word "missing". Like, "Add missing PCI_EXP_LNKCAP_MLW
> > > > > handling".
> > > >
> > > > I got it.
> > > >
> > > > > On Fri, Jul 21, 2023 at 04:44:41PM +0900, Yoshihiro Shimoda wrote:
> > > > > > Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
> > > > > > In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> > > > > > the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> > > > > > field there is another one which needs to be updated. It's
> > > > > > LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> > > > > > the very least the maximum link-width capability CSR won't expose
> > > > > > the actual maximum capability.
> > > > > >
> > > > > > [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.60a, March 2015, p.1032
> > > > > > [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.70a, March 2016, p.1065
> > > > > > [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 4.90a, March 2016, p.1057
> > > > > > ...
> > > > > > [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> > > > > > Version 5.40a, March 2019, p.1396
> > > > > > [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> > > > > > Version 5.40a, March 2019, p.1266
> > > > > >
> > > > > > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > > > >
> > > > > Add Reported-by also?
> > > >
> > > > I don't think so because Serge suggested the commit description from my submitted patch [1].
> > > >
> > > > [1]
> > > >
> > <snip URL>
> > > >
> > >
> > > Fine then.
> > >
> > > > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > >
> > > > > This looks like a potential bug fix to me. So please move this change before the
> > > > > previous patch that introduces dw_pcie_link_set_max_link_width(), tag fixes and
> > > > > CC stable list for backporting.
> > > >
> > > > I think that this patch should be a next branch because this is possible to
> > > > cause side effective. Almost all drivers/pcie/controller/dwc/ host drivers except
> > > > pcie-tegra194.c doesn't have this setting, but I assume that the drivers work correctly
> > > > without this setting.
> > > >
> > > > Also, to be honest, I could not find a suitable commit ID for this patch's "Fixes" tag.
> > > > Additionally, I could not determine which old kernel versions should have this patch
> > > > applied as backporting.
> > > >
> > >
>
> > > Ok. But you can still move this patch as I suggested. If we happen to hit any
> > > issue with this setting, then we can easily revert it.
> >
> > I got it. I'll move this patch as you suggested.
>
> No. By moving this patch to be implemented before the patch:
> [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
> you won't be able to easily revert it afterwards because the patch #8
> will move the code added by the patch #9 to the
> dw_pcie_link_set_max_link_width() function. Basically you suggest to
> switch the preparation and functional patches order which doesn't look
> right.
>
> Basically the Link-width-related part of this series currently implies
> the next logic:
>
> 1. Prepare the DW PCIe core driver to implementing a comprehensive
> Max-link-width setup methods (aka as it's done in
> dw_pcie_link_set_max_speed()) by moving the Link-width related code to
> a dedicated method:
> [PATCH v18 08/20] PCI: dwc: Add dw_pcie_link_set_max_link_width()
>
> 2. Add the PCI_EXP_LNKCAP_MLW field update, which
> dw_pcie_link_set_max_link_width() lacks to be comprehensive:
> [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
>
> 3. Drop the duplicating code from the Tegra194 PCIe driver:
> [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
>
> In case if the patch #9 appears to be a bug fix, then it will need to
> be backported together with patch #8 which isn't a problem at all
> (though it's doubtfully to happen since nobody reported any problem
> with that so far). But if patch #9 turns out to break something in
> current circumstances we'll be able to either easily revert it (since
> it's applied after the preparation patch) or fix somehow. If you
> switch patch #8 and #9 order, the reversion will require to be
> performed for both these patches to avoid the conflicts. Thus I'd
> suggest to leave the patches order as is which looks more natural and
> won't cause any problems to revert the functional change or to
> backport it.
>
Hmm, I overlooked the dependency. Let's keep the order as it is.
- Mani
> -Serge(y)
>
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > - Mani
> > >
> > > > Best regards,
> > > > Yoshihiro Shimoda
> > > >
> > > > > - Mani
> > > > >
> > > > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > > > ---
> > > > > > drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> > > > > > 1 file changed, 8 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > index 5cca34140d2a..c4998194fe74 100644
> > > > > > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > > > > > @@ -730,7 +730,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
> > > > > >
> > > > > > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > {
> > > > > > - u32 lwsc, plc;
> > > > > > + u32 lnkcap, lwsc, plc;
> > > > > > + u8 cap;
> > > > > >
> > > > > > if (!num_lanes)
> > > > > > return;
> > > > > > @@ -766,6 +767,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> > > > > > }
> > > > > > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> > > > > > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> > > > > > +
> > > > > > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> > > > > > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> > > > > > + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> > > > > > + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> > > > > > + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> > > > > > }
> > > > > >
> > > > > > void dw_pcie_iatu_detect(struct dw_pcie *pci)
> > > > > > --
> > > > > > 2.25.1
> > > > > >
> > > > >
> > > > > --
> > > > > மணிவண்ணன் சதாசிவம்
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting.
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (8 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 09/20] PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 11:29 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
` (10 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Thierry Reding,
Jonathan Hunter
dw_pcie_setup() will set PCI_EXP_LNKSTA_NLW to PCI_EXP_LNKCAP register
so that drop such setting from tegra_pcie_dw_host_init().
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 85cc64324efd..3bba174b1701 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -922,12 +922,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
AMBA_ERROR_RESPONSE_CRS_SHIFT);
dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
- /* Configure Max lane width from DT */
- val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_MLW;
- val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
- dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
-
/* Clear Slot Clock Configuration bit if SRNS configuration */
if (pcie->enable_srns) {
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting.
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
@ 2023-07-24 11:29 ` Manivannan Sadhasivam
2023-07-26 2:26 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 11:29 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc,
Thierry Reding, Jonathan Hunter
Remove full stop from subject.
On Fri, Jul 21, 2023 at 04:44:42PM +0900, Yoshihiro Shimoda wrote:
> dw_pcie_setup() will set PCI_EXP_LNKSTA_NLW to PCI_EXP_LNKCAP register
> so that drop such setting from tegra_pcie_dw_host_init().
>
How about,
dw_pcie_setup() is already setting PCI_EXP_LNKCAP_MLW to pcie->num_lanes in the
PCI_EXP_LNKCAP register for programming maximum link width. Hence, remove the
redundant setting here.
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
With that,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Jonathan Hunter <jonathanh@nvidia.com>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 85cc64324efd..3bba174b1701 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -922,12 +922,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> AMBA_ERROR_RESPONSE_CRS_SHIFT);
> dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
>
> - /* Configure Max lane width from DT */
> - val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
> - val &= ~PCI_EXP_LNKCAP_MLW;
> - val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
> - dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
> -
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting.
2023-07-24 11:29 ` Manivannan Sadhasivam
@ 2023-07-26 2:26 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-26 2:26 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Thierry Reding,
Jonathan Hunter
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:29 PM
>
> Remove full stop from subject.
I will remove "." from the subject.
> On Fri, Jul 21, 2023 at 04:44:42PM +0900, Yoshihiro Shimoda wrote:
> > dw_pcie_setup() will set PCI_EXP_LNKSTA_NLW to PCI_EXP_LNKCAP register
> > so that drop such setting from tegra_pcie_dw_host_init().
> >
>
> How about,
>
> dw_pcie_setup() is already setting PCI_EXP_LNKCAP_MLW to pcie->num_lanes in the
> PCI_EXP_LNKCAP register for programming maximum link width. Hence, remove the
> redundant setting here.
Thank you for the suggestion. I'll fix the description.
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> With that,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thank you for your review!
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > Cc: Thierry Reding <thierry.reding@gmail.com>
> > Cc: Jonathan Hunter <jonathanh@nvidia.com>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
> > 1 file changed, 6 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > index 85cc64324efd..3bba174b1701 100644
> > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > @@ -922,12 +922,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> > AMBA_ERROR_RESPONSE_CRS_SHIFT);
> > dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
> >
> > - /* Configure Max lane width from DT */
> > - val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
> > - val &= ~PCI_EXP_LNKCAP_MLW;
> > - val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
> > - dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
> > -
> > /* Clear Slot Clock Configuration bit if SRNS configuration */
> > if (pcie->enable_srns) {
> > val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (9 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 10/20] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 11:35 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
` (9 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Renesas R-Car Gen4 PCIe controllers have an unexpected register value on
the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL"
which would force the unrolled eDMA mapping for the problematic device.
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++-
drivers/pci/controller/dwc/pcie-designware.h | 5 +++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index c4998194fe74..4812ce040f1e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -883,8 +883,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
* Indirect eDMA CSRs access has been completely removed since v5.40a
* thus no space is now reserved for the eDMA channels viewport and
* former DMA CTRL register is no longer fixed to FFs.
+ *
+ * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason
+ * have zeros in the eDMA CTRL register even though the HW-manual
+ * explicitly states there must FFs if the unrolled mapping is enabled.
+ * For such cases the low-level drivers are supposed to manually
+ * activate the unrolled mapping to bypass the auto-detection procedure.
*/
- if (dw_pcie_ver_is_ge(pci, 540A))
+ if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL))
val = 0xFFFFFFFF;
else
val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 94bc20f5f600..6821446d7c66 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -51,8 +51,9 @@
/* DWC PCIe controller capabilities */
#define DW_PCIE_CAP_REQ_RES 0
-#define DW_PCIE_CAP_IATU_UNROLL 1
-#define DW_PCIE_CAP_CDM_CHECK 2
+#define DW_PCIE_CAP_EDMA_UNROLL 1
+#define DW_PCIE_CAP_IATU_UNROLL 2
+#define DW_PCIE_CAP_CDM_CHECK 3
#define dw_pcie_cap_is(_pci, _cap) \
test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
@ 2023-07-24 11:35 ` Manivannan Sadhasivam
2023-07-26 2:58 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 11:35 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:43PM +0900, Yoshihiro Shimoda wrote:
> Renesas R-Car Gen4 PCIe controllers have an unexpected register value on
> the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL"
s/in the dbi+0x97b/in the eDMA CTRL
> which would force the unrolled eDMA mapping for the problematic device.
>
> Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 5 +++--
> 2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index c4998194fe74..4812ce040f1e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -883,8 +883,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> * Indirect eDMA CSRs access has been completely removed since v5.40a
> * thus no space is now reserved for the eDMA channels viewport and
> * former DMA CTRL register is no longer fixed to FFs.
> + *
> + * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason
> + * have zeros in the eDMA CTRL register even though the HW-manual
> + * explicitly states there must FFs if the unrolled mapping is enabled.
> + * For such cases the low-level drivers are supposed to manually
> + * activate the unrolled mapping to bypass the auto-detection procedure.
> */
> - if (dw_pcie_ver_is_ge(pci, 540A))
> + if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL))
> val = 0xFFFFFFFF;
> else
> val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 94bc20f5f600..6821446d7c66 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -51,8 +51,9 @@
>
> /* DWC PCIe controller capabilities */
> #define DW_PCIE_CAP_REQ_RES 0
> -#define DW_PCIE_CAP_IATU_UNROLL 1
> -#define DW_PCIE_CAP_CDM_CHECK 2
> +#define DW_PCIE_CAP_EDMA_UNROLL 1
> +#define DW_PCIE_CAP_IATU_UNROLL 2
> +#define DW_PCIE_CAP_CDM_CHECK 3
>
> #define dw_pcie_cap_is(_pci, _cap) \
> test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* RE: [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag
2023-07-24 11:35 ` Manivannan Sadhasivam
@ 2023-07-26 2:58 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-26 2:58 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:35 PM
>
> On Fri, Jul 21, 2023 at 04:44:43PM +0900, Yoshihiro Shimoda wrote:
> > Renesas R-Car Gen4 PCIe controllers have an unexpected register value on
> > the dbi+0x97b register. So, add a new capability flag "EDMA_UNROLL"
>
> s/in the dbi+0x97b/in the eDMA CTRL
I'll fix it.
> > which would force the unrolled eDMA mapping for the problematic device.
> >
> > Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thank you for your review!
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++-
> > drivers/pci/controller/dwc/pcie-designware.h | 5 +++--
> > 2 files changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index c4998194fe74..4812ce040f1e 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -883,8 +883,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
> > * Indirect eDMA CSRs access has been completely removed since v5.40a
> > * thus no space is now reserved for the eDMA channels viewport and
> > * former DMA CTRL register is no longer fixed to FFs.
> > + *
> > + * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason
> > + * have zeros in the eDMA CTRL register even though the HW-manual
> > + * explicitly states there must FFs if the unrolled mapping is enabled.
> > + * For such cases the low-level drivers are supposed to manually
> > + * activate the unrolled mapping to bypass the auto-detection procedure.
> > */
> > - if (dw_pcie_ver_is_ge(pci, 540A))
> > + if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL))
> > val = 0xFFFFFFFF;
> > else
> > val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 94bc20f5f600..6821446d7c66 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -51,8 +51,9 @@
> >
> > /* DWC PCIe controller capabilities */
> > #define DW_PCIE_CAP_REQ_RES 0
> > -#define DW_PCIE_CAP_IATU_UNROLL 1
> > -#define DW_PCIE_CAP_CDM_CHECK 2
> > +#define DW_PCIE_CAP_EDMA_UNROLL 1
> > +#define DW_PCIE_CAP_IATU_UNROLL 2
> > +#define DW_PCIE_CAP_CDM_CHECK 3
> >
> > #define dw_pcie_cap_is(_pci, _cap) \
> > test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (10 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 11/20] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 11:36 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
` (8 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Since no PCIe controller drivers call this, this change is not required
for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
and if the controller driver is built as a kernel module, the following
build error happens. So, expose dw_pcie_ep_exit() for it.
ERROR: modpost: "dw_pcie_ep_exit" [drivers/pci/controller/dwc/pcie-rcar-gen4-ep-drv.ko] undefined!
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index bd57516d5313..14c641395c3b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -695,6 +695,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc);
}
+EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
@ 2023-07-24 11:36 ` Manivannan Sadhasivam
0 siblings, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 11:36 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:44PM +0900, Yoshihiro Shimoda wrote:
> Since no PCIe controller drivers call this, this change is not required
> for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
> and if the controller driver is built as a kernel module, the following
> build error happens. So, expose dw_pcie_ep_exit() for it.
>
> ERROR: modpost: "dw_pcie_ep_exit" [drivers/pci/controller/dwc/pcie-rcar-gen4-ep-drv.ko] undefined!
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index bd57516d5313..14c641395c3b 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -695,6 +695,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
>
> pci_epc_mem_exit(epc);
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
>
> static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
> {
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (11 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 12/20] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
` (2 more replies)
2023-07-21 7:44 ` [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
` (7 subsequent siblings)
20 siblings, 3 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Renesas R-Car Gen4 PCIe controllers require vender-specific
initialization before .ep_init(). To use dw->dbi and dw->num-lanes
in the initialization code, introduce .ep_pre_init() into struct
dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
by using vender-specific de-initialization.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
drivers/pci/controller/dwc/pcie-designware.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 14c641395c3b..52b3e7f67513 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct pci_epc *epc = ep->epc;
+ if (ep->ops->ep_deinit)
+ ep->ops->ep_deinit(ep);
+
dw_pcie_edma_remove(pci);
if (ep->intx_mem)
@@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->phys_base = res->start;
ep->addr_size = resource_size(res);
+ if (ep->ops->ep_pre_init)
+ ep->ops->ep_pre_init(ep);
+
dw_pcie_version_detect(pci);
dw_pcie_iatu_detect(pci);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 6821446d7c66..c3aeafd0f4c9 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -332,7 +332,9 @@ struct dw_pcie_rp {
};
struct dw_pcie_ep_ops {
+ void (*ep_pre_init)(struct dw_pcie_ep *ep);
void (*ep_init)(struct dw_pcie_ep *ep);
+ void (*ep_deinit)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
@ 2023-07-21 9:23 ` Sergei Shtylyov
2023-07-24 11:40 ` Manivannan Sadhasivam
2023-08-01 0:22 ` Serge Semin
2 siblings, 0 replies; 90+ messages in thread
From: Sergei Shtylyov @ 2023-07-21 9:23 UTC (permalink / raw)
To: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, manivannan.sadhasivam, bhelgaas, kishon,
krzysztof.kozlowski+dt, conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc
On 7/21/23 10:44 AM, Yoshihiro Shimoda wrote:
> Renesas R-Car Gen4 PCIe controllers require vender-specific
It's "vendor". :-)
> initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> in the initialization code, introduce .ep_pre_init() into struct
> dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> by using vender-specific de-initialization.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
@ 2023-07-24 11:40 ` Manivannan Sadhasivam
2023-07-26 3:02 ` Yoshihiro Shimoda
2023-08-01 0:22 ` Serge Semin
2 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 11:40 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> Renesas R-Car Gen4 PCIe controllers require vender-specific
> initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> in the initialization code, introduce .ep_pre_init() into struct
> dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> by using vender-specific de-initialization.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 14c641395c3b..52b3e7f67513 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct pci_epc *epc = ep->epc;
>
> + if (ep->ops->ep_deinit)
> + ep->ops->ep_deinit(ep);
> +
> dw_pcie_edma_remove(pci);
>
> if (ep->intx_mem)
> @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> + if (ep->ops->ep_pre_init)
> + ep->ops->ep_pre_init(ep);
> +
> dw_pcie_version_detect(pci);
>
> dw_pcie_iatu_detect(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 6821446d7c66..c3aeafd0f4c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> };
>
> struct dw_pcie_ep_ops {
> + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> void (*ep_init)(struct dw_pcie_ep *ep);
> + void (*ep_deinit)(struct dw_pcie_ep *ep);
Since the struct name itself has "ep", there is no need to add the "ep" suffix
to callbacks. You should fix the existing ep_init callback too in a separate
patch.
(this series is just GROWING!!!)
- Mani
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> enum pci_epc_irq_type type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-24 11:40 ` Manivannan Sadhasivam
@ 2023-07-26 3:02 ` Yoshihiro Shimoda
2023-08-01 0:15 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-26 3:02 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, fancer.lancer@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Manivannan,
> From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:40 PM
>
> On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> > Renesas R-Car Gen4 PCIe controllers require vender-specific
> > initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> > in the initialization code, introduce .ep_pre_init() into struct
> > dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> > by using vender-specific de-initialization.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> > drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 14c641395c3b..52b3e7f67513 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct pci_epc *epc = ep->epc;
> >
> > + if (ep->ops->ep_deinit)
> > + ep->ops->ep_deinit(ep);
> > +
> > dw_pcie_edma_remove(pci);
> >
> > if (ep->intx_mem)
> > @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > ep->phys_base = res->start;
> > ep->addr_size = resource_size(res);
> >
> > + if (ep->ops->ep_pre_init)
> > + ep->ops->ep_pre_init(ep);
> > +
> > dw_pcie_version_detect(pci);
> >
> > dw_pcie_iatu_detect(pci);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 6821446d7c66..c3aeafd0f4c9 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> > };
> >
> > struct dw_pcie_ep_ops {
> > + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> > void (*ep_init)(struct dw_pcie_ep *ep);
> > + void (*ep_deinit)(struct dw_pcie_ep *ep);
>
> Since the struct name itself has "ep", there is no need to add the "ep" suffix
> to callbacks. You should fix the existing ep_init callback too in a separate
> patch.
I got it. I'll make such a separate patch before this patch.
Best regards,
Yoshihiro Shimoda
> (this series is just GROWING!!!)
>
> - Mani
>
> > int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> > enum pci_epc_irq_type type, u16 interrupt_num);
> > const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-26 3:02 ` Yoshihiro Shimoda
@ 2023-08-01 0:15 ` Serge Semin
2023-08-02 10:40 ` Manivannan Sadhasivam
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-01 0:15 UTC (permalink / raw)
To: Yoshihiro Shimoda, Manivannan Sadhasivam, Manivannan Sadhasivam
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Wed, Jul 26, 2023 at 03:02:13AM +0000, Yoshihiro Shimoda wrote:
> Hi Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:40 PM
> >
> > On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> > > Renesas R-Car Gen4 PCIe controllers require vender-specific
> > > initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> > > in the initialization code, introduce .ep_pre_init() into struct
> > > dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> > > by using vender-specific de-initialization.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > ---
> > > drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> > > drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> > > 2 files changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > index 14c641395c3b..52b3e7f67513 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > struct pci_epc *epc = ep->epc;
> > >
> > > + if (ep->ops->ep_deinit)
> > > + ep->ops->ep_deinit(ep);
> > > +
> > > dw_pcie_edma_remove(pci);
> > >
> > > if (ep->intx_mem)
> > > @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > > ep->phys_base = res->start;
> > > ep->addr_size = resource_size(res);
> > >
> > > + if (ep->ops->ep_pre_init)
> > > + ep->ops->ep_pre_init(ep);
> > > +
> > > dw_pcie_version_detect(pci);
> > >
> > > dw_pcie_iatu_detect(pci);
> > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > index 6821446d7c66..c3aeafd0f4c9 100644
> > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> > > };
> > >
> > > struct dw_pcie_ep_ops {
> > > + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> > > void (*ep_init)(struct dw_pcie_ep *ep);
> > > + void (*ep_deinit)(struct dw_pcie_ep *ep);
> >
> > Since the struct name itself has "ep", there is no need to add the "ep" suffix
> > to callbacks. You should fix the existing ep_init callback too in a separate
> > patch.
>
> I got it. I'll make such a separate patch before this patch.
>
> Best regards,
> Yoshihiro Shimoda
>
> > (this series is just GROWING!!!)
The series indeed gets to be too bulky. What about moving that cleanup
patch to a separate patchset which Yoshihiro promised to create
afterwards? Mani?
Anyway should you provide the init()/deinit() callbacks prefix
dropping patch it should fix the dw_pcie_host_ops fields too. It also
has a redundant prefix/suffix. Though it's up to Mani to decide
whether it should be really done.
-Serge(y)
> >
> > - Mani
> >
> > > int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> > > enum pci_epc_irq_type type, u16 interrupt_num);
> > > const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-08-01 0:15 ` Serge Semin
@ 2023-08-02 10:40 ` Manivannan Sadhasivam
0 siblings, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-08-02 10:40 UTC (permalink / raw)
To: Serge Semin
Cc: Yoshihiro Shimoda, Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Tue, Aug 01, 2023 at 03:15:41AM +0300, Serge Semin wrote:
> On Wed, Jul 26, 2023 at 03:02:13AM +0000, Yoshihiro Shimoda wrote:
> > Hi Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Monday, July 24, 2023 8:40 PM
> > >
> > > On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> > > > Renesas R-Car Gen4 PCIe controllers require vender-specific
> > > > initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> > > > in the initialization code, introduce .ep_pre_init() into struct
> > > > dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> > > > by using vender-specific de-initialization.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > ---
> > > > drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> > > > drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> > > > 2 files changed, 8 insertions(+)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > index 14c641395c3b..52b3e7f67513 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > > > @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> > > > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > struct pci_epc *epc = ep->epc;
> > > >
> > > > + if (ep->ops->ep_deinit)
> > > > + ep->ops->ep_deinit(ep);
> > > > +
> > > > dw_pcie_edma_remove(pci);
> > > >
> > > > if (ep->intx_mem)
> > > > @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > > > ep->phys_base = res->start;
> > > > ep->addr_size = resource_size(res);
> > > >
> > > > + if (ep->ops->ep_pre_init)
> > > > + ep->ops->ep_pre_init(ep);
> > > > +
> > > > dw_pcie_version_detect(pci);
> > > >
> > > > dw_pcie_iatu_detect(pci);
> > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > > > index 6821446d7c66..c3aeafd0f4c9 100644
> > > > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > > > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > > > @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> > > > };
> > > >
> > > > struct dw_pcie_ep_ops {
> > > > + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> > > > void (*ep_init)(struct dw_pcie_ep *ep);
> > > > + void (*ep_deinit)(struct dw_pcie_ep *ep);
> > >
> > > Since the struct name itself has "ep", there is no need to add the "ep" suffix
> > > to callbacks. You should fix the existing ep_init callback too in a separate
> > > patch.
> >
>
> > I got it. I'll make such a separate patch before this patch.
> >
> > Best regards,
> > Yoshihiro Shimoda
> >
> > > (this series is just GROWING!!!)
>
> The series indeed gets to be too bulky. What about moving that cleanup
> patch to a separate patchset which Yoshihiro promised to create
> afterwards? Mani?
>
> Anyway should you provide the init()/deinit() callbacks prefix
> dropping patch it should fix the dw_pcie_host_ops fields too. It also
> has a redundant prefix/suffix. Though it's up to Mani to decide
> whether it should be really done.
>
I'm fine with a separate cleanup series/patch later.
- Mani
> -Serge(y)
>
> > >
> > > - Mani
> > >
> > > > int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> > > > enum pci_epc_irq_type type, u16 interrupt_num);
> > > > const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
2023-07-21 9:23 ` Sergei Shtylyov
2023-07-24 11:40 ` Manivannan Sadhasivam
@ 2023-08-01 0:22 ` Serge Semin
2023-08-01 6:27 ` Yoshihiro Shimoda
2 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-01 0:22 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> Renesas R-Car Gen4 PCIe controllers require vender-specific
> initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> in the initialization code, introduce .ep_pre_init() into struct
> dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> by using vender-specific de-initialization.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 14c641395c3b..52b3e7f67513 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> struct pci_epc *epc = ep->epc;
>
> + if (ep->ops->ep_deinit)
> + ep->ops->ep_deinit(ep);
> +
This doesn't seem like a correct place to call the de-initialization
callback. I also don't see you adding the de-initialization to the
cleanup-on-error path of the dw_pcie_ep_init() method. You need to add
it there it. Afterwards you'll see a correct place for it in the
dw_pcie_ep_exit() function.
-Serge(y)
> dw_pcie_edma_remove(pci);
>
> if (ep->intx_mem)
> @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> + if (ep->ops->ep_pre_init)
> + ep->ops->ep_pre_init(ep);
> +
> dw_pcie_version_detect(pci);
>
> dw_pcie_iatu_detect(pci);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 6821446d7c66..c3aeafd0f4c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> };
>
> struct dw_pcie_ep_ops {
> + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> void (*ep_init)(struct dw_pcie_ep *ep);
> + void (*ep_deinit)(struct dw_pcie_ep *ep);
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> enum pci_epc_irq_type type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
2023-08-01 0:22 ` Serge Semin
@ 2023-08-01 6:27 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 6:27 UTC (permalink / raw)
To: Serge Semin
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 9:22 AM
>
> On Fri, Jul 21, 2023 at 04:44:45PM +0900, Yoshihiro Shimoda wrote:
> > Renesas R-Car Gen4 PCIe controllers require vender-specific
> > initialization before .ep_init(). To use dw->dbi and dw->num-lanes
> > in the initialization code, introduce .ep_pre_init() into struct
> > dw_pcie_ep_ops. Also introduce .ep_deinit() to disable the controller
> > by using vender-specific de-initialization.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++
> > drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> > 2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index 14c641395c3b..52b3e7f67513 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -684,6 +684,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > struct pci_epc *epc = ep->epc;
> >
>
> > + if (ep->ops->ep_deinit)
> > + ep->ops->ep_deinit(ep);
> > +
>
> This doesn't seem like a correct place to call the de-initialization
> callback. I also don't see you adding the de-initialization to the
> cleanup-on-error path of the dw_pcie_ep_init() method. You need to add
> it there it. Afterwards you'll see a correct place for it in the
> dw_pcie_ep_exit() function.
I understood it. I'll fix these functions on v19.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> > dw_pcie_edma_remove(pci);
> >
> > if (ep->intx_mem)
> > @@ -797,6 +800,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> > ep->phys_base = res->start;
> > ep->addr_size = resource_size(res);
> >
> > + if (ep->ops->ep_pre_init)
> > + ep->ops->ep_pre_init(ep);
> > +
> > dw_pcie_version_detect(pci);
> >
> > dw_pcie_iatu_detect(pci);
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 6821446d7c66..c3aeafd0f4c9 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -332,7 +332,9 @@ struct dw_pcie_rp {
> > };
> >
> > struct dw_pcie_ep_ops {
> > + void (*ep_pre_init)(struct dw_pcie_ep *ep);
> > void (*ep_init)(struct dw_pcie_ep *ep);
> > + void (*ep_deinit)(struct dw_pcie_ep *ep);
> > int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> > enum pci_epc_irq_type type, u16 interrupt_num);
> > const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (12 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 13/20] PCI: dwc: Introduce .ep_pre_init() and .ep_deinit() Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
` (6 subsequent siblings)
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Rob Herring,
Manivannan Sadhasivam
Update maxItems of reg and reg-names on both host and endpoint
for supporting Renesas R-Car Gen4 PCIe controllers later.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++--
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index 8fc2151691a4..cb727f60be0b 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -33,11 +33,11 @@ properties:
normal controller functioning. iATU memory IO region is also required
if the space is unrolled (IP-core version >= 4.80a).
minItems: 2
- maxItems: 5
+ maxItems: 6
reg-names:
minItems: 2
- maxItems: 5
+ maxItems: 6
items:
oneOf:
- description:
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index 1a83f0f65f19..0bfcfd6ccb5f 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -33,11 +33,11 @@ properties:
are required for the normal controller work. iATU memory IO region is
also required if the space is unrolled (IP-core version >= 4.80a).
minItems: 2
- maxItems: 5
+ maxItems: 6
reg-names:
minItems: 2
- maxItems: 5
+ maxItems: 6
items:
oneOf:
- description:
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (13 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 14/20] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
` (5 subsequent siblings)
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Rob Herring
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe host module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
.../bindings/pci/rcar-gen4-pci-host.yaml | 123 ++++++++++++++++++
1 file changed, 123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
new file mode 100644
index 000000000000..513a3416dd8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Host
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie # R-Car Gen4
+
+ reg:
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: dma
+ - const: app
+ - const: config
+
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: dma
+ - const: sft_ce
+ - const: app
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: ref
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ resets-names:
+ items:
+ - const: pwr
+
+ max-link-speed:
+ maximum: 4
+
+ num-lanes:
+ maximum: 4
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>, <&clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <4>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (14 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 15/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
` (4 subsequent siblings)
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Rob Herring,
Manivannan Sadhasivam
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe endpoint module.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
.../bindings/pci/rcar-gen4-pci-ep.yaml | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
new file mode 100644
index 000000000000..4e6be856104c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Endpoint
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
+
+ reg:
+ maxItems: 6
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: dma
+ - const: app
+ - const: addr_space
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: dma
+ - const: sft_ce
+ - const: app
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: ref
+
+ max-functions:
+ maximum: 2
+
+ max-link-speed:
+ maximum: 4
+
+ num-lanes:
+ maximum: 4
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - resets
+ - power-domains
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
+ interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ max-link-speed = <4>;
+ max-functions = /bits/ 8 <2>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (15 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 16/20] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 12:28 ` Manivannan Sadhasivam
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
` (3 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Add R-Car Gen4 PCIe Host support. This controller is based on
Synopsys DesignWare PCIe, but this controller has vendor-specific
registers so that requires initialization code like mode setting
and retraining and so on.
To reduce code delta, adds some helper functions which are used by
both the host driver and the endpoint driver (which is added
immediately afterwards) into a separate file.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile | 2 +
.../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
5 files changed, 404 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ab96da43e0c2..64d4d37bc891 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST
Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
This driver supports TMPV7708 SoC.
+config PCIE_RCAR_GEN4
+ tristate "Renesas R-Car Gen4 PCIe Host controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_MSI
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
+ This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index bf5c311875a1..486cf706b53d 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
+pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
+obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
new file mode 100644
index 000000000000..3168f5d98a79
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022-2023 Renesas Electronics Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+ u32 val;
+
+ gpiod_set_value_cansleep(dw->pe_rst, 1);
+
+ ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ if (ret) {
+ dev_err(dw->dev, "Failed to enable ref clocks\n");
+ return ret;
+ }
+
+ ret = rcar_gen4_pcie_basic_init(rcar);
+ if (ret < 0) {
+ clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ return ret;
+ }
+
+ /*
+ * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
+ * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
+ * assignment during device enumeration.
+ */
+ dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
+ dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ /* Enable MSI interrupt signal */
+ val = readl(rcar->base + PCIEINTSTS0EN);
+ val |= MSI_CTRL_INT;
+ writel(val, rcar->base + PCIEINTSTS0EN);
+ }
+
+ msleep(100); /* pe_rst requires 100msec delay */
+
+ gpiod_set_value_cansleep(dw->pe_rst, 0);
+
+ return 0;
+}
+
+static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ gpiod_set_value_cansleep(dw->pe_rst, 1);
+ rcar_gen4_pcie_basic_deinit(rcar);
+ clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+}
+
+static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
+ .host_init = rcar_gen4_pcie_host_init,
+ .host_deinit = rcar_gen4_pcie_host_deinit,
+};
+
+static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie_rp *pp = &rcar->dw.pp;
+
+ pp->num_vectors = MAX_MSI_IRQS;
+ pp->ops = &rcar_gen4_pcie_host_ops;
+ rcar->mode = DW_PCIE_RC_TYPE;
+
+ return dw_pcie_host_init(pp);
+}
+
+static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_host_deinit(&rcar->dw.pp);
+ gpiod_set_value_cansleep(rcar->dw.pe_rst, 1);
+}
+
+static int rcar_gen4_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+ int err;
+
+ rcar = rcar_gen4_pcie_devm_alloc(pdev);
+ if (!rcar)
+ return -ENOMEM;
+
+ err = rcar_gen4_pcie_get_resources(rcar);
+ if (err < 0) {
+ dev_err(dev, "Failed to request resource: %d\n", err);
+ return err;
+ }
+
+ err = rcar_gen4_pcie_prepare(rcar);
+ if (err < 0)
+ return err;
+
+ err = rcar_gen4_add_dw_pcie_rp(rcar);
+ if (err < 0)
+ goto err_add;
+
+ return 0;
+
+err_add:
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return err;
+}
+
+static void rcar_gen4_pcie_remove(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
+
+ rcar_gen4_remove_dw_pcie_rp(rcar);
+ rcar_gen4_pcie_unprepare(rcar);
+}
+
+static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ { .compatible = "renesas,rcar-gen4-pcie", },
+ {},
+};
+
+static struct platform_driver rcar_gen4_pcie_driver = {
+ .driver = {
+ .name = "pcie-rcar-gen4",
+ .of_match_table = rcar_gen4_pcie_of_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = rcar_gen4_pcie_probe,
+ .remove_new = rcar_gen4_pcie_remove,
+};
+module_platform_driver(rcar_gen4_pcie_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
new file mode 100644
index 000000000000..a5fb9aae0a6f
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022-2023 Renesas Electronics Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+/* Renesas-specific */
+#define PCIERSTCTRL1 0x0014
+#define APP_HOLD_PHY_RST BIT(16)
+#define APP_LTSSM_ENABLE BIT(0)
+
+#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
+#define RCAR_MAX_LINK_SPEED 4
+
+static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
+ bool enable)
+{
+ u32 val;
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ if (enable) {
+ val |= APP_LTSSM_ENABLE;
+ val &= ~APP_HOLD_PHY_RST;
+ } else {
+ /*
+ * Since the datasheet of R-Car doesn't mention how to assert
+ * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
+ * hang-up issue happened in the dw_edma_core_off() when
+ * the controller didn't detect a PCI device.
+ */
+ val &= ~APP_LTSSM_ENABLE;
+ }
+ writel(val, rcar->base + PCIERSTCTRL1);
+}
+
+static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ u32 val, mask;
+
+ val = readl(rcar->base + PCIEINTSTS0);
+ mask = RDLH_LINK_UP | SMLH_LINK_UP;
+
+ return (val & mask) == mask;
+}
+
+static bool rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
+{
+ u32 val;
+ int i;
+
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+ for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ if (!(val & PORT_LOGIC_SPEED_CHANGE))
+ return true;
+ usleep_range(10000, 11000);
+ }
+
+ return false;
+}
+
+static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int i, changes;
+
+ rcar_gen4_pcie_ltssm_enable(rcar, true);
+
+ /*
+ * Require direct speed change with retrying here if the link_gen is
+ * PCIe Gen2 or higher.
+ */
+ changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
+
+ /*
+ * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
+ * So, this needs remaining times for up to PCIe Gen4 if RC mode.
+ */
+ if (changes && rcar->mode == DW_PCIE_RC_TYPE)
+ changes--;
+
+ for (i = 0; i < changes; i++) {
+ if (!rcar_gen4_pcie_speed_change(dw))
+ break; /* No error because possible disconnected here if EP mode */
+ }
+
+ return 0;
+}
+
+static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ rcar_gen4_pcie_ltssm_enable(rcar, false);
+}
+
+int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+
+ if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
+ reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+
+ val = readl(rcar->base + PCIEMSR0);
+ if (rcar->mode == DW_PCIE_RC_TYPE)
+ val |= DEVICE_TYPE_RC;
+ else if (rcar->mode == DW_PCIE_EP_TYPE)
+ val |= DEVICE_TYPE_EP;
+ else
+ return -EINVAL;
+
+ if (dw->num_lanes < 4)
+ val |= BIFUR_MOD_SET_ON;
+
+ writel(val, rcar->base + PCIEMSR0);
+
+ return reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+}
+
+void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+
+ reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+}
+
+int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+ int err;
+
+ pm_runtime_enable(dev);
+ err = pm_runtime_resume_and_get(dev);
+ if (err < 0) {
+ dev_err(dev, "Failed to resume/get Runtime PM\n");
+ pm_runtime_disable(dev);
+ }
+
+ return err;
+}
+
+void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+
+ pm_runtime_put(dev);
+ pm_runtime_disable(dev);
+}
+
+int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
+{
+ /* Renesas-specific registers */
+ rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
+
+ return IS_ERR(rcar->base) ? PTR_ERR(rcar->base) : 0;
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = rcar_gen4_pcie_start_link,
+ .stop_link = rcar_gen4_pcie_stop_link,
+ .link_up = rcar_gen4_pcie_link_up,
+};
+
+struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+
+ rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
+ if (!rcar)
+ return NULL;
+
+ rcar->dw.dev = dev;
+ rcar->dw.ops = &dw_pcie_ops;
+ dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
+ dw_pcie_cap_set(&rcar->dw, REQ_RES);
+ rcar->pdev = pdev;
+ platform_set_drvdata(pdev, rcar);
+
+ return rcar;
+}
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
new file mode 100644
index 000000000000..781165422739
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022-2023 Renesas Electronics Corporation
+ */
+
+#ifndef _PCIE_RCAR_GEN4_H_
+#define _PCIE_RCAR_GEN4_H_
+
+#include <linux/io.h>
+#include <linux/pci.h>
+
+#include "pcie-designware.h"
+
+/* Renesas-specific */
+#define PCIEMSR0 0x0000
+#define BIFUR_MOD_SET_ON BIT(0)
+#define DEVICE_TYPE_EP 0
+#define DEVICE_TYPE_RC BIT(4)
+
+#define PCIEINTSTS0 0x0084
+#define PCIEINTSTS0EN 0x0310
+#define MSI_CTRL_INT BIT(26)
+#define SMLH_LINK_UP BIT(7)
+#define RDLH_LINK_UP BIT(6)
+#define PCIEDMAINTSTSEN 0x0314
+#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
+
+struct rcar_gen4_pcie {
+ struct dw_pcie dw;
+ void __iomem *base;
+ struct platform_device *pdev;
+ enum dw_pcie_device_mode mode;
+};
+#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
+
+int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar);
+void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar);
+int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar);
+void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar);
+int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar);
+struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev);
+
+#endif /* _PCIE_RCAR_GEN4_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
@ 2023-07-24 12:28 ` Manivannan Sadhasivam
2023-08-01 1:06 ` Serge Semin
0 siblings, 1 reply; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-07-24 12:28 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw, bhelgaas,
kishon, krzysztof.kozlowski+dt, conor+dt, marek.vasut+renesas,
fancer.lancer, linux-pci, devicetree, linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:49PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe Host support. This controller is based on
> Synopsys DesignWare PCIe, but this controller has vendor-specific
> registers so that requires initialization code like mode setting
> and retraining and so on.
>
> To reduce code delta, adds some helper functions which are used by
> both the host driver and the endpoint driver (which is added
> immediately afterwards) into a separate file.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 9 +
> drivers/pci/controller/dwc/Makefile | 2 +
> .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> 5 files changed, 404 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index ab96da43e0c2..64d4d37bc891 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST
> Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> This driver supports TMPV7708 SoC.
>
> +config PCIE_RCAR_GEN4
> + tristate "Renesas R-Car Gen4 PCIe Host controller"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + depends on PCI_MSI
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
Add a line about module option and specify the module name. Like,
To compile this driver as a module, choose M here: the module will be called
pcie-rcar-gen4-host-drv.ko.
I have a suggestion for module name change below...
> + This uses the DesignWare core.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index bf5c311875a1..486cf706b53d 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
It'd be better to call the module as pcie-rcar-gen4-host and the file as
pcie-rcar-gen4-host-drv.c
Also, move the goal definition first.
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> new file mode 100644
> index 000000000000..3168f5d98a79
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +
> +#include "pcie-rcar-gen4.h"
> +#include "pcie-designware.h"
> +
> +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int ret;
> + u32 val;
> +
> + gpiod_set_value_cansleep(dw->pe_rst, 1);
> +
> + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> + if (ret) {
> + dev_err(dw->dev, "Failed to enable ref clocks\n");
> + return ret;
> + }
> +
> + ret = rcar_gen4_pcie_basic_init(rcar);
> + if (ret < 0) {
Use "if (ret)" for consistency.
> + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> + return ret;
> + }
> +
> + /*
> + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> + * assignment during device enumeration.
> + */
> + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> +
> + if (IS_ENABLED(CONFIG_PCI_MSI)) {
Driver depends on PCI_MSI, so there is no need of this check.
> + /* Enable MSI interrupt signal */
> + val = readl(rcar->base + PCIEINTSTS0EN);
> + val |= MSI_CTRL_INT;
> + writel(val, rcar->base + PCIEINTSTS0EN);
> + }
> +
> + msleep(100); /* pe_rst requires 100msec delay */
> +
> + gpiod_set_value_cansleep(dw->pe_rst, 0);
> +
> + return 0;
> +}
> +
> +static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> +
> + gpiod_set_value_cansleep(dw->pe_rst, 1);
> + rcar_gen4_pcie_basic_deinit(rcar);
> + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> +}
> +
> +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
> + .host_init = rcar_gen4_pcie_host_init,
> + .host_deinit = rcar_gen4_pcie_host_deinit,
> +};
> +
> +static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> +{
> + struct dw_pcie_rp *pp = &rcar->dw.pp;
> +
> + pp->num_vectors = MAX_MSI_IRQS;
> + pp->ops = &rcar_gen4_pcie_host_ops;
> + rcar->mode = DW_PCIE_RC_TYPE;
> +
> + return dw_pcie_host_init(pp);
> +}
> +
> +static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> +{
> + dw_pcie_host_deinit(&rcar->dw.pp);
> + gpiod_set_value_cansleep(rcar->dw.pe_rst, 1);
> +}
> +
> +static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rcar_gen4_pcie *rcar;
> + int err;
> +
> + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> + if (!rcar)
> + return -ENOMEM;
> +
> + err = rcar_gen4_pcie_get_resources(rcar);
> + if (err < 0) {
> + dev_err(dev, "Failed to request resource: %d\n", err);
Use dev_err_probe().
> + return err;
> + }
> +
> + err = rcar_gen4_pcie_prepare(rcar);
> + if (err < 0)
> + return err;
> +
> + err = rcar_gen4_add_dw_pcie_rp(rcar);
> + if (err < 0)
> + goto err_add;
> +
> + return 0;
> +
> +err_add:
err_prepare
> + rcar_gen4_pcie_unprepare(rcar);
> +
> + return err;
> +}
> +
> +static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> +{
> + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> +
> + rcar_gen4_remove_dw_pcie_rp(rcar);
> + rcar_gen4_pcie_unprepare(rcar);
> +}
> +
> +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> + { .compatible = "renesas,rcar-gen4-pcie", },
> + {},
> +};
Missing MODULE_DEVICE_TABLE since this driver can be built as a module.
> +
> +static struct platform_driver rcar_gen4_pcie_driver = {
> + .driver = {
> + .name = "pcie-rcar-gen4",
> + .of_match_table = rcar_gen4_pcie_of_match,
> + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> + },
> + .probe = rcar_gen4_pcie_probe,
> + .remove_new = rcar_gen4_pcie_remove,
> +};
> +module_platform_driver(rcar_gen4_pcie_driver);
> +
> +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> new file mode 100644
> index 000000000000..a5fb9aae0a6f
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -0,0 +1,200 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +
> +#include "pcie-rcar-gen4.h"
> +#include "pcie-designware.h"
> +
> +/* Renesas-specific */
> +#define PCIERSTCTRL1 0x0014
> +#define APP_HOLD_PHY_RST BIT(16)
Spacing is not consistent.
> +#define APP_LTSSM_ENABLE BIT(0)
> +
> +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> +#define RCAR_MAX_LINK_SPEED 4
> +
> +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> + bool enable)
> +{
> + u32 val;
> +
> + val = readl(rcar->base + PCIERSTCTRL1);
> + if (enable) {
> + val |= APP_LTSSM_ENABLE;
> + val &= ~APP_HOLD_PHY_RST;
> + } else {
> + /*
> + * Since the datasheet of R-Car doesn't mention how to assert
> + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> + * hang-up issue happened in the dw_edma_core_off() when
> + * the controller didn't detect a PCI device.
> + */
> + val &= ~APP_LTSSM_ENABLE;
> + }
> + writel(val, rcar->base + PCIERSTCTRL1);
> +}
> +
> +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + u32 val, mask;
> +
> + val = readl(rcar->base + PCIEINTSTS0);
> + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> +
> + return (val & mask) == mask;
> +}
> +
> +static bool rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
It'd be good to add a comment for this function.
> +{
> + u32 val;
> + int i;
> +
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val &= ~PORT_LOGIC_SPEED_CHANGE;
> + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val |= PORT_LOGIC_SPEED_CHANGE;
> + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +
> + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> + return true;
> + usleep_range(10000, 11000);
> + }
> +
> + return false;
> +}
> +
> +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
For this one too.
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int i, changes;
> +
> + rcar_gen4_pcie_ltssm_enable(rcar, true);
> +
> + /*
> + * Require direct speed change with retrying here if the link_gen is
> + * PCIe Gen2 or higher.
> + */
> + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> +
> + /*
> + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> + */
> + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> + changes--;
> +
> + for (i = 0; i < changes; i++) {
> + if (!rcar_gen4_pcie_speed_change(dw))
> + break; /* No error because possible disconnected here if EP mode */
> + }
> +
> + return 0;
> +}
> +
> +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> +
> + rcar_gen4_pcie_ltssm_enable(rcar, false);
> +}
> +
> +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar)
s/basic/common
- Mani
> +{
> + struct dw_pcie *dw = &rcar->dw;
> + u32 val;
> +
> + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> +
> + val = readl(rcar->base + PCIEMSR0);
> + if (rcar->mode == DW_PCIE_RC_TYPE)
> + val |= DEVICE_TYPE_RC;
> + else if (rcar->mode == DW_PCIE_EP_TYPE)
> + val |= DEVICE_TYPE_EP;
> + else
> + return -EINVAL;
> +
> + if (dw->num_lanes < 4)
> + val |= BIFUR_MOD_SET_ON;
> +
> + writel(val, rcar->base + PCIEMSR0);
> +
> + return reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> +}
> +
> +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar)
> +{
> + struct dw_pcie *dw = &rcar->dw;
> +
> + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> +}
> +
> +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> +{
> + struct device *dev = rcar->dw.dev;
> + int err;
> +
> + pm_runtime_enable(dev);
> + err = pm_runtime_resume_and_get(dev);
> + if (err < 0) {
> + dev_err(dev, "Failed to resume/get Runtime PM\n");
> + pm_runtime_disable(dev);
> + }
> +
> + return err;
> +}
> +
> +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> +{
> + struct device *dev = rcar->dw.dev;
> +
> + pm_runtime_put(dev);
> + pm_runtime_disable(dev);
> +}
> +
> +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> +{
> + /* Renesas-specific registers */
> + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> +
> + return IS_ERR(rcar->base) ? PTR_ERR(rcar->base) : 0;
> +}
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> + .start_link = rcar_gen4_pcie_start_link,
> + .stop_link = rcar_gen4_pcie_stop_link,
> + .link_up = rcar_gen4_pcie_link_up,
> +};
> +
> +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rcar_gen4_pcie *rcar;
> +
> + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> + if (!rcar)
> + return NULL;
> +
> + rcar->dw.dev = dev;
> + rcar->dw.ops = &dw_pcie_ops;
> + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> + rcar->pdev = pdev;
> + platform_set_drvdata(pdev, rcar);
> +
> + return rcar;
> +}
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> new file mode 100644
> index 000000000000..781165422739
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> + */
> +
> +#ifndef _PCIE_RCAR_GEN4_H_
> +#define _PCIE_RCAR_GEN4_H_
> +
> +#include <linux/io.h>
> +#include <linux/pci.h>
> +
> +#include "pcie-designware.h"
> +
> +/* Renesas-specific */
> +#define PCIEMSR0 0x0000
> +#define BIFUR_MOD_SET_ON BIT(0)
> +#define DEVICE_TYPE_EP 0
> +#define DEVICE_TYPE_RC BIT(4)
> +
> +#define PCIEINTSTS0 0x0084
> +#define PCIEINTSTS0EN 0x0310
> +#define MSI_CTRL_INT BIT(26)
> +#define SMLH_LINK_UP BIT(7)
> +#define RDLH_LINK_UP BIT(6)
> +#define PCIEDMAINTSTSEN 0x0314
> +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> +
> +struct rcar_gen4_pcie {
> + struct dw_pcie dw;
> + void __iomem *base;
> + struct platform_device *pdev;
> + enum dw_pcie_device_mode mode;
> +};
> +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> +
> +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar);
> +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar);
> +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar);
> +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar);
> +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar);
> +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev);
> +
> +#endif /* _PCIE_RCAR_GEN4_H_ */
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-07-24 12:28 ` Manivannan Sadhasivam
@ 2023-08-01 1:06 ` Serge Semin
2023-08-01 6:46 ` Yoshihiro Shimoda
2023-08-02 10:36 ` Manivannan Sadhasivam
0 siblings, 2 replies; 90+ messages in thread
From: Serge Semin @ 2023-08-01 1:06 UTC (permalink / raw)
To: Yoshihiro Shimoda, Manivannan Sadhasivam
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc
On Mon, Jul 24, 2023 at 05:58:20PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Jul 21, 2023 at 04:44:49PM +0900, Yoshihiro Shimoda wrote:
> > Add R-Car Gen4 PCIe Host support. This controller is based on
> > Synopsys DesignWare PCIe, but this controller has vendor-specific
> > registers so that requires initialization code like mode setting
> > and retraining and so on.
> >
> > To reduce code delta, adds some helper functions which are used by
> > both the host driver and the endpoint driver (which is added
> > immediately afterwards) into a separate file.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > drivers/pci/controller/dwc/Kconfig | 9 +
> > drivers/pci/controller/dwc/Makefile | 2 +
> > .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> > drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> > 5 files changed, 404 insertions(+)
> > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
> >
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index ab96da43e0c2..64d4d37bc891 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST
> > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > This driver supports TMPV7708 SoC.
> >
> > +config PCIE_RCAR_GEN4
> > + tristate "Renesas R-Car Gen4 PCIe Host controller"
> > + depends on ARCH_RENESAS || COMPILE_TEST
> > + depends on PCI_MSI
> > + select PCIE_DW_HOST
> > + help
> > + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
>
> Add a line about module option and specify the module name. Like,
>
> To compile this driver as a module, choose M here: the module will be called
> pcie-rcar-gen4-host-drv.ko.
>
> I have a suggestion for module name change below...
>
> > + This uses the DesignWare core.
> > +
> > endmenu
> > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > index bf5c311875a1..486cf706b53d 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
>
> It'd be better to call the module as pcie-rcar-gen4-host and the file as
> pcie-rcar-gen4-host-drv.c
>
> Also, move the goal definition first.
>
> >
> > # The following drivers are for devices that use the generic ACPI
> > # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > new file mode 100644
> > index 000000000000..3168f5d98a79
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > @@ -0,0 +1,149 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
> > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "pcie-rcar-gen4.h"
> > +#include "pcie-designware.h"
> > +
> > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + int ret;
> > + u32 val;
> > +
> > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > +
> > + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > + if (ret) {
> > + dev_err(dw->dev, "Failed to enable ref clocks\n");
> > + return ret;
> > + }
> > +
> > + ret = rcar_gen4_pcie_basic_init(rcar);
> > + if (ret < 0) {
>
> Use "if (ret)" for consistency.
>
> > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > + return ret;
> > + }
> > +
> > + /*
> > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > + * assignment during device enumeration.
> > + */
> > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> > +
> > + if (IS_ENABLED(CONFIG_PCI_MSI)) {
>
> Driver depends on PCI_MSI, so there is no need of this check.
>
> > + /* Enable MSI interrupt signal */
> > + val = readl(rcar->base + PCIEINTSTS0EN);
> > + val |= MSI_CTRL_INT;
> > + writel(val, rcar->base + PCIEINTSTS0EN);
> > + }
> > +
> > + msleep(100); /* pe_rst requires 100msec delay */
> > +
> > + gpiod_set_value_cansleep(dw->pe_rst, 0);
> > +
> > + return 0;
> > +}
> > +
> > +static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > +
> > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > + rcar_gen4_pcie_basic_deinit(rcar);
> > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > +}
> > +
> > +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
> > + .host_init = rcar_gen4_pcie_host_init,
> > + .host_deinit = rcar_gen4_pcie_host_deinit,
> > +};
> > +
> > +static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct dw_pcie_rp *pp = &rcar->dw.pp;
> > +
> > + pp->num_vectors = MAX_MSI_IRQS;
> > + pp->ops = &rcar_gen4_pcie_host_ops;
> > + rcar->mode = DW_PCIE_RC_TYPE;
> > +
> > + return dw_pcie_host_init(pp);
> > +}
> > +
> > +static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > +{
> > + dw_pcie_host_deinit(&rcar->dw.pp);
> > + gpiod_set_value_cansleep(rcar->dw.pe_rst, 1);
> > +}
> > +
> > +static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct rcar_gen4_pcie *rcar;
> > + int err;
> > +
> > + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> > + if (!rcar)
> > + return -ENOMEM;
> > +
> > + err = rcar_gen4_pcie_get_resources(rcar);
> > + if (err < 0) {
> > + dev_err(dev, "Failed to request resource: %d\n", err);
>
> Use dev_err_probe().
Right. Can't believe I missed that and the error checks.
>
> > + return err;
> > + }
> > +
> > + err = rcar_gen4_pcie_prepare(rcar);
> > + if (err < 0)
> > + return err;
> > +
> > + err = rcar_gen4_add_dw_pcie_rp(rcar);
> > + if (err < 0)
> > + goto err_add;
> > +
> > + return 0;
> > +
> > +err_add:
>
> err_prepare
IMO either "err_unprepare" or "err_add_rp". First option seems better
since unlike the second version it would look correct in case of
having multiple gotos to the same label.
"err_prepare" doesn't indicate neither the target code nor the source
of the jump. So the name doesn't sound descriptive if not to say
misleading.
>
> > + rcar_gen4_pcie_unprepare(rcar);
> > +
> > + return err;
> > +}
> > +
> > +static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> > +
> > + rcar_gen4_remove_dw_pcie_rp(rcar);
> > + rcar_gen4_pcie_unprepare(rcar);
> > +}
> > +
> > +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> > + { .compatible = "renesas,rcar-gen4-pcie", },
> > + {},
> > +};
>
> Missing MODULE_DEVICE_TABLE since this driver can be built as a module.
>
> > +
> > +static struct platform_driver rcar_gen4_pcie_driver = {
> > + .driver = {
> > + .name = "pcie-rcar-gen4",
> > + .of_match_table = rcar_gen4_pcie_of_match,
> > + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> > + },
> > + .probe = rcar_gen4_pcie_probe,
> > + .remove_new = rcar_gen4_pcie_remove,
> > +};
> > +module_platform_driver(rcar_gen4_pcie_driver);
> > +
> > +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > new file mode 100644
> > index 000000000000..a5fb9aae0a6f
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > @@ -0,0 +1,200 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +
> > +#include "pcie-rcar-gen4.h"
> > +#include "pcie-designware.h"
> > +
> > +/* Renesas-specific */
> > +#define PCIERSTCTRL1 0x0014
> > +#define APP_HOLD_PHY_RST BIT(16)
>
> Spacing is not consistent.
>
> > +#define APP_LTSSM_ENABLE BIT(0)
> > +
> > +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> > +#define RCAR_MAX_LINK_SPEED 4
> > +
> > +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> > + bool enable)
> > +{
> > + u32 val;
> > +
> > + val = readl(rcar->base + PCIERSTCTRL1);
> > + if (enable) {
> > + val |= APP_LTSSM_ENABLE;
> > + val &= ~APP_HOLD_PHY_RST;
> > + } else {
> > + /*
> > + * Since the datasheet of R-Car doesn't mention how to assert
> > + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > + * hang-up issue happened in the dw_edma_core_off() when
> > + * the controller didn't detect a PCI device.
> > + */
> > + val &= ~APP_LTSSM_ENABLE;
> > + }
> > + writel(val, rcar->base + PCIERSTCTRL1);
> > +}
> > +
> > +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + u32 val, mask;
> > +
> > + val = readl(rcar->base + PCIEINTSTS0);
> > + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> > +
> > + return (val & mask) == mask;
> > +}
> > +
> > +static bool rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
>
> It'd be good to add a comment for this function.
>
> > +{
> > + u32 val;
> > + int i;
> > +
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + val &= ~PORT_LOGIC_SPEED_CHANGE;
> > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > +
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + val |= PORT_LOGIC_SPEED_CHANGE;
> > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > +
> > + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> > + return true;
> > + usleep_range(10000, 11000);
> > + }
> > +
> > + return false;
> > +}
> > +
> > +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
>
> For this one too.
>
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + int i, changes;
> > +
> > + rcar_gen4_pcie_ltssm_enable(rcar, true);
> > +
> > + /*
> > + * Require direct speed change with retrying here if the link_gen is
> > + * PCIe Gen2 or higher.
> > + */
> > + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> > +
> > + /*
> > + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> > + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> > + */
> > + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> > + changes--;
> > +
> > + for (i = 0; i < changes; i++) {
> > + if (!rcar_gen4_pcie_speed_change(dw))
> > + break; /* No error because possible disconnected here if EP mode */
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > +
> > + rcar_gen4_pcie_ltssm_enable(rcar, false);
> > +}
> > +
> > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar)
>
> s/basic/common
>
> - Mani
>
> > +{
> > + struct dw_pcie *dw = &rcar->dw;
> > + u32 val;
> > +
> > + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > +
> > + val = readl(rcar->base + PCIEMSR0);
> > + if (rcar->mode == DW_PCIE_RC_TYPE)
> > + val |= DEVICE_TYPE_RC;
> > + else if (rcar->mode == DW_PCIE_EP_TYPE)
> > + val |= DEVICE_TYPE_EP;
> > + else
> > + return -EINVAL;
> > +
> > + if (dw->num_lanes < 4)
> > + val |= BIFUR_MOD_SET_ON;
> > +
> > + writel(val, rcar->base + PCIEMSR0);
> > +
> > + return reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > +}
> > +
> > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct dw_pcie *dw = &rcar->dw;
> > +
> > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > +}
> > +
> > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct device *dev = rcar->dw.dev;
> > + int err;
> > +
> > + pm_runtime_enable(dev);
> > + err = pm_runtime_resume_and_get(dev);
> > + if (err < 0) {
> > + dev_err(dev, "Failed to resume/get Runtime PM\n");
> > + pm_runtime_disable(dev);
> > + }
> > +
> > + return err;
> > +}
> > +
> > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct device *dev = rcar->dw.dev;
> > +
> > + pm_runtime_put(dev);
> > + pm_runtime_disable(dev);
> > +}
> > +
> > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> > +{
> > + /* Renesas-specific registers */
> > + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> > +
> > + return IS_ERR(rcar->base) ? PTR_ERR(rcar->base) : 0;
This can be replaced with PTR_ERR_OR_ZERO().
> > +}
> > +
> > +static const struct dw_pcie_ops dw_pcie_ops = {
> > + .start_link = rcar_gen4_pcie_start_link,
> > + .stop_link = rcar_gen4_pcie_stop_link,
> > + .link_up = rcar_gen4_pcie_link_up,
> > +};
> > +
> > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct rcar_gen4_pcie *rcar;
> > +
> > + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> > + if (!rcar)
> > + return NULL;
A better approach would be to return ERR_PTR(-ENOMEM) here and convert
the method caller to performing "if (IS_ERR(rcar)) return
PTR_ERR(rcar)". Thus in case if you decide to extend this method
semantics with additional checks you won't need to update the caller
and all the errors returned will be propagated up to the kernel
device-driver subsystem.
-Serge(y)
> > +
> > + rcar->dw.dev = dev;
> > + rcar->dw.ops = &dw_pcie_ops;
> > + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> > + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> > + rcar->pdev = pdev;
> > + platform_set_drvdata(pdev, rcar);
> > +
> > + return rcar;
> > +}
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > new file mode 100644
> > index 000000000000..781165422739
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > @@ -0,0 +1,44 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > + */
> > +
> > +#ifndef _PCIE_RCAR_GEN4_H_
> > +#define _PCIE_RCAR_GEN4_H_
> > +
> > +#include <linux/io.h>
> > +#include <linux/pci.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +/* Renesas-specific */
> > +#define PCIEMSR0 0x0000
> > +#define BIFUR_MOD_SET_ON BIT(0)
> > +#define DEVICE_TYPE_EP 0
> > +#define DEVICE_TYPE_RC BIT(4)
> > +
> > +#define PCIEINTSTS0 0x0084
> > +#define PCIEINTSTS0EN 0x0310
> > +#define MSI_CTRL_INT BIT(26)
> > +#define SMLH_LINK_UP BIT(7)
> > +#define RDLH_LINK_UP BIT(6)
> > +#define PCIEDMAINTSTSEN 0x0314
> > +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> > +
> > +struct rcar_gen4_pcie {
> > + struct dw_pcie dw;
> > + void __iomem *base;
> > + struct platform_device *pdev;
> > + enum dw_pcie_device_mode mode;
> > +};
> > +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> > +
> > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar);
> > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar);
> > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar);
> > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar);
> > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar);
> > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev);
> > +
> > +#endif /* _PCIE_RCAR_GEN4_H_ */
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-08-01 1:06 ` Serge Semin
@ 2023-08-01 6:46 ` Yoshihiro Shimoda
2023-08-01 18:28 ` Serge Semin
2023-08-02 10:36 ` Manivannan Sadhasivam
1 sibling, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 6:46 UTC (permalink / raw)
To: Serge Semin, Manivannan Sadhasivam
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
bhelgaas@google.com, kishon@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 10:07 AM
>
> On Mon, Jul 24, 2023 at 05:58:20PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Jul 21, 2023 at 04:44:49PM +0900, Yoshihiro Shimoda wrote:
> > > Add R-Car Gen4 PCIe Host support. This controller is based on
> > > Synopsys DesignWare PCIe, but this controller has vendor-specific
> > > registers so that requires initialization code like mode setting
> > > and retraining and so on.
> > >
> > > To reduce code delta, adds some helper functions which are used by
> > > both the host driver and the endpoint driver (which is added
> > > immediately afterwards) into a separate file.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > ---
> > > drivers/pci/controller/dwc/Kconfig | 9 +
> > > drivers/pci/controller/dwc/Makefile | 2 +
> > > .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> > > drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> > > 5 files changed, 404 insertions(+)
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > >
> > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > > index ab96da43e0c2..64d4d37bc891 100644
> > > --- a/drivers/pci/controller/dwc/Kconfig
> > > +++ b/drivers/pci/controller/dwc/Kconfig
> > > @@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST
> > > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > > This driver supports TMPV7708 SoC.
> > >
> > > +config PCIE_RCAR_GEN4
> > > + tristate "Renesas R-Car Gen4 PCIe Host controller"
> > > + depends on ARCH_RENESAS || COMPILE_TEST
> > > + depends on PCI_MSI
> > > + select PCIE_DW_HOST
> > > + help
> > > + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
> >
> > Add a line about module option and specify the module name. Like,
> >
> > To compile this driver as a module, choose M here: the module will be called
> > pcie-rcar-gen4-host-drv.ko.
> >
> > I have a suggestion for module name change below...
> >
> > > + This uses the DesignWare core.
> > > +
> > > endmenu
> > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > > index bf5c311875a1..486cf706b53d 100644
> > > --- a/drivers/pci/controller/dwc/Makefile
> > > +++ b/drivers/pci/controller/dwc/Makefile
> > > @@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > > +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> > > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
> >
> > It'd be better to call the module as pcie-rcar-gen4-host and the file as
> > pcie-rcar-gen4-host-drv.c
> >
> > Also, move the goal definition first.
> >
> > >
> > > # The following drivers are for devices that use the generic ACPI
> > > # pci_root.c driver but don't support standard ECAM config access.
> > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > new file mode 100644
> > > index 000000000000..3168f5d98a79
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > @@ -0,0 +1,149 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
> > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > + */
> > > +
> > > +#include <linux/delay.h>
> > > +#include <linux/interrupt.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +#include "pcie-rcar-gen4.h"
> > > +#include "pcie-designware.h"
> > > +
> > > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > > +{
> > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > + int ret;
> > > + u32 val;
> > > +
> > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > +
> > > + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > + if (ret) {
> > > + dev_err(dw->dev, "Failed to enable ref clocks\n");
> > > + return ret;
> > > + }
> > > +
> > > + ret = rcar_gen4_pcie_basic_init(rcar);
> > > + if (ret < 0) {
> >
> > Use "if (ret)" for consistency.
> >
> > > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > + return ret;
> > > + }
> > > +
> > > + /*
> > > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > > + * assignment during device enumeration.
> > > + */
> > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> > > +
> > > + if (IS_ENABLED(CONFIG_PCI_MSI)) {
> >
> > Driver depends on PCI_MSI, so there is no need of this check.
> >
> > > + /* Enable MSI interrupt signal */
> > > + val = readl(rcar->base + PCIEINTSTS0EN);
> > > + val |= MSI_CTRL_INT;
> > > + writel(val, rcar->base + PCIEINTSTS0EN);
> > > + }
> > > +
> > > + msleep(100); /* pe_rst requires 100msec delay */
> > > +
> > > + gpiod_set_value_cansleep(dw->pe_rst, 0);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
> > > +{
> > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > +
> > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > + rcar_gen4_pcie_basic_deinit(rcar);
> > > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > +}
> > > +
> > > +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
> > > + .host_init = rcar_gen4_pcie_host_init,
> > > + .host_deinit = rcar_gen4_pcie_host_deinit,
> > > +};
> > > +
> > > +static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + struct dw_pcie_rp *pp = &rcar->dw.pp;
> > > +
> > > + pp->num_vectors = MAX_MSI_IRQS;
> > > + pp->ops = &rcar_gen4_pcie_host_ops;
> > > + rcar->mode = DW_PCIE_RC_TYPE;
> > > +
> > > + return dw_pcie_host_init(pp);
> > > +}
> > > +
> > > +static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + dw_pcie_host_deinit(&rcar->dw.pp);
> > > + gpiod_set_value_cansleep(rcar->dw.pe_rst, 1);
> > > +}
> > > +
> > > +static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct rcar_gen4_pcie *rcar;
> > > + int err;
> > > +
> > > + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> > > + if (!rcar)
> > > + return -ENOMEM;
> > > +
> > > + err = rcar_gen4_pcie_get_resources(rcar);
>
> > > + if (err < 0) {
> > > + dev_err(dev, "Failed to request resource: %d\n", err);
> >
> > Use dev_err_probe().
>
> Right. Can't believe I missed that and the error checks.
>
> >
> > > + return err;
> > > + }
> > > +
> > > + err = rcar_gen4_pcie_prepare(rcar);
> > > + if (err < 0)
> > > + return err;
> > > +
>
> > > + err = rcar_gen4_add_dw_pcie_rp(rcar);
> > > + if (err < 0)
> > > + goto err_add;
> > > +
> > > + return 0;
> > > +
> > > +err_add:
> >
> > err_prepare
>
> IMO either "err_unprepare" or "err_add_rp". First option seems better
> since unlike the second version it would look correct in case of
> having multiple gotos to the same label.
>
> "err_prepare" doesn't indicate neither the target code nor the source
> of the jump. So the name doesn't sound descriptive if not to say
> misleading.
Thank you for your suggestion. I checked pcie-designware-{ep,host}.c and
it seems that the goto labels are:
err_{part_of_calling_function_name}:
For example:
err_stop_link:
dw_pcie_stop_link(pci);
err_remove_edma:
dw_pcie_edma_remove(pci);
So, err_unprepare: here is a good label, I think. I'll fix the label
on v19.
Best regards,
Yoshihiro Shimoda
> >
> > > + rcar_gen4_pcie_unprepare(rcar);
> > > +
> > > + return err;
> > > +}
> > > +
> > > +static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> > > +{
> > > + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> > > +
> > > + rcar_gen4_remove_dw_pcie_rp(rcar);
> > > + rcar_gen4_pcie_unprepare(rcar);
> > > +}
> > > +
> > > +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> > > + { .compatible = "renesas,rcar-gen4-pcie", },
> > > + {},
> > > +};
> >
> > Missing MODULE_DEVICE_TABLE since this driver can be built as a module.
> >
> > > +
> > > +static struct platform_driver rcar_gen4_pcie_driver = {
> > > + .driver = {
> > > + .name = "pcie-rcar-gen4",
> > > + .of_match_table = rcar_gen4_pcie_of_match,
> > > + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> > > + },
> > > + .probe = rcar_gen4_pcie_probe,
> > > + .remove_new = rcar_gen4_pcie_remove,
> > > +};
> > > +module_platform_driver(rcar_gen4_pcie_driver);
> > > +
> > > +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
> > > +MODULE_LICENSE("GPL");
> > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > new file mode 100644
> > > index 000000000000..a5fb9aae0a6f
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > @@ -0,0 +1,200 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > + */
> > > +
> > > +#include <linux/delay.h>
> > > +#include <linux/io.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/pm_runtime.h>
> > > +#include <linux/reset.h>
> > > +
> > > +#include "pcie-rcar-gen4.h"
> > > +#include "pcie-designware.h"
> > > +
> > > +/* Renesas-specific */
> > > +#define PCIERSTCTRL1 0x0014
> > > +#define APP_HOLD_PHY_RST BIT(16)
> >
> > Spacing is not consistent.
> >
> > > +#define APP_LTSSM_ENABLE BIT(0)
> > > +
> > > +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> > > +#define RCAR_MAX_LINK_SPEED 4
> > > +
> > > +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> > > + bool enable)
> > > +{
> > > + u32 val;
> > > +
> > > + val = readl(rcar->base + PCIERSTCTRL1);
> > > + if (enable) {
> > > + val |= APP_LTSSM_ENABLE;
> > > + val &= ~APP_HOLD_PHY_RST;
> > > + } else {
> > > + /*
> > > + * Since the datasheet of R-Car doesn't mention how to assert
> > > + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > > + * hang-up issue happened in the dw_edma_core_off() when
> > > + * the controller didn't detect a PCI device.
> > > + */
> > > + val &= ~APP_LTSSM_ENABLE;
> > > + }
> > > + writel(val, rcar->base + PCIERSTCTRL1);
> > > +}
> > > +
> > > +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> > > +{
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > + u32 val, mask;
> > > +
> > > + val = readl(rcar->base + PCIEINTSTS0);
> > > + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> > > +
> > > + return (val & mask) == mask;
> > > +}
> > > +
> > > +static bool rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> >
> > It'd be good to add a comment for this function.
> >
> > > +{
> > > + u32 val;
> > > + int i;
> > > +
> > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > + val &= ~PORT_LOGIC_SPEED_CHANGE;
> > > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > > +
> > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > + val |= PORT_LOGIC_SPEED_CHANGE;
> > > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > > +
> > > + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> > > + return true;
> > > + usleep_range(10000, 11000);
> > > + }
> > > +
> > > + return false;
> > > +}
> > > +
> > > +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> >
> > For this one too.
> >
> > > +{
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > + int i, changes;
> > > +
> > > + rcar_gen4_pcie_ltssm_enable(rcar, true);
> > > +
> > > + /*
> > > + * Require direct speed change with retrying here if the link_gen is
> > > + * PCIe Gen2 or higher.
> > > + */
> > > + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> > > +
> > > + /*
> > > + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> > > + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> > > + */
> > > + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> > > + changes--;
> > > +
> > > + for (i = 0; i < changes; i++) {
> > > + if (!rcar_gen4_pcie_speed_change(dw))
> > > + break; /* No error because possible disconnected here if EP mode */
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> > > +{
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > +
> > > + rcar_gen4_pcie_ltssm_enable(rcar, false);
> > > +}
> > > +
> > > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar)
> >
> > s/basic/common
> >
> > - Mani
> >
> > > +{
> > > + struct dw_pcie *dw = &rcar->dw;
> > > + u32 val;
> > > +
> > > + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> > > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > +
> > > + val = readl(rcar->base + PCIEMSR0);
> > > + if (rcar->mode == DW_PCIE_RC_TYPE)
> > > + val |= DEVICE_TYPE_RC;
> > > + else if (rcar->mode == DW_PCIE_EP_TYPE)
> > > + val |= DEVICE_TYPE_EP;
> > > + else
> > > + return -EINVAL;
> > > +
> > > + if (dw->num_lanes < 4)
> > > + val |= BIFUR_MOD_SET_ON;
> > > +
> > > + writel(val, rcar->base + PCIEMSR0);
> > > +
> > > + return reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > +}
> > > +
> > > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + struct dw_pcie *dw = &rcar->dw;
> > > +
> > > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > +}
> > > +
> > > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + struct device *dev = rcar->dw.dev;
> > > + int err;
> > > +
> > > + pm_runtime_enable(dev);
> > > + err = pm_runtime_resume_and_get(dev);
> > > + if (err < 0) {
> > > + dev_err(dev, "Failed to resume/get Runtime PM\n");
> > > + pm_runtime_disable(dev);
> > > + }
> > > +
> > > + return err;
> > > +}
> > > +
> > > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + struct device *dev = rcar->dw.dev;
> > > +
> > > + pm_runtime_put(dev);
> > > + pm_runtime_disable(dev);
> > > +}
> > > +
> > > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> > > +{
> > > + /* Renesas-specific registers */
> > > + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> > > +
>
> > > + return IS_ERR(rcar->base) ? PTR_ERR(rcar->base) : 0;
>
> This can be replaced with PTR_ERR_OR_ZERO().
>
> > > +}
> > > +
> > > +static const struct dw_pcie_ops dw_pcie_ops = {
> > > + .start_link = rcar_gen4_pcie_start_link,
> > > + .stop_link = rcar_gen4_pcie_stop_link,
> > > + .link_up = rcar_gen4_pcie_link_up,
> > > +};
> > > +
> > > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct rcar_gen4_pcie *rcar;
> > > +
>
> > > + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> > > + if (!rcar)
> > > + return NULL;
>
> A better approach would be to return ERR_PTR(-ENOMEM) here and convert
> the method caller to performing "if (IS_ERR(rcar)) return
> PTR_ERR(rcar)". Thus in case if you decide to extend this method
> semantics with additional checks you won't need to update the caller
> and all the errors returned will be propagated up to the kernel
> device-driver subsystem.
>
> -Serge(y)
>
> > > +
> > > + rcar->dw.dev = dev;
> > > + rcar->dw.ops = &dw_pcie_ops;
> > > + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> > > + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> > > + rcar->pdev = pdev;
> > > + platform_set_drvdata(pdev, rcar);
> > > +
> > > + return rcar;
> > > +}
> > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > > new file mode 100644
> > > index 000000000000..781165422739
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > > @@ -0,0 +1,44 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > + */
> > > +
> > > +#ifndef _PCIE_RCAR_GEN4_H_
> > > +#define _PCIE_RCAR_GEN4_H_
> > > +
> > > +#include <linux/io.h>
> > > +#include <linux/pci.h>
> > > +
> > > +#include "pcie-designware.h"
> > > +
> > > +/* Renesas-specific */
> > > +#define PCIEMSR0 0x0000
> > > +#define BIFUR_MOD_SET_ON BIT(0)
> > > +#define DEVICE_TYPE_EP 0
> > > +#define DEVICE_TYPE_RC BIT(4)
> > > +
> > > +#define PCIEINTSTS0 0x0084
> > > +#define PCIEINTSTS0EN 0x0310
> > > +#define MSI_CTRL_INT BIT(26)
> > > +#define SMLH_LINK_UP BIT(7)
> > > +#define RDLH_LINK_UP BIT(6)
> > > +#define PCIEDMAINTSTSEN 0x0314
> > > +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> > > +
> > > +struct rcar_gen4_pcie {
> > > + struct dw_pcie dw;
> > > + void __iomem *base;
> > > + struct platform_device *pdev;
> > > + enum dw_pcie_device_mode mode;
> > > +};
> > > +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> > > +
> > > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar);
> > > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar);
> > > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar);
> > > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar);
> > > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar);
> > > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev);
> > > +
> > > +#endif /* _PCIE_RCAR_GEN4_H_ */
> > > --
> > > 2.25.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread* Re: [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-08-01 6:46 ` Yoshihiro Shimoda
@ 2023-08-01 18:28 ` Serge Semin
0 siblings, 0 replies; 90+ messages in thread
From: Serge Semin @ 2023-08-01 18:28 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Manivannan Sadhasivam, jingoohan1@gmail.com,
gustavo.pimentel@synopsys.com, lpieralisi@kernel.org,
robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
On Tue, Aug 01, 2023 at 06:46:00AM +0000, Yoshihiro Shimoda wrote:
> Hi Serge,
>
> > From: Serge Semin, Sent: Tuesday, August 1, 2023 10:07 AM
> >
> > On Mon, Jul 24, 2023 at 05:58:20PM +0530, Manivannan Sadhasivam wrote:
> > > On Fri, Jul 21, 2023 at 04:44:49PM +0900, Yoshihiro Shimoda wrote:
> > > > Add R-Car Gen4 PCIe Host support. This controller is based on
> > > > Synopsys DesignWare PCIe, but this controller has vendor-specific
> > > > registers so that requires initialization code like mode setting
> > > > and retraining and so on.
> > > >
> > > > To reduce code delta, adds some helper functions which are used by
> > > > both the host driver and the endpoint driver (which is added
> > > > immediately afterwards) into a separate file.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > ---
> > > > drivers/pci/controller/dwc/Kconfig | 9 +
> > > > drivers/pci/controller/dwc/Makefile | 2 +
> > > > .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> > > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> > > > drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> > > > 5 files changed, 404 insertions(+)
> > > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > > > index ab96da43e0c2..64d4d37bc891 100644
> > > > --- a/drivers/pci/controller/dwc/Kconfig
> > > > +++ b/drivers/pci/controller/dwc/Kconfig
> > > > @@ -415,4 +415,13 @@ config PCIE_VISCONTI_HOST
> > > > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > > > This driver supports TMPV7708 SoC.
> > > >
> > > > +config PCIE_RCAR_GEN4
> > > > + tristate "Renesas R-Car Gen4 PCIe Host controller"
> > > > + depends on ARCH_RENESAS || COMPILE_TEST
> > > > + depends on PCI_MSI
> > > > + select PCIE_DW_HOST
> > > > + help
> > > > + Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
> > >
> > > Add a line about module option and specify the module name. Like,
> > >
> > > To compile this driver as a module, choose M here: the module will be called
> > > pcie-rcar-gen4-host-drv.ko.
> > >
> > > I have a suggestion for module name change below...
> > >
> > > > + This uses the DesignWare core.
> > > > +
> > > > endmenu
> > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > > > index bf5c311875a1..486cf706b53d 100644
> > > > --- a/drivers/pci/controller/dwc/Makefile
> > > > +++ b/drivers/pci/controller/dwc/Makefile
> > > > @@ -26,6 +26,8 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > > > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > > > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > > > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > > > +pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> > > > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
> > >
> > > It'd be better to call the module as pcie-rcar-gen4-host and the file as
> > > pcie-rcar-gen4-host-drv.c
> > >
> > > Also, move the goal definition first.
> > >
> > > >
> > > > # The following drivers are for devices that use the generic ACPI
> > > > # pci_root.c driver but don't support standard ECAM config access.
> > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > > new file mode 100644
> > > > index 000000000000..3168f5d98a79
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > > @@ -0,0 +1,149 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > +/*
> > > > + * PCIe host controller driver for Renesas R-Car Gen4 Series SoCs
> > > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > > + */
> > > > +
> > > > +#include <linux/delay.h>
> > > > +#include <linux/interrupt.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of_device.h>
> > > > +#include <linux/pci.h>
> > > > +#include <linux/platform_device.h>
> > > > +
> > > > +#include "pcie-rcar-gen4.h"
> > > > +#include "pcie-designware.h"
> > > > +
> > > > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > > > +{
> > > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > + int ret;
> > > > + u32 val;
> > > > +
> > > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > > +
> > > > + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > > + if (ret) {
> > > > + dev_err(dw->dev, "Failed to enable ref clocks\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = rcar_gen4_pcie_basic_init(rcar);
> > > > + if (ret < 0) {
> > >
> > > Use "if (ret)" for consistency.
> > >
> > > > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + /*
> > > > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > > > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > > > + * assignment during device enumeration.
> > > > + */
> > > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> > > > +
> > > > + if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > >
> > > Driver depends on PCI_MSI, so there is no need of this check.
> > >
> > > > + /* Enable MSI interrupt signal */
> > > > + val = readl(rcar->base + PCIEINTSTS0EN);
> > > > + val |= MSI_CTRL_INT;
> > > > + writel(val, rcar->base + PCIEINTSTS0EN);
> > > > + }
> > > > +
> > > > + msleep(100); /* pe_rst requires 100msec delay */
> > > > +
> > > > + gpiod_set_value_cansleep(dw->pe_rst, 0);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
> > > > +{
> > > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > +
> > > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > > + rcar_gen4_pcie_basic_deinit(rcar);
> > > > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > > > +}
> > > > +
> > > > +static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
> > > > + .host_init = rcar_gen4_pcie_host_init,
> > > > + .host_deinit = rcar_gen4_pcie_host_deinit,
> > > > +};
> > > > +
> > > > +static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + struct dw_pcie_rp *pp = &rcar->dw.pp;
> > > > +
> > > > + pp->num_vectors = MAX_MSI_IRQS;
> > > > + pp->ops = &rcar_gen4_pcie_host_ops;
> > > > + rcar->mode = DW_PCIE_RC_TYPE;
> > > > +
> > > > + return dw_pcie_host_init(pp);
> > > > +}
> > > > +
> > > > +static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + dw_pcie_host_deinit(&rcar->dw.pp);
> > > > + gpiod_set_value_cansleep(rcar->dw.pe_rst, 1);
> > > > +}
> > > > +
> > > > +static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> > > > +{
> > > > + struct device *dev = &pdev->dev;
> > > > + struct rcar_gen4_pcie *rcar;
> > > > + int err;
> > > > +
> > > > + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> > > > + if (!rcar)
> > > > + return -ENOMEM;
> > > > +
> > > > + err = rcar_gen4_pcie_get_resources(rcar);
> >
> > > > + if (err < 0) {
> > > > + dev_err(dev, "Failed to request resource: %d\n", err);
> > >
> > > Use dev_err_probe().
> >
> > Right. Can't believe I missed that and the error checks.
> >
> > >
> > > > + return err;
> > > > + }
> > > > +
> > > > + err = rcar_gen4_pcie_prepare(rcar);
> > > > + if (err < 0)
> > > > + return err;
> > > > +
> >
> > > > + err = rcar_gen4_add_dw_pcie_rp(rcar);
> > > > + if (err < 0)
> > > > + goto err_add;
> > > > +
> > > > + return 0;
> > > > +
> > > > +err_add:
> > >
> > > err_prepare
> >
> > IMO either "err_unprepare" or "err_add_rp". First option seems better
> > since unlike the second version it would look correct in case of
> > having multiple gotos to the same label.
> >
> > "err_prepare" doesn't indicate neither the target code nor the source
> > of the jump. So the name doesn't sound descriptive if not to say
> > misleading.
>
> Thank you for your suggestion. I checked pcie-designware-{ep,host}.c and
> it seems that the goto labels are:
>
> err_{part_of_calling_function_name}:
>
> For example:
>
> err_stop_link:
> dw_pcie_stop_link(pci);
>
> err_remove_edma:
> dw_pcie_edma_remove(pci);
>
> So, err_unprepare: here is a good label, I think. I'll fix the label
> on v19.
Ok! That's my preference too.
-Serge(y)
>
> Best regards,
> Yoshihiro Shimoda
>
> > >
> > > > + rcar_gen4_pcie_unprepare(rcar);
> > > > +
> > > > + return err;
> > > > +}
> > > > +
> > > > +static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> > > > +{
> > > > + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> > > > +
> > > > + rcar_gen4_remove_dw_pcie_rp(rcar);
> > > > + rcar_gen4_pcie_unprepare(rcar);
> > > > +}
> > > > +
> > > > +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> > > > + { .compatible = "renesas,rcar-gen4-pcie", },
> > > > + {},
> > > > +};
> > >
> > > Missing MODULE_DEVICE_TABLE since this driver can be built as a module.
> > >
> > > > +
> > > > +static struct platform_driver rcar_gen4_pcie_driver = {
> > > > + .driver = {
> > > > + .name = "pcie-rcar-gen4",
> > > > + .of_match_table = rcar_gen4_pcie_of_match,
> > > > + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> > > > + },
> > > > + .probe = rcar_gen4_pcie_probe,
> > > > + .remove_new = rcar_gen4_pcie_remove,
> > > > +};
> > > > +module_platform_driver(rcar_gen4_pcie_driver);
> > > > +
> > > > +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe host controller driver");
> > > > +MODULE_LICENSE("GPL");
> > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > new file mode 100644
> > > > index 000000000000..a5fb9aae0a6f
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > @@ -0,0 +1,200 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > +/*
> > > > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > > + */
> > > > +
> > > > +#include <linux/delay.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/of_device.h>
> > > > +#include <linux/pci.h>
> > > > +#include <linux/pm_runtime.h>
> > > > +#include <linux/reset.h>
> > > > +
> > > > +#include "pcie-rcar-gen4.h"
> > > > +#include "pcie-designware.h"
> > > > +
> > > > +/* Renesas-specific */
> > > > +#define PCIERSTCTRL1 0x0014
> > > > +#define APP_HOLD_PHY_RST BIT(16)
> > >
> > > Spacing is not consistent.
> > >
> > > > +#define APP_LTSSM_ENABLE BIT(0)
> > > > +
> > > > +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> > > > +#define RCAR_MAX_LINK_SPEED 4
> > > > +
> > > > +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> > > > + bool enable)
> > > > +{
> > > > + u32 val;
> > > > +
> > > > + val = readl(rcar->base + PCIERSTCTRL1);
> > > > + if (enable) {
> > > > + val |= APP_LTSSM_ENABLE;
> > > > + val &= ~APP_HOLD_PHY_RST;
> > > > + } else {
> > > > + /*
> > > > + * Since the datasheet of R-Car doesn't mention how to assert
> > > > + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > > > + * hang-up issue happened in the dw_edma_core_off() when
> > > > + * the controller didn't detect a PCI device.
> > > > + */
> > > > + val &= ~APP_LTSSM_ENABLE;
> > > > + }
> > > > + writel(val, rcar->base + PCIERSTCTRL1);
> > > > +}
> > > > +
> > > > +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> > > > +{
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > + u32 val, mask;
> > > > +
> > > > + val = readl(rcar->base + PCIEINTSTS0);
> > > > + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> > > > +
> > > > + return (val & mask) == mask;
> > > > +}
> > > > +
> > > > +static bool rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> > >
> > > It'd be good to add a comment for this function.
> > >
> > > > +{
> > > > + u32 val;
> > > > + int i;
> > > > +
> > > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > > + val &= ~PORT_LOGIC_SPEED_CHANGE;
> > > > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > > > +
> > > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > > + val |= PORT_LOGIC_SPEED_CHANGE;
> > > > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > > > +
> > > > + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> > > > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > > > + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> > > > + return true;
> > > > + usleep_range(10000, 11000);
> > > > + }
> > > > +
> > > > + return false;
> > > > +}
> > > > +
> > > > +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> > >
> > > For this one too.
> > >
> > > > +{
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > + int i, changes;
> > > > +
> > > > + rcar_gen4_pcie_ltssm_enable(rcar, true);
> > > > +
> > > > + /*
> > > > + * Require direct speed change with retrying here if the link_gen is
> > > > + * PCIe Gen2 or higher.
> > > > + */
> > > > + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> > > > +
> > > > + /*
> > > > + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> > > > + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> > > > + */
> > > > + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> > > > + changes--;
> > > > +
> > > > + for (i = 0; i < changes; i++) {
> > > > + if (!rcar_gen4_pcie_speed_change(dw))
> > > > + break; /* No error because possible disconnected here if EP mode */
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> > > > +{
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > +
> > > > + rcar_gen4_pcie_ltssm_enable(rcar, false);
> > > > +}
> > > > +
> > > > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar)
> > >
> > > s/basic/common
> > >
> > > - Mani
> > >
> > > > +{
> > > > + struct dw_pcie *dw = &rcar->dw;
> > > > + u32 val;
> > > > +
> > > > + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> > > > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > > +
> > > > + val = readl(rcar->base + PCIEMSR0);
> > > > + if (rcar->mode == DW_PCIE_RC_TYPE)
> > > > + val |= DEVICE_TYPE_RC;
> > > > + else if (rcar->mode == DW_PCIE_EP_TYPE)
> > > > + val |= DEVICE_TYPE_EP;
> > > > + else
> > > > + return -EINVAL;
> > > > +
> > > > + if (dw->num_lanes < 4)
> > > > + val |= BIFUR_MOD_SET_ON;
> > > > +
> > > > + writel(val, rcar->base + PCIEMSR0);
> > > > +
> > > > + return reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > > +}
> > > > +
> > > > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + struct dw_pcie *dw = &rcar->dw;
> > > > +
> > > > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > > > +}
> > > > +
> > > > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + struct device *dev = rcar->dw.dev;
> > > > + int err;
> > > > +
> > > > + pm_runtime_enable(dev);
> > > > + err = pm_runtime_resume_and_get(dev);
> > > > + if (err < 0) {
> > > > + dev_err(dev, "Failed to resume/get Runtime PM\n");
> > > > + pm_runtime_disable(dev);
> > > > + }
> > > > +
> > > > + return err;
> > > > +}
> > > > +
> > > > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + struct device *dev = rcar->dw.dev;
> > > > +
> > > > + pm_runtime_put(dev);
> > > > + pm_runtime_disable(dev);
> > > > +}
> > > > +
> > > > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> > > > +{
> > > > + /* Renesas-specific registers */
> > > > + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> > > > +
> >
> > > > + return IS_ERR(rcar->base) ? PTR_ERR(rcar->base) : 0;
> >
> > This can be replaced with PTR_ERR_OR_ZERO().
> >
> > > > +}
> > > > +
> > > > +static const struct dw_pcie_ops dw_pcie_ops = {
> > > > + .start_link = rcar_gen4_pcie_start_link,
> > > > + .stop_link = rcar_gen4_pcie_stop_link,
> > > > + .link_up = rcar_gen4_pcie_link_up,
> > > > +};
> > > > +
> > > > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> > > > +{
> > > > + struct device *dev = &pdev->dev;
> > > > + struct rcar_gen4_pcie *rcar;
> > > > +
> >
> > > > + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> > > > + if (!rcar)
> > > > + return NULL;
> >
> > A better approach would be to return ERR_PTR(-ENOMEM) here and convert
> > the method caller to performing "if (IS_ERR(rcar)) return
> > PTR_ERR(rcar)". Thus in case if you decide to extend this method
> > semantics with additional checks you won't need to update the caller
> > and all the errors returned will be propagated up to the kernel
> > device-driver subsystem.
> >
> > -Serge(y)
> >
> > > > +
> > > > + rcar->dw.dev = dev;
> > > > + rcar->dw.ops = &dw_pcie_ops;
> > > > + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> > > > + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> > > > + rcar->pdev = pdev;
> > > > + platform_set_drvdata(pdev, rcar);
> > > > +
> > > > + return rcar;
> > > > +}
> > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.h b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > > > new file mode 100644
> > > > index 000000000000..781165422739
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > > > @@ -0,0 +1,44 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > +/*
> > > > + * PCIe host/endpoint controller driver for Renesas R-Car Gen4 Series SoCs
> > > > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > > > + */
> > > > +
> > > > +#ifndef _PCIE_RCAR_GEN4_H_
> > > > +#define _PCIE_RCAR_GEN4_H_
> > > > +
> > > > +#include <linux/io.h>
> > > > +#include <linux/pci.h>
> > > > +
> > > > +#include "pcie-designware.h"
> > > > +
> > > > +/* Renesas-specific */
> > > > +#define PCIEMSR0 0x0000
> > > > +#define BIFUR_MOD_SET_ON BIT(0)
> > > > +#define DEVICE_TYPE_EP 0
> > > > +#define DEVICE_TYPE_RC BIT(4)
> > > > +
> > > > +#define PCIEINTSTS0 0x0084
> > > > +#define PCIEINTSTS0EN 0x0310
> > > > +#define MSI_CTRL_INT BIT(26)
> > > > +#define SMLH_LINK_UP BIT(7)
> > > > +#define RDLH_LINK_UP BIT(6)
> > > > +#define PCIEDMAINTSTSEN 0x0314
> > > > +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> > > > +
> > > > +struct rcar_gen4_pcie {
> > > > + struct dw_pcie dw;
> > > > + void __iomem *base;
> > > > + struct platform_device *pdev;
> > > > + enum dw_pcie_device_mode mode;
> > > > +};
> > > > +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> > > > +
> > > > +int rcar_gen4_pcie_basic_init(struct rcar_gen4_pcie *rcar);
> > > > +void rcar_gen4_pcie_basic_deinit(struct rcar_gen4_pcie *rcar);
> > > > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar);
> > > > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar);
> > > > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar);
> > > > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev);
> > > > +
> > > > +#endif /* _PCIE_RCAR_GEN4_H_ */
> > > > --
> > > > 2.25.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* Re: [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
2023-08-01 1:06 ` Serge Semin
2023-08-01 6:46 ` Yoshihiro Shimoda
@ 2023-08-02 10:36 ` Manivannan Sadhasivam
1 sibling, 0 replies; 90+ messages in thread
From: Manivannan Sadhasivam @ 2023-08-02 10:36 UTC (permalink / raw)
To: Serge Semin
Cc: Yoshihiro Shimoda, jingoohan1, gustavo.pimentel, lpieralisi,
robh+dt, kw, bhelgaas, kishon, krzysztof.kozlowski+dt, conor+dt,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc
On Tue, Aug 01, 2023 at 04:06:32AM +0300, Serge Semin wrote:
> On Mon, Jul 24, 2023 at 05:58:20PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Jul 21, 2023 at 04:44:49PM +0900, Yoshihiro Shimoda wrote:
> > > Add R-Car Gen4 PCIe Host support. This controller is based on
> > > Synopsys DesignWare PCIe, but this controller has vendor-specific
> > > registers so that requires initialization code like mode setting
> > > and retraining and so on.
> > >
> > > To reduce code delta, adds some helper functions which are used by
> > > both the host driver and the endpoint driver (which is added
> > > immediately afterwards) into a separate file.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > ---
> > > drivers/pci/controller/dwc/Kconfig | 9 +
> > > drivers/pci/controller/dwc/Makefile | 2 +
> > > .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> > > drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> > > 5 files changed, 404 insertions(+)
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
> > >
[...]
> >
> > > + return err;
> > > + }
> > > +
> > > + err = rcar_gen4_pcie_prepare(rcar);
> > > + if (err < 0)
> > > + return err;
> > > +
>
> > > + err = rcar_gen4_add_dw_pcie_rp(rcar);
> > > + if (err < 0)
> > > + goto err_add;
> > > +
> > > + return 0;
> > > +
> > > +err_add:
> >
> > err_prepare
>
> IMO either "err_unprepare" or "err_add_rp". First option seems better
> since unlike the second version it would look correct in case of
> having multiple gotos to the same label.
>
> "err_prepare" doesn't indicate neither the target code nor the source
> of the jump. So the name doesn't sound descriptive if not to say
> misleading.
>
I just blindly went with the function name. Yes, "err_unprepare" would be the
correct label name.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (16 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 17/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-08-01 1:36 ` Serge Semin
2023-07-21 7:44 ` [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
` (2 subsequent siblings)
20 siblings, 1 reply; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda
Add R-Car Gen4 PCIe Endpoint support. This controller is based on
Synopsys DesignWare PCIe.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile | 2 +
.../pci/controller/dwc/pcie-rcar-gen4-ep.c | 189 ++++++++++++++++++
3 files changed, 200 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 64d4d37bc891..4d877cd18374 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -424,4 +424,13 @@ config PCIE_RCAR_GEN4
Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
This uses the DesignWare core.
+config PCIE_RCAR_GEN4_EP
+ tristate "Renesas R-Car Gen4 PCIe Endpoint controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ help
+ Say Y here if you want PCIe endpoint controller support on R-Car Gen4
+ SoCs. This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 486cf706b53d..0fb0bde26ac4 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
+pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o
+obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
new file mode 100644
index 000000000000..3970a920f3fe
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022-2023 Renesas Electronics Corporation
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar-gen4.h"
+#include "pcie-designware.h"
+
+#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
+#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+
+static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ if (ret) {
+ dev_err(dw->dev, "Failed to enable ref clocks\n");
+ return;
+ }
+
+ rcar_gen4_pcie_basic_init(rcar);
+
+ writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
+}
+
+static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ enum pci_barno bar;
+
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ writel(0, rcar->base + PCIEDMAINTSTSEN);
+ rcar_gen4_pcie_basic_deinit(rcar);
+ clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+}
+
+static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_EPC_IRQ_INTX:
+ return dw_pcie_ep_raise_intx_irq(ep, func_no);
+ case PCI_EPC_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(dw->dev, "Unknown IRQ type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
+ .align = SZ_1M,
+};
+
+static const struct pci_epc_features*
+rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
+{
+ return &rcar_gen4_pcie_epc_features;
+}
+
+static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
+ u8 func_no)
+{
+ return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
+}
+
+static unsigned int rcar_gen4_pcie_ep_func_conf_select2(struct dw_pcie_ep *ep,
+ u8 func_no)
+{
+ return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
+}
+
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
+ .ep_pre_init = rcar_gen4_pcie_ep_pre_init,
+ .ep_init = rcar_gen4_pcie_ep_init,
+ .ep_deinit = rcar_gen4_pcie_ep_deinit,
+ .raise_irq = rcar_gen4_pcie_ep_raise_irq,
+ .get_features = rcar_gen4_pcie_ep_get_features,
+ .func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
+ .func_conf_select2 = rcar_gen4_pcie_ep_func_conf_select2,
+};
+
+static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar,
+ struct platform_device *pdev)
+{
+ struct dw_pcie_ep *ep = &rcar->dw.ep;
+ int ret;
+
+ rcar->mode = DW_PCIE_EP_TYPE;
+ ep->ops = &pcie_ep_ops;
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to initialize endpoint\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_ep_exit(&rcar->dw.ep);
+}
+
+static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+ int err;
+
+ rcar = rcar_gen4_pcie_devm_alloc(pdev);
+ if (!rcar)
+ return -ENOMEM;
+
+ err = rcar_gen4_pcie_get_resources(rcar);
+ if (err < 0) {
+ dev_err(dev, "Failed to request resource: %d\n", err);
+ return err;
+ }
+
+ err = rcar_gen4_pcie_prepare(rcar);
+ if (err < 0)
+ return err;
+
+ err = rcar_gen4_add_pcie_ep(rcar, pdev);
+ if (err < 0)
+ goto err_add;
+
+ return 0;
+
+err_add:
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return err;
+}
+
+static void rcar_gen4_pcie_ep_remove(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
+
+ rcar_gen4_remove_pcie_ep(rcar);
+ rcar_gen4_pcie_unprepare(rcar);
+}
+
+static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ { .compatible = "renesas,rcar-gen4-pcie-ep", },
+ {},
+};
+
+static struct platform_driver rcar_gen4_pcie_ep_driver = {
+ .driver = {
+ .name = "pcie-rcar-gen4-ep",
+ .of_match_table = rcar_gen4_pcie_of_match,
+ },
+ .probe = rcar_gen4_pcie_ep_probe,
+ .remove_new = rcar_gen4_pcie_ep_remove,
+};
+module_platform_driver(rcar_gen4_pcie_ep_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
@ 2023-08-01 1:36 ` Serge Semin
2023-08-01 6:59 ` Yoshihiro Shimoda
0 siblings, 1 reply; 90+ messages in thread
From: Serge Semin @ 2023-08-01 1:36 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
On Fri, Jul 21, 2023 at 04:44:50PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe Endpoint support. This controller is based on
> Synopsys DesignWare PCIe.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 9 +
> drivers/pci/controller/dwc/Makefile | 2 +
> .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 189 ++++++++++++++++++
> 3 files changed, 200 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 64d4d37bc891..4d877cd18374 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -424,4 +424,13 @@ config PCIE_RCAR_GEN4
> Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
> This uses the DesignWare core.
>
> +config PCIE_RCAR_GEN4_EP
> + tristate "Renesas R-Car Gen4 PCIe Endpoint controller"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + depends on PCI_ENDPOINT
> + select PCIE_DW_EP
> + help
> + Say Y here if you want PCIe endpoint controller support on R-Car Gen4
> + SoCs. This uses the DesignWare core.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index 486cf706b53d..0fb0bde26ac4 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -28,6 +28,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
> +pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o
> +obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> new file mode 100644
> index 000000000000..3970a920f3fe
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +
> +#include "pcie-rcar-gen4.h"
> +#include "pcie-designware.h"
> +
> +#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
> +#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
> +
> +static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> + if (ret) {
> + dev_err(dw->dev, "Failed to enable ref clocks\n");
> + return;
> + }
> +
> + rcar_gen4_pcie_basic_init(rcar);
> +
> + writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
> +}
> +
> +static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + enum pci_barno bar;
> +
> + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> + dw_pcie_ep_reset_bar(pci, bar);
> +}
> +
> +static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> +
> + writel(0, rcar->base + PCIEDMAINTSTSEN);
> + rcar_gen4_pcie_basic_deinit(rcar);
> + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> +}
> +
> +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> + enum pci_epc_irq_type type,
> + u16 interrupt_num)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> +
> + switch (type) {
> + case PCI_EPC_IRQ_INTX:
> + return dw_pcie_ep_raise_intx_irq(ep, func_no);
> + case PCI_EPC_IRQ_MSI:
> + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> + default:
> + dev_err(dw->dev, "Unknown IRQ type\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> + .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
> + .align = SZ_1M,
> +};
> +
> +static const struct pci_epc_features*
> +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
> +{
> + return &rcar_gen4_pcie_epc_features;
> +}
> +
> +static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
> + u8 func_no)
> +{
> + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
> +}
> +
> +static unsigned int rcar_gen4_pcie_ep_func_conf_select2(struct dw_pcie_ep *ep,
> + u8 func_no)
> +{
> + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
> +}
> +
> +static const struct dw_pcie_ep_ops pcie_ep_ops = {
> + .ep_pre_init = rcar_gen4_pcie_ep_pre_init,
> + .ep_init = rcar_gen4_pcie_ep_init,
> + .ep_deinit = rcar_gen4_pcie_ep_deinit,
> + .raise_irq = rcar_gen4_pcie_ep_raise_irq,
> + .get_features = rcar_gen4_pcie_ep_get_features,
> + .func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
> + .func_conf_select2 = rcar_gen4_pcie_ep_func_conf_select2,
> +};
> +
> +static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar,
> + struct platform_device *pdev)
Drop this argument. rcar already has the pdev pointer.
> +{
> + struct dw_pcie_ep *ep = &rcar->dw.ep;
> + int ret;
> +
> + rcar->mode = DW_PCIE_EP_TYPE;
> + ep->ops = &pcie_ep_ops;
> +
> + ret = dw_pcie_ep_init(ep);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to initialize endpoint\n");
Even though half the DW PCIe EP LLDDs are doing the same I would have
either dropped the error printed here or converted it to
dev_err_probe(). First option is more preferable because thus your RP
and EP adding methods will turn to look similar.
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar)
> +{
> + dw_pcie_ep_exit(&rcar->dw.ep);
> +}
> +
> +static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct rcar_gen4_pcie *rcar;
> + int err;
> +
> + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> + if (!rcar)
> + return -ENOMEM;
> +
> + err = rcar_gen4_pcie_get_resources(rcar);
> + if (err < 0) {
As Mani correctly noticed the checks should be converted to "if (err)...".
> + dev_err(dev, "Failed to request resource: %d\n", err);
I would have moved this error printed to the
rcar_gen4_pcie_get_resources() method (similar fix should be in the
Root Port patch too). Thus the probe method will turn to look neat and
you'll be able to drop the dev pointer from here.
> + return err;
> + }
> +
> + err = rcar_gen4_pcie_prepare(rcar);
> + if (err < 0)
if (err) ?
> + return err;
> +
> + err = rcar_gen4_add_pcie_ep(rcar, pdev);
> + if (err < 0)
ditto
> + goto err_add;
> +
> + return 0;
> +
> +err_add:
See the comments in the patch 17/20 regarding the label name.
> + rcar_gen4_pcie_unprepare(rcar);
> +
> + return err;
> +}
> +
> +static void rcar_gen4_pcie_ep_remove(struct platform_device *pdev)
> +{
> + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> +
> + rcar_gen4_remove_pcie_ep(rcar);
> + rcar_gen4_pcie_unprepare(rcar);
> +}
> +
> +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> + { .compatible = "renesas,rcar-gen4-pcie-ep", },
> + {},
> +};
As Mani noted: missing MODULE_DEVICE_TABLE().
-Serge(y)
> +
> +static struct platform_driver rcar_gen4_pcie_ep_driver = {
> + .driver = {
> + .name = "pcie-rcar-gen4-ep",
> + .of_match_table = rcar_gen4_pcie_of_match,
> + },
> + .probe = rcar_gen4_pcie_ep_probe,
> + .remove_new = rcar_gen4_pcie_ep_remove,
> +};
> +module_platform_driver(rcar_gen4_pcie_ep_driver);
> +
> +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver");
> +MODULE_LICENSE("GPL");
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 90+ messages in thread* RE: [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support
2023-08-01 1:36 ` Serge Semin
@ 2023-08-01 6:59 ` Yoshihiro Shimoda
0 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-08-01 6:59 UTC (permalink / raw)
To: Serge Semin
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, bhelgaas@google.com,
kishon@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, marek.vasut+renesas@gmail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Hi Serge,
> From: Serge Semin, Sent: Tuesday, August 1, 2023 10:36 AM
> To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com; lpieralisi@kernel.org; robh+dt@kernel.org; kw@linux.com;
> manivannan.sadhasivam@linaro.org; bhelgaas@google.com; kishon@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; marek.vasut+renesas@gmail.com; linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-renesas-soc@vger.kernel.org
> Subject: Re: [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support
>
> On Fri, Jul 21, 2023 at 04:44:50PM +0900, Yoshihiro Shimoda wrote:
> > Add R-Car Gen4 PCIe Endpoint support. This controller is based on
> > Synopsys DesignWare PCIe.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > ---
> > drivers/pci/controller/dwc/Kconfig | 9 +
> > drivers/pci/controller/dwc/Makefile | 2 +
> > .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 189 ++++++++++++++++++
> > 3 files changed, 200 insertions(+)
> > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> >
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index 64d4d37bc891..4d877cd18374 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -424,4 +424,13 @@ config PCIE_RCAR_GEN4
> > Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs.
> > This uses the DesignWare core.
> >
> > +config PCIE_RCAR_GEN4_EP
> > + tristate "Renesas R-Car Gen4 PCIe Endpoint controller"
> > + depends on ARCH_RENESAS || COMPILE_TEST
> > + depends on PCI_ENDPOINT
> > + select PCIE_DW_EP
> > + help
> > + Say Y here if you want PCIe endpoint controller support on R-Car Gen4
> > + SoCs. This uses the DesignWare core.
> > +
> > endmenu
> > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > index 486cf706b53d..0fb0bde26ac4 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -28,6 +28,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o
> > obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o
> > +pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o
> > +obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o
> >
> > # The following drivers are for devices that use the generic ACPI
> > # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> > new file mode 100644
> > index 000000000000..3970a920f3fe
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> > @@ -0,0 +1,189 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs
> > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > + */
> > +
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "pcie-rcar-gen4.h"
> > +#include "pcie-designware.h"
> > +
> > +#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
> > +#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
> > +
> > +static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + int ret;
> > +
> > + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > + if (ret) {
> > + dev_err(dw->dev, "Failed to enable ref clocks\n");
> > + return;
> > + }
> > +
> > + rcar_gen4_pcie_basic_init(rcar);
> > +
> > + writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
> > +}
> > +
> > +static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
> > +{
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + enum pci_barno bar;
> > +
> > + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> > + dw_pcie_ep_reset_bar(pci, bar);
> > +}
> > +
> > +static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > +
> > + writel(0, rcar->base + PCIEDMAINTSTSEN);
> > + rcar_gen4_pcie_basic_deinit(rcar);
> > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > +}
> > +
> > +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > + enum pci_epc_irq_type type,
> > + u16 interrupt_num)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> > +
> > + switch (type) {
> > + case PCI_EPC_IRQ_INTX:
> > + return dw_pcie_ep_raise_intx_irq(ep, func_no);
> > + case PCI_EPC_IRQ_MSI:
> > + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > + default:
> > + dev_err(dw->dev, "Unknown IRQ type\n");
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
> > + .linkup_notifier = false,
> > + .msi_capable = true,
> > + .msix_capable = false,
> > + .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
> > + .align = SZ_1M,
> > +};
> > +
> > +static const struct pci_epc_features*
> > +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
> > +{
> > + return &rcar_gen4_pcie_epc_features;
> > +}
> > +
> > +static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
> > + u8 func_no)
> > +{
> > + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
> > +}
> > +
> > +static unsigned int rcar_gen4_pcie_ep_func_conf_select2(struct dw_pcie_ep *ep,
> > + u8 func_no)
> > +{
> > + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
> > +}
> > +
> > +static const struct dw_pcie_ep_ops pcie_ep_ops = {
> > + .ep_pre_init = rcar_gen4_pcie_ep_pre_init,
> > + .ep_init = rcar_gen4_pcie_ep_init,
> > + .ep_deinit = rcar_gen4_pcie_ep_deinit,
> > + .raise_irq = rcar_gen4_pcie_ep_raise_irq,
> > + .get_features = rcar_gen4_pcie_ep_get_features,
> > + .func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
> > + .func_conf_select2 = rcar_gen4_pcie_ep_func_conf_select2,
> > +};
> > +
> > +static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar,
>
> > + struct platform_device *pdev)
>
> Drop this argument. rcar already has the pdev pointer.
Oops. I'll fix it.
> > +{
> > + struct dw_pcie_ep *ep = &rcar->dw.ep;
> > + int ret;
> > +
> > + rcar->mode = DW_PCIE_EP_TYPE;
> > + ep->ops = &pcie_ep_ops;
> > +
> > + ret = dw_pcie_ep_init(ep);
> > + if (ret) {
>
> > + dev_err(&pdev->dev, "Failed to initialize endpoint\n");
>
> Even though half the DW PCIe EP LLDDs are doing the same I would have
> either dropped the error printed here or converted it to
> dev_err_probe(). First option is more preferable because thus your RP
> and EP adding methods will turn to look similar.
I prefer keeping dev_err_probe() here because it's possible to fail without
any error message, IIUC.
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar)
> > +{
> > + dw_pcie_ep_exit(&rcar->dw.ep);
> > +}
> > +
> > +static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct rcar_gen4_pcie *rcar;
> > + int err;
> > +
> > + rcar = rcar_gen4_pcie_devm_alloc(pdev);
> > + if (!rcar)
> > + return -ENOMEM;
> > +
> > + err = rcar_gen4_pcie_get_resources(rcar);
>
> > + if (err < 0) {
>
> As Mani correctly noticed the checks should be converted to "if (err)...".
I got it.
> > + dev_err(dev, "Failed to request resource: %d\n", err);
>
> I would have moved this error printed to the
> rcar_gen4_pcie_get_resources() method (similar fix should be in the
> Root Port patch too). Thus the probe method will turn to look neat and
> you'll be able to drop the dev pointer from here.
I got it. I'll fix them.
> > + return err;
> > + }
> > +
> > + err = rcar_gen4_pcie_prepare(rcar);
>
> > + if (err < 0)
>
> if (err) ?
>
> > + return err;
> > +
> > + err = rcar_gen4_add_pcie_ep(rcar, pdev);
>
> > + if (err < 0)
>
> ditto
I'll fix them as "if(err)"
> > + goto err_add;
> > +
> > + return 0;
> > +
>
> > +err_add:
>
> See the comments in the patch 17/20 regarding the label name.
I'll rename the label to "err_unprepare".
> > + rcar_gen4_pcie_unprepare(rcar);
> > +
> > + return err;
> > +}
> > +
> > +static void rcar_gen4_pcie_ep_remove(struct platform_device *pdev)
> > +{
> > + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
> > +
> > + rcar_gen4_remove_pcie_ep(rcar);
> > + rcar_gen4_pcie_unprepare(rcar);
> > +}
> > +
> > +static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> > + { .compatible = "renesas,rcar-gen4-pcie-ep", },
> > + {},
> > +};
>
> As Mani noted: missing MODULE_DEVICE_TABLE().
I got it.
Best regards,
Yoshihiro Shimoda
> -Serge(y)
>
> > +
> > +static struct platform_driver rcar_gen4_pcie_ep_driver = {
> > + .driver = {
> > + .name = "pcie-rcar-gen4-ep",
> > + .of_match_table = rcar_gen4_pcie_of_match,
> > + },
> > + .probe = rcar_gen4_pcie_ep_probe,
> > + .remove_new = rcar_gen4_pcie_ep_remove,
> > +};
> > +module_platform_driver(rcar_gen4_pcie_ep_driver);
> > +
> > +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver");
> > +MODULE_LICENSE("GPL");
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 90+ messages in thread
* [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (17 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 18/20] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-21 7:44 ` [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-07-24 10:53 ` [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Manivannan Sadhasivam
Update this entry for R-Car Gen4's source code.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3be1bdfe8ecc..d12ec66f5098 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16273,6 +16273,7 @@ L: linux-renesas-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/*rcar*
F: drivers/pci/controller/*rcar*
+F: drivers/pci/controller/dwc/*rcar*
PCI DRIVER FOR SAMSUNG EXYNOS
M: Jingoo Han <jingoohan1@gmail.com>
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (18 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 19/20] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
@ 2023-07-21 7:44 ` Yoshihiro Shimoda
2023-07-24 10:53 ` [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Serge Semin
20 siblings, 0 replies; 90+ messages in thread
From: Yoshihiro Shimoda @ 2023-07-21 7:44 UTC (permalink / raw)
To: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt
Cc: marek.vasut+renesas, fancer.lancer, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Manivannan Sadhasivam
Add Renesas R8A779F0 in pci_device_id table so that pci-epf-test
can be used for testing PCIe EP on R-Car S4-8.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
drivers/misc/pci_endpoint_test.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index ed4d0ef5e5c3..150083dab71a 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -81,6 +81,7 @@
#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
+#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
static DEFINE_IDA(pci_endpoint_test_ida);
@@ -990,6 +991,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
+ .driver_data = (kernel_ulong_t)&default_data,
+ },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
.driver_data = (kernel_ulong_t)&j721e_data,
},
--
2.25.1
^ permalink raw reply related [flat|nested] 90+ messages in thread* Re: [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support
2023-07-21 7:44 [PATCH v18 00/20] PCI: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (19 preceding siblings ...)
2023-07-21 7:44 ` [PATCH v18 20/20] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
@ 2023-07-24 10:53 ` Serge Semin
20 siblings, 0 replies; 90+ messages in thread
From: Serge Semin @ 2023-07-24 10:53 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: jingoohan1, gustavo.pimentel, lpieralisi, robh+dt, kw,
manivannan.sadhasivam, bhelgaas, kishon, krzysztof.kozlowski+dt,
conor+dt, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc
Hi Yoshihiro
On Fri, Jul 21, 2023 at 04:44:32PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car S4-8 (R-Car Gen4) PCIe Host and Endpoint support.
> To support them, modify PCIe DesignWare common codes.
I'll have a closer look at the series later on this week.
-Serge(y)
>
> Changes from v17:
> https://lore.kernel.org/linux-pci/20230705114206.3585188-1-yoshihiro.shimoda.uh@renesas.com/
> - Based on the latest pci.git / next branch.
> - Add comments in the commit log in the patch 01/20.
> - Drop "Implicit" from "Message Routing" in the patch 01/20.
> - Add Reviewed-by tag in the patch 0[14569]/20.
> - Fix typo in the patch 07/20.
> - Drop unnecessary description from the commit log in the patch 09/20.
> - Add clk_bulk_disable_unprepare() calling in the patch 1[78]/20.
> - Use .remove_new() in the patch 1[78]/20.
> - Add rcar_gen4_pcie_basic_deinit() and .deinit() in the patch 17/20.
> - Call rcar_gen4_pcie_basic_deinit() in .ep_deinit() in the patch 18/20.
> - Minor updates for improved code readability in the patch 1[78]/20.
>
> Changes from v16:
> https://lore.kernel.org/linux-pci/20230510062234.201499-1-yoshihiro.shimoda.uh@renesas.com/
> - Based on next-20230704.
> - Drop a patch about PCI_EXP_LNKCAP_MLW.
> - Drop a patch about PCI_HEADER_TYPE_MULTI_FUNC.
> - Update comments in the patch [01/20].
> - Drop CC-list from actual commit log in the patch [02/20].
> - Update the commit log in the patch [04/20].
> - Remove unnecessary bit setting in the patch [05/20].
> - (New) Add .func_conf_select2() ops for multiple PFs support in the patch [07/20].
> - Modify dw_pcie_link_set_max_link_width() refactoring in the patch [08/20].
> - Use FIELD_PREP() to improve code readability in the patch [09/20].
> - Add Reviewed-by in the patch [1[02]/20] (Thanks, Serge!).
> - Minor fix of the commit log in the patch [11/20].
> - Add clock-names property in the patch [1[56]/20].
> - Add max-functions property in the patch [16/20].
> - Drop unnecessary dw_pcie_dbi_ro_wr_en() in the patch [17/20].
> - Modify .stark_link() handling in the patch [17/20].
> - Change function name of rcar_gen4_pcie_set_device_type() in the patch [17/20].
> - Modify reset/clock handling in the patch [17/20].
> - Add enum dw_pcie_device_mode handling in the patch [17/20].
> - Drop single-function setting in the patch [18/20].
> - Add multi PFs support in the patch [18/20].
> - Fix .reserved_bar value in the patch [18/20].
>
> Yoshihiro Shimoda (20):
> PCI: Add INTx Mechanism Messages macros
> PCI: Rename PCI_EPC_IRQ_LEGACY to PCI_EPC_IRQ_INTX
> PCI: dwc: Rename "legacy_irq" to "INTx_irq"
> PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
> PCI: dwc: Add outbound MSG TLPs support
> PCI: designware-ep: Add INTx IRQs support
> PCI: dwc: endpoint: Add multiple PFs support for dbi2
> PCI: dwc: Add dw_pcie_link_set_max_link_width()
> PCI: dwc: Add PCI_EXP_LNKCAP_MLW handling
> PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting.
> PCI: dwc: Add EDMA_UNROLL capability flag
> PCI: dwc: Expose dw_pcie_ep_exit() to module
> PCI: dwc: Introduce .ep_pre_init() and .ep_deinit()
> dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
> dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
> dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
> PCI: rcar-gen4: Add R-Car Gen4 PCIe Host support
> PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support
> MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
> misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
>
> .../bindings/pci/rcar-gen4-pci-ep.yaml | 106 ++++++++++
> .../bindings/pci/rcar-gen4-pci-host.yaml | 123 +++++++++++
> .../bindings/pci/snps,dw-pcie-ep.yaml | 4 +-
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +-
> MAINTAINERS | 1 +
> drivers/misc/pci_endpoint_test.c | 4 +
> .../pci/controller/cadence/pcie-cadence-ep.c | 2 +-
> drivers/pci/controller/dwc/Kconfig | 18 ++
> drivers/pci/controller/dwc/Makefile | 4 +
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> drivers/pci/controller/dwc/pci-imx6.c | 4 +-
> drivers/pci/controller/dwc/pci-keystone.c | 2 +-
> .../pci/controller/dwc/pci-layerscape-ep.c | 4 +-
> drivers/pci/controller/dwc/pcie-artpec6.c | 2 +-
> .../pci/controller/dwc/pcie-designware-ep.c | 133 ++++++++++--
> .../pci/controller/dwc/pcie-designware-host.c | 52 +++--
> .../pci/controller/dwc/pcie-designware-plat.c | 4 +-
> drivers/pci/controller/dwc/pcie-designware.c | 155 +++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 35 ++-
> drivers/pci/controller/dwc/pcie-keembay.c | 2 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +-
> .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 189 +++++++++++++++++
> .../pci/controller/dwc/pcie-rcar-gen4-host.c | 149 +++++++++++++
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 200 ++++++++++++++++++
> drivers/pci/controller/dwc/pcie-rcar-gen4.h | 44 ++++
> drivers/pci/controller/dwc/pcie-tegra194.c | 8 +-
> drivers/pci/controller/dwc/pcie-uniphier-ep.c | 2 +-
> drivers/pci/controller/pcie-rcar-ep.c | 2 +-
> drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
> drivers/pci/endpoint/functions/pci-epf-test.c | 10 +-
> drivers/pci/pci.h | 18 ++
> include/linux/pci-epc.h | 4 +-
> 32 files changed, 1134 insertions(+), 159 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-host.c
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.h
>
> --
> 2.25.1
>
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