Re: [PATCH 4/5] cxl/type3: add an optional mhd validation function for memory accesses

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Thu, 31 Aug 2023 21:29:13 -0400
Gregory Price <gourry.memverge@gmail.com> wrote:

> When memory accesses are made, some MHSLD's would validate the address
> is within the scope of allocated sections.  To do this, the base device
> must call an optional function set by inherited devices.
> 
> Signed-off-by: Gregory Price <gregory.price@memverge.com>

This sort of callback addition can be done via class initialization.
E.g. get_lsa_size()
https://elixir.bootlin.com/qemu/latest/source/hw/mem/cxl_type3.c#L1494
as the callback is the same for all instances of the class which
in next patch is CXLNiagraClass where you already set the
PCIClass callbacks in cxl_niagara_class_init()

You can then use something like:
CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d);
cvc->mhd_access_valid(ct3d, dpa_offset, size);

Jonathan

> ---
>  hw/mem/cxl_type3.c          | 15 +++++++++++++++
>  include/hw/cxl/cxl_device.h |  3 +++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index a8d4a12f3e..8e1565f2fc 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1034,6 +1034,10 @@ void ct3_realize(PCIDevice *pci_dev, Error **errp)
>              goto err_release_cdat;
>          }
>      }
> +
> +    /* Devices which inherit ct3d should initialize these after ct3_realize */
> +    ct3d->mhd_access_valid = NULL;
> +
>      return;
>  
>  err_release_cdat:
> @@ -1259,6 +1263,11 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
>          return MEMTX_ERROR;
>      }
>  
> +    if (ct3d->mhd_access_valid &&
> +        !ct3d->mhd_access_valid(d, dpa_offset, size)) {
> +        return MEMTX_ERROR;
> +    }
> +
>      if (sanitize_running(&ct3d->cci)) {
>          qemu_guest_getrandom_nofail(data, size);
>          return MEMTX_OK;
> @@ -1279,6 +1288,12 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
>      if (res) {
>          return MEMTX_ERROR;
>      }
> +
> +    if (ct3d->mhd_access_valid &&
> +        !ct3d->mhd_access_valid(d, dpa_offset, size)) {
> +        return MEMTX_ERROR;
> +    }
> +
>      if (sanitize_running(&ct3d->cci)) {
>          return MEMTX_OK;
>      }
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 4ad38b689c..b1b39a9aa0 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -489,6 +489,9 @@ struct CXLType3Dev {
>          uint8_t num_regions; /* 0-8 regions */
>          CXLDCDRegion regions[DCD_MAX_REGION_NUM];
>      } dc;
> +
> +    /* Multi-headed Device */
> +    bool (*mhd_access_valid)(PCIDevice *d, uint64_t addr, unsigned int size);
>  };
>  
>  #define TYPE_CXL_TYPE3 "cxl-type3"