From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
Richard Weinberger <richard@nod.at>,
intel-gfx@lists.freedesktop.org, Michael Walle <michael@walle.cc>,
linux-spi@vger.kernel.org,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Vitaly Lubart <vitaly.lubart@intel.com>,
Pratyush Yadav <pratyush@kernel.org>
Subject: Re: [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Mon, 11 Sep 2023 09:42:33 +0200 [thread overview]
Message-ID: <20230911094233.326fd936@xps-13> (raw)
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
Hi Alexander,
+ Mark Brown + spi list
+ spi-nor maintainers
alexander.usyskin@intel.com wrote on Sun, 10 Sep 2023 15:39:39 +0300:
> Add driver for access to the discrete graphics card
> internal SPI device.
> Expose device on auxiliary bus and provide driver to register
> this device with MTD framework.
Maybe you can explain why you think auxiliary bus is relevant here? The
cover letter might maybe be a bit more verbose to give us more context?
I've looked at the series, it looks like you try to expose a spi
memory connected to a spi controller on your hardware. We usually
expect the spi controller driver to register in the spi core and
provide spi-mem operations for that.
I don't know if this memory is supposed to be used as general purpose,
but if it's not I would advise to use some kind of firmware mechanism
instead. Also, what is the purpose of exposing this content in this
case?
Well, I'm partially convinced here, I would like to hear from the other
maintainers, maybe your choices are legitimate and I'm off topic.
Thanks,
Miquèl
> This series is intended to be upstreamed through drm tree.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
>
>
> Alexander Usyskin (3):
> drm/i915/spi: align 64bit read and write
> drm/i915/spi: wake card on operations
> drm/i915/spi: add support for access mode
>
> Jani Nikula (1):
> drm/i915/spi: add spi device for discrete graphics
>
> Tomas Winkler (6):
> drm/i915/spi: add intel_spi_region map
> drm/i915/spi: add driver for on-die spi device
> drm/i915/spi: implement region enumeration
> drm/i915/spi: implement spi access functions
> drm/i915/spi: spi register with mtd
> drm/i915/spi: mtd: implement access handlers
>
> drivers/gpu/drm/i915/Kconfig | 1 +
> drivers/gpu/drm/i915/Makefile | 6 +
> drivers/gpu/drm/i915/i915_driver.c | 7 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/spi/intel_spi.c | 101 +++
> drivers/gpu/drm/i915/spi/intel_spi.h | 33 +
> drivers/gpu/drm/i915/spi/intel_spi_drv.c | 865 +++++++++++++++++++++++
> 8 files changed, 1018 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi_drv.c
Thanks,
Miquèl
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Vitaly Lubart <vitaly.lubart@intel.com>,
linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org,
Mark Brown <broonie@kernel.org>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
linux-spi@vger.kernel.org
Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Mon, 11 Sep 2023 09:42:33 +0200 [thread overview]
Message-ID: <20230911094233.326fd936@xps-13> (raw)
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
Hi Alexander,
+ Mark Brown + spi list
+ spi-nor maintainers
alexander.usyskin@intel.com wrote on Sun, 10 Sep 2023 15:39:39 +0300:
> Add driver for access to the discrete graphics card
> internal SPI device.
> Expose device on auxiliary bus and provide driver to register
> this device with MTD framework.
Maybe you can explain why you think auxiliary bus is relevant here? The
cover letter might maybe be a bit more verbose to give us more context?
I've looked at the series, it looks like you try to expose a spi
memory connected to a spi controller on your hardware. We usually
expect the spi controller driver to register in the spi core and
provide spi-mem operations for that.
I don't know if this memory is supposed to be used as general purpose,
but if it's not I would advise to use some kind of firmware mechanism
instead. Also, what is the purpose of exposing this content in this
case?
Well, I'm partially convinced here, I would like to hear from the other
maintainers, maybe your choices are legitimate and I'm off topic.
Thanks,
Miquèl
> This series is intended to be upstreamed through drm tree.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
>
>
> Alexander Usyskin (3):
> drm/i915/spi: align 64bit read and write
> drm/i915/spi: wake card on operations
> drm/i915/spi: add support for access mode
>
> Jani Nikula (1):
> drm/i915/spi: add spi device for discrete graphics
>
> Tomas Winkler (6):
> drm/i915/spi: add intel_spi_region map
> drm/i915/spi: add driver for on-die spi device
> drm/i915/spi: implement region enumeration
> drm/i915/spi: implement spi access functions
> drm/i915/spi: spi register with mtd
> drm/i915/spi: mtd: implement access handlers
>
> drivers/gpu/drm/i915/Kconfig | 1 +
> drivers/gpu/drm/i915/Makefile | 6 +
> drivers/gpu/drm/i915/i915_driver.c | 7 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/spi/intel_spi.c | 101 +++
> drivers/gpu/drm/i915/spi/intel_spi.h | 33 +
> drivers/gpu/drm/i915/spi/intel_spi_drv.c | 865 +++++++++++++++++++++++
> 8 files changed, 1018 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi_drv.c
Thanks,
Miquèl
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Vitaly Lubart <vitaly.lubart@intel.com>,
linux-mtd@lists.infradead.org, intel-gfx@lists.freedesktop.org,
Mark Brown <broonie@kernel.org>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <michael@walle.cc>,
linux-spi@vger.kernel.org
Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Mon, 11 Sep 2023 09:42:33 +0200 [thread overview]
Message-ID: <20230911094233.326fd936@xps-13> (raw)
In-Reply-To: <20230910123949.1251964-1-alexander.usyskin@intel.com>
Hi Alexander,
+ Mark Brown + spi list
+ spi-nor maintainers
alexander.usyskin@intel.com wrote on Sun, 10 Sep 2023 15:39:39 +0300:
> Add driver for access to the discrete graphics card
> internal SPI device.
> Expose device on auxiliary bus and provide driver to register
> this device with MTD framework.
Maybe you can explain why you think auxiliary bus is relevant here? The
cover letter might maybe be a bit more verbose to give us more context?
I've looked at the series, it looks like you try to expose a spi
memory connected to a spi controller on your hardware. We usually
expect the spi controller driver to register in the spi core and
provide spi-mem operations for that.
I don't know if this memory is supposed to be used as general purpose,
but if it's not I would advise to use some kind of firmware mechanism
instead. Also, what is the purpose of exposing this content in this
case?
Well, I'm partially convinced here, I would like to hear from the other
maintainers, maybe your choices are legitimate and I'm off topic.
Thanks,
Miquèl
> This series is intended to be upstreamed through drm tree.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
>
>
> Alexander Usyskin (3):
> drm/i915/spi: align 64bit read and write
> drm/i915/spi: wake card on operations
> drm/i915/spi: add support for access mode
>
> Jani Nikula (1):
> drm/i915/spi: add spi device for discrete graphics
>
> Tomas Winkler (6):
> drm/i915/spi: add intel_spi_region map
> drm/i915/spi: add driver for on-die spi device
> drm/i915/spi: implement region enumeration
> drm/i915/spi: implement spi access functions
> drm/i915/spi: spi register with mtd
> drm/i915/spi: mtd: implement access handlers
>
> drivers/gpu/drm/i915/Kconfig | 1 +
> drivers/gpu/drm/i915/Makefile | 6 +
> drivers/gpu/drm/i915/i915_driver.c | 7 +
> drivers/gpu/drm/i915/i915_drv.h | 4 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/spi/intel_spi.c | 101 +++
> drivers/gpu/drm/i915/spi/intel_spi.h | 33 +
> drivers/gpu/drm/i915/spi/intel_spi_drv.c | 865 +++++++++++++++++++++++
> 8 files changed, 1018 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.c
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi.h
> create mode 100644 drivers/gpu/drm/i915/spi/intel_spi_drv.c
Thanks,
Miquèl
next prev parent reply other threads:[~2023-09-11 12:34 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-10 12:39 [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 01/10] drm/i915/spi: add spi device " Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-11 15:41 ` [Intel-gfx] " Jani Nikula
2023-09-11 15:41 ` Jani Nikula
2023-09-12 10:47 ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 10:47 ` Usyskin, Alexander
2023-09-10 12:39 ` [Intel-gfx] [PATCH 02/10] drm/i915/spi: add intel_spi_region map Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 03/10] drm/i915/spi: add driver for on-die spi device Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 04/10] drm/i915/spi: implement region enumeration Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 05/10] drm/i915/spi: implement spi access functions Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-10-16 8:39 ` [Intel-gfx] " Miquel Raynal
2023-10-16 8:39 ` Miquel Raynal
2023-10-17 11:54 ` [Intel-gfx] " Usyskin, Alexander
2023-10-17 11:54 ` Usyskin, Alexander
2023-10-17 13:55 ` [Intel-gfx] " Miquel Raynal
2023-10-17 13:55 ` Miquel Raynal
2023-10-17 14:20 ` [Intel-gfx] " Usyskin, Alexander
2023-10-17 14:20 ` Usyskin, Alexander
2023-10-17 14:46 ` [Intel-gfx] " Miquel Raynal
2023-10-17 14:46 ` Miquel Raynal
2023-11-14 8:47 ` [Intel-gfx] " Usyskin, Alexander
2023-11-14 8:47 ` Usyskin, Alexander
2023-11-14 9:13 ` [Intel-gfx] " Miquel Raynal
2023-11-14 9:13 ` Miquel Raynal
2024-02-14 12:16 ` Usyskin, Alexander
2024-02-14 12:16 ` Usyskin, Alexander
2024-02-19 9:09 ` Miquel Raynal
2024-02-19 9:09 ` Miquel Raynal
2023-09-10 12:39 ` [Intel-gfx] [PATCH 07/10] drm/i915/spi: mtd: implement access handlers Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 08/10] drm/i915/spi: align 64bit read and write Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 09/10] drm/i915/spi: wake card on operations Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 10/10] drm/i915/spi: add support for access mode Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/spi: spi access for discrete graphics Patchwork
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-11 7:42 ` Miquel Raynal [this message]
2023-09-11 7:42 ` [PATCH 00/10] " Miquel Raynal
2023-09-11 7:42 ` Miquel Raynal
2023-09-12 10:50 ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 10:50 ` Usyskin, Alexander
2023-09-12 10:50 ` Usyskin, Alexander
2023-09-12 12:14 ` [Intel-gfx] " Mark Brown
2023-09-12 12:14 ` Mark Brown
2023-09-12 12:14 ` Mark Brown
2023-09-12 13:15 ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 13:15 ` Usyskin, Alexander
2023-09-12 13:15 ` Usyskin, Alexander
2023-09-12 13:21 ` [Intel-gfx] " Miquel Raynal
2023-09-12 13:21 ` Miquel Raynal
2023-09-12 13:21 ` Miquel Raynal
2023-09-12 13:36 ` [Intel-gfx] " Mark Brown
2023-09-12 13:36 ` Mark Brown
2023-09-12 13:36 ` Mark Brown
2023-09-20 13:52 ` [Intel-gfx] " Usyskin, Alexander
2023-09-20 13:52 ` Usyskin, Alexander
2023-09-20 13:52 ` Usyskin, Alexander
2023-09-20 15:54 ` [Intel-gfx] " Mark Brown
2023-09-20 15:54 ` Mark Brown
2023-09-20 15:54 ` Mark Brown
2023-09-20 21:00 ` [Intel-gfx] " Winkler, Tomas
2023-09-20 21:00 ` Winkler, Tomas
2023-09-20 21:00 ` Winkler, Tomas
2023-09-21 11:29 ` [Intel-gfx] " Mark Brown
2023-09-21 11:29 ` Mark Brown
2023-09-21 11:29 ` Mark Brown
2023-09-27 14:11 ` [Intel-gfx] " Usyskin, Alexander
2023-09-27 14:11 ` Usyskin, Alexander
2023-09-27 14:11 ` Usyskin, Alexander
2023-09-27 14:37 ` [Intel-gfx] " Mark Brown
2023-09-27 14:37 ` Mark Brown
2023-09-27 14:37 ` Mark Brown
2023-09-27 14:54 ` [Intel-gfx] " Miquel Raynal
2023-09-27 14:54 ` Miquel Raynal
2023-09-27 14:54 ` Miquel Raynal
2023-09-28 6:33 ` [Intel-gfx] " Usyskin, Alexander
2023-09-28 6:33 ` Usyskin, Alexander
2023-09-28 6:33 ` Usyskin, Alexander
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