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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
	Richard Weinberger <richard@nod.at>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Usyskin, Alexander" <alexander.usyskin@intel.com>,
	Michael Walle <michael@walle.cc>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	"Winkler, Tomas" <tomas.winkler@intel.com>,
	"Lubart, Vitaly" <vitaly.lubart@intel.com>,
	Pratyush Yadav <pratyush@kernel.org>
Subject: Re: [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Wed, 27 Sep 2023 16:54:38 +0200	[thread overview]
Message-ID: <20230927165350.470bea0f@xps-13> (raw)
In-Reply-To: <ZRQ+LzIoD+J0BzVp@finisterre.sirena.org.uk>

Hi Mark,

broonie@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200:

> On Wed, Sep 27, 2023 at 02:11:47PM +0000, Usyskin, Alexander wrote:
> 
> > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > The embedded SPI is not visible to OS.
> > There is another HW in the chip that gates access to the controller and
> > exposes registers for:
> > region select; read and write (4 and 8 bytes); erase (4K); error register;   
> 
> So assuming that's flash region select it sounds like this is a MTD
> controller and the fact that there's SPI isn't really relevant at all
> from a programming model point of view and it should probably be
> described as a MTD controller of some kind.  Does that sound about
> right?

Yeah in this case it seems the best option if the OS only has access to
a very small subset of what the spi controller can do.

Thanks,
Miquèl

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: "Usyskin, Alexander" <alexander.usyskin@intel.com>,
	"Winkler, Tomas" <tomas.winkler@intel.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	"Lubart, Vitaly" <vitaly.lubart@intel.com>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Pratyush Yadav <pratyush@kernel.org>,
	Michael Walle <michael@walle.cc>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>
Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Wed, 27 Sep 2023 16:54:38 +0200	[thread overview]
Message-ID: <20230927165350.470bea0f@xps-13> (raw)
In-Reply-To: <ZRQ+LzIoD+J0BzVp@finisterre.sirena.org.uk>

Hi Mark,

broonie@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200:

> On Wed, Sep 27, 2023 at 02:11:47PM +0000, Usyskin, Alexander wrote:
> 
> > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > The embedded SPI is not visible to OS.
> > There is another HW in the chip that gates access to the controller and
> > exposes registers for:
> > region select; read and write (4 and 8 bytes); erase (4K); error register;   
> 
> So assuming that's flash region select it sounds like this is a MTD
> controller and the fact that there's SPI isn't really relevant at all
> from a programming model point of view and it should probably be
> described as a MTD controller of some kind.  Does that sound about
> right?

Yeah in this case it seems the best option if the OS only has access to
a very small subset of what the spi controller can do.

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>
Cc: "Usyskin, Alexander" <alexander.usyskin@intel.com>,
	"Winkler, Tomas" <tomas.winkler@intel.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	"Lubart, Vitaly" <vitaly.lubart@intel.com>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Pratyush Yadav <pratyush@kernel.org>,
	Michael Walle <michael@walle.cc>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>
Subject: Re: [PATCH 00/10] drm/i915/spi: spi access for discrete graphics
Date: Wed, 27 Sep 2023 16:54:38 +0200	[thread overview]
Message-ID: <20230927165350.470bea0f@xps-13> (raw)
In-Reply-To: <ZRQ+LzIoD+J0BzVp@finisterre.sirena.org.uk>

Hi Mark,

broonie@kernel.org wrote on Wed, 27 Sep 2023 16:37:35 +0200:

> On Wed, Sep 27, 2023 at 02:11:47PM +0000, Usyskin, Alexander wrote:
> 
> > There is a Discreet Graphic device with embedded SPI (controller & flash).
> > The embedded SPI is not visible to OS.
> > There is another HW in the chip that gates access to the controller and
> > exposes registers for:
> > region select; read and write (4 and 8 bytes); erase (4K); error register;   
> 
> So assuming that's flash region select it sounds like this is a MTD
> controller and the fact that there's SPI isn't really relevant at all
> from a programming model point of view and it should probably be
> described as a MTD controller of some kind.  Does that sound about
> right?

Yeah in this case it seems the best option if the OS only has access to
a very small subset of what the spi controller can do.

Thanks,
Miquèl

  reply	other threads:[~2023-09-27 14:54 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-10 12:39 [Intel-gfx] [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Alexander Usyskin
2023-09-10 12:39 ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 01/10] drm/i915/spi: add spi device " Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-11 15:41   ` [Intel-gfx] " Jani Nikula
2023-09-11 15:41     ` Jani Nikula
2023-09-12 10:47     ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 10:47       ` Usyskin, Alexander
2023-09-10 12:39 ` [Intel-gfx] [PATCH 02/10] drm/i915/spi: add intel_spi_region map Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 03/10] drm/i915/spi: add driver for on-die spi device Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 04/10] drm/i915/spi: implement region enumeration Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 05/10] drm/i915/spi: implement spi access functions Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-10-16  8:39   ` [Intel-gfx] " Miquel Raynal
2023-10-16  8:39     ` Miquel Raynal
2023-10-17 11:54     ` [Intel-gfx] " Usyskin, Alexander
2023-10-17 11:54       ` Usyskin, Alexander
2023-10-17 13:55       ` [Intel-gfx] " Miquel Raynal
2023-10-17 13:55         ` Miquel Raynal
2023-10-17 14:20         ` [Intel-gfx] " Usyskin, Alexander
2023-10-17 14:20           ` Usyskin, Alexander
2023-10-17 14:46           ` [Intel-gfx] " Miquel Raynal
2023-10-17 14:46             ` Miquel Raynal
2023-11-14  8:47             ` [Intel-gfx] " Usyskin, Alexander
2023-11-14  8:47               ` Usyskin, Alexander
2023-11-14  9:13               ` [Intel-gfx] " Miquel Raynal
2023-11-14  9:13                 ` Miquel Raynal
2024-02-14 12:16                 ` Usyskin, Alexander
2024-02-14 12:16                   ` Usyskin, Alexander
2024-02-19  9:09                   ` Miquel Raynal
2024-02-19  9:09                     ` Miquel Raynal
2023-09-10 12:39 ` [Intel-gfx] [PATCH 07/10] drm/i915/spi: mtd: implement access handlers Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 08/10] drm/i915/spi: align 64bit read and write Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 09/10] drm/i915/spi: wake card on operations Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 12:39 ` [Intel-gfx] [PATCH 10/10] drm/i915/spi: add support for access mode Alexander Usyskin
2023-09-10 12:39   ` Alexander Usyskin
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/spi: spi access for discrete graphics Patchwork
2023-09-10 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-11  7:42 ` [Intel-gfx] [PATCH 00/10] " Miquel Raynal
2023-09-11  7:42   ` Miquel Raynal
2023-09-11  7:42   ` Miquel Raynal
2023-09-12 10:50   ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 10:50     ` Usyskin, Alexander
2023-09-12 10:50     ` Usyskin, Alexander
2023-09-12 12:14     ` [Intel-gfx] " Mark Brown
2023-09-12 12:14       ` Mark Brown
2023-09-12 12:14       ` Mark Brown
2023-09-12 13:15       ` [Intel-gfx] " Usyskin, Alexander
2023-09-12 13:15         ` Usyskin, Alexander
2023-09-12 13:15         ` Usyskin, Alexander
2023-09-12 13:21         ` [Intel-gfx] " Miquel Raynal
2023-09-12 13:21           ` Miquel Raynal
2023-09-12 13:21           ` Miquel Raynal
2023-09-12 13:36           ` [Intel-gfx] " Mark Brown
2023-09-12 13:36             ` Mark Brown
2023-09-12 13:36             ` Mark Brown
2023-09-20 13:52             ` [Intel-gfx] " Usyskin, Alexander
2023-09-20 13:52               ` Usyskin, Alexander
2023-09-20 13:52               ` Usyskin, Alexander
2023-09-20 15:54               ` [Intel-gfx] " Mark Brown
2023-09-20 15:54                 ` Mark Brown
2023-09-20 15:54                 ` Mark Brown
2023-09-20 21:00                 ` [Intel-gfx] " Winkler, Tomas
2023-09-20 21:00                   ` Winkler, Tomas
2023-09-20 21:00                   ` Winkler, Tomas
2023-09-21 11:29                   ` [Intel-gfx] " Mark Brown
2023-09-21 11:29                     ` Mark Brown
2023-09-21 11:29                     ` Mark Brown
2023-09-27 14:11                     ` [Intel-gfx] " Usyskin, Alexander
2023-09-27 14:11                       ` Usyskin, Alexander
2023-09-27 14:11                       ` Usyskin, Alexander
2023-09-27 14:37                       ` [Intel-gfx] " Mark Brown
2023-09-27 14:37                         ` Mark Brown
2023-09-27 14:37                         ` Mark Brown
2023-09-27 14:54                         ` Miquel Raynal [this message]
2023-09-27 14:54                           ` Miquel Raynal
2023-09-27 14:54                           ` Miquel Raynal
2023-09-28  6:33                           ` [Intel-gfx] " Usyskin, Alexander
2023-09-28  6:33                             ` Usyskin, Alexander
2023-09-28  6:33                             ` Usyskin, Alexander

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