From: Conor Dooley <conor@kernel.org>
To: Inochi Amaoto <inochiama@outlook.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com,
evicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
guoren@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, robh+dt@kernel.org,
xiaoguang.xing@sophgo.com, Chen Wang <wangchen20@iscas.ac.cn>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
Date: Fri, 22 Sep 2023 08:43:29 +0100 [thread overview]
Message-ID: <20230922-thumb-galvanize-bef393a1bda4@spud> (raw)
In-Reply-To: <IA1PR20MB4953D983915AD8E35FD3E51FBBFFA@IA1PR20MB4953.namprd20.prod.outlook.com>
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On Fri, Sep 22, 2023 at 01:16:35PM +0800, Inochi Amaoto wrote:
> >> The SiFive CLINT has flexibility related limitations which makes it
> >> not useful for multi-socket and mult-die systems. The SiFive CLINT
> >> is also not useful for systems with AIA because with AIA M-mode has
> >> a new way of doing M-mode IPIs. Due to this reasons, the RISC-V
> >> ACLINT spec breaks down traditional SiFive CLINT into two separate
> >> devices namely mtimer and mswi. This allows platforms to implement
> >> only the required set of devices. The mtimer as defined by the ACLINT
> >> specifications also allows platforms to place mtime and mtimecmp
> >> registers at different locations.
> >>
> >> Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >>
> >> We need a separate DT bindings document for ACLINT MTIMER
> >> and ACLINT MSWI because these are separate devices. The
> >> Sophgo sg2042 SoC should add their implementation specific
> >> compatible strings in this document.
> >
> >If the spec isn't frozen, I'm not accepting a binding for the "generic"
> >version of it. Bindings for this specific implemtnation are okay.
> >For sure though, squeezing this into the sifive,plic binding isn't
> >appropriate.
> >
>
> It seems I have missed a point. I wonder whether it is better to add a
> "aclint" binding firstly and then add sg2042 to it, or just use sg2042
> specific binding?
sg2042 specific, being frozen is a requirement for merging patches
related to RVI specifications.
> If use "aclint" binding, I wonder it is OK to add
> thead quirks as compatible specific properties, or left this to the SBI to
> handle? e.g. T-HEAD timer is not 64bit timer, and we should identify this.
The compatible string alone should be sufficient to identify the width
of the timer etc.
Thanks,
Conor.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Inochi Amaoto <inochiama@outlook.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com,
evicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
guoren@kernel.org, jszhang@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, robh+dt@kernel.org,
xiaoguang.xing@sophgo.com, Chen Wang <wangchen20@iscas.ac.cn>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
Date: Fri, 22 Sep 2023 08:43:29 +0100 [thread overview]
Message-ID: <20230922-thumb-galvanize-bef393a1bda4@spud> (raw)
In-Reply-To: <IA1PR20MB4953D983915AD8E35FD3E51FBBFFA@IA1PR20MB4953.namprd20.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 1857 bytes --]
On Fri, Sep 22, 2023 at 01:16:35PM +0800, Inochi Amaoto wrote:
> >> The SiFive CLINT has flexibility related limitations which makes it
> >> not useful for multi-socket and mult-die systems. The SiFive CLINT
> >> is also not useful for systems with AIA because with AIA M-mode has
> >> a new way of doing M-mode IPIs. Due to this reasons, the RISC-V
> >> ACLINT spec breaks down traditional SiFive CLINT into two separate
> >> devices namely mtimer and mswi. This allows platforms to implement
> >> only the required set of devices. The mtimer as defined by the ACLINT
> >> specifications also allows platforms to place mtime and mtimecmp
> >> registers at different locations.
> >>
> >> Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >>
> >> We need a separate DT bindings document for ACLINT MTIMER
> >> and ACLINT MSWI because these are separate devices. The
> >> Sophgo sg2042 SoC should add their implementation specific
> >> compatible strings in this document.
> >
> >If the spec isn't frozen, I'm not accepting a binding for the "generic"
> >version of it. Bindings for this specific implemtnation are okay.
> >For sure though, squeezing this into the sifive,plic binding isn't
> >appropriate.
> >
>
> It seems I have missed a point. I wonder whether it is better to add a
> "aclint" binding firstly and then add sg2042 to it, or just use sg2042
> specific binding?
sg2042 specific, being frozen is a requirement for merging patches
related to RVI specifications.
> If use "aclint" binding, I wonder it is OK to add
> thead quirks as compatible specific properties, or left this to the SBI to
> handle? e.g. T-HEAD timer is not 64bit timer, and we should identify this.
The compatible string alone should be sufficient to identify the width
of the timer etc.
Thanks,
Conor.
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next prev parent reply other threads:[~2023-09-22 7:43 UTC|newest]
Thread overview: 176+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-20 6:33 [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-09-20 6:33 ` Chen Wang
2023-09-20 6:34 ` [PATCH v2 01/11] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
2023-09-20 6:34 ` Chen Wang
2023-09-20 7:34 ` Guo Ren
2023-09-20 7:34 ` Guo Ren
2023-09-20 8:21 ` Conor Dooley
2023-09-20 8:21 ` Conor Dooley
2023-09-20 6:37 ` [PATCH v2 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Chen Wang
2023-09-20 6:37 ` Chen Wang
2023-09-20 7:38 ` Guo Ren
2023-09-20 7:38 ` Guo Ren
2023-09-20 8:22 ` Conor Dooley
2023-09-20 8:22 ` Conor Dooley
2023-09-20 9:14 ` Chen Wang
2023-09-20 9:14 ` Chen Wang
2023-09-20 6:37 ` [PATCH v2 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Chen Wang
2023-09-20 6:37 ` Chen Wang
2023-09-20 7:43 ` Guo Ren
2023-09-20 7:43 ` Guo Ren
2023-09-20 8:28 ` Conor Dooley
2023-09-20 8:28 ` Conor Dooley
2023-09-21 10:21 ` Chen Wang
2023-09-21 10:21 ` Chen Wang
2023-09-21 12:18 ` Conor Dooley
2023-09-21 12:18 ` Conor Dooley
2023-09-21 13:40 ` Chen Wang
2023-09-21 13:40 ` Chen Wang
2023-09-21 13:51 ` Chen Wang
2023-09-21 13:51 ` Chen Wang
2023-09-21 14:00 ` Conor Dooley
2023-09-21 14:00 ` Conor Dooley
2023-09-22 1:48 ` Chen Wang
2023-09-22 1:48 ` Chen Wang
2023-09-20 11:55 ` Krzysztof Kozlowski
2023-09-20 11:55 ` Krzysztof Kozlowski
2023-09-20 12:03 ` 汪辰
2023-09-20 12:03 ` 汪辰
2023-09-21 0:48 ` Jisheng Zhang
2023-09-21 0:48 ` Jisheng Zhang
2023-09-20 6:38 ` [PATCH v2 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Chen Wang
2023-09-20 6:38 ` Chen Wang
2023-09-20 7:44 ` Guo Ren
2023-09-20 7:44 ` Guo Ren
2023-09-20 8:37 ` Conor Dooley
2023-09-20 8:37 ` Conor Dooley
2023-09-20 6:39 ` [PATCH v2 05/11] dt-bindings: interrupt-controller: Add SOPHGO's SG2042 PLIC Chen Wang
2023-09-20 6:39 ` Chen Wang
2023-09-20 7:45 ` Guo Ren
2023-09-20 7:45 ` Guo Ren
2023-09-20 8:57 ` Conor Dooley
2023-09-20 8:57 ` Conor Dooley
2023-09-20 6:39 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Chen Wang
2023-09-20 6:39 ` Chen Wang
2023-09-20 8:12 ` Guo Ren
2023-09-20 8:12 ` Guo Ren
2023-09-20 8:50 ` Conor Dooley
2023-09-20 8:50 ` Conor Dooley
2023-09-20 9:08 ` Inochi Amaoto
2023-09-20 9:08 ` Inochi Amaoto
2023-09-20 9:53 ` Conor Dooley
2023-09-20 9:53 ` Conor Dooley
2023-09-20 11:24 ` Inochi Amaoto
2023-09-20 11:24 ` Inochi Amaoto
2023-09-20 13:03 ` Conor Dooley
2023-09-20 13:03 ` Conor Dooley
2023-09-21 0:43 ` Inochi Amaoto
2023-09-21 0:43 ` Inochi Amaoto
2023-09-21 8:05 ` Conor Dooley
2023-09-21 8:05 ` Conor Dooley
2023-09-21 8:18 ` Inochi Amaoto
2023-09-21 8:18 ` Inochi Amaoto
2023-09-21 8:52 ` Conor Dooley
2023-09-21 8:52 ` Conor Dooley
2023-09-21 9:44 ` Inochi Amaoto
2023-09-21 9:44 ` Inochi Amaoto
2023-09-20 11:57 ` Krzysztof Kozlowski
2023-09-20 11:57 ` Krzysztof Kozlowski
2023-09-20 12:15 ` Inochi Amaoto
2023-09-20 12:15 ` Inochi Amaoto
2023-09-20 12:30 ` Krzysztof Kozlowski
2023-09-20 12:30 ` Krzysztof Kozlowski
2023-09-20 12:40 ` Inochi Amaoto
2023-09-20 12:40 ` Inochi Amaoto
2023-09-20 12:58 ` Conor Dooley
2023-09-20 12:58 ` Conor Dooley
2023-09-20 13:09 ` Krzysztof Kozlowski
2023-09-20 13:09 ` Krzysztof Kozlowski
2023-09-20 14:38 ` Anup Patel
2023-09-20 14:38 ` Anup Patel
2023-09-20 14:51 ` Conor Dooley
2023-09-20 14:51 ` Conor Dooley
2023-09-20 22:20 ` Inochi Amaoto
2023-09-20 22:20 ` Inochi Amaoto
2023-09-22 5:16 ` Inochi Amaoto
2023-09-22 5:16 ` Inochi Amaoto
2023-09-22 7:43 ` Conor Dooley [this message]
2023-09-22 7:43 ` Conor Dooley
2023-09-22 8:18 ` Inochi Amaoto
2023-09-22 8:18 ` Inochi Amaoto
2023-09-20 6:39 ` [PATCH v2 07/11] dt-bindings: serial: snps-dw-apb-uart: Add Sophgo SG2042 uarts Chen Wang
2023-09-20 6:39 ` Chen Wang
2023-09-20 7:51 ` Guo Ren
2023-09-20 7:51 ` Guo Ren
2023-09-20 8:37 ` Conor Dooley
2023-09-20 8:37 ` Conor Dooley
2023-09-20 6:40 ` [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support Chen Wang
2023-09-20 6:40 ` Chen Wang
2023-09-20 7:53 ` Guo Ren
2023-09-20 7:53 ` Guo Ren
2023-09-20 8:05 ` Chen Wang
2023-09-20 8:05 ` Chen Wang
2023-09-20 8:08 ` Guo Ren
2023-09-20 8:08 ` Guo Ren
2023-09-22 9:41 ` Ben Dooks
2023-09-22 9:41 ` Ben Dooks
2023-09-22 10:40 ` Emil Renner Berthing
2023-09-22 10:40 ` Emil Renner Berthing
2023-09-22 11:39 ` Chen Wang
2023-09-22 11:39 ` Chen Wang
2023-09-26 7:38 ` Chen Wang
2023-09-26 7:38 ` Chen Wang
2023-09-20 6:40 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
2023-09-20 6:40 ` Chen Wang
2023-09-20 8:04 ` Guo Ren
2023-09-20 8:04 ` Guo Ren
2023-09-20 8:57 ` Conor Dooley
2023-09-20 8:57 ` Conor Dooley
2023-09-20 9:07 ` [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Inochi Amaoto
2023-09-20 9:07 ` Inochi Amaoto
2023-09-21 9:56 ` [PATCH v2 09/11] riscv: dts: add initial SOPHGO SG2042 SoC device tree Chen Wang
2023-09-21 9:56 ` Chen Wang
2023-09-21 10:15 ` Conor Dooley
2023-09-21 10:15 ` Conor Dooley
2023-09-21 10:27 ` Chen Wang
2023-09-21 10:27 ` Chen Wang
2023-09-21 12:06 ` Conor Dooley
2023-09-21 12:06 ` Conor Dooley
2023-09-20 11:32 ` Emil Renner Berthing
2023-09-20 11:32 ` Emil Renner Berthing
2023-09-20 12:09 ` 汪辰
2023-09-20 12:09 ` 汪辰
2023-09-20 12:32 ` Emil Renner Berthing
2023-09-20 12:32 ` Emil Renner Berthing
2023-09-20 12:37 ` 汪辰
2023-09-20 12:37 ` 汪辰
2023-09-20 15:19 ` Palmer Dabbelt
2023-09-20 15:19 ` Palmer Dabbelt
2023-09-20 15:31 ` Conor Dooley
2023-09-20 15:31 ` Conor Dooley
2023-09-20 6:40 ` [PATCH v2 10/11] riscv: dts: sophgo: add Milk-V Pioneer board " Chen Wang
2023-09-20 6:40 ` Chen Wang
2023-09-20 8:05 ` Guo Ren
2023-09-20 8:05 ` Guo Ren
2023-09-20 8:16 ` Conor Dooley
2023-09-20 8:16 ` Conor Dooley
2023-09-20 11:59 ` Krzysztof Kozlowski
2023-09-20 11:59 ` Krzysztof Kozlowski
2023-09-20 6:41 ` [PATCH v2 11/11] riscv: defconfig: enable SOPHGO SoC Chen Wang
2023-09-20 6:41 ` Chen Wang
2023-09-20 8:06 ` Guo Ren
2023-09-20 8:06 ` Guo Ren
2023-09-20 8:58 ` Conor Dooley
2023-09-20 8:58 ` Conor Dooley
2023-09-20 10:01 ` [PATCH v2 00/11] Add Milk-V Pioneer RISC-V board support Conor Dooley
2023-09-20 10:01 ` Conor Dooley
2023-09-22 10:24 ` Chen Wang
2023-09-22 10:24 ` Chen Wang
2023-09-22 10:50 ` Conor Dooley
2023-09-22 10:50 ` Conor Dooley
2023-09-22 11:28 ` Chen Wang
2023-09-22 11:28 ` Chen Wang
2023-09-20 15:22 ` Palmer Dabbelt
2023-09-20 15:22 ` Palmer Dabbelt
2023-09-26 10:29 ` Chen Wang
2023-09-26 10:29 ` Chen Wang
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