From: Anup Patel <apatel@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension
Date: Fri, 20 Oct 2023 12:51:32 +0530 [thread overview]
Message-ID: <20231020072140.900967-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
We add SBI debug console extension related defines/enum to the
asm/sbi.h header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/sbi.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..12dfda6bb924 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_DBCN = 0x4442434E,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+enum sbi_ext_dbcn_fid {
+ SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+ SBI_EXT_DBCN_CONSOLE_READ = 1,
+ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension
Date: Fri, 20 Oct 2023 12:51:32 +0530 [thread overview]
Message-ID: <20231020072140.900967-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
We add SBI debug console extension related defines/enum to the
asm/sbi.h header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/sbi.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..12dfda6bb924 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_DBCN = 0x4442434E,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+enum sbi_ext_dbcn_fid {
+ SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+ SBI_EXT_DBCN_CONSOLE_READ = 1,
+ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.34.1
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linux-riscv@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension
Date: Fri, 20 Oct 2023 12:51:32 +0530 [thread overview]
Message-ID: <20231020072140.900967-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
We add SBI debug console extension related defines/enum to the
asm/sbi.h header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/sbi.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..12dfda6bb924 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_DBCN = 0x4442434E,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+enum sbi_ext_dbcn_fid {
+ SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+ SBI_EXT_DBCN_CONSOLE_READ = 1,
+ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
linux-serial@vger.kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension
Date: Fri, 20 Oct 2023 12:51:32 +0530 [thread overview]
Message-ID: <20231020072140.900967-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
We add SBI debug console extension related defines/enum to the
asm/sbi.h header.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/sbi.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 5b4a1bf5f439..12dfda6bb924 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -30,6 +30,7 @@ enum sbi_ext_id {
SBI_EXT_HSM = 0x48534D,
SBI_EXT_SRST = 0x53525354,
SBI_EXT_PMU = 0x504D55,
+ SBI_EXT_DBCN = 0x4442434E,
/* Experimentals extensions must lie within this range */
SBI_EXT_EXPERIMENTAL_START = 0x08000000,
@@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type {
/* Flags defined for counter stop function */
#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
+enum sbi_ext_dbcn_fid {
+ SBI_EXT_DBCN_CONSOLE_WRITE = 0,
+ SBI_EXT_DBCN_CONSOLE_READ = 1,
+ SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
+};
+
#define SBI_SPEC_VERSION_DEFAULT 0x1
#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
--
2.34.1
next prev parent reply other threads:[~2023-10-20 7:21 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 7:21 [PATCH v3 0/9] RISC-V SBI debug console extension support Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel [this message]
2023-10-20 7:21 ` [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 2/9] RISC-V: KVM: Change the SBI specification version to v2.0 Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 3/9] RISC-V: KVM: Allow some SBI extensions to be disabled by default Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 7:21 ` [PATCH v3 4/9] RISC-V: KVM: Forward SBI DBCN extension to user-space Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 5/9] KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 7:21 ` [PATCH v3 6/9] RISC-V: Add stubs for sbi_console_putchar/getchar() Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 7/9] tty/serial: Add RISC-V SBI debug console based earlycon Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 9/9] RISC-V: Enable SBI based earlycon support Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 11:13 ` [PATCH v3 0/9] RISC-V SBI debug console extension support Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
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