From: Anup Patel <apatel@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver
Date: Fri, 20 Oct 2023 12:51:39 +0530 [thread overview]
Message-ID: <20231020072140.900967-9-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
From: Atish Patra <atishp@rivosinc.com>
RISC-V SBI specification supports advanced debug console
support via SBI DBCN extension.
Extend the HVC SBI driver to support it.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/tty/hvc/Kconfig | 2 +-
drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++---
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index 4f9264d005c0..6e05c5c7bca1 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP
config HVC_RISCV_SBI
bool "RISC-V SBI console support"
- depends on RISCV_SBI_V01
+ depends on RISCV_SBI
select HVC_DRIVER
help
This enables support for console output via RISC-V SBI calls, which
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 31f53fa77e4a..56da1a4b5aca 100644
--- a/drivers/tty/hvc/hvc_riscv_sbi.c
+++ b/drivers/tty/hvc/hvc_riscv_sbi.c
@@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count)
return i;
}
-static const struct hv_ops hvc_sbi_ops = {
+static const struct hv_ops hvc_sbi_v01_ops = {
.get_chars = hvc_sbi_tty_get,
.put_chars = hvc_sbi_tty_put,
};
-static int __init hvc_sbi_init(void)
+static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
{
- return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return count;
}
-device_initcall(hvc_sbi_init);
-static int __init hvc_sbi_console_init(void)
+static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
{
- hvc_instantiate(0, 0, &hvc_sbi_ops);
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return ret.value;
+}
+
+static const struct hv_ops hvc_sbi_dbcn_ops = {
+ .put_chars = hvc_sbi_dbcn_tty_put,
+ .get_chars = hvc_sbi_dbcn_tty_get,
+};
+
+static int __init hvc_sbi_init(void)
+{
+ int err;
+
+ if ((sbi_spec_version >= sbi_mk_version(2, 0)) &&
+ (sbi_probe_extension(SBI_EXT_DBCN) > 0)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
+ } else {
+ if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
+ } else {
+ return -ENODEV;
+ }
+ }
return 0;
}
-console_initcall(hvc_sbi_console_init);
+device_initcall(hvc_sbi_init);
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver
Date: Fri, 20 Oct 2023 12:51:39 +0530 [thread overview]
Message-ID: <20231020072140.900967-9-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
From: Atish Patra <atishp@rivosinc.com>
RISC-V SBI specification supports advanced debug console
support via SBI DBCN extension.
Extend the HVC SBI driver to support it.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/tty/hvc/Kconfig | 2 +-
drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++---
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index 4f9264d005c0..6e05c5c7bca1 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP
config HVC_RISCV_SBI
bool "RISC-V SBI console support"
- depends on RISCV_SBI_V01
+ depends on RISCV_SBI
select HVC_DRIVER
help
This enables support for console output via RISC-V SBI calls, which
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 31f53fa77e4a..56da1a4b5aca 100644
--- a/drivers/tty/hvc/hvc_riscv_sbi.c
+++ b/drivers/tty/hvc/hvc_riscv_sbi.c
@@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count)
return i;
}
-static const struct hv_ops hvc_sbi_ops = {
+static const struct hv_ops hvc_sbi_v01_ops = {
.get_chars = hvc_sbi_tty_get,
.put_chars = hvc_sbi_tty_put,
};
-static int __init hvc_sbi_init(void)
+static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
{
- return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return count;
}
-device_initcall(hvc_sbi_init);
-static int __init hvc_sbi_console_init(void)
+static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
{
- hvc_instantiate(0, 0, &hvc_sbi_ops);
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return ret.value;
+}
+
+static const struct hv_ops hvc_sbi_dbcn_ops = {
+ .put_chars = hvc_sbi_dbcn_tty_put,
+ .get_chars = hvc_sbi_dbcn_tty_get,
+};
+
+static int __init hvc_sbi_init(void)
+{
+ int err;
+
+ if ((sbi_spec_version >= sbi_mk_version(2, 0)) &&
+ (sbi_probe_extension(SBI_EXT_DBCN) > 0)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
+ } else {
+ if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
+ } else {
+ return -ENODEV;
+ }
+ }
return 0;
}
-console_initcall(hvc_sbi_console_init);
+device_initcall(hvc_sbi_init);
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver
Date: Fri, 20 Oct 2023 12:51:39 +0530 [thread overview]
Message-ID: <20231020072140.900967-9-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
From: Atish Patra <atishp@rivosinc.com>
RISC-V SBI specification supports advanced debug console
support via SBI DBCN extension.
Extend the HVC SBI driver to support it.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/tty/hvc/Kconfig | 2 +-
drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++---
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index 4f9264d005c0..6e05c5c7bca1 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP
config HVC_RISCV_SBI
bool "RISC-V SBI console support"
- depends on RISCV_SBI_V01
+ depends on RISCV_SBI
select HVC_DRIVER
help
This enables support for console output via RISC-V SBI calls, which
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 31f53fa77e4a..56da1a4b5aca 100644
--- a/drivers/tty/hvc/hvc_riscv_sbi.c
+++ b/drivers/tty/hvc/hvc_riscv_sbi.c
@@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count)
return i;
}
-static const struct hv_ops hvc_sbi_ops = {
+static const struct hv_ops hvc_sbi_v01_ops = {
.get_chars = hvc_sbi_tty_get,
.put_chars = hvc_sbi_tty_put,
};
-static int __init hvc_sbi_init(void)
+static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
{
- return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return count;
}
-device_initcall(hvc_sbi_init);
-static int __init hvc_sbi_console_init(void)
+static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
{
- hvc_instantiate(0, 0, &hvc_sbi_ops);
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return ret.value;
+}
+
+static const struct hv_ops hvc_sbi_dbcn_ops = {
+ .put_chars = hvc_sbi_dbcn_tty_put,
+ .get_chars = hvc_sbi_dbcn_tty_get,
+};
+
+static int __init hvc_sbi_init(void)
+{
+ int err;
+
+ if ((sbi_spec_version >= sbi_mk_version(2, 0)) &&
+ (sbi_probe_extension(SBI_EXT_DBCN) > 0)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
+ } else {
+ if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
+ } else {
+ return -ENODEV;
+ }
+ }
return 0;
}
-console_initcall(hvc_sbi_console_init);
+device_initcall(hvc_sbi_init);
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jirislaby@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
linux-serial@vger.kernel.org, kvm@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>,
linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver
Date: Fri, 20 Oct 2023 12:51:39 +0530 [thread overview]
Message-ID: <20231020072140.900967-9-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com>
From: Atish Patra <atishp@rivosinc.com>
RISC-V SBI specification supports advanced debug console
support via SBI DBCN extension.
Extend the HVC SBI driver to support it.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/tty/hvc/Kconfig | 2 +-
drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++---
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
index 4f9264d005c0..6e05c5c7bca1 100644
--- a/drivers/tty/hvc/Kconfig
+++ b/drivers/tty/hvc/Kconfig
@@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP
config HVC_RISCV_SBI
bool "RISC-V SBI console support"
- depends on RISCV_SBI_V01
+ depends on RISCV_SBI
select HVC_DRIVER
help
This enables support for console output via RISC-V SBI calls, which
diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c
index 31f53fa77e4a..56da1a4b5aca 100644
--- a/drivers/tty/hvc/hvc_riscv_sbi.c
+++ b/drivers/tty/hvc/hvc_riscv_sbi.c
@@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count)
return i;
}
-static const struct hv_ops hvc_sbi_ops = {
+static const struct hv_ops hvc_sbi_v01_ops = {
.get_chars = hvc_sbi_tty_get,
.put_chars = hvc_sbi_tty_put,
};
-static int __init hvc_sbi_init(void)
+static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
{
- return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return count;
}
-device_initcall(hvc_sbi_init);
-static int __init hvc_sbi_console_init(void)
+static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
{
- hvc_instantiate(0, 0, &hvc_sbi_ops);
+ phys_addr_t pa;
+ struct sbiret ret;
+
+ if (is_vmalloc_addr(buf)) {
+ pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
+ if (PAGE_SIZE < (offset_in_page(buf) + count))
+ count = PAGE_SIZE - offset_in_page(buf);
+ } else {
+ pa = __pa(buf);
+ }
+
+ if (IS_ENABLED(CONFIG_32BIT))
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, lower_32_bits(pa), upper_32_bits(pa),
+ 0, 0, 0);
+ else
+ ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ,
+ count, pa, 0, 0, 0, 0);
+ if (ret.error)
+ return 0;
+
+ return ret.value;
+}
+
+static const struct hv_ops hvc_sbi_dbcn_ops = {
+ .put_chars = hvc_sbi_dbcn_tty_put,
+ .get_chars = hvc_sbi_dbcn_tty_get,
+};
+
+static int __init hvc_sbi_init(void)
+{
+ int err;
+
+ if ((sbi_spec_version >= sbi_mk_version(2, 0)) &&
+ (sbi_probe_extension(SBI_EXT_DBCN) > 0)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops);
+ } else {
+ if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) {
+ err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16));
+ if (err)
+ return err;
+ hvc_instantiate(0, 0, &hvc_sbi_v01_ops);
+ } else {
+ return -ENODEV;
+ }
+ }
return 0;
}
-console_initcall(hvc_sbi_console_init);
+device_initcall(hvc_sbi_init);
--
2.34.1
next prev parent reply other threads:[~2023-10-20 7:21 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 7:21 [PATCH v3 0/9] RISC-V SBI debug console extension support Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 2/9] RISC-V: KVM: Change the SBI specification version to v2.0 Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 3/9] RISC-V: KVM: Allow some SBI extensions to be disabled by default Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 8:13 ` Andrew Jones
2023-10-20 7:21 ` [PATCH v3 4/9] RISC-V: KVM: Forward SBI DBCN extension to user-space Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 5/9] KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 8:15 ` Andrew Jones
2023-10-20 7:21 ` [PATCH v3 6/9] RISC-V: Add stubs for sbi_console_putchar/getchar() Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-10-21 16:35 ` Greg Kroah-Hartman
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-11-17 13:04 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 7/9] tty/serial: Add RISC-V SBI debug console based earlycon Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-10-21 16:45 ` Greg Kroah-Hartman
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-11-17 13:10 ` Anup Patel
2023-10-20 7:21 ` Anup Patel [this message]
2023-10-20 7:21 ` [PATCH v3 8/9] tty: Add SBI debug console support to HVC SBI driver Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 9:55 ` Björn Töpel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:06 ` Anup Patel
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 10:46 ` Andrew Jones
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-20 13:47 ` Anup Patel
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-10-21 16:46 ` Greg Kroah-Hartman
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-11-17 13:11 ` Anup Patel
2023-10-20 7:21 ` [PATCH v3 9/9] RISC-V: Enable SBI based earlycon support Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 7:21 ` Anup Patel
2023-10-20 11:13 ` [PATCH v3 0/9] RISC-V SBI debug console extension support Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-10-20 11:13 ` Anup Patel
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
2023-11-12 0:55 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231020072140.900967-9-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.