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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU
Date: Wed, 1 Nov 2023 10:19:48 +0100	[thread overview]
Message-ID: <20231101-2b306f5b57863cf8136f568a@orel> (raw)
In-Reply-To: <20231031203916.197332-2-dbarboza@ventanamicro.com>

On Tue, Oct 31, 2023 at 05:39:01PM -0300, Daniel Henrique Barboza wrote:
> We want to add a new CPU type for bare CPUs that will inherit specific
> traits of the 2 existing types:
> 
> - it will allow for extensions to be enabled/disabled, like generic
>   CPUs;
> 
> - it will NOT inherit defaults, like vendor CPUs.
> 
> We can make this conditions met by adding an explicit type for the
> existing vendor CPUs and change the existing logic to not imply that
> "not generic" means vendor CPUs.
> 
> Let's add the "vendor" CPU type first.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu-qom.h |  1 +
>  target/riscv/cpu.c     | 30 +++++++++++++++++++++---------
>  2 files changed, 22 insertions(+), 9 deletions(-)
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


  reply	other threads:[~2023-11-01  9:20 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-31 20:39 [PATCH v7 00/16] rv64i CPU, RVA22U64 profile support Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-11-01  9:19   ` Andrew Jones [this message]
2023-10-31 20:39 ` [PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-01  9:20   ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 03/16] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-01  9:02   ` Andrew Jones
2023-11-01  9:27     ` Daniel Henrique Barboza
2023-11-01  9:47       ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 04/16] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-01  9:04   ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 06/16] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 07/16] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 08/16] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 09/16] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 10/16] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 11/16] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 12/16] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 13/16] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 14/16] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-10-31 20:39 ` [PATCH v7 15/16] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-01  9:17   ` Andrew Jones
2023-10-31 20:39 ` [PATCH v7 16/16] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2023-11-01  9:19   ` Andrew Jones

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