From: Jason Gunthorpe <jgg@nvidia.com>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH v1 07/13] iommu/amd: Consolidate device IOTLB flush code
Date: Fri, 3 Nov 2023 15:44:27 -0300 [thread overview]
Message-ID: <20231103184427.GG223197@nvidia.com> (raw)
In-Reply-To: <20231006101624.5912-8-vasant.hegde@amd.com>
On Fri, Oct 06, 2023 at 10:16:18AM +0000, Vasant Hegde wrote:
> @@ -1380,12 +1396,13 @@ void amd_iommu_flush_all_caches(struct amd_iommu *iommu)
> /*
> * Command send function for flushing on-device TLB
> */
> -static int device_flush_iotlb(struct iommu_dev_data *dev_data,
> - u64 address, size_t size)
> +static int device_flush_iotlb_range(struct iommu_dev_data *dev_data,
> + ioasid_t pasid, u64 address, size_t size)
> {
> struct amd_iommu *iommu;
> struct iommu_cmd cmd;
> int qdep;
> + bool gn = is_pasid_valid(pasid);
I've read this a few times, and this just looks really ugly..
Something has gone off if you have to encode the type of invalidation
to do inside the PASID.
I don't have a good advice for you, but I suspect this is a
consequence of not having robust datastructures. There is not a single
handle you can use here to refer to the thing that needs to be
invalidated.
I'm not sure unifying the v1/v2 flows is actually an improvement in
clarity. In all cases the caller should already know if it is a v1/v2
object, calling a specific function is not such a burden.
Regardless, don't let this remark discrouage Joerg from merging it,
just something to think about.
Jason
next prev parent reply other threads:[~2023-11-03 18:44 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-06 10:16 [PATCH v1 00/13] Improve TLB invalidation logic Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 01/13] iommu/amd: Rename iommu_flush_all_caches() -> amd_iommu_flush_all_caches() Vasant Hegde
2023-11-03 18:08 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 02/13] iommu/amd: Remove redundant domain flush from attach_device() Vasant Hegde
2023-11-03 18:09 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 03/13] iommu/amd: Remove redundant passing of PDE bit Vasant Hegde
2023-11-03 18:11 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 04/13] iommu/amd: Add support to invalidate multiple guest pages Vasant Hegde
2023-11-03 18:23 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 05/13] iommu/amd: Refactor IOMMU tlb invalidation code Vasant Hegde
2023-11-03 18:25 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 06/13] iommu/amd: Refactor device iotlb " Vasant Hegde
2023-11-03 18:25 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 07/13] iommu/amd: Consolidate device IOTLB flush code Vasant Hegde
2023-11-03 18:44 ` Jason Gunthorpe [this message]
2023-11-06 11:39 ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 08/13] iommu/amd: Consolidate amd_iommu_domain_flush_complete() call Vasant Hegde
2023-11-03 18:45 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 09/13] iommu/amd: Refactor domain flush global function Vasant Hegde
2023-11-05 17:52 ` Jason Gunthorpe
2023-11-06 10:53 ` Vasant Hegde
2023-11-06 13:01 ` Jason Gunthorpe
2023-11-07 4:53 ` Vasant Hegde
2023-11-07 13:11 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 10/13] iommu/amd: Consolidate domain flush logic Vasant Hegde
2023-11-05 17:55 ` Jason Gunthorpe
2023-11-06 11:12 ` Vasant Hegde
2023-11-06 13:13 ` Jason Gunthorpe
2023-11-07 4:44 ` Vasant Hegde
2023-11-07 13:09 ` Jason Gunthorpe
2023-11-09 13:52 ` Vasant Hegde
2023-11-09 14:10 ` Jason Gunthorpe
2023-11-10 5:28 ` Vasant Hegde
2023-11-10 14:02 ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 11/13] iommu/amd/pgtbl_v2: Invalidate updated page ranges only Vasant Hegde
2023-11-05 17:57 ` Jason Gunthorpe
2023-11-06 11:16 ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 12/13] iommu/amd: Remove unused flush pasid functions Vasant Hegde
2023-11-05 17:58 ` Jason Gunthorpe
2023-11-06 11:19 ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 13/13] iommu/amd: Rearrange device flush code Vasant Hegde
2023-11-05 17:59 ` Jason Gunthorpe
2023-11-06 11:45 ` Vasant Hegde
2023-10-12 6:17 ` [PATCH v1 00/13] Improve TLB invalidation logic Suthikulpanit, Suravee
2023-10-16 10:18 ` Vasant Hegde
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231103184427.GG223197@nvidia.com \
--to=jgg@nvidia.com \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=suravee.suthikulpanit@amd.com \
--cc=vasant.hegde@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.