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From: Jason Gunthorpe <jgg@nvidia.com>
To: Vasant Hegde <vasant.hegde@amd.com>
Cc: iommu@lists.linux.dev, joro@8bytes.org, suravee.suthikulpanit@amd.com
Subject: Re: [PATCH v1 11/13] iommu/amd/pgtbl_v2: Invalidate updated page ranges only
Date: Sun, 5 Nov 2023 13:57:23 -0400	[thread overview]
Message-ID: <20231105175723.GK223197@nvidia.com> (raw)
In-Reply-To: <20231006101624.5912-12-vasant.hegde@amd.com>

On Fri, Oct 06, 2023 at 10:16:22AM +0000, Vasant Hegde wrote:
> amd_iommu_domain_flush_pages() uses protection domain page table mode
> to detect/get default PASID. Hence we can use this function to
> invalidate v2 page table as well.
> 
> Also in __set_gcr3()/__clear_gcr3() path call domain_flush_pages()
> directly. So that we can remove __amd_iommu_flush_tlb() and related
> functions. This works fine as we have GCR3 table per domain.
> 
> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
> ---
>  drivers/iommu/amd/io_pgtable_v2.c | 10 ++--------
>  drivers/iommu/amd/iommu.c         |  6 ++++--
>  2 files changed, 6 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtable_v2.c
> index f818a7e254d4..6d69ba60744f 100644
> --- a/drivers/iommu/amd/io_pgtable_v2.c
> +++ b/drivers/iommu/amd/io_pgtable_v2.c
> @@ -244,7 +244,6 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
>  	unsigned long mapped_size = 0;
>  	unsigned long o_iova = iova;
>  	size_t size = pgcount << __ffs(pgsize);
> -	int count = 0;
>  	int ret = 0;
>  	bool updated = false;
>  
> @@ -265,19 +264,14 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
>  
>  		*pte = set_pte_attr(paddr, map_size, prot);
>  
> -		count++;
>  		iova += map_size;
>  		paddr += map_size;
>  		mapped_size += map_size;
>  	}
>  
>  out:
> -	if (updated) {
> -		if (count > 1)
> -			amd_iommu_flush_tlb(&pdom->domain, 0);
> -		else
> -			amd_iommu_flush_page(&pdom->domain, 0, o_iova);
> -	}
> +	if (updated)
> +		amd_iommu_domain_flush_pages(pdom, o_iova, size);
>  
>  	if (mapped)
>  		*mapped += mapped_size;
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 8da445e51251..764a5656b56b 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -2698,7 +2698,8 @@ static int __set_gcr3(struct protection_domain *domain, u32 pasid,
>  
>  	*pte = (cr3 & PAGE_MASK) | GCR3_VALID;
>  
> -	return __amd_iommu_flush_tlb(domain, pasid);
> +	domain_flush_pages(domain, pasid, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS);
> +	return 0;
>  }
>  
>  static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
> @@ -2714,7 +2715,8 @@ static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
>  
>  	*pte = 0;
>  
> -	return __amd_iommu_flush_tlb(domain, pasid);
> +	domain_flush_pages(domain, pasid, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS);
> +	return 0;
>  }

You should make the other "flush all" wrapper accept a PASID and call
it here as well instead of open coding it, or do away with the flush
all wraper completely.

Jason

  reply	other threads:[~2023-11-05 17:57 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-06 10:16 [PATCH v1 00/13] Improve TLB invalidation logic Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 01/13] iommu/amd: Rename iommu_flush_all_caches() -> amd_iommu_flush_all_caches() Vasant Hegde
2023-11-03 18:08   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 02/13] iommu/amd: Remove redundant domain flush from attach_device() Vasant Hegde
2023-11-03 18:09   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 03/13] iommu/amd: Remove redundant passing of PDE bit Vasant Hegde
2023-11-03 18:11   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 04/13] iommu/amd: Add support to invalidate multiple guest pages Vasant Hegde
2023-11-03 18:23   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 05/13] iommu/amd: Refactor IOMMU tlb invalidation code Vasant Hegde
2023-11-03 18:25   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 06/13] iommu/amd: Refactor device iotlb " Vasant Hegde
2023-11-03 18:25   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 07/13] iommu/amd: Consolidate device IOTLB flush code Vasant Hegde
2023-11-03 18:44   ` Jason Gunthorpe
2023-11-06 11:39     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 08/13] iommu/amd: Consolidate amd_iommu_domain_flush_complete() call Vasant Hegde
2023-11-03 18:45   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 09/13] iommu/amd: Refactor domain flush global function Vasant Hegde
2023-11-05 17:52   ` Jason Gunthorpe
2023-11-06 10:53     ` Vasant Hegde
2023-11-06 13:01       ` Jason Gunthorpe
2023-11-07  4:53         ` Vasant Hegde
2023-11-07 13:11           ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 10/13] iommu/amd: Consolidate domain flush logic Vasant Hegde
2023-11-05 17:55   ` Jason Gunthorpe
2023-11-06 11:12     ` Vasant Hegde
2023-11-06 13:13       ` Jason Gunthorpe
2023-11-07  4:44         ` Vasant Hegde
2023-11-07 13:09           ` Jason Gunthorpe
2023-11-09 13:52             ` Vasant Hegde
2023-11-09 14:10               ` Jason Gunthorpe
2023-11-10  5:28                 ` Vasant Hegde
2023-11-10 14:02                   ` Jason Gunthorpe
2023-10-06 10:16 ` [PATCH v1 11/13] iommu/amd/pgtbl_v2: Invalidate updated page ranges only Vasant Hegde
2023-11-05 17:57   ` Jason Gunthorpe [this message]
2023-11-06 11:16     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 12/13] iommu/amd: Remove unused flush pasid functions Vasant Hegde
2023-11-05 17:58   ` Jason Gunthorpe
2023-11-06 11:19     ` Vasant Hegde
2023-10-06 10:16 ` [PATCH v1 13/13] iommu/amd: Rearrange device flush code Vasant Hegde
2023-11-05 17:59   ` Jason Gunthorpe
2023-11-06 11:45     ` Vasant Hegde
2023-10-12  6:17 ` [PATCH v1 00/13] Improve TLB invalidation logic Suthikulpanit, Suravee
2023-10-16 10:18 ` Vasant Hegde

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