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From: Lukas Wunner <lukas@wunner.de>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: "open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
	"Karol Herbst" <kherbst@redhat.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<nouveau@lists.freedesktop.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<dri-devel@lists.freedesktop.org>,
	"open list:X86 PLATFORM DRIVERS"
	<platform-driver-x86@vger.kernel.org>,
	"Andreas Noever" <andreas.noever@gmail.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"David Airlie" <airlied@gmail.com>,
	"Marek Behún" <kabel@kernel.org>,
	"open list:RADEON and AMDGPU DRM DRIVERS"
	<amd-gfx@lists.freedesktop.org>,
	"open list:ACPI" <linux-acpi@vger.kernel.org>,
	"Danilo Krummrich" <dakr@redhat.com>,
	"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Michael Jamet" <michael.jamet@intel.com>,
	"Mark Gross" <markgross@kernel.org>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Xinhui Pan" <Xinhui.Pan@amd.com>,
	"open list" <linux-kernel@vger.kernel.org>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Yehezkel Bernat" <YehezkelShB@gmail.com>,
	"Pali Rohár" <pali@kernel.org>,
	"Christian König" <christian.koenig@amd.com>,
	"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available()
Date: Mon, 6 Nov 2023 19:56:52 +0100	[thread overview]
Message-ID: <20231106185652.GA3360@wunner.de> (raw)
In-Reply-To: <712ebb25-3fc0-49b5-96a1-a13c3c4c4921@amd.com>

On Mon, Nov 06, 2023 at 12:44:25PM -0600, Mario Limonciello wrote:
> Tangentially related; the link speed is currently symmetric but there are
> two sysfs files.  Mika left a comment in drivers/thunderbolt/switch.c it may
> be asymmetric in the future. So we may need to keep that in mind on any
> design that builds on top of them.

Aren't asymmetric Thunderbolt speeds just a DisplayPort thing?


> As 'thunderbolt' can be a module or built in, we need to bring code into PCI
> core so that it works in early boot before it loads.

tb_switch_get_generation() is small enough that it could be moved to the
PCI core.  I doubt that we need to make thunderbolt built-in only
or move a large amount of code to the PCI core.

Thanks,

Lukas

WARNING: multiple messages have this Message-ID (diff)
From: Lukas Wunner <lukas@wunner.de>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: "Karol Herbst" <kherbst@redhat.com>,
	"Lyude Paul" <lyude@redhat.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Danilo Krummrich" <dakr@redhat.com>,
	"David Airlie" <airlied@gmail.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Xinhui Pan" <Xinhui.Pan@amd.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Mark Gross" <markgross@kernel.org>,
	"Andreas Noever" <andreas.noever@gmail.com>,
	"Michael Jamet" <michael.jamet@intel.com>,
	"Yehezkel Bernat" <YehezkelShB@gmail.com>,
	"Pali Rohár" <pali@kernel.org>, "Marek Behún" <kabel@kernel.org>,
	"Maciej W . Rozycki" <macro@orcam.me.uk>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<dri-devel@lists.freedesktop.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<nouveau@lists.freedesktop.org>,
	"open list" <linux-kernel@vger.kernel.org>,
	"open list:RADEON and AMDGPU DRM DRIVERS"
	<amd-gfx@lists.freedesktop.org>,
	"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
	"open list:ACPI" <linux-acpi@vger.kernel.org>,
	"open list:X86 PLATFORM DRIVERS"
	<platform-driver-x86@vger.kernel.org>,
	"open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>
Subject: Re: [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available()
Date: Mon, 6 Nov 2023 19:56:52 +0100	[thread overview]
Message-ID: <20231106185652.GA3360@wunner.de> (raw)
In-Reply-To: <712ebb25-3fc0-49b5-96a1-a13c3c4c4921@amd.com>

On Mon, Nov 06, 2023 at 12:44:25PM -0600, Mario Limonciello wrote:
> Tangentially related; the link speed is currently symmetric but there are
> two sysfs files.  Mika left a comment in drivers/thunderbolt/switch.c it may
> be asymmetric in the future. So we may need to keep that in mind on any
> design that builds on top of them.

Aren't asymmetric Thunderbolt speeds just a DisplayPort thing?


> As 'thunderbolt' can be a module or built in, we need to bring code into PCI
> core so that it works in early boot before it loads.

tb_switch_get_generation() is small enough that it could be moved to the
PCI core.  I doubt that we need to make thunderbolt built-in only
or move a large amount of code to the PCI core.

Thanks,

Lukas

WARNING: multiple messages have this Message-ID (diff)
From: Lukas Wunner <lukas@wunner.de>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: "open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<nouveau@lists.freedesktop.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<dri-devel@lists.freedesktop.org>,
	"open list:X86 PLATFORM DRIVERS"
	<platform-driver-x86@vger.kernel.org>,
	"Andreas Noever" <andreas.noever@gmail.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Marek Behún" <kabel@kernel.org>,
	"open list:RADEON and AMDGPU DRM DRIVERS"
	<amd-gfx@lists.freedesktop.org>,
	"open list:ACPI" <linux-acpi@vger.kernel.org>,
	"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Michael Jamet" <michael.jamet@intel.com>,
	"Mark Gross" <markgross@kernel.org>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Xinhui Pan" <Xinhui.Pan@amd.com>,
	"open list" <linux-kernel@vger.kernel.org>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Yehezkel Bernat" <YehezkelShB@gmail.com>,
	"Pali Rohár" <pali@kernel.org>,
	"Christian König" <christian.koenig@amd.com>,
	"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [Nouveau] [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available()
Date: Mon, 6 Nov 2023 19:56:52 +0100	[thread overview]
Message-ID: <20231106185652.GA3360@wunner.de> (raw)
In-Reply-To: <712ebb25-3fc0-49b5-96a1-a13c3c4c4921@amd.com>

On Mon, Nov 06, 2023 at 12:44:25PM -0600, Mario Limonciello wrote:
> Tangentially related; the link speed is currently symmetric but there are
> two sysfs files.  Mika left a comment in drivers/thunderbolt/switch.c it may
> be asymmetric in the future. So we may need to keep that in mind on any
> design that builds on top of them.

Aren't asymmetric Thunderbolt speeds just a DisplayPort thing?


> As 'thunderbolt' can be a module or built in, we need to bring code into PCI
> core so that it works in early boot before it loads.

tb_switch_get_generation() is small enough that it could be moved to the
PCI core.  I doubt that we need to make thunderbolt built-in only
or move a large amount of code to the PCI core.

Thanks,

Lukas

WARNING: multiple messages have this Message-ID (diff)
From: Lukas Wunner <lukas@wunner.de>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: "open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
	"Karol Herbst" <kherbst@redhat.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<nouveau@lists.freedesktop.org>,
	"open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS"
	<dri-devel@lists.freedesktop.org>,
	"open list:X86 PLATFORM DRIVERS"
	<platform-driver-x86@vger.kernel.org>,
	"Andreas Noever" <andreas.noever@gmail.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Marek Behún" <kabel@kernel.org>,
	"open list:RADEON and AMDGPU DRM DRIVERS"
	<amd-gfx@lists.freedesktop.org>,
	"open list:ACPI" <linux-acpi@vger.kernel.org>,
	"Danilo Krummrich" <dakr@redhat.com>,
	"open list:PCI SUBSYSTEM" <linux-pci@vger.kernel.org>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Michael Jamet" <michael.jamet@intel.com>,
	"Mark Gross" <markgross@kernel.org>,
	"Hans de Goede" <hdegoede@redhat.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Mika Westerberg" <mika.westerberg@linux.intel.com>,
	"Xinhui Pan" <Xinhui.Pan@amd.com>,
	"open list" <linux-kernel@vger.kernel.org>,
	"Yehezkel Bernat" <YehezkelShB@gmail.com>,
	"Pali Rohár" <pali@kernel.org>,
	"Christian König" <christian.koenig@amd.com>,
	"Maciej W . Rozycki" <macro@orcam.me.uk>
Subject: Re: [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available()
Date: Mon, 6 Nov 2023 19:56:52 +0100	[thread overview]
Message-ID: <20231106185652.GA3360@wunner.de> (raw)
In-Reply-To: <712ebb25-3fc0-49b5-96a1-a13c3c4c4921@amd.com>

On Mon, Nov 06, 2023 at 12:44:25PM -0600, Mario Limonciello wrote:
> Tangentially related; the link speed is currently symmetric but there are
> two sysfs files.  Mika left a comment in drivers/thunderbolt/switch.c it may
> be asymmetric in the future. So we may need to keep that in mind on any
> design that builds on top of them.

Aren't asymmetric Thunderbolt speeds just a DisplayPort thing?


> As 'thunderbolt' can be a module or built in, we need to bring code into PCI
> core so that it works in early boot before it loads.

tb_switch_get_generation() is small enough that it could be moved to the
PCI core.  I doubt that we need to make thunderbolt built-in only
or move a large amount of code to the PCI core.

Thanks,

Lukas

  reply	other threads:[~2023-11-06 18:56 UTC|newest]

Thread overview: 127+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-03 19:07 [PATCH v2 0/9] Improvements to pcie_bandwidth_available() for eGPUs Mario Limonciello
2023-11-03 19:07 ` Mario Limonciello
2023-11-03 19:07 ` [Nouveau] " Mario Limonciello
2023-11-03 19:07 ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 1/9] drm/nouveau: Switch from pci_is_thunderbolt_attached() to dev_is_removable() Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-06 12:25   ` Ilpo Järvinen
2023-11-06 12:25     ` Ilpo Järvinen
2023-11-06 12:25     ` Ilpo Järvinen
2023-11-06 12:25     ` Ilpo Järvinen
2023-11-06 16:47     ` Mika Westerberg
2023-11-06 16:47       ` Mika Westerberg
2023-11-06 16:47       ` [Nouveau] " Mika Westerberg
2023-11-06 16:47       ` Mika Westerberg
2023-11-06 16:49       ` Mario Limonciello
2023-11-06 16:49         ` Mario Limonciello
2023-11-06 16:49         ` [Nouveau] " Mario Limonciello
2023-11-06 16:49         ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 2/9] drm/radeon: " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-06 12:27   ` Ilpo Järvinen
2023-11-06 12:27     ` Ilpo Järvinen
2023-11-06 12:27     ` Ilpo Järvinen
2023-11-06 12:27     ` Ilpo Järvinen
2023-11-03 19:07 ` [PATCH v2 3/9] PCI: Drop pci_is_thunderbolt_attached() Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-04  0:37   ` kernel test robot
2023-11-04  0:37     ` kernel test robot
2023-11-04  0:37     ` kernel test robot
2023-11-06 12:33   ` Ilpo Järvinen
2023-11-06 12:33     ` Ilpo Järvinen
2023-11-06 12:33     ` Ilpo Järvinen
2023-11-06 12:33     ` Ilpo Järvinen
2023-11-06 16:46     ` Mario Limonciello
2023-11-06 16:46       ` Mario Limonciello
2023-11-06 16:46       ` [Nouveau] " Mario Limonciello
2023-11-06 16:46       ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 4/9] PCI: Move the `PCI_CLASS_SERIAL_USB_USB4` definition to common header Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 5/9] PCI: pciehp: Move check for is_thunderbolt into a quirk Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-06 12:41   ` Ilpo Järvinen
2023-11-06 12:41     ` Ilpo Järvinen
2023-11-06 12:41     ` Ilpo Järvinen
2023-11-06 12:41     ` Ilpo Järvinen
2023-11-06 16:50     ` Mario Limonciello
2023-11-06 16:50       ` Mario Limonciello
2023-11-06 16:50       ` [Nouveau] " Mario Limonciello
2023-11-06 16:50       ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 6/9] PCI: Rename is_thunderbolt to is_tunneled Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:38   ` Hans de Goede
2023-11-03 19:38     ` Hans de Goede
2023-11-03 19:38     ` [Nouveau] " Hans de Goede
2023-11-03 19:38     ` Hans de Goede
2023-11-05 17:39   ` Lukas Wunner
2023-11-05 17:39     ` Lukas Wunner
2023-11-05 17:39     ` [Nouveau] " Lukas Wunner
2023-11-05 17:39     ` Lukas Wunner
2023-11-06 16:59     ` Mario Limonciello
2023-11-06 16:59       ` Mario Limonciello
2023-11-06 16:59       ` [Nouveau] " Mario Limonciello
2023-11-06 16:59       ` Mario Limonciello
2023-11-06 18:18       ` Lukas Wunner
2023-11-06 18:18         ` Lukas Wunner
2023-11-06 18:18         ` [Nouveau] " Lukas Wunner
2023-11-06 18:18         ` Lukas Wunner
2023-11-03 19:07 ` [PATCH v2 7/9] PCI: ACPI: Detect PCIe root ports that are used for tunneling Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07 ` [PATCH v2 8/9] PCI: Exclude PCIe ports used for tunneling in pcie_bandwidth_available() Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-04  6:57   ` Lazar, Lijo
2023-11-04  6:57     ` Lazar, Lijo
2023-11-04  6:57     ` Lazar, Lijo
2023-11-04  6:57     ` Lazar, Lijo
2023-11-06 12:52   ` Ilpo Järvinen
2023-11-06 12:52     ` Ilpo Järvinen
2023-11-06 12:52     ` Ilpo Järvinen
2023-11-06 12:52     ` Ilpo Järvinen
2023-11-06 16:51     ` Mario Limonciello
2023-11-06 16:51       ` Mario Limonciello
2023-11-06 16:51       ` [Nouveau] " Mario Limonciello
2023-11-06 16:51       ` Mario Limonciello
2023-11-06 18:10   ` Lukas Wunner
2023-11-06 18:10     ` Lukas Wunner
2023-11-06 18:10     ` [Nouveau] " Lukas Wunner
2023-11-06 18:10     ` Lukas Wunner
2023-11-06 18:44     ` Mario Limonciello
2023-11-06 18:44       ` Mario Limonciello
2023-11-06 18:44       ` [Nouveau] " Mario Limonciello
2023-11-06 18:44       ` Mario Limonciello
2023-11-06 18:56       ` Lukas Wunner [this message]
2023-11-06 18:56         ` Lukas Wunner
2023-11-06 18:56         ` [Nouveau] " Lukas Wunner
2023-11-06 18:56         ` Lukas Wunner
2023-11-07  5:45         ` Mika Westerberg
2023-11-07  5:45           ` Mika Westerberg
2023-11-07  5:45           ` [Nouveau] " Mika Westerberg
2023-11-07  5:45           ` Mika Westerberg
2023-11-07  6:24           ` Mika Westerberg
2023-11-07  6:24             ` Mika Westerberg
2023-11-07  6:24             ` [Nouveau] " Mika Westerberg
2023-11-07  6:24             ` Mika Westerberg
2023-11-03 19:07 ` [PATCH v2 9/9] PCI: Add a quirk to mark 0x8086 : 0x9a23 as supporting PCIe tunneling Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:07   ` [Nouveau] " Mario Limonciello
2023-11-03 19:07   ` Mario Limonciello
2023-11-03 19:20 ` [PATCH v2 0/9] Improvements to pcie_bandwidth_available() for eGPUs Bjorn Helgaas
2023-11-03 19:20   ` Bjorn Helgaas
2023-11-03 19:20   ` [Nouveau] " Bjorn Helgaas
2023-11-03 19:20   ` Bjorn Helgaas

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