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From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>, "Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Björn Töpel" <bjorn@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v3 08/17] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries
Date: Tue, 19 Dec 2023 23:15:17 +0530	[thread overview]
Message-ID: <20231219174526.2235150-9-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231219174526.2235150-1-sunilvl@ventanamicro.com>

ACPI MADT entries for interrupt controllers don't have a way to describe
the hierarchy. However, the hierarchy is known to the architecture and
on RISC-V platforms, the MADT sub table types are ordered in the
incremental order from the root controller which is RINTC. So, add
architecture function for RISC-V to reorder the interrupt controller
probing as per the hierarchy as below.

RINTC->IMSIC->APLIC->PLIC

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/acpi/riscv/Makefile |  2 +-
 drivers/acpi/riscv/irq.c    | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 drivers/acpi/riscv/irq.c

diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 8b3b126e0b94..f80b3da230e9 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-y 	+= rhct.o
+obj-y 	+= rhct.o irq.o
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..36e0525b3235
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+	struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+	struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+	return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
+ * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
+ * order, this arch function will reorder the probe functions as per the
+ * required order for the architecture.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+	struct acpi_probe_entry *ape = ap_head;
+
+	if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+		return;
+	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
-- 
2.39.2


WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org
Cc: "Marc Zyngier" <maz@kernel.org>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Will Deacon" <will@kernel.org>, "Len Brown" <lenb@kernel.org>
Subject: [RFC PATCH v3 08/17] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries
Date: Tue, 19 Dec 2023 23:15:17 +0530	[thread overview]
Message-ID: <20231219174526.2235150-9-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231219174526.2235150-1-sunilvl@ventanamicro.com>

ACPI MADT entries for interrupt controllers don't have a way to describe
the hierarchy. However, the hierarchy is known to the architecture and
on RISC-V platforms, the MADT sub table types are ordered in the
incremental order from the root controller which is RINTC. So, add
architecture function for RISC-V to reorder the interrupt controller
probing as per the hierarchy as below.

RINTC->IMSIC->APLIC->PLIC

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/acpi/riscv/Makefile |  2 +-
 drivers/acpi/riscv/irq.c    | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 drivers/acpi/riscv/irq.c

diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 8b3b126e0b94..f80b3da230e9 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-y 	+= rhct.o
+obj-y 	+= rhct.o irq.o
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..36e0525b3235
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+	struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+	struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+	return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
+ * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
+ * order, this arch function will reorder the probe functions as per the
+ * required order for the architecture.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+	struct acpi_probe_entry *ape = ap_head;
+
+	if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+		return;
+	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
-- 
2.39.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Len Brown" <lenb@kernel.org>, "Anup Patel" <anup@brainfault.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Haibo Xu" <haibo1.xu@intel.com>,
	"Conor Dooley" <conor.dooley@microchip.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Björn Töpel" <bjorn@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
	"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v3 08/17] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries
Date: Tue, 19 Dec 2023 23:15:17 +0530	[thread overview]
Message-ID: <20231219174526.2235150-9-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231219174526.2235150-1-sunilvl@ventanamicro.com>

ACPI MADT entries for interrupt controllers don't have a way to describe
the hierarchy. However, the hierarchy is known to the architecture and
on RISC-V platforms, the MADT sub table types are ordered in the
incremental order from the root controller which is RINTC. So, add
architecture function for RISC-V to reorder the interrupt controller
probing as per the hierarchy as below.

RINTC->IMSIC->APLIC->PLIC

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 drivers/acpi/riscv/Makefile |  2 +-
 drivers/acpi/riscv/irq.c    | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)
 create mode 100644 drivers/acpi/riscv/irq.c

diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
index 8b3b126e0b94..f80b3da230e9 100644
--- a/drivers/acpi/riscv/Makefile
+++ b/drivers/acpi/riscv/Makefile
@@ -1,2 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-y 	+= rhct.o
+obj-y 	+= rhct.o irq.o
diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
new file mode 100644
index 000000000000..36e0525b3235
--- /dev/null
+++ b/drivers/acpi/riscv/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, Ventana Micro Systems Inc
+ *	Author: Sunil V L <sunilvl@ventanamicro.com>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/sort.h>
+
+static int irqchip_cmp_func(const void *in0, const void *in1)
+{
+	struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
+	struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
+
+	return (elem0->type > elem1->type) - (elem0->type < elem1->type);
+}
+
+/*
+ * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
+ * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
+ * order, this arch function will reorder the probe functions as per the
+ * required order for the architecture.
+ */
+void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
+{
+	struct acpi_probe_entry *ape = ap_head;
+
+	if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
+		return;
+	sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
+}
-- 
2.39.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-12-19 17:46 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-19 17:45 [RFC PATCH v3 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2023-12-19 17:45 ` Sunil V L
2023-12-19 17:45 ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 02/17] RISC-V: ACPI: Implement PCI related functionality Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 03/17] PCI: Make pci_create_root_bus() declare its reliance on MSI domains Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-26 23:56   ` Bjorn Helgaas
2023-12-26 23:56     ` Bjorn Helgaas
2023-12-26 23:56     ` Bjorn Helgaas
2023-12-28 13:08     ` Sunil V L
2023-12-28 13:08       ` Sunil V L
2023-12-28 13:08       ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 04/17] ACPI: Add fw_devlink support for ACPI fwnode for IRQ dependency Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 05/17] ACPI: irq: Add support for deferred probe in acpi_register_gsi() Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 06/17] pnp.h: Reconfigure IRQ in pnp_irq() to support deferred probe Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 07/17] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` Sunil V L [this message]
2023-12-19 17:45   ` [RFC PATCH v3 08/17] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 09/17] irqchip: riscv-intc: Add ACPI support for AIA Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 10/17] irqchip: riscv-imsic: Add ACPI support Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 11/17] irqchip: riscv-aplic: " Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 12/17] irqchip: irq-sifive-plic: " Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 13/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 14/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 15/17] ACPI: RISC-V: Create APLIC platform device Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 16/17] ACPI: RISC-V: Create PLIC " Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 17/17] irqchip: riscv-intc: Set ACPI irqmodel Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:45   ` Sunil V L
2023-12-19 17:50 ` [RFC PATCH v3 00/17] RISC-V: ACPI: Add external interrupt controller support Rafael J. Wysocki
2023-12-19 17:50   ` Rafael J. Wysocki
2023-12-19 17:50   ` Rafael J. Wysocki
2023-12-20  3:49   ` Sunil V L
2023-12-20  3:49     ` Sunil V L
2023-12-20  3:49     ` Sunil V L
2024-01-30  6:02   ` Sunil V L
2024-01-30  6:02     ` Sunil V L
2024-01-30  6:02     ` Sunil V L
2024-02-01 18:10     ` Rafael J. Wysocki
2024-02-01 18:10       ` Rafael J. Wysocki
2024-02-01 18:10       ` Rafael J. Wysocki
2024-02-02 12:17       ` Sunil V L
2024-02-02 12:17         ` Sunil V L
2024-02-02 12:17         ` Sunil V L
2024-03-04 10:20         ` Sunil V L
2024-03-04 10:20           ` Sunil V L
2024-03-04 10:20           ` Sunil V L
2024-04-15 15:09       ` Sunil V L
2024-04-15 15:09         ` Sunil V L
2024-04-15 15:09         ` Sunil V L
2024-04-15 15:18         ` Rafael J. Wysocki
2024-04-15 15:18           ` Rafael J. Wysocki
2024-04-15 15:18           ` Rafael J. Wysocki

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