* [RFC v1 0/1] Enable SPCR table for console output on RISC-V @ 2023-12-29 6:54 ` Sia Jee Heng 0 siblings, 0 replies; 8+ messages in thread From: Sia Jee Heng @ 2023-12-29 6:54 UTC (permalink / raw) To: linux-kernel, linux-riscv Cc: aou, jeeheng.sia, rafael.j.wysocki, conor.dooley, palmer, paul.walmsley, ajones This patch will enable the SPCR table for RISC-V. Vendor will enable/disable the SPCR table in the firmware based on the platform design. However, in cases where the SPCR table is not usable, a kernel parameter could be used to specify the preferred console. This patch depends on Sunil's patch series, as indicated in [1] and the corresponding Qemu patch can be found at [2]. [1] https://lore.kernel.org/lkml/20231219174526.2235150-1-sunilvl@ventanamicro.com/ [2] https://lore.kernel.org/qemu-devel/20231228080616.158822-1-jeeheng.sia@starfivetech.com/ Sia Jee Heng (1): RISC-V: ACPI: Enable SPCR table for console output on RISC-V arch/riscv/kernel/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC v1 0/1] Enable SPCR table for console output on RISC-V @ 2023-12-29 6:54 ` Sia Jee Heng 0 siblings, 0 replies; 8+ messages in thread From: Sia Jee Heng @ 2023-12-29 6:54 UTC (permalink / raw) To: linux-kernel, linux-riscv Cc: rafael.j.wysocki, ajones, conor.dooley, sunilvl, jeeheng.sia, aou, palmer, paul.walmsley This patch will enable the SPCR table for RISC-V. Vendor will enable/disable the SPCR table in the firmware based on the platform design. However, in cases where the SPCR table is not usable, a kernel parameter could be used to specify the preferred console. This patch depends on Sunil's patch series, as indicated in [1] and the corresponding Qemu patch can be found at [2]. [1] https://lore.kernel.org/lkml/20231219174526.2235150-1-sunilvl@ventanamicro.com/ [2] https://lore.kernel.org/qemu-devel/20231228080616.158822-1-jeeheng.sia@starfivetech.com/ Sia Jee Heng (1): RISC-V: ACPI: Enable SPCR table for console output on RISC-V arch/riscv/kernel/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.34.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V 2023-12-29 6:54 ` Sia Jee Heng @ 2023-12-29 6:54 ` Sia Jee Heng -1 siblings, 0 replies; 8+ messages in thread From: Sia Jee Heng @ 2023-12-29 6:54 UTC (permalink / raw) To: linux-kernel, linux-riscv Cc: aou, jeeheng.sia, rafael.j.wysocki, conor.dooley, palmer, paul.walmsley, ajones The ACPI SPCR code has been used to enable console output for ARM64 and X86. The same code can be reused for RISC-V. Vendor will enable/disable the SPCR table in the firmware based on the platform design. However, in cases where the SPCR table is not usable, a kernel parameter could be used to specify the preferred console. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> --- arch/riscv/kernel/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..5ec2fdf9e09f 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/memblock.h> #include <linux/pci.h> +#include <linux/serial_core.h> int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) if (!param_acpi_force) disable_acpi(); } + + if (!acpi_disabled) + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); } static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V @ 2023-12-29 6:54 ` Sia Jee Heng 0 siblings, 0 replies; 8+ messages in thread From: Sia Jee Heng @ 2023-12-29 6:54 UTC (permalink / raw) To: linux-kernel, linux-riscv Cc: rafael.j.wysocki, ajones, conor.dooley, sunilvl, jeeheng.sia, aou, palmer, paul.walmsley The ACPI SPCR code has been used to enable console output for ARM64 and X86. The same code can be reused for RISC-V. Vendor will enable/disable the SPCR table in the firmware based on the platform design. However, in cases where the SPCR table is not usable, a kernel parameter could be used to specify the preferred console. Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> --- arch/riscv/kernel/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..5ec2fdf9e09f 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -18,6 +18,7 @@ #include <linux/io.h> #include <linux/memblock.h> #include <linux/pci.h> +#include <linux/serial_core.h> int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) if (!param_acpi_force) disable_acpi(); } + + if (!acpi_disabled) + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); } static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) -- 2.34.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V 2023-12-29 6:54 ` Sia Jee Heng @ 2024-01-02 15:39 ` Andrew Jones -1 siblings, 0 replies; 8+ messages in thread From: Andrew Jones @ 2024-01-02 15:39 UTC (permalink / raw) To: Sia Jee Heng Cc: aou, rafael.j.wysocki, linux-kernel, conor.dooley, palmer, paul.walmsley, linux-riscv On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote: > The ACPI SPCR code has been used to enable console output for ARM64 and > X86. The same code can be reused for RISC-V. > > Vendor will enable/disable the SPCR table in the firmware based on the > platform design. However, in cases where the SPCR table is not usable, > a kernel parameter could be used to specify the preferred console. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > --- > arch/riscv/kernel/acpi.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c > index e619edc8b0cc..5ec2fdf9e09f 100644 > --- a/arch/riscv/kernel/acpi.c > +++ b/arch/riscv/kernel/acpi.c > @@ -18,6 +18,7 @@ > #include <linux/io.h> > #include <linux/memblock.h> > #include <linux/pci.h> > +#include <linux/serial_core.h> > > int acpi_noirq = 1; /* skip ACPI IRQ initialization */ > int acpi_disabled = 1; > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) > if (!param_acpi_force) > disable_acpi(); > } > + > + if (!acpi_disabled) > + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that not necessary for RISC-V? Thanks, drew > } > > static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V @ 2024-01-02 15:39 ` Andrew Jones 0 siblings, 0 replies; 8+ messages in thread From: Andrew Jones @ 2024-01-02 15:39 UTC (permalink / raw) To: Sia Jee Heng Cc: linux-kernel, linux-riscv, rafael.j.wysocki, conor.dooley, sunilvl, aou, palmer, paul.walmsley On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote: > The ACPI SPCR code has been used to enable console output for ARM64 and > X86. The same code can be reused for RISC-V. > > Vendor will enable/disable the SPCR table in the firmware based on the > platform design. However, in cases where the SPCR table is not usable, > a kernel parameter could be used to specify the preferred console. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > --- > arch/riscv/kernel/acpi.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c > index e619edc8b0cc..5ec2fdf9e09f 100644 > --- a/arch/riscv/kernel/acpi.c > +++ b/arch/riscv/kernel/acpi.c > @@ -18,6 +18,7 @@ > #include <linux/io.h> > #include <linux/memblock.h> > #include <linux/pci.h> > +#include <linux/serial_core.h> > > int acpi_noirq = 1; /* skip ACPI IRQ initialization */ > int acpi_disabled = 1; > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) > if (!param_acpi_force) > disable_acpi(); > } > + > + if (!acpi_disabled) > + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that not necessary for RISC-V? Thanks, drew > } > > static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V 2024-01-02 15:39 ` Andrew Jones @ 2024-01-05 12:12 ` JeeHeng Sia -1 siblings, 0 replies; 8+ messages in thread From: JeeHeng Sia @ 2024-01-05 12:12 UTC (permalink / raw) To: Andrew Jones Cc: aou@eecs.berkeley.edu, rafael.j.wysocki@intel.com, linux-kernel@vger.kernel.org, conor.dooley@microchip.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org > -----Original Message----- > From: Andrew Jones <ajones@ventanamicro.com> > Sent: Tuesday, January 2, 2024 11:39 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; rafael.j.wysocki@intel.com; conor.dooley@microchip.com; > sunilvl@ventanamicro.com; aou@eecs.berkeley.edu; palmer@dabbelt.com; paul.walmsley@sifive.com > Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V > > On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote: > > The ACPI SPCR code has been used to enable console output for ARM64 and > > X86. The same code can be reused for RISC-V. > > > > Vendor will enable/disable the SPCR table in the firmware based on the > > platform design. However, in cases where the SPCR table is not usable, > > a kernel parameter could be used to specify the preferred console. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > --- > > arch/riscv/kernel/acpi.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c > > index e619edc8b0cc..5ec2fdf9e09f 100644 > > --- a/arch/riscv/kernel/acpi.c > > +++ b/arch/riscv/kernel/acpi.c > > @@ -18,6 +18,7 @@ > > #include <linux/io.h> > > #include <linux/memblock.h> > > #include <linux/pci.h> > > +#include <linux/serial_core.h> > > > > int acpi_noirq = 1; /* skip ACPI IRQ initialization */ > > int acpi_disabled = 1; > > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) > > if (!param_acpi_force) > > disable_acpi(); > > } > > + > > + if (!acpi_disabled) > > + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); > > Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when > acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that > not necessary for RISC-V? It is needed for device tree support. However, since this patch targets ACPI, that's why I didn't include a DT solution in this patch. I can submit a separate patch targeting DT-based earlycon if needed. Please let me know if you think otherwise. > > Thanks, > drew > > > } > > > > static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) > > -- > > 2.34.1 > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V @ 2024-01-05 12:12 ` JeeHeng Sia 0 siblings, 0 replies; 8+ messages in thread From: JeeHeng Sia @ 2024-01-05 12:12 UTC (permalink / raw) To: Andrew Jones Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, rafael.j.wysocki@intel.com, conor.dooley@microchip.com, sunilvl@ventanamicro.com, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com > -----Original Message----- > From: Andrew Jones <ajones@ventanamicro.com> > Sent: Tuesday, January 2, 2024 11:39 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org; rafael.j.wysocki@intel.com; conor.dooley@microchip.com; > sunilvl@ventanamicro.com; aou@eecs.berkeley.edu; palmer@dabbelt.com; paul.walmsley@sifive.com > Subject: Re: [RFC v1 1/1] RISC-V: ACPI: Enable SPCR table for console output on RISC-V > > On Fri, Dec 29, 2023 at 02:54:05PM +0800, Sia Jee Heng wrote: > > The ACPI SPCR code has been used to enable console output for ARM64 and > > X86. The same code can be reused for RISC-V. > > > > Vendor will enable/disable the SPCR table in the firmware based on the > > platform design. However, in cases where the SPCR table is not usable, > > a kernel parameter could be used to specify the preferred console. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > --- > > arch/riscv/kernel/acpi.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c > > index e619edc8b0cc..5ec2fdf9e09f 100644 > > --- a/arch/riscv/kernel/acpi.c > > +++ b/arch/riscv/kernel/acpi.c > > @@ -18,6 +18,7 @@ > > #include <linux/io.h> > > #include <linux/memblock.h> > > #include <linux/pci.h> > > +#include <linux/serial_core.h> > > > > int acpi_noirq = 1; /* skip ACPI IRQ initialization */ > > int acpi_disabled = 1; > > @@ -151,6 +152,9 @@ void __init acpi_boot_table_init(void) > > if (!param_acpi_force) > > disable_acpi(); > > } > > + > > + if (!acpi_disabled) > > + acpi_parse_spcr(earlycon_acpi_spcr_enable, true); > > Both arm64 and loongarch call early_init_dt_scan_chosen_stdout() when > acpi_disabled and earlycon_acpi_spcr_enable are both true. Is that > not necessary for RISC-V? It is needed for device tree support. However, since this patch targets ACPI, that's why I didn't include a DT solution in this patch. I can submit a separate patch targeting DT-based earlycon if needed. Please let me know if you think otherwise. > > Thanks, > drew > > > } > > > > static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) > > -- > > 2.34.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-01-05 12:13 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-29 6:54 [RFC v1 0/1] Enable SPCR table for console output on RISC-V Sia Jee Heng 2023-12-29 6:54 ` Sia Jee Heng 2023-12-29 6:54 ` [RFC v1 1/1] RISC-V: ACPI: " Sia Jee Heng 2023-12-29 6:54 ` Sia Jee Heng 2024-01-02 15:39 ` Andrew Jones 2024-01-02 15:39 ` Andrew Jones 2024-01-05 12:12 ` JeeHeng Sia 2024-01-05 12:12 ` JeeHeng Sia
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