[PATCH RFC v2 00/23] Enable display cpuinfo to get the reset cause

[PATCH RFC v2 00/23] Enable display cpuinfo to get the reset cause

[Anand Moon]

All the Rockchip SoC support reset cauee like POR_RST, GLB_RST,
TSADC_RST, WD_RST by reading the clock reset unit register.

V2: with the feedback from Jonas Karlman and Quentin Schulz
    drop the inply for CONFIG_DISPLAY_CPUINFO as it defaault enabled.
    re-organized the code.

As pointed only as of now RK3328, RK3399 supports this feature for POR
and RST.

On RK3568 and RK3588 SoC it only return POR, for all the case of reboot 
and poweroff. I have tried to debug this issue, found Clock Reset Unit 
will bind to rockchip_sysreset to determine the reset cause.
if there is ant input on this please share.

I have update two new patches from u-boot-radxa, but with no success.

[0] https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3568.c#L2945

# dm tree # RK3568
 clk           5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c0000
 sysreset      0  [   ]   rockchip_sysreset     |   |-- sysreset
 reset         0  [ + ]   rockchip_reset        |   `-- reset

[1] https://elixir.bootlin.com/u-boot/v2024.07-rc3/source/drivers/clk/rockchip/clk_rk3588.c#L2006

# dm tree  # RK3588
 clk           5  [ + ]   rockchip_rk3588_cru   |-- clock-controller@fd7c0000
 sysreset      0  [   ]   rockchip_sysreset     |   |-- sysreset
 reset         0  [   ]   rockchip_reset        |   `-- reset


Tested on Rock64, Rock-3a, Rock-5b boards.

I have update few Rockchip SoC to verify this feature,
Only Build to since I dont have the hardware.

Thanks
-Anand

Anand Moon (21):
  rockchip: RK3328: Read the reset cause from clock reset unit for
    RK3328 SoC
  rockchip: RK3328: Enable display cpuinfo support on all boards
  rockchip: RK3399: Read the reset cause from clock reset unit for
    RK3399 SoC
  rockchip: RK3399: Enable display cpuinfo support on all boards
  arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD
  rockchip: RK3568: Read the reset cause from clock reset unit for
    RK356x SoC
  rockchip: RK3568: Enable display cpuinfo support on all boards
  rockchip: RK3588: Read the reset cause from clock reset unit for
    RK3588 SoC
  rockchip: RK3588: Enable display cpuinfo support on all boards
  rockchip: PX30: Read the reset cause from clock reset unit for PX30
    SoC
  rockchip: PX30: Enable display cpuinfo support on all boards
  rockchip: RK3288: Read the reset cause from clock reset unit for
    RK3288 SoC
  rockchip: RK3288: Enable display cpuinfo support on all boards
  rockchip: RK3308: Read the reset cause from clock reset unit for
    RK3308 SoC
  rockchip: RK3308: Enable display cpuinfo support on all boards
  rockchip: RK3368: Read the reset cause from clock reset unit for
    RK3368 SoC
  rockchip: RK3368: Enable display cpuinfo support on all boards
  rockchip: RV1108: Read the reset cause from clock reset unit for
    RV1108 SoC
  rockchip: RV1108: Enable display cpuinfo support on all boards
  rockchip: RV1126: Read the reset cause from clock reset unit for
    RV1126 SoC
  rockchip: RV1126: Enable display cpuinfo support on all boards

Andy Yan (1):
  sysreset: rockchip: use dev_read_addr_ptr get cru base

Kever Yang (1):
  sysreset: rockchip: use fst reset for ARM64 SOC

 arch/arm/include/asm/arch-rockchip/cru.h      | 14 +++++++++++++
 arch/arm/mach-rockchip/Makefile               |  3 ---
 arch/arm/mach-rockchip/cpu-info.c             | 20 +++++++++++++++++++
 configs/anbernic-rgxx3-rk3566_defconfig       |  1 -
 configs/bpi-r2-pro-rk3568_defconfig           |  1 -
 configs/chromebit_mickey_defconfig            |  1 -
 configs/chromebook_bob_defconfig              |  1 -
 configs/chromebook_jerry_defconfig            |  1 -
 configs/chromebook_kevin_defconfig            |  1 -
 configs/chromebook_minnie_defconfig           |  1 -
 configs/chromebook_speedy_defconfig           |  1 -
 configs/coolpi-4b-rk3588s_defconfig           |  1 -
 configs/coolpi-cm5-evb-rk3588_defconfig       |  1 -
 configs/elgin-rv1108_defconfig                |  1 -
 configs/evb-px30_defconfig                    |  1 -
 configs/evb-px5_defconfig                     |  1 -
 configs/evb-rk3308_defconfig                  |  1 -
 configs/evb-rk3328_defconfig                  |  1 -
 configs/evb-rk3568_defconfig                  |  1 -
 configs/evb-rk3588_defconfig                  |  1 -
 configs/evb-rv1108_defconfig                  |  1 -
 configs/firefly-px30_defconfig                |  1 -
 configs/geekbox_defconfig                     |  1 -
 configs/generic-rk3568_defconfig              |  1 -
 configs/generic-rk3588_defconfig              |  1 -
 configs/jaguar-rk3588_defconfig               |  1 -
 configs/lion-rk3368_defconfig                 |  1 -
 configs/lubancat-2-rk3568_defconfig           |  1 -
 configs/nanopc-t6-rk3588_defconfig            |  1 -
 configs/nanopi-r2c-plus-rk3328_defconfig      |  1 -
 configs/nanopi-r2c-rk3328_defconfig           |  1 -
 configs/nanopi-r2s-rk3328_defconfig           |  1 -
 configs/nanopi-r5c-rk3568_defconfig           |  1 -
 configs/nanopi-r5s-rk3568_defconfig           |  1 -
 configs/neu2-io-rv1126_defconfig              |  1 -
 configs/neu6a-io-rk3588_defconfig             |  1 -
 configs/neu6b-io-rk3588_defconfig             |  1 -
 configs/odroid-m1-rk3568_defconfig            |  1 -
 configs/orangepi-5-plus-rk3588_defconfig      |  1 -
 configs/orangepi-5-rk3588s_defconfig          |  1 -
 configs/orangepi-r1-plus-lts-rk3328_defconfig |  1 -
 configs/orangepi-r1-plus-rk3328_defconfig     |  1 -
 configs/pinetab2-rk3566_defconfig             |  1 -
 configs/px30-core-ctouch2-of10-px30_defconfig |  1 -
 configs/px30-core-ctouch2-px30_defconfig      |  1 -
 configs/px30-core-edimm2.2-px30_defconfig     |  1 -
 configs/quartz64-a-rk3566_defconfig           |  1 -
 configs/quartz64-b-rk3566_defconfig           |  1 -
 configs/quartzpro64-rk3588_defconfig          |  1 -
 configs/radxa-cm3-io-rk3566_defconfig         |  1 -
 configs/radxa-e25-rk3568_defconfig            |  1 -
 configs/ringneck-px30_defconfig               |  1 -
 configs/roc-cc-rk3308_defconfig               |  1 -
 configs/roc-cc-rk3328_defconfig               |  1 -
 configs/rock-3a-rk3568_defconfig              |  1 -
 configs/rock-pi-e-rk3328_defconfig            |  1 -
 configs/rock-pi-s-rk3308_defconfig            |  1 -
 configs/rock5a-rk3588s_defconfig              |  1 -
 configs/rock5b-rk3588_defconfig               |  1 -
 configs/rock64-rk3328_defconfig               |  1 -
 configs/sheep-rk3368_defconfig                |  1 -
 configs/sonoff-ihost-rv1126_defconfig         |  1 -
 configs/soquartz-blade-rk3566_defconfig       |  1 -
 configs/soquartz-cm4-rk3566_defconfig         |  1 -
 configs/soquartz-model-a-rk3566_defconfig     |  1 -
 configs/toybrick-rk3588_defconfig             |  1 -
 configs/turing-rk1-rk3588_defconfig           |  1 -
 drivers/sysreset/sysreset_rockchip.c          |  9 +++++++--
 68 files changed, 41 insertions(+), 69 deletions(-)

-- 
2.44.0

[PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3328 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 9778790f34..a1499e9652 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -13,6 +13,8 @@
 
 #if defined(CONFIG_ROCKCHIP_RK3288)
 # include <asm/arch-rockchip/cru_rk3288.h>
+#elif defined(CONFIG_ROCKCHIP_RK3328)
+#include <asm/arch-rockchip/cru_rk3328.h>
 #elif defined(CONFIG_ROCKCHIP_RK3399)
 # include <asm/arch-rockchip/cru_rk3399.h>
 #elif defined(CONFIG_ROCKCHIP_RK3568)
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index a62ff53c6a..86b0c02970 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -14,7 +14,9 @@
 
 char *get_reset_cause(void)
 {
-	struct rockchip_cru *cru = rockchip_get_cru();
+#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
+	struct rk3328_cru *cru = rockchip_get_cru();
+#endif
 	char *cause = NULL;
 
 	if (IS_ERR(cru))
-- 
2.44.0

Re: [PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RK3328 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 9778790f34..a1499e9652 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,6 +13,8 @@
> 
>  #if defined(CONFIG_ROCKCHIP_RK3288)
>  # include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3328)
> +#include <asm/arch-rockchip/cru_rk3328.h>

A single space character should be added between "#" and "include",
for consistency.

>  #elif defined(CONFIG_ROCKCHIP_RK3399)
>  # include <asm/arch-rockchip/cru_rk3399.h>
>  #elif defined(CONFIG_ROCKCHIP_RK3568)
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index a62ff53c6a..86b0c02970 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -14,7 +14,9 @@
> 
>  char *get_reset_cause(void)
>  {
> -	struct rockchip_cru *cru = rockchip_get_cru();
> +#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
> +	struct rk3328_cru *cru = rockchip_get_cru();
> +#endif
>  	char *cause = NULL;
> 
>  	if (IS_ERR(cru))

Re: [PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Kever Yang]

Hi Anand,

On 2024/5/31 22:18, Anand Moon wrote:
> From: Anand Moon<anand@edgeble.ai>
>
> Read the reset cause from clock reset unit for RK3328 SoC.
>
> Cc: Jagan Teki<jagan@edgeble.ai>
> Signed-off-by: Anand Moon<anand@edgeble.ai>
> Signed-off-by: Anand Moon<linux.amoon@gmail.com>
I thing one signature is enough for you, right?
> ---
>   arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>   arch/arm/mach-rockchip/cpu-info.c        | 4 +++-
>   2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> index 9778790f34..a1499e9652 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,6 +13,8 @@
>   
>   #if defined(CONFIG_ROCKCHIP_RK3288)
>   # include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3328)
> +#include <asm/arch-rockchip/cru_rk3328.h>
>   #elif defined(CONFIG_ROCKCHIP_RK3399)
>   # include <asm/arch-rockchip/cru_rk3399.h>
>   #elif defined(CONFIG_ROCKCHIP_RK3568)
> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
> index a62ff53c6a..86b0c02970 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -14,7 +14,9 @@
>   
>   char *get_reset_cause(void)
>   {
> -	struct rockchip_cru *cru = rockchip_get_cru();
> +#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
> +	struct rk3328_cru *cru = rockchip_get_cru();
> +#endif

I think we can use "rockchip_cru" for all the SoC with below define in 
cru_rk3568.h?

#define rockchip_cru rk3328_cru


Thanks,
- Kever
>   	char *cause = NULL;
>   
>   	if (IS_ERR(cru))

Re: [PATCH RFC v2 01/23] rockchip: RK3328: Read the reset cause from clock reset unit for RK3328 SoC

[Anand Moon]

Hi Kever,

On Tue, 16 Jul 2024 at 07:58, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Anand,
>
> On 2024/5/31 22:18, Anand Moon wrote:
>
> From: Anand Moon <anand@edgeble.ai>
>
> Read the reset cause from clock reset unit for RK3328 SoC.
>
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>
> I thing one signature is enough for you, right?

Ok, earlier the emails were bouncing back
>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
> index 9778790f34..a1499e9652 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -13,6 +13,8 @@
>
>  #if defined(CONFIG_ROCKCHIP_RK3288)
>  # include <asm/arch-rockchip/cru_rk3288.h>
> +#elif defined(CONFIG_ROCKCHIP_RK3328)
> +#include <asm/arch-rockchip/cru_rk3328.h>
>  #elif defined(CONFIG_ROCKCHIP_RK3399)
>  # include <asm/arch-rockchip/cru_rk3399.h>
>  #elif defined(CONFIG_ROCKCHIP_RK3568)
> diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
> index a62ff53c6a..86b0c02970 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -14,7 +14,9 @@
>
>  char *get_reset_cause(void)
>  {
> - struct rockchip_cru *cru = rockchip_get_cru();
> +#if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
> + struct rk3328_cru *cru = rockchip_get_cru();
> +#endif
>
> I think we can use "rockchip_cru" for all the SoC with below define in cru_rk3568.h?
>
> #define rockchip_cru rk3328_cru
>
Ok, I will follow this in the next version.
>
> Thanks,
> - Kever
Thanks
-Anand

[PATCH RFC v2 02/23] rockchip: RK3328: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3328 boards,
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/evb-rk3328_defconfig                  | 1 -
 configs/nanopi-r2c-plus-rk3328_defconfig      | 1 -
 configs/nanopi-r2c-rk3328_defconfig           | 1 -
 configs/nanopi-r2s-rk3328_defconfig           | 1 -
 configs/orangepi-r1-plus-lts-rk3328_defconfig | 1 -
 configs/orangepi-r1-plus-rk3328_defconfig     | 1 -
 configs/roc-cc-rk3328_defconfig               | 1 -
 configs/rock-pi-e-rk3328_defconfig            | 1 -
 configs/rock64-rk3328_defconfig               | 1 -
 9 files changed, 9 deletions(-)

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index bfb8522343..e1c2016cb3 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
index f311a0a80b..700ce47696 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 533dc1029f..a594f329bf 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 2591a9cc8a..c1d0a1f396 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 14cdbd813c..7e0b1b2773 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index 7fe58e7a14..4525c99ca2 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 91b9422e26..c1eb03c5e8 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 5cc54af3ca..bb99670b8c 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 9d77dfb709..836f18a806 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
-- 
2.44.0

[PATCH RFC v2 03/23] rockchip: RK3399: Read the reset cause from clock reset unit for RK3399 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3399 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 86b0c02970..e7cbcf5090 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -16,6 +16,8 @@ char *get_reset_cause(void)
 {
 #if IS_ENABLED(CONFIG_ROCKCHIP_RK3328)
 	struct rk3328_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
+	struct rockchip_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 04/23] rockchip: RK3399: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3399 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/chromebook_bob_defconfig   | 1 -
 configs/chromebook_kevin_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index acfe393410..2c1a8141c0 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -30,7 +30,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index 95fdb418d8..f6649804c7 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -31,7 +31,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 # CONFIG_SPL_FIT_SIGNATURE is not set
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-kevin.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BLOBLIST=y
-- 
2.44.0

[PATCH RFC v2 05/23] arm: rockchip: Enable display cpuinfo to be build with SPL_BUILD

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Changes help enable CONFIG_DISPLAY_CPUINFO to build with SPL_BUILD for
SoC RK356x and RK3588.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/mach-rockchip/Makefile | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c07bdaee4c..254c26034f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -23,9 +23,6 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 # meaning "turn it off".
 obj-y += boot_mode.o
 obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
-endif
-
-ifeq ($(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o
 endif
 
-- 
2.44.0

[PATCH RFC v2 06/23] rockchip: RK3568: Read the reset cause from clock reset unit for RK356x SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK356x SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index e7cbcf5090..e12f84a1d2 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -18,6 +18,8 @@ char *get_reset_cause(void)
 	struct rk3328_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3399)
 	struct rockchip_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
+	struct rk3568_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 07/23] rockchip: RK3568: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3568 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/anbernic-rgxx3-rk3566_defconfig   | 1 -
 configs/bpi-r2-pro-rk3568_defconfig       | 1 -
 configs/evb-rk3568_defconfig              | 1 -
 configs/generic-rk3568_defconfig          | 1 -
 configs/lubancat-2-rk3568_defconfig       | 1 -
 configs/nanopi-r5c-rk3568_defconfig       | 1 -
 configs/nanopi-r5s-rk3568_defconfig       | 1 -
 configs/odroid-m1-rk3568_defconfig        | 1 -
 configs/pinetab2-rk3566_defconfig         | 1 -
 configs/quartz64-a-rk3566_defconfig       | 1 -
 configs/quartz64-b-rk3566_defconfig       | 1 -
 configs/radxa-cm3-io-rk3566_defconfig     | 1 -
 configs/radxa-e25-rk3568_defconfig        | 1 -
 configs/rock-3a-rk3568_defconfig          | 1 -
 configs/soquartz-blade-rk3566_defconfig   | 1 -
 configs/soquartz-cm4-rk3566_defconfig     | 1 -
 configs/soquartz-model-a-rk3566_defconfig | 1 -
 17 files changed, 17 deletions(-)

diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index a03509bf46..95f7cf0739 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -21,7 +21,6 @@ CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-anbernic-rgxx3.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_RNG_SEED=y
 CONFIG_SPL_MAX_SIZE=0x40000
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
index eccc15a0ae..4955fd907c 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index 2076f55122..e6da8fd246 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index 66a33afbba..ba2d995cdc 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index 88593bfa70..384d0ecfc5 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index 4a6c320faf..b83796083d 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index 7ab12e619a..5d500963a2 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index b5263caff6..7bea6e6851 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig
index e46acf3a3b..1441feb796 100644
--- a/configs/pinetab2-rk3566_defconfig
+++ b/configs/pinetab2-rk3566_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-pinetab2-v2.0.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index 1ea8e0f40c..458d6d6e81 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -24,7 +24,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index f61b2c181a..029c184177 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 48c8fcf5a6..8d6990c403 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -15,7 +15,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index 496fee0e0a..2cfa34956d 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -18,7 +18,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 66ac2f6d7a..9ac9ef8827 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index 82910daf7c..3d5344e43a 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -18,7 +18,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index 5744f1baa8..99e5dbe4fc 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -18,7 +18,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index 920df9b622..656e0ef178 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -18,7 +18,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
-- 
2.44.0

[PATCH RFC v2 08/23] rockchip: RK3588: Read the reset cause from clock reset unit for RK3588 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3588 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index a1499e9652..19bd2b405b 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -19,6 +19,8 @@
 # include <asm/arch-rockchip/cru_rk3399.h>
 #elif defined(CONFIG_ROCKCHIP_RK3568)
 #include <asm/arch-rockchip/cru_rk3568.h>
+#elif defined(CONFIG_ROCKCHIP_RK3588)
+#include <asm/arch-rockchip/cru_rk3588.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index e12f84a1d2..113a03acdf 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -20,6 +20,8 @@ char *get_reset_cause(void)
 	struct rockchip_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
 	struct rk3568_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
+	struct rk3588_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 08/23] rockchip: RK3588: Read the reset cause from clock reset unit for RK3588 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RK3588 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index a1499e9652..19bd2b405b 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -19,6 +19,8 @@
>  # include <asm/arch-rockchip/cru_rk3399.h>
>  #elif defined(CONFIG_ROCKCHIP_RK3568)
>  #include <asm/arch-rockchip/cru_rk3568.h>

Although not related to this patch directly, single space character
should be added between "#" and "include", for consistency.

> +#elif defined(CONFIG_ROCKCHIP_RK3588)
> +#include <asm/arch-rockchip/cru_rk3588.h>

The same comment as above, bit this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index e12f84a1d2..113a03acdf 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -20,6 +20,8 @@ char *get_reset_cause(void)
>  	struct rockchip_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3568)
>  	struct rk3568_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
> +	struct rk3588_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

[PATCH RFC v2 09/23] rockchip: RK3588: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3588 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/coolpi-4b-rk3588s_defconfig      | 1 -
 configs/coolpi-cm5-evb-rk3588_defconfig  | 1 -
 configs/evb-rk3588_defconfig             | 1 -
 configs/generic-rk3588_defconfig         | 1 -
 configs/jaguar-rk3588_defconfig          | 1 -
 configs/nanopc-t6-rk3588_defconfig       | 1 -
 configs/neu6a-io-rk3588_defconfig        | 1 -
 configs/neu6b-io-rk3588_defconfig        | 1 -
 configs/orangepi-5-plus-rk3588_defconfig | 1 -
 configs/orangepi-5-rk3588s_defconfig     | 1 -
 configs/quartzpro64-rk3588_defconfig     | 1 -
 configs/rock5a-rk3588s_defconfig         | 1 -
 configs/rock5b-rk3588_defconfig          | 1 -
 configs/toybrick-rk3588_defconfig        | 1 -
 configs/turing-rk1-rk3588_defconfig      | 1 -
 15 files changed, 15 deletions(-)

diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig
index 3d45d939ab..b094224f6e 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig
index 5190d69c1c..382ee97fc9 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 1d5585677a..bfc505a4b7 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index 42bc2c9a76..ddb23b035b 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -17,7 +17,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index b69cf4cd05..712a936539 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -22,7 +22,6 @@ CONFIG_SPL_LOAD_FIT=y
 # CONFIG_BOOTMETH_VBE is not set
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CYCLIC=y
 CONFIG_SPL_MAX_SIZE=0x40000
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index 926267f93a..978c62aee6 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index ac281e6539..6f2765c640 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index c01e5fb0d0..13b542a752 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
index 138a633f32..c8c64bdeaf 100644
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -24,7 +24,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
index 33529d4cac..d71eb7c3f9 100644
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
index 06c5cff3ca..99422282bc 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index c09e6655f0..a64d8a071d 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index fc118cea7b..234bc76bf2 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -24,7 +24,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig
index 5a190357e4..bd33c648ed 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -16,7 +16,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig
index e6e1bda7ec..0ca33e95d7 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -19,7 +19,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
-- 
2.44.0

[PATCH RFC v2 10/23] rockchip: PX30: Read the reset cause from clock reset unit for PX30 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for PX30 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 19bd2b405b..7a69a839e6 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -21,6 +21,8 @@
 #include <asm/arch-rockchip/cru_rk3568.h>
 #elif defined(CONFIG_ROCKCHIP_RK3588)
 #include <asm/arch-rockchip/cru_rk3588.h>
+#elif defined(CONFIG_ROCKCHIP_PX30)
+#include <asm/arch-rockchip/cru_px30.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 113a03acdf..9be28754fd 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -22,6 +22,8 @@ char *get_reset_cause(void)
 	struct rk3568_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
 	struct rk3588_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_PX30)
+	struct px30_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 10/23] rockchip: PX30: Read the reset cause from clock reset unit for PX30 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for PX30 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 19bd2b405b..7a69a839e6 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -21,6 +21,8 @@
>  #include <asm/arch-rockchip/cru_rk3568.h>

Although not related to this patch directly, a single space character
should be added between "#" and "include", for consistency.

>  #elif defined(CONFIG_ROCKCHIP_RK3588)
>  #include <asm/arch-rockchip/cru_rk3588.h>

The same comment as above.

> +#elif defined(CONFIG_ROCKCHIP_PX30)
> +#include <asm/arch-rockchip/cru_px30.h>

The same comment as above, bit this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index 113a03acdf..9be28754fd 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -22,6 +22,8 @@ char *get_reset_cause(void)
>  	struct rk3568_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3588)
>  	struct rk3588_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_PX30)
> +	struct px30_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

[PATCH RFC v2 11/23] rockchip: PX30: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all PX30 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/evb-px30_defconfig                    | 1 -
 configs/firefly-px30_defconfig                | 1 -
 configs/px30-core-ctouch2-of10-px30_defconfig | 1 -
 configs/px30-core-ctouch2-px30_defconfig      | 1 -
 configs/px30-core-edimm2.2-px30_defconfig     | 1 -
 configs/ringneck-px30_defconfig               | 1 -
 6 files changed, 6 deletions(-)

diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 73a3c6120e..72b562ed69 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -32,7 +32,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 0a14b39366..2310c0bdc5 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index 87a39e115d..3c9b9b8493 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 7162c117be..3040fc5405 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 1182f60358..7431bedf7a 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -33,7 +33,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
 # CONFIG_CONSOLE_MUX is not set
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig
index 94179dca3a..f571eb6b11 100644
--- a/configs/ringneck-px30_defconfig
+++ b/configs/ringneck-px30_defconfig
@@ -21,7 +21,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/px30-ringneck-haikou.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
-- 
2.44.0

[PATCH RFC v2 12/23] rockchip: RK3288: Read the reset cause from clock reset unit for RK3288 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3288 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/mach-rockchip/cpu-info.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 9be28754fd..383aa3d2ee 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -24,6 +24,8 @@ char *get_reset_cause(void)
 	struct rk3588_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_PX30)
 	struct px30_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3288)
+	struct rockchip_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

[PATCH RFC v2 13/23] rockchip: RK3288: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3288 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/chromebit_mickey_defconfig  | 1 -
 configs/chromebook_jerry_defconfig  | 1 -
 configs/chromebook_minnie_defconfig | 1 -
 configs/chromebook_speedy_defconfig | 1 -
 4 files changed, 4 deletions(-)

diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index e5d805d7da..e1d31d0b4c 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 9bc59539dc..dba1466689 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -30,7 +30,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 26fa05e543..e6cf734b14 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 5deb09b28e..90364dfc48 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -31,7 +31,6 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_SPL_PAD_TO=0x7f8000
-- 
2.44.0

[PATCH RFC v2 14/23] rockchip: RK3308: Read the reset cause from clock reset unit for RK3308 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3308 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 7a69a839e6..6fe73ad0cc 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -23,6 +23,8 @@
 #include <asm/arch-rockchip/cru_rk3588.h>
 #elif defined(CONFIG_ROCKCHIP_PX30)
 #include <asm/arch-rockchip/cru_px30.h>
+#elif defined(CONFIG_ROCKCHIP_RK3308)
+#include <asm/arch-rockchip/cru_rk3308.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index 383aa3d2ee..dbc126c862 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -26,6 +26,8 @@ char *get_reset_cause(void)
 	struct px30_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3288)
 	struct rockchip_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
+	struct rk3308_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 14/23] rockchip: RK3308: Read the reset cause from clock reset unit for RK3308 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RK3308 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 7a69a839e6..6fe73ad0cc 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -23,6 +23,8 @@
>  #include <asm/arch-rockchip/cru_rk3588.h>

Although not related to this patch directly, a single space character
should be added between "#" and "include", for consistency.

>  #elif defined(CONFIG_ROCKCHIP_PX30)
>  #include <asm/arch-rockchip/cru_px30.h>

The same comment as above.

> +#elif defined(CONFIG_ROCKCHIP_RK3308)
> +#include <asm/arch-rockchip/cru_rk3308.h>

The same comment as above, bit this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index 383aa3d2ee..dbc126c862 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -26,6 +26,8 @@ char *get_reset_cause(void)
>  	struct px30_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3288)
>  	struct rockchip_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
> +	struct rk3308_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

[PATCH RFC v2 15/23] rockchip: RK3308: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3308 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/evb-rk3308_defconfig       | 1 -
 configs/roc-cc-rk3308_defconfig    | 1 -
 configs/rock-pi-s-rk3308_defconfig | 1 -
 3 files changed, 3 deletions(-)

diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index f4c2ea12ad..4622b2b2d4 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index 862ea4301f..cb5a868944 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index c15ba3d8a4..d888cfaa36 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -16,7 +16,6 @@ CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-- 
2.44.0

[PATCH RFC v2 16/23] rockchip: RK3368: Read the reset cause from clock reset unit for RK3368 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RK3368 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 6fe73ad0cc..9cdd960fb1 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -25,6 +25,8 @@
 #include <asm/arch-rockchip/cru_px30.h>
 #elif defined(CONFIG_ROCKCHIP_RK3308)
 #include <asm/arch-rockchip/cru_rk3308.h>
+#elif defined(CONFIG_ROCKCHIP_RK3368)
+#include <asm/arch-rockchip/cru_rk3368.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index dbc126c862..b9d2756a70 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -28,6 +28,8 @@ char *get_reset_cause(void)
 	struct rockchip_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
 	struct rk3308_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
+	struct rk3368_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 16/23] rockchip: RK3368: Read the reset cause from clock reset unit for RK3368 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RK3368 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 6fe73ad0cc..9cdd960fb1 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -25,6 +25,8 @@
>  #include <asm/arch-rockchip/cru_px30.h>

Although not related to this patch directly, a single space character
should be added between "#" and "include", for consistency.

>  #elif defined(CONFIG_ROCKCHIP_RK3308)
>  #include <asm/arch-rockchip/cru_rk3308.h>

The same comment as above.

> +#elif defined(CONFIG_ROCKCHIP_RK3368)
> +#include <asm/arch-rockchip/cru_rk3368.h>

The same comment as above, bit this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index dbc126c862..b9d2756a70 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -28,6 +28,8 @@ char *get_reset_cause(void)
>  	struct rockchip_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3308)
>  	struct rk3308_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
> +	struct rk3368_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

[PATCH RFC v2 17/23] rockchip: RK3368: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RK3368 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/evb-px5_defconfig      | 1 -
 configs/geekbox_defconfig      | 1 -
 configs/lion-rk3368_defconfig  | 1 -
 configs/sheep-rk3368_defconfig | 1 -
 4 files changed, 4 deletions(-)

diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index ccd3883153..9be143487e 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -37,7 +37,6 @@ CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index 8f4be79831..de526ae14d 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -15,7 +15,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-geekbox.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_REGMAP=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index a4a7f1a5cb..e5bcc13038 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -34,7 +34,6 @@ CONFIG_SPL_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_BOOTSTAGE_FDT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-lion-haikou.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x7f8000
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index a591b2741d..5e58877012 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -15,7 +15,6 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_DEBUG_UART=y
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-sheep.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_CMD_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-- 
2.44.0

[PATCH RFC v2 18/23] rockchip: RV1108: Read the reset cause from clock reset unit for RV1108 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RV1108 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index 9cdd960fb1..e886adf515 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -27,6 +27,8 @@
 #include <asm/arch-rockchip/cru_rk3308.h>
 #elif defined(CONFIG_ROCKCHIP_RK3368)
 #include <asm/arch-rockchip/cru_rk3368.h>
+#elif defined(CONFIG_ROCKCHIP_RV1108)
+#include <asm/arch-rockchip/cru_rv1108.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index b9d2756a70..b2cfdade13 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -30,6 +30,8 @@ char *get_reset_cause(void)
 	struct rk3308_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
 	struct rk3368_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
+	struct rv1108_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 18/23] rockchip: RV1108: Read the reset cause from clock reset unit for RV1108 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RV1108 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index 9cdd960fb1..e886adf515 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -27,6 +27,8 @@
>  #include <asm/arch-rockchip/cru_rk3308.h>

Although not related to this patch directly, a single space character
should be added between "#" and "include", for consistency.

>  #elif defined(CONFIG_ROCKCHIP_RK3368)
>  #include <asm/arch-rockchip/cru_rk3368.h>

The same comment as above.

> +#elif defined(CONFIG_ROCKCHIP_RV1108)
> +#include <asm/arch-rockchip/cru_rv1108.h>

The same comment as above, bit this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index b9d2756a70..b2cfdade13 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -30,6 +30,8 @@ char *get_reset_cause(void)
>  	struct rk3308_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RK3368)
>  	struct rk3368_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
> +	struct rv1108_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

[PATCH RFC v2 19/23] rockchip: RV1108: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RV1108 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/elgin-rv1108_defconfig | 1 -
 configs/evb-rv1108_defconfig   | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig
index 454ed9e0a6..1fffa99793 100644
--- a/configs/elgin-rv1108_defconfig
+++ b/configs/elgin-rv1108_defconfig
@@ -17,7 +17,6 @@ CONFIG_SYS_LOAD_ADDR=0x62000000
 CONFIG_DEBUG_UART=y
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_DEFAULT_FDT_FILE="rv1108-elgin-r1.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index 6204cb4b96..8bff3a99e5 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -14,7 +14,6 @@ CONFIG_SYS_LOAD_ADDR=0x62000000
 CONFIG_DEBUG_UART=y
 CONFIG_BOOTCOMMAND="sf probe;sf read 0x62000000 0x140800 0x500000;dcache off;go 0x62000000"
 CONFIG_DEFAULT_FDT_FILE="rv1108-evb.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_CMD_USB=y
-- 
2.44.0

[PATCH RFC v2 20/23] rockchip: RV1126: Read the reset cause from clock reset unit for RV1126 SoC

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Read the reset cause from clock reset unit for RV1126 SoC.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
 arch/arm/mach-rockchip/cpu-info.c        | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h
index e886adf515..e1a8d8adad 100644
--- a/arch/arm/include/asm/arch-rockchip/cru.h
+++ b/arch/arm/include/asm/arch-rockchip/cru.h
@@ -29,6 +29,8 @@
 #include <asm/arch-rockchip/cru_rk3368.h>
 #elif defined(CONFIG_ROCKCHIP_RV1108)
 #include <asm/arch-rockchip/cru_rv1108.h>
+#elif defined(CONFIG_ROCKCHIP_RV1126)
+#include <asm/arch-rockchip/cru_rv1126.h>
 #endif
 
 /* CRU_GLB_RST_ST */
diff --git a/arch/arm/mach-rockchip/cpu-info.c b/arch/arm/mach-rockchip/cpu-info.c
index b2cfdade13..cb4ac39884 100644
--- a/arch/arm/mach-rockchip/cpu-info.c
+++ b/arch/arm/mach-rockchip/cpu-info.c
@@ -32,6 +32,8 @@ char *get_reset_cause(void)
 	struct rk3368_cru *cru = rockchip_get_cru();
 #elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
 	struct rv1108_cru *cru = rockchip_get_cru();
+#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1126)
+	struct rv1126_cru *cru = rockchip_get_cru();
 #endif
 	char *cause = NULL;
 
-- 
2.44.0

Re: [PATCH RFC v2 20/23] rockchip: RV1126: Read the reset cause from clock reset unit for RV1126 SoC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Anand Moon <anand@edgeble.ai>
> 
> Read the reset cause from clock reset unit for RV1126 SoC.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Anand Moon <anand@edgeble.ai>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
>  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> b/arch/arm/include/asm/arch-rockchip/cru.h
> index e886adf515..e1a8d8adad 100644
> --- a/arch/arm/include/asm/arch-rockchip/cru.h
> +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> @@ -29,6 +29,8 @@
>  #include <asm/arch-rockchip/cru_rk3368.h>

Although not related to this patch directly, a single space character
should be added between "#" and "include", for consistency.

>  #elif defined(CONFIG_ROCKCHIP_RV1108)
>  #include <asm/arch-rockchip/cru_rv1108.h>

The same comment as above.

> +#elif defined(CONFIG_ROCKCHIP_RV1126)
> +#include <asm/arch-rockchip/cru_rv1126.h>

The same comment as above, but this time related to this patch.

>  #endif
> 
>  /* CRU_GLB_RST_ST */
> diff --git a/arch/arm/mach-rockchip/cpu-info.c
> b/arch/arm/mach-rockchip/cpu-info.c
> index b2cfdade13..cb4ac39884 100644
> --- a/arch/arm/mach-rockchip/cpu-info.c
> +++ b/arch/arm/mach-rockchip/cpu-info.c
> @@ -32,6 +32,8 @@ char *get_reset_cause(void)
>  	struct rk3368_cru *cru = rockchip_get_cru();
>  #elif IS_ENABLED(CONFIG_ROCKCHIP_RV1108)
>  	struct rv1108_cru *cru = rockchip_get_cru();
> +#elif IS_ENABLED(CONFIG_ROCKCHIP_RV1126)
> +	struct rv1126_cru *cru = rockchip_get_cru();
>  #endif
>  	char *cause = NULL;

Re: [PATCH RFC v2 20/23] rockchip: RV1126: Read the reset cause from clock reset unit for RV1126 SoC

[Anand Moon]

Hi Dragan,

On Sat, 1 Jun 2024 at 03:23, Dragan Simic <dsimic@manjaro.org> wrote:
>
> Hello Anand,
>
> On 2024-05-31 16:18, Anand Moon wrote:
> > From: Anand Moon <anand@edgeble.ai>
> >
> > Read the reset cause from clock reset unit for RV1126 SoC.
> >
> > Cc: Jagan Teki <jagan@edgeble.ai>
> > Signed-off-by: Anand Moon <anand@edgeble.ai>
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > ---
> >  arch/arm/include/asm/arch-rockchip/cru.h | 2 ++
> >  arch/arm/mach-rockchip/cpu-info.c        | 2 ++
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-rockchip/cru.h
> > b/arch/arm/include/asm/arch-rockchip/cru.h
> > index e886adf515..e1a8d8adad 100644
> > --- a/arch/arm/include/asm/arch-rockchip/cru.h
> > +++ b/arch/arm/include/asm/arch-rockchip/cru.h
> > @@ -29,6 +29,8 @@
> >  #include <asm/arch-rockchip/cru_rk3368.h>
>
> Although not related to this patch directly, a single space character
> should be added between "#" and "include", for consistency.
>
Not sure of this.
> >  #elif defined(CONFIG_ROCKCHIP_RV1108)
> >  #include <asm/arch-rockchip/cru_rv1108.h>
>
> The same comment as above.
>
> > +#elif defined(CONFIG_ROCKCHIP_RV1126)
> > +#include <asm/arch-rockchip/cru_rv1126.h>
>
> The same comment as above, but this time related to this patch.
>
> >  #endif

Let me check this again if needed. I will update in the next version.

Thanks
-Anand

[PATCH RFC v2 21/23] rockchip: RV1126: Enable display cpuinfo support on all boards

[Anand Moon]

From: Anand Moon <anand@edgeble.ai>

Enable DISPLAY_CPUINFO options to support on all RV1126 boards.
Its used to determine the reset cause of the board.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 configs/neu2-io-rv1126_defconfig      | 1 -
 configs/sonoff-ihost-rv1126_defconfig | 1 -
 2 files changed, 2 deletions(-)

diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index 2a4c9b45a0..0bca5dfffb 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -16,7 +16,6 @@ CONFIG_DEBUG_UART=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig
index 4890644c7e..aa77ff3be4 100644
--- a/configs/sonoff-ihost-rv1126_defconfig
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -17,7 +17,6 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
-- 
2.44.0

[PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Anand Moon]

From: Kever Yang <kever.yang@rock-chips.com>

Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
 drivers/sysreset/sysreset_rockchip.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
index f353f9b4c7..17aa191349 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
 
 	switch (type) {
 	case SYSRESET_WARM:
+#ifdef CONFIG_ARM64
+		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
+		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
+#else
 		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
+#endif
 		break;
 	case SYSRESET_COLD:
 		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
-- 
2.44.0

Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Jonas Karlman]

Hi Anand and Kever,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Kever Yang <kever.yang@rock-chips.com>
> 
> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

What is this trying to fix? And what SoCs is affected?

My arm64 RK SoCs seem to reset using warm reset (second global reset).

> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>  drivers/sysreset/sysreset_rockchip.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
> index f353f9b4c7..17aa191349 100644
> --- a/drivers/sysreset/sysreset_rockchip.c
> +++ b/drivers/sysreset/sysreset_rockchip.c
> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
>  
>  	switch (type) {
>  	case SYSRESET_WARM:
> +#ifdef CONFIG_ARM64
> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> +#else
>  		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> +#endif

If this is needed maybe use something like this and let it fall through
to SYSRESET_COLD?

  if (!IS_ENABLED(CONFIG_ARM64)) {
	writel(0xeca8, cru_base + offset->glb_srst_snd_value);
	break;
  }

Regards,
Jonas

>  		break;
>  	case SYSRESET_COLD:
>  		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);

Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Anand Moon]

Hi Jonas

On Fri, 31 May 2024 at 22:14, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Anand and Kever,
>
> On 2024-05-31 16:18, Anand Moon wrote:
> > From: Kever Yang <kever.yang@rock-chips.com>
> >
> > Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
>
> What is this trying to fix? And what SoCs is affected?
>
> My arm64 RK SoCs seem to reset using warm reset (second global reset).
>
I found this patch related to CRU so it was added in this series.
My goal is to test all the remaining SoC and see if any thing is missing
in my testing.

> >
> > Cc: Jagan Teki <jagan@edgeble.ai>
> > Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> > ---
> >  drivers/sysreset/sysreset_rockchip.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
> > index f353f9b4c7..17aa191349 100644
> > --- a/drivers/sysreset/sysreset_rockchip.c
> > +++ b/drivers/sysreset/sysreset_rockchip.c
> > @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
> >
> >       switch (type) {
> >       case SYSRESET_WARM:
> > +#ifdef CONFIG_ARM64
> > +             /* Rockchip 64bit SOC need fst reset for cpu reset entry */
> > +             writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> > +#else
> >               writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> > +#endif
>
> If this is needed maybe use something like this and let it fall through
> to SYSRESET_COLD?
>
>   if (!IS_ENABLED(CONFIG_ARM64)) {
>         writel(0xeca8, cru_base + offset->glb_srst_snd_value);
>         break;
>   }
>

Ok I will update this in next version

> Regards,
> Jonas
Thanks
-Anand

Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Kever Yang]

On 2024/6/1 00:44, Jonas Karlman wrote:
> Hi Anand and Kever,
>
> On 2024-05-31 16:18, Anand Moon wrote:
>> From: Kever Yang <kever.yang@rock-chips.com>
>>
>> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
> What is this trying to fix? And what SoCs is affected?

Both fst and snd softreset are available for SoCs, but the fst reset 
more thing.

This commit msg is about: in some case the CPU entry may change after 
system boot,

eg. the wakeup code for deep sleep mode(which may power off) is locate 
at a different address;

with fst reset, the CPU entry is reset to the one bootRom used but the 
snd reset can not.

All the mass produced product with ARM64 SoCs are using the first global 
reset for warn reset now.


Thanks,
- Kever
> My arm64 RK SoCs seem to reset using warm reset (second global reset).
>
>> Cc: Jagan Teki <jagan@edgeble.ai>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>   drivers/sysreset/sysreset_rockchip.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
>> index f353f9b4c7..17aa191349 100644
>> --- a/drivers/sysreset/sysreset_rockchip.c
>> +++ b/drivers/sysreset/sysreset_rockchip.c
>> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
>>   
>>   	switch (type) {
>>   	case SYSRESET_WARM:
>> +#ifdef CONFIG_ARM64
>> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
>> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
>> +#else
>>   		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
>> +#endif
> If this is needed maybe use something like this and let it fall through
> to SYSRESET_COLD?
>
>    if (!IS_ENABLED(CONFIG_ARM64)) {
> 	writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> 	break;
>    }
>
> Regards,
> Jonas
>
>>   		break;
>>   	case SYSRESET_COLD:
>>   		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);

Re: [PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Dragan Simic]

Hello Anand,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Kever Yang <kever.yang@rock-chips.com>
> 
> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.
> 
> Cc: Jagan Teki <jagan@edgeble.ai>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>  drivers/sysreset/sysreset_rockchip.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/sysreset/sysreset_rockchip.c
> b/drivers/sysreset/sysreset_rockchip.c
> index f353f9b4c7..17aa191349 100644
> --- a/drivers/sysreset/sysreset_rockchip.c
> +++ b/drivers/sysreset/sysreset_rockchip.c
> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev,
> enum sysreset_t type)
> 
>  	switch (type) {
>  	case SYSRESET_WARM:
> +#ifdef CONFIG_ARM64
> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */

s/Rockchip 64bit SOC need fst reset for cpu reset entry
  /Rockchip 64-bit SoCs need FST reset for CPU reset entry/

> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> +#else
>  		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> +#endif
>  		break;
>  	case SYSRESET_COLD:
>  		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);

[PATCH RFC v2 23/23] sysreset: rockchip: use dev_read_addr_ptr get cru base

[Anand Moon]

From: Andy Yan <andy.yan@rock-chips.com>

Use system api dev_read_addr_ptr to get cru reg base,
rather than rockchip private api rockchip_get_cru, which
will be cleanup later.

Cc: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
 drivers/sysreset/sysreset_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
index 17aa191349..df6422c08b 100644
--- a/drivers/sysreset/sysreset_rockchip.c
+++ b/drivers/sysreset/sysreset_rockchip.c
@@ -8,14 +8,14 @@
 #include <errno.h>
 #include <sysreset.h>
 #include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/cru_rk3328.h>
+#include <asm/arch-rockchip/cru.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <linux/err.h>
 
 int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct sysreset_reg *offset = dev_get_priv(dev);
-	unsigned long cru_base = (unsigned long)rockchip_get_cru();
+	unsigned long cru_base = (unsigned long)dev_read_addr_ptr(dev->parent);
 
 	if (IS_ERR_VALUE(cru_base))
 		return (int)cru_base;
-- 
2.44.0