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From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Cleber Rosa" <crosa@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
	"Beraldo Leal" <bleal@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<yunlin.tang@aspeedtech.com>
Subject: [PATCH v5 14/17] aspeed: Add an AST2700 eval board
Date: Tue, 4 Jun 2024 13:44:35 +0800	[thread overview]
Message-ID: <20240604054438.3424349-15-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20240604054438.3424349-1-jamin_lin@aspeedtech.com>

AST2700 CPU is ARM Cortex-A35 which is 64 bits.
Add TARGET_AARCH64 to build this machine.

According to the design of ast2700, it has a bootmcu(riscv-32) which
is used for executing SPL.
Then, CPUs(cortex-a35) execute u-boot, kernel and rofs.

Currently, qemu not support emulate two CPU architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 93ca87fda2..40dc0e4c76 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -178,6 +178,12 @@ struct AspeedMachineState {
 #define AST2600_EVB_HW_STRAP1 0x000000C0
 #define AST2600_EVB_HW_STRAP2 0x00000003
 
+#ifdef TARGET_AARCH64
+/* AST2700 evb hardware value */
+#define AST2700_EVB_HW_STRAP1 0x000000C0
+#define AST2700_EVB_HW_STRAP2 0x00000003
+#endif
+
 /* Tacoma hardware value */
 #define TACOMA_BMC_HW_STRAP1  0x00000000
 #define TACOMA_BMC_HW_STRAP2  0x00000040
@@ -1588,6 +1594,26 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
     aspeed_machine_class_init_cpus_defaults(mc);
 }
 
+#ifdef TARGET_AARCH64
+static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->desc = "Aspeed AST2700 EVB (Cortex-A35)";
+    amc->soc_name  = "ast2700-a0";
+    amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+    amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+    amc->fmc_model = "w25q01jvq";
+    amc->spi_model = "w25q512jv";
+    amc->num_cs    = 2;
+    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+    amc->uart_default = ASPEED_DEV_UART12;
+    mc->default_ram_size = 1 * GiB;
+    aspeed_machine_class_init_cpus_defaults(mc);
+}
+#endif
+
 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
                                                      void *data)
 {
@@ -1711,6 +1737,12 @@ static const TypeInfo aspeed_machine_types[] = {
         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
         .parent         = TYPE_ASPEED_MACHINE,
         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
+#ifdef TARGET_AARCH64
+    }, {
+        .name          = MACHINE_TYPE_NAME("ast2700-evb"),
+        .parent        = TYPE_ASPEED_MACHINE,
+        .class_init    = aspeed_machine_ast2700_evb_class_init,
+#endif
     }, {
         .name          = TYPE_ASPEED_MACHINE,
         .parent        = TYPE_MACHINE,
-- 
2.25.1


  parent reply	other threads:[~2024-06-04  5:47 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-04  5:44 [PATCH v5 00/17] Add AST2700 support Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 01/17] aspeed/wdt: " Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 02/17] aspeed/sli: " Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 03/17] aspeed/sdmc: remove redundant macros Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 04/17] aspeed/sdmc: fix coding style Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 05/17] aspeed/sdmc: Add AST2700 support Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  6:10   ` Cédric Le Goater
2024-06-04  5:44 ` [PATCH v5 06/17] aspeed/smc: correct device description Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 07/17] aspeed/smc: support dma start length and 1 byte length unit Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 08/17] aspeed/smc: support 64 bits dma dram address Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 09/17] aspeed/smc: support different memory region ops for SMC flash region Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  6:11   ` Cédric Le Goater
2024-06-04  5:44 ` [PATCH v5 10/17] aspeed/smc: Add AST2700 support Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  6:12   ` Cédric Le Goater
2024-06-04  5:44 ` [PATCH v5 11/17] aspeed/scu: " Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 12/17] aspeed/intc: " Jamin Lin via
2024-06-04  7:18   ` Cédric Le Goater
2024-06-04  5:44 ` [PATCH v5 13/17] aspeed/soc: " Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04  6:17   ` Cédric Le Goater
2025-01-30 15:13   ` Philippe Mathieu-Daudé
2025-02-03  7:28     ` Jamin Lin
2025-02-03  7:43       ` Jamin Lin
2025-02-03 16:40         ` Philippe Mathieu-Daudé
2025-02-04  3:22           ` Jamin Lin
2024-06-04  5:44 ` Jamin Lin via [this message]
2024-06-04  5:44 ` [PATCH v5 15/17] aspeed/soc: fix incorrect dram size for AST2700 Jamin Lin via
2024-06-04  6:13   ` Cédric Le Goater
2024-06-04  5:44 ` [PATCH v5 16/17] test/avocado/machine_aspeed.py: Add AST2700 test case Jamin Lin via
2024-06-04  5:44 ` [PATCH v5 17/17] docs:aspeed: Add AST2700 Evaluation board Jamin Lin via
2024-06-04  5:44   ` Jamin Lin via
2024-06-04 11:51 ` [PATCH v5 00/17] Add AST2700 support Cédric Le Goater
2024-06-05  0:40   ` Jamin Lin
2024-06-10  9:23 ` Cédric Le Goater

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