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From: Conor Dooley <conor.dooley@microchip.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: <linux-riscv@lists.infradead.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>, <linux-kernel@vger.kernel.org>,
	Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v2 3/3] riscv: Call riscv_user_isa_enable() only on the boot hart
Date: Fri, 14 Jun 2024 11:32:44 +0100	[thread overview]
Message-ID: <20240614-ambition-machine-e7ece59835b2@wendy> (raw)
In-Reply-To: <20240613171447.3176616-4-samuel.holland@sifive.com>


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On Thu, Jun 13, 2024 at 10:14:41AM -0700, Samuel Holland wrote:
> Now that the [ms]envcfg CSR value is maintained per thread, not per
> hart, riscv_user_isa_enable() only needs to be called once during boot,
> to set the value for the init task. This also allows it to be marked as
> __init. riscv_isa_extension_check() sets any_cpu_has_zicboz, so it also
> needs to be marked __init; it could have had this annotation already.
> 
> Reviewed-by: Deepak Gupta <debug@rivosinc.com>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: <linux-riscv@lists.infradead.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>, <linux-kernel@vger.kernel.org>,
	Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v2 3/3] riscv: Call riscv_user_isa_enable() only on the boot hart
Date: Fri, 14 Jun 2024 11:32:44 +0100	[thread overview]
Message-ID: <20240614-ambition-machine-e7ece59835b2@wendy> (raw)
In-Reply-To: <20240613171447.3176616-4-samuel.holland@sifive.com>

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On Thu, Jun 13, 2024 at 10:14:41AM -0700, Samuel Holland wrote:
> Now that the [ms]envcfg CSR value is maintained per thread, not per
> hart, riscv_user_isa_enable() only needs to be called once during boot,
> to set the value for the init task. This also allows it to be marked as
> __init. riscv_isa_extension_check() sets any_cpu_has_zicboz, so it also
> needs to be marked __init; it could have had this annotation already.
> 
> Reviewed-by: Deepak Gupta <debug@rivosinc.com>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


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  reply	other threads:[~2024-06-14 10:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-13 17:14 [PATCH v2 0/3] riscv: Per-thread envcfg CSR support Samuel Holland
2024-06-13 17:14 ` Samuel Holland
2024-06-13 17:14 ` [PATCH v2 1/3] riscv: Enable cbo.zero only when all harts support Zicboz Samuel Holland
2024-06-13 17:14   ` Samuel Holland
2024-06-14 10:31   ` Conor Dooley
2024-06-14 10:31     ` Conor Dooley
2024-06-13 17:14 ` [PATCH v2 2/3] riscv: Add support for per-thread envcfg CSR values Samuel Holland
2024-06-13 17:14   ` Samuel Holland
2024-06-13 17:14 ` [PATCH v2 3/3] riscv: Call riscv_user_isa_enable() only on the boot hart Samuel Holland
2024-06-13 17:14   ` Samuel Holland
2024-06-14 10:32   ` Conor Dooley [this message]
2024-06-14 10:32     ` Conor Dooley
2024-06-21 12:54 ` [PATCH v2 0/3] riscv: Per-thread envcfg CSR support Andrew Jones
2024-06-21 12:54   ` Andrew Jones

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