Re: [PATCH v2 0/3] riscv: Per-thread envcfg CSR support

From: Andrew Jones <ajones@ventanamicro.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Conor Dooley <conor@kernel.org>,
	linux-kernel@vger.kernel.org, Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v2 0/3] riscv: Per-thread envcfg CSR support
Date: Fri, 21 Jun 2024 14:54:43 +0200	[thread overview]
Message-ID: <20240621-368af6395900f29559358915@orel> (raw)
In-Reply-To: <20240613171447.3176616-1-samuel.holland@sifive.com>

On Thu, Jun 13, 2024 at 10:14:38AM GMT, Samuel Holland wrote:
> This series (or equivalent) is a prerequisite for both user-mode pointer
> masking and CFI support, as those are per-thread features are controlled
> by fields in the envcfg CSR. These patches are based on v1 of the
> pointer masking series[1], with significant input from both Deepak and
> Andrew. By sending this as a separate series, hopefully we can converge
> on a single implementation of this functionality.
> 
> [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/
> 
> Changes in v2:
>  - Rebase on riscv/linux.git for-next
> 
> Samuel Holland (3):
>   riscv: Enable cbo.zero only when all harts support Zicboz
>   riscv: Add support for per-thread envcfg CSR values
>   riscv: Call riscv_user_isa_enable() only on the boot hart
>

For the series,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew

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