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From: Cheng Ming Lin <linchengming884@gmail.com>
To: miquel.raynal@bootlin.com, vigneshr@ti.com,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw,
	Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: [PATCH v2 0/2] Add fixups for two-plane serial NAND flash
Date: Thu, 18 Jul 2024 15:53:54 +0800	[thread overview]
Message-ID: <20240718075356.488253-1-linchengming884@gmail.com> (raw)

From: Cheng Ming Lin <chengminglin@mxic.com.tw>

Macronix serial NAND flash with a two-plane structure
requires insertion of Plane Select bit into the column
address during the write_to_cache operation.

Additionally, for MX35{U,F}2G14AC, insertion of Plane
Select bit into the column address is required during
the read_from_cache operation.

These flashes have been validated on Xilinx zynq-picozed
board which included Macronix SPI Host.

Cheng Ming Lin (2):
  mtd: spinand: Add fixups for spinand
  mtd: spinand: macronix: Fixups for Plane Select bit

 drivers/mtd/nand/spi/core.c     |  7 ++++
 drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++---
 include/linux/mtd/spinand.h     | 17 +++++++++
 3 files changed, 84 insertions(+), 6 deletions(-)

-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Cheng Ming Lin <linchengming884@gmail.com>
To: miquel.raynal@bootlin.com, vigneshr@ti.com,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw,
	Cheng Ming Lin <chengminglin@mxic.com.tw>
Subject: [PATCH v2 0/2] Add fixups for two-plane serial NAND flash
Date: Thu, 18 Jul 2024 15:53:54 +0800	[thread overview]
Message-ID: <20240718075356.488253-1-linchengming884@gmail.com> (raw)

From: Cheng Ming Lin <chengminglin@mxic.com.tw>

Macronix serial NAND flash with a two-plane structure
requires insertion of Plane Select bit into the column
address during the write_to_cache operation.

Additionally, for MX35{U,F}2G14AC, insertion of Plane
Select bit into the column address is required during
the read_from_cache operation.

These flashes have been validated on Xilinx zynq-picozed
board which included Macronix SPI Host.

Cheng Ming Lin (2):
  mtd: spinand: Add fixups for spinand
  mtd: spinand: macronix: Fixups for Plane Select bit

 drivers/mtd/nand/spi/core.c     |  7 ++++
 drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++---
 include/linux/mtd/spinand.h     | 17 +++++++++
 3 files changed, 84 insertions(+), 6 deletions(-)

-- 
2.25.1


             reply	other threads:[~2024-07-18  7:55 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-18  7:53 Cheng Ming Lin [this message]
2024-07-18  7:53 ` [PATCH v2 0/2] Add fixups for two-plane serial NAND flash Cheng Ming Lin
2024-07-18  7:53 ` [PATCH v2 1/2] mtd: spinand: Add fixups for spinand Cheng Ming Lin
2024-07-18  7:53   ` Cheng Ming Lin
2024-07-18  7:53 ` [PATCH v2 2/2] mtd: spinand: macronix: Fixups for Plane Select bit Cheng Ming Lin
2024-07-18  7:53   ` Cheng Ming Lin
2024-08-12  8:56 ` [PATCH v2 0/2] Add fixups for two-plane serial NAND flash Miquel Raynal
2024-08-12  8:56   ` Miquel Raynal
2024-08-13  6:02   ` Cheng Ming Lin
2024-08-13  6:02     ` Cheng Ming Lin
2024-08-23 15:48     ` Miquel Raynal
2024-08-23 15:48       ` Miquel Raynal

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