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From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	 Jernej Skrabec <jernej.skrabec@gmail.com>,
	 Samuel Holland <samuel@sholland.org>,
	 Samuel Holland <samuel.holland@sifive.com>,
	 Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	 Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
	 Andy Chiu <andy.chiu@sifive.com>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	 Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	 linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	 Charlie Jenkins <charlie@rivosinc.com>,
	 Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v7 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
Date: Wed, 24 Jul 2024 12:13:54 -0700	[thread overview]
Message-ID: <20240724-xtheadvector-v7-3-b741910ada3e@rivosinc.com> (raw)
In-Reply-To: <20240724-xtheadvector-v7-0-b741910ada3e@rivosinc.com>

The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..6367112e614a 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,8 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

-- 
2.44.0


WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	 Jernej Skrabec <jernej.skrabec@gmail.com>,
	 Samuel Holland <samuel@sholland.org>,
	 Samuel Holland <samuel.holland@sifive.com>,
	 Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
	 Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
	 Andy Chiu <andy.chiu@sifive.com>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	 Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
	 linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	 Charlie Jenkins <charlie@rivosinc.com>,
	 Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v7 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree
Date: Wed, 24 Jul 2024 12:13:54 -0700	[thread overview]
Message-ID: <20240724-xtheadvector-v7-3-b741910ada3e@rivosinc.com> (raw)
In-Reply-To: <20240724-xtheadvector-v7-0-b741910ada3e@rivosinc.com>

The D1/D1s SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe0..6367112e614a 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,8 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

-- 
2.44.0


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  parent reply	other threads:[~2024-07-24 19:14 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-24 19:13 [PATCH v7 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins [this message]
2024-07-24 19:13   ` [PATCH v7 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-07-24 19:13   ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-07-24 19:14   ` Charlie Jenkins
2024-07-25  3:23   ` Palmer Dabbelt
2024-07-25  3:23     ` Palmer Dabbelt
2024-07-25  4:17     ` Charlie Jenkins
2024-07-25  4:17       ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-07-24 19:14   ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-07-24 19:14   ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-07-24 19:14   ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-07-24 19:14   ` Charlie Jenkins

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