From: Charlie Jenkins <charlie@rivosinc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Conor Dooley <conor@kernel.org>,
robh@kernel.org, krzk+dt@kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, jszhang@kernel.org, wens@csie.org,
jernej.skrabec@gmail.com, samuel@sholland.org,
samuel.holland@sifive.com, corbet@lwn.net, shuah@kernel.org,
guoren@kernel.org, Evan Green <evan@rivosinc.com>,
andy.chiu@sifive.com, jrtc27@jrtc27.com, ajones@ventanamicro.com,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v7 09/13] riscv: vector: Support xtheadvector save/restore
Date: Wed, 24 Jul 2024 21:17:16 -0700 [thread overview]
Message-ID: <ZqHRzAI0O+zsZd3A@ghost> (raw)
In-Reply-To: <mhng-28424e23-c9b4-407e-97d8-9dbb09101781@palmer-ri-x1c9>
On Wed, Jul 24, 2024 at 08:23:27PM -0700, Palmer Dabbelt wrote:
> On Wed, 24 Jul 2024 12:14:00 PDT (-0700), Charlie Jenkins wrote:
> > Use alternatives to add support for xtheadvector vector save/restore
> > routines.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> b4 isn't applying this, either on top of your last patch set or rc1 -- the
> base commit in the header isn't a hash I have, so I'm not sure where it's
> mean to apply to.
>
> Also...
>
> > ---
> > arch/riscv/include/asm/csr.h | 6 +
> > arch/riscv/include/asm/switch_to.h | 2 +-
> > arch/riscv/include/asm/vector.h | 225 +++++++++++++++++++++++++--------
> > arch/riscv/kernel/cpufeature.c | 5 +-
> > arch/riscv/kernel/kernel_mode_vector.c | 8 +-
> > arch/riscv/kernel/process.c | 4 +-
> > arch/riscv/kernel/signal.c | 6 +-
> > arch/riscv/kernel/vector.c | 12 +-
> > 8 files changed, 198 insertions(+), 70 deletions(-)
>
> [...]
>
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index bf25215bad24..cb48092fdc5d 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -845,10 +845,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
> > riscv_isa_set_ext(ext, source_isa);
> > }
> >
> > -<<<<<<< HEAD
> > riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
> > -=======
> > ->>>>>>> 0f260ac829ca (riscv: Extend cpufeature.c to detect vendor extensions)
> > riscv_fill_cpu_vendor_ext(cpu_node, cpu);
> >
> > of_node_put(cpu_node);
>
> This chunk isn't applying, and it's got a conflict marker in there. So I
> think that means something's gone off the rails?
I really messed that up... Okay I sent a new version that is based off
of your for-next that should work?
- Charlie
WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Conor Dooley <conor@kernel.org>,
robh@kernel.org, krzk+dt@kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, jszhang@kernel.org, wens@csie.org,
jernej.skrabec@gmail.com, samuel@sholland.org,
samuel.holland@sifive.com, corbet@lwn.net, shuah@kernel.org,
guoren@kernel.org, Evan Green <evan@rivosinc.com>,
andy.chiu@sifive.com, jrtc27@jrtc27.com, ajones@ventanamicro.com,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v7 09/13] riscv: vector: Support xtheadvector save/restore
Date: Wed, 24 Jul 2024 21:17:16 -0700 [thread overview]
Message-ID: <ZqHRzAI0O+zsZd3A@ghost> (raw)
In-Reply-To: <mhng-28424e23-c9b4-407e-97d8-9dbb09101781@palmer-ri-x1c9>
On Wed, Jul 24, 2024 at 08:23:27PM -0700, Palmer Dabbelt wrote:
> On Wed, 24 Jul 2024 12:14:00 PDT (-0700), Charlie Jenkins wrote:
> > Use alternatives to add support for xtheadvector vector save/restore
> > routines.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> b4 isn't applying this, either on top of your last patch set or rc1 -- the
> base commit in the header isn't a hash I have, so I'm not sure where it's
> mean to apply to.
>
> Also...
>
> > ---
> > arch/riscv/include/asm/csr.h | 6 +
> > arch/riscv/include/asm/switch_to.h | 2 +-
> > arch/riscv/include/asm/vector.h | 225 +++++++++++++++++++++++++--------
> > arch/riscv/kernel/cpufeature.c | 5 +-
> > arch/riscv/kernel/kernel_mode_vector.c | 8 +-
> > arch/riscv/kernel/process.c | 4 +-
> > arch/riscv/kernel/signal.c | 6 +-
> > arch/riscv/kernel/vector.c | 12 +-
> > 8 files changed, 198 insertions(+), 70 deletions(-)
>
> [...]
>
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index bf25215bad24..cb48092fdc5d 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -845,10 +845,7 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
> > riscv_isa_set_ext(ext, source_isa);
> > }
> >
> > -<<<<<<< HEAD
> > riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
> > -=======
> > ->>>>>>> 0f260ac829ca (riscv: Extend cpufeature.c to detect vendor extensions)
> > riscv_fill_cpu_vendor_ext(cpu_node, cpu);
> >
> > of_node_put(cpu_node);
>
> This chunk isn't applying, and it's got a conflict marker in there. So I
> think that means something's gone off the rails?
I really messed that up... Okay I sent a new version that is based off
of your for-next that should work?
- Charlie
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next prev parent reply other threads:[~2024-07-25 4:17 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-24 19:13 [PATCH v7 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:13 ` [PATCH v7 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-07-24 19:13 ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-07-24 19:14 ` Charlie Jenkins
2024-07-25 3:23 ` Palmer Dabbelt
2024-07-25 3:23 ` Palmer Dabbelt
2024-07-25 4:17 ` Charlie Jenkins [this message]
2024-07-25 4:17 ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-07-24 19:14 ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-07-24 19:14 ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-07-24 19:14 ` Charlie Jenkins
2024-07-24 19:14 ` [PATCH v7 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-07-24 19:14 ` Charlie Jenkins
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