From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: kernel test robot <lkp@intel.com>
Cc: Manivannan Sadhasivam via B4 Relay
<devnull+manivannan.sadhasivam.linaro.org@kernel.org>,
Bjorn Helgaas <helgaas@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
oe-kbuild-all@lists.linux.dev, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
lukas@wunner.de, mika.westerberg@linux.intel.com,
Hsin-Yi Wang <hsinyi@chromium.org>
Subject: Re: [PATCH v5 2/4] PCI: Rename pci_bridge_d3_possible() to pci_bridge_d3_allowed()
Date: Mon, 5 Aug 2024 18:56:53 +0530 [thread overview]
Message-ID: <20240805132653.GB7274@thinkpad> (raw)
In-Reply-To: <202408031855.TEPJlfzl-lkp@intel.com>
On Sat, Aug 03, 2024 at 07:03:56PM +0800, kernel test robot wrote:
> Hi Manivannan,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on 705c1da8fa4816fb0159b5602fef1df5946a3ee2]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Manivannan-Sadhasivam-via-B4-Relay/PCI-portdrv-Make-use-of-pci_dev-bridge_d3-for-checking-the-D3-possibility/20240803-074434
> base: 705c1da8fa4816fb0159b5602fef1df5946a3ee2
> patch link: https://lore.kernel.org/r/20240802-pci-bridge-d3-v5-2-2426dd9e8e27%40linaro.org
> patch subject: [PATCH v5 2/4] PCI: Rename pci_bridge_d3_possible() to pci_bridge_d3_allowed()
> config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20240803/202408031855.TEPJlfzl-lkp@intel.com/config)
> compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240803/202408031855.TEPJlfzl-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202408031855.TEPJlfzl-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> drivers/gpu/drm/radeon/radeon_atpx_handler.c: In function 'radeon_atpx_detect':
> >> drivers/gpu/drm/radeon/radeon_atpx_handler.c:568:59: error: 'struct pci_dev' has no member named 'bridge_d3'
> 568 | d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> | ^~
> drivers/gpu/drm/radeon/radeon_atpx_handler.c:578:59: error: 'struct pci_dev' has no member named 'bridge_d3'
> 578 | d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> | ^~
> --
> drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c: In function 'amdgpu_atpx_detect':
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:628:59: error: 'struct pci_dev' has no member named 'bridge_d3'
> 628 | d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> | ^~
> drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c:638:59: error: 'struct pci_dev' has no member named 'bridge_d3'
> 638 | d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> | ^~
> --
> drivers/gpu/drm/nouveau/nouveau_acpi.c: In function 'nouveau_dsm_pci_probe':
> >> drivers/gpu/drm/nouveau/nouveau_acpi.c:229:32: error: 'struct pci_dev' has no member named 'bridge_d3'
> 229 | if (parent_pdev->bridge_d3)
> | ^~
Ok, there seems to be a couple of drivers making use of pci_dev::bridge_d3 to
check if D3Cold is supported or not. And this further strengthens the fact that
PCI core should not rely on pci_bridge_d3_possible() as proposed in patch 1.
- Mani
>
>
> vim +568 drivers/gpu/drm/radeon/radeon_atpx_handler.c
>
> 6a9ee8af344e3b Dave Airlie 2010-02-01 545
> 82e029357d4726 Alex Deucher 2012-08-16 546 /**
> 82e029357d4726 Alex Deucher 2012-08-16 547 * radeon_atpx_detect - detect whether we have PX
> 82e029357d4726 Alex Deucher 2012-08-16 548 *
> 82e029357d4726 Alex Deucher 2012-08-16 549 * Check if we have a PX system (all asics).
> 82e029357d4726 Alex Deucher 2012-08-16 550 * Returns true if we have a PX system, false if not.
> 82e029357d4726 Alex Deucher 2012-08-16 551 */
> 6a9ee8af344e3b Dave Airlie 2010-02-01 552 static bool radeon_atpx_detect(void)
> 6a9ee8af344e3b Dave Airlie 2010-02-01 553 {
> 6a9ee8af344e3b Dave Airlie 2010-02-01 554 char acpi_method_name[255] = { 0 };
> 6a9ee8af344e3b Dave Airlie 2010-02-01 555 struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
> 6a9ee8af344e3b Dave Airlie 2010-02-01 556 struct pci_dev *pdev = NULL;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 557 bool has_atpx = false;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 558 int vga_count = 0;
> bcfdd5d5105087 Alex Deucher 2016-11-28 559 bool d3_supported = false;
> bcfdd5d5105087 Alex Deucher 2016-11-28 560 struct pci_dev *parent_pdev;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 561
> 6a9ee8af344e3b Dave Airlie 2010-02-01 562 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
> 6a9ee8af344e3b Dave Airlie 2010-02-01 563 vga_count++;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 564
> 6a9ee8af344e3b Dave Airlie 2010-02-01 565 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
> bcfdd5d5105087 Alex Deucher 2016-11-28 566
> bcfdd5d5105087 Alex Deucher 2016-11-28 567 parent_pdev = pci_upstream_bridge(pdev);
> bcfdd5d5105087 Alex Deucher 2016-11-28 @568 d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 569 }
> 6a9ee8af344e3b Dave Airlie 2010-02-01 570
> e9a4099a59cc59 Alex Deucher 2014-04-15 571 /* some newer PX laptops mark the dGPU as a non-VGA display device */
> e9a4099a59cc59 Alex Deucher 2014-04-15 572 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
> e9a4099a59cc59 Alex Deucher 2014-04-15 573 vga_count++;
> e9a4099a59cc59 Alex Deucher 2014-04-15 574
> e9a4099a59cc59 Alex Deucher 2014-04-15 575 has_atpx |= (radeon_atpx_pci_probe_handle(pdev) == true);
> bcfdd5d5105087 Alex Deucher 2016-11-28 576
> bcfdd5d5105087 Alex Deucher 2016-11-28 577 parent_pdev = pci_upstream_bridge(pdev);
> bcfdd5d5105087 Alex Deucher 2016-11-28 578 d3_supported |= parent_pdev && parent_pdev->bridge_d3;
> e9a4099a59cc59 Alex Deucher 2014-04-15 579 }
> e9a4099a59cc59 Alex Deucher 2014-04-15 580
> 6a9ee8af344e3b Dave Airlie 2010-02-01 581 if (has_atpx && vga_count == 2) {
> 492b49a2f21a7c Alex Deucher 2012-08-16 582 acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
> 7ca85295d8cc28 Joe Perches 2017-02-28 583 pr_info("vga_switcheroo: detected switching method %s handle\n",
> 6a9ee8af344e3b Dave Airlie 2010-02-01 584 acpi_method_name);
> 6a9ee8af344e3b Dave Airlie 2010-02-01 585 radeon_atpx_priv.atpx_detected = true;
> bcfdd5d5105087 Alex Deucher 2016-11-28 586 radeon_atpx_priv.bridge_pm_usable = d3_supported;
> 69ee9742f945cd Alex Deucher 2016-07-27 587 radeon_atpx_init();
> 6a9ee8af344e3b Dave Airlie 2010-02-01 588 return true;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 589 }
> 6a9ee8af344e3b Dave Airlie 2010-02-01 590 return false;
> 6a9ee8af344e3b Dave Airlie 2010-02-01 591 }
> 6a9ee8af344e3b Dave Airlie 2010-02-01 592
>
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-08-05 13:27 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 5:54 [PATCH v5 0/4] PCI: Allow D3Hot for PCI bridges in Devicetree based platforms Manivannan Sadhasivam
2024-08-02 5:54 ` Manivannan Sadhasivam via B4 Relay
2024-08-02 5:55 ` [PATCH v5 1/4] PCI/portdrv: Make use of pci_dev::bridge_d3 for checking the D3 possibility Manivannan Sadhasivam
2024-08-02 5:55 ` Manivannan Sadhasivam via B4 Relay
2024-08-02 9:49 ` Lukas Wunner
2024-08-02 11:19 ` Rafael J. Wysocki
2024-08-02 20:07 ` Lukas Wunner
2024-08-05 13:24 ` Manivannan Sadhasivam
2024-08-06 6:46 ` Lukas Wunner
2024-08-06 11:48 ` Manivannan Sadhasivam
2024-08-02 5:55 ` [PATCH v5 2/4] PCI: Rename pci_bridge_d3_possible() to pci_bridge_d3_allowed() Manivannan Sadhasivam
2024-08-02 5:55 ` Manivannan Sadhasivam via B4 Relay
2024-08-03 11:03 ` kernel test robot
2024-08-05 13:26 ` Manivannan Sadhasivam [this message]
2024-08-02 5:55 ` [PATCH v5 3/4] PCI: Decouple D3Hot and D3Cold handling for bridges Manivannan Sadhasivam
2024-08-02 5:55 ` Manivannan Sadhasivam via B4 Relay
2024-08-19 12:44 ` Oliver Neukum
2024-08-20 6:00 ` Manivannan Sadhasivam
2024-08-20 23:45 ` Bjorn Helgaas
2024-08-29 6:10 ` Manivannan Sadhasivam
2024-08-21 1:45 ` Bjorn Helgaas
2024-08-28 15:52 ` Manivannan Sadhasivam
2024-08-28 21:07 ` Bjorn Helgaas
2024-08-29 5:22 ` Manivannan Sadhasivam
2024-11-21 18:54 ` Brian Norris
2024-08-02 5:55 ` [PATCH v5 4/4] PCI: Allow PCI bridges to go to D3Hot on all Devicetree based platforms Manivannan Sadhasivam
2024-08-02 5:55 ` Manivannan Sadhasivam via B4 Relay
2024-08-02 10:13 ` Lukas Wunner
2024-08-05 13:35 ` Manivannan Sadhasivam
2024-08-06 6:53 ` Lukas Wunner
2024-08-06 12:41 ` Manivannan Sadhasivam
2024-08-06 13:02 ` Lukas Wunner
2024-08-06 14:39 ` Manivannan Sadhasivam
2024-08-06 20:20 ` Lukas Wunner
2024-08-19 15:34 ` Manivannan Sadhasivam
2024-08-06 20:58 ` Hsin-Yi Wang
2024-11-21 18:53 ` Brian Norris
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