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From: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
To: Jonathan Cameron <jic23@kernel.org>,
	 Lars-Peter Clausen <lars@metafoo.de>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Chen Wang <unicorn_wang@outlook.com>,
	 Inochi Amaoto <inochiama@outlook.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Miquèl Raynal" <miquel.raynal@bootlin.com>,
	linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Thomas Bonnefille" <thomas.bonnefille@bootlin.com>
Subject: [PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for Sophgo CV18XX
Date: Mon, 12 Aug 2024 17:00:57 +0200	[thread overview]
Message-ID: <20240812-sg2002-adc-v4-3-599bdb67592f@bootlin.com> (raw)
In-Reply-To: <20240812-sg2002-adc-v4-0-599bdb67592f@bootlin.com>

Adds SARADC nodes for the common Successive Approximation Analog to
Digital Converter used in Sophgo CV18xx series SoC.
This patch adds two nodes for the two controllers the board, one in
the Active domain and the other in the No-Die domain.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..71a2618852fa 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -133,6 +133,26 @@ portd: gpio-controller@0 {
 			};
 		};
 
+		saradc: adc@30f0000 {
+			compatible = "sophgo,cv1800b-saradc";
+			reg = <0x030f0000 0x1000>;
+			clocks = <&clk CLK_SARADC>;
+			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			channel@0 {
+				reg = <0>;
+			};
+			channel@1 {
+				reg = <1>;
+			};
+			channel@2 {
+				reg = <2>;
+			};
+		};
+
 		i2c0: i2c@4000000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x04000000 0x10000>;

-- 
2.46.0


WARNING: multiple messages have this Message-ID (diff)
From: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
To: Jonathan Cameron <jic23@kernel.org>,
	 Lars-Peter Clausen <lars@metafoo.de>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Chen Wang <unicorn_wang@outlook.com>,
	 Inochi Amaoto <inochiama@outlook.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Miquèl Raynal" <miquel.raynal@bootlin.com>,
	linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	"Thomas Bonnefille" <thomas.bonnefille@bootlin.com>
Subject: [PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for Sophgo CV18XX
Date: Mon, 12 Aug 2024 17:00:57 +0200	[thread overview]
Message-ID: <20240812-sg2002-adc-v4-3-599bdb67592f@bootlin.com> (raw)
In-Reply-To: <20240812-sg2002-adc-v4-0-599bdb67592f@bootlin.com>

Adds SARADC nodes for the common Successive Approximation Analog to
Digital Converter used in Sophgo CV18xx series SoC.
This patch adds two nodes for the two controllers the board, one in
the Active domain and the other in the No-Die domain.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..71a2618852fa 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -133,6 +133,26 @@ portd: gpio-controller@0 {
 			};
 		};
 
+		saradc: adc@30f0000 {
+			compatible = "sophgo,cv1800b-saradc";
+			reg = <0x030f0000 0x1000>;
+			clocks = <&clk CLK_SARADC>;
+			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			channel@0 {
+				reg = <0>;
+			};
+			channel@1 {
+				reg = <1>;
+			};
+			channel@2 {
+				reg = <2>;
+			};
+		};
+
 		i2c0: i2c@4000000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x04000000 0x10000>;

-- 
2.46.0


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  parent reply	other threads:[~2024-08-12 15:01 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-12 15:00 [PATCH v4 0/3] Add SARADC support on Sophgo CV18XX series Thomas Bonnefille
2024-08-12 15:00 ` Thomas Bonnefille
2024-08-12 15:00 ` [PATCH v4 1/3] dt-bindings: iio: adc: sophgo,cv18xx-saradc.yaml: Add Sophgo CV18XX SARADC binding Thomas Bonnefille
2024-08-12 15:00   ` Thomas Bonnefille
2024-08-12 15:53   ` Conor Dooley
2024-08-12 15:53     ` Conor Dooley
2024-08-20 16:21     ` Thomas Bonnefille
2024-08-20 16:21       ` Thomas Bonnefille
2024-08-20 16:38       ` Conor Dooley
2024-08-20 16:38         ` Conor Dooley
2024-08-21  7:41         ` Miquel Raynal
2024-08-21  7:41           ` Miquel Raynal
2024-08-21 15:29           ` Conor Dooley
2024-08-21 15:29             ` Conor Dooley
2024-08-22  8:52             ` Miquel Raynal
2024-08-22  8:52               ` Miquel Raynal
2024-08-13  9:50   ` Krzysztof Kozlowski
2024-08-13  9:50     ` Krzysztof Kozlowski
2024-08-12 15:00 ` [PATCH v4 2/3] iio: adc: sophgo-saradc: Add driver for Sophgo CV18XX series SARADC Thomas Bonnefille
2024-08-12 15:00   ` Thomas Bonnefille
2024-08-13  1:39   ` Chen Wang
2024-08-13  1:39     ` Chen Wang
2024-08-17 13:05   ` Jonathan Cameron
2024-08-17 13:05     ` Jonathan Cameron
2024-08-12 15:00 ` Thomas Bonnefille [this message]
2024-08-12 15:00   ` [PATCH v4 3/3] riscv: dts: sophgo: Add SARADC description for Sophgo CV18XX Thomas Bonnefille
2024-08-13  1:45   ` Chen Wang
2024-08-13  1:45     ` Chen Wang
2024-08-13  1:50     ` Inochi Amaoto
2024-08-13  1:50       ` Inochi Amaoto
2024-08-13 23:32       ` Chen Wang
2024-08-13 23:32         ` Chen Wang

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