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From: <daire.mcnamara@microchip.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <conor.dooley@microchip.com>, <lpieralisi@kernel.org>,
	<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<daire.mcnamara@microchip.com>, <ilpo.jarvinen@linux.intel.com>,
	<kevin.xie@starfivetech.com>
Subject: [PATCH v10 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
Date: Fri, 11 Oct 2024 15:00:43 +0100	[thread overview]
Message-ID: <20241011140043.1250030-4-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20241011140043.1250030-1-daire.mcnamara@microchip.com>

From: Conor Dooley <conor.dooley@microchip.com>

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 612633ba59e2..5f5f2b25d797 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -44,6 +44,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-coherent: true
+
   ranges:
     minItems: 1
     maxItems: 3
-- 
2.43.0


WARNING: multiple messages have this Message-ID (diff)
From: <daire.mcnamara@microchip.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <conor.dooley@microchip.com>, <lpieralisi@kernel.org>,
	<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<daire.mcnamara@microchip.com>, <ilpo.jarvinen@linux.intel.com>,
	<kevin.xie@starfivetech.com>
Subject: [PATCH v10 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent
Date: Fri, 11 Oct 2024 15:00:43 +0100	[thread overview]
Message-ID: <20241011140043.1250030-4-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20241011140043.1250030-1-daire.mcnamara@microchip.com>

From: Conor Dooley <conor.dooley@microchip.com>

PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 612633ba59e2..5f5f2b25d797 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -44,6 +44,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-coherent: true
+
   ranges:
     minItems: 1
     maxItems: 3
-- 
2.43.0


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  parent reply	other threads:[~2024-10-11 14:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-11 14:00 [PATCH v10 0/3] Fix address translations on MPFS PCIe controller daire.mcnamara
2024-10-11 14:00 ` daire.mcnamara
2024-10-11 14:00 ` [PATCH v10 1/3] PCI: microchip: Fix outbound address translation tables daire.mcnamara
2024-10-11 14:00   ` daire.mcnamara
2025-01-15  0:13   ` Bjorn Helgaas
2025-01-15  0:13     ` Bjorn Helgaas
2025-01-16 15:42     ` Bjorn Helgaas
2025-01-16 15:42       ` Bjorn Helgaas
2025-01-16 16:46       ` Conor Dooley
2025-01-16 16:46         ` Conor Dooley
2025-01-16 17:07         ` Bjorn Helgaas
2025-01-16 17:07           ` Bjorn Helgaas
2025-01-16 17:45           ` Conor Dooley
2025-01-16 17:45             ` Conor Dooley
2025-01-16 18:02             ` Bjorn Helgaas
2025-01-16 18:02               ` Bjorn Helgaas
2025-01-17 10:53               ` Conor Dooley
2025-01-17 10:53                 ` Conor Dooley
2025-01-17 17:30                 ` Bjorn Helgaas
2025-01-17 17:30                   ` Bjorn Helgaas
2025-01-17 21:27                   ` Frank Li
2025-01-17 21:27                     ` Frank Li
2024-10-11 14:00 ` [PATCH v10 2/3] PCI: microchip: Fix inbound " daire.mcnamara
2024-10-11 14:00   ` daire.mcnamara
2024-10-11 14:00 ` daire.mcnamara [this message]
2024-10-11 14:00   ` [PATCH v10 3/3] dt-bindings: PCI: microchip,pcie-host: allow dma-noncoherent daire.mcnamara
2024-11-13 11:50 ` [PATCH v10 0/3] Fix address translations on MPFS PCIe controller Conor Dooley
2024-11-13 11:50   ` Conor Dooley
2025-01-14 17:16   ` Conor Dooley
2025-01-14 17:16     ` Conor Dooley
2025-01-14 23:19     ` Bjorn Helgaas
2025-01-14 23:19       ` Bjorn Helgaas

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