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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>, <dave.jiang@intel.com>,
	<linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v2 3/6] cxl/acpi: Ensure ports ready at cxl_acpi_probe() return
Date: Thu, 24 Oct 2024 10:44:20 +0100	[thread overview]
Message-ID: <20241024104420.00004f90@Huawei.com> (raw)
In-Reply-To: <172964781969.81806.17276352414854540808.stgit@dwillia2-xfh.jf.intel.com>

On Tue, 22 Oct 2024 18:43:40 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> In order to ensure root CXL ports are enabled upon cxl_acpi_probe()
> when the 'cxl_port' driver is built as a module, arrange for the
> module to be pre-loaded or built-in.
> 
> The "Fixes:" but no "Cc: stable" on this patch reflects that the issue
> is merely by inspection since the bug that triggered the discovery of
> this potential problem [1] is fixed by other means. However, a stable
> backport should do no harm.
> 
> Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver")
> Link: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.net [1]
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Seems reasonable to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/acpi.c |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
> index 82b78e331d8e..432b7cfd12a8 100644
> --- a/drivers/cxl/acpi.c
> +++ b/drivers/cxl/acpi.c
> @@ -924,6 +924,13 @@ static void __exit cxl_acpi_exit(void)
>  
>  /* load before dax_hmem sees 'Soft Reserved' CXL ranges */
>  subsys_initcall(cxl_acpi_init);
> +
> +/*
> + * Arrange for host-bridge ports to be active synchronous with
> + * cxl_acpi_probe() exit.
> + */
> +MODULE_SOFTDEP("pre: cxl_port");
> +
>  module_exit(cxl_acpi_exit);
>  MODULE_DESCRIPTION("CXL ACPI: Platform Support");
>  MODULE_LICENSE("GPL v2");
> 
> 


  parent reply	other threads:[~2024-10-24  9:44 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-23  1:43 [PATCH v2 0/6] cxl: Initialization and shutdown fixes Dan Williams
2024-10-23  1:43 ` [PATCH v2 1/6] cxl/port: Fix CXL port initialization order when the subsystem is built-in Dan Williams
2024-10-24  9:42   ` Jonathan Cameron
2024-10-24 16:19     ` Dan Williams
2024-10-24 16:39       ` Jonathan Cameron
2024-10-24 10:36   ` Alejandro Lucero Palau
2024-10-24 16:32     ` Dan Williams
2024-10-25  8:43       ` Alejandro Lucero Palau
2024-10-25 15:19         ` Dan Williams
2024-10-24 14:14   ` Ira Weiny
2024-10-25 19:32   ` [PATCH v3 " Dan Williams
2024-10-23  1:43 ` [PATCH v2 2/6] cxl/port: Fix cxl_bus_rescan() vs bus_rescan_devices() Dan Williams
2024-10-23 15:57   ` Gregory Price
2024-10-24  9:43   ` Jonathan Cameron
2024-10-24 14:29   ` Ira Weiny
2024-10-23  1:43 ` [PATCH v2 3/6] cxl/acpi: Ensure ports ready at cxl_acpi_probe() return Dan Williams
2024-10-23 15:58   ` Gregory Price
2024-10-24  9:44   ` Jonathan Cameron [this message]
2024-10-24 14:34   ` Ira Weiny
2024-10-23  1:43 ` [PATCH v2 4/6] cxl/port: Fix use-after-free, permit out-of-order decoder shutdown Dan Williams
2024-10-24 15:55   ` Ira Weiny
2024-10-23  1:43 ` [PATCH v2 5/6] cxl/port: Prevent out-of-order decoder allocation Dan Williams
2024-10-24 12:10   ` Jonathan Cameron
2024-10-24 16:20   ` Ira Weiny
2024-10-23  1:44 ` [PATCH v2 6/6] cxl/test: Improve init-order fidelity relative to real-world systems Dan Williams
2024-10-24 12:17   ` Jonathan Cameron
2024-10-24 16:32   ` Ira Weiny
2024-10-23 13:12 ` [PATCH v2 0/6] cxl: Initialization and shutdown fixes Robert Richter
2024-10-23 16:00   ` Gregory Price
2024-10-23 20:34   ` Dan Williams
2024-10-24 11:56     ` Robert Richter

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