From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <ira.weiny@intel.com>, Gregory Price <gourry@gourry.net>,
<stable@vger.kernel.org>, Davidlohr Bueso <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
<linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v2 1/6] cxl/port: Fix CXL port initialization order when the subsystem is built-in
Date: Thu, 24 Oct 2024 17:39:37 +0100 [thread overview]
Message-ID: <20241024173937.00003d80@Huawei.com> (raw)
In-Reply-To: <671a7384ec43f_10e5929493@dwillia2-xfh.jf.intel.com.notmuch>
On Thu, 24 Oct 2024 09:19:17 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Jonathan Cameron wrote:
> > On Tue, 22 Oct 2024 18:43:24 -0700
> > Dan Williams <dan.j.williams@intel.com> wrote:
> >
> > > When the CXL subsystem is built-in the module init order is determined
> > > by Makefile order. That order violates expectations. The expectation is
> > > that cxl_acpi and cxl_mem can race to attach and that if cxl_acpi wins
> > > the race cxl_mem will find the enabled CXL root ports it needs and if
> > > cxl_acpi loses the race it will retrigger cxl_mem to attach via
> > > cxl_bus_rescan(). That only works if cxl_acpi can assume ports are
> > > enabled immediately upon cxl_acpi_probe() return. That in turn can only
> > > happen in the CONFIG_CXL_ACPI=y case if the cxl_port object appears
> > > before the cxl_acpi object in the Makefile.
> > >
> > > Fix up the order to prevent initialization failures, and make sure that
> > > cxl_port is built-in if cxl_acpi is also built-in.
> > >
> > > As for what contributed to this not being found earlier, the CXL
> > > regression environment, cxl_test, builds all CXL functionality as a
> > > module to allow to symbol mocking and other dynamic reload tests. As a
> > > result there is no regression coverage for the built-in case.
> > >
> > > Reported-by: Gregory Price <gourry@gourry.net>
> > > Closes: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.net
> > > Tested-by: Gregory Price <gourry@gourry.net>
> > > Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver")
> >
> > I don't like this due to likely long term fragility, but any other
>
> Please be specific about the fragility and how is this different than
> any other Makefile order fragility, like the many cases in
> drivers/Makefile/, or patches fixing up initcall order?
Sure, I don't like any of them ;) Mostly was having a grumpy day
rather than suggesting a change in this.
>
> Now, an argument can be made that there are too many CXL sub-objects and
> more can be merged into a monolithic cxl_core object. The flipside of
> that is reduced testability, at least via symbol mocking techniques.
> Just look at the recent case where the fact that
> drivers/cxl/core/region.c is built into cxl_core.o rather than its own
> cxl_region.o object results in an in-line code change to support
> cxl_test [1]. There are tradeoffs.
Absolutely agree.
>
> > solution is probably more painful. Long term we should really get
> > a regression test for these ordering issues in place in one of
> > the CIs.
>
> The final patch in this series does improve cxl_test's ability to catch
> regressions in module init order, and that ordering change did uncover a
> bug. The system works! 😅
That was indeed good to see!
>
> Going further the test mode that is needed, in addition to QEMU
> emulation and cxl_test interface mocking, is kunit or similar [2]
> infrastructure for some function-scope unit tests.
>
> [1]: http://lore.kernel.org/20241022030054.258942-1-lizhijian@fujitsu.com
> [2]: http://lore.kernel.org/170795677066.3697776.12587812713093908173.stgit@ubuntu
>
Yeah, we have a long way to go on testing (common problem!)
Jonathan
next prev parent reply other threads:[~2024-10-24 16:39 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-23 1:43 [PATCH v2 0/6] cxl: Initialization and shutdown fixes Dan Williams
2024-10-23 1:43 ` [PATCH v2 1/6] cxl/port: Fix CXL port initialization order when the subsystem is built-in Dan Williams
2024-10-24 9:42 ` Jonathan Cameron
2024-10-24 16:19 ` Dan Williams
2024-10-24 16:39 ` Jonathan Cameron [this message]
2024-10-24 10:36 ` Alejandro Lucero Palau
2024-10-24 16:32 ` Dan Williams
2024-10-25 8:43 ` Alejandro Lucero Palau
2024-10-25 15:19 ` Dan Williams
2024-10-24 14:14 ` Ira Weiny
2024-10-25 19:32 ` [PATCH v3 " Dan Williams
2024-10-23 1:43 ` [PATCH v2 2/6] cxl/port: Fix cxl_bus_rescan() vs bus_rescan_devices() Dan Williams
2024-10-23 15:57 ` Gregory Price
2024-10-24 9:43 ` Jonathan Cameron
2024-10-24 14:29 ` Ira Weiny
2024-10-23 1:43 ` [PATCH v2 3/6] cxl/acpi: Ensure ports ready at cxl_acpi_probe() return Dan Williams
2024-10-23 15:58 ` Gregory Price
2024-10-24 9:44 ` Jonathan Cameron
2024-10-24 14:34 ` Ira Weiny
2024-10-23 1:43 ` [PATCH v2 4/6] cxl/port: Fix use-after-free, permit out-of-order decoder shutdown Dan Williams
2024-10-24 15:55 ` Ira Weiny
2024-10-23 1:43 ` [PATCH v2 5/6] cxl/port: Prevent out-of-order decoder allocation Dan Williams
2024-10-24 12:10 ` Jonathan Cameron
2024-10-24 16:20 ` Ira Weiny
2024-10-23 1:44 ` [PATCH v2 6/6] cxl/test: Improve init-order fidelity relative to real-world systems Dan Williams
2024-10-24 12:17 ` Jonathan Cameron
2024-10-24 16:32 ` Ira Weiny
2024-10-23 13:12 ` [PATCH v2 0/6] cxl: Initialization and shutdown fixes Robert Richter
2024-10-23 16:00 ` Gregory Price
2024-10-23 20:34 ` Dan Williams
2024-10-24 11:56 ` Robert Richter
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