[PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.

Tianling Shen (7):
  arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
  arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
  arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi
    R3S
  arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
  arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
  arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
  board: rockchip: add FriendlyElec NanoPi R3S

 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi    |   8 +
 board/rockchip/evb_rk3568/MAINTAINERS         |   7 +
 configs/nanopi-r3s-rk3566_defconfig           |  74 +++
 doc/board/rockchip/rockchip.rst               |   1 +
 .../src/arm64/rockchip/rk3566-nanopi-r3s.dts  | 554 ++++++++++++++++++
 5 files changed, 644 insertions(+)
 create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
 create mode 100644 configs/nanopi-r3s-rk3566_defconfig
 create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts

-- 
2.47.0

[PATCH 1/7] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board

[Tianling Shen]

The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.

Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 50decd493c8394c52d04561fe4ede34df27a46ba ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 .../src/arm64/rockchip/rk3566-nanopi-r3s.dts  | 554 ++++++++++++++++++
 1 file changed, 554 insertions(+)
 create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
new file mode 100644
index 0000000000..a7a55d68db
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -0,0 +1,554 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3566.dtsi"
+
+/ {
+	model = "FriendlyARM NanoPi R3S";
+	compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&reset_button_pin>;
+
+		button-reset {
+			label = "reset";
+			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <50>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
+
+		power_led: led-0 {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		lan_led: led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
+		};
+
+		wan_led: led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vdd_usbc>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0_usb {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_host_en>;
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vdd_usbc: regulator-vdd-usbc {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_usbc";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "output";
+	phy-mode = "rgmii-id";
+	phy-handle = <&rgmii_phy1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+		     &gmac1m0_tx_bus2_level3
+		     &gmac1m0_rx_bus2
+		     &gmac1m0_rgmii_clk_level2
+		     &gmac1m0_rgmii_bus_level3>;
+	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		system-power-controller;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-initial-mode = <0x2>;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-min-microvolt = <950000>;
+				regulator-max-microvolt = <950000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&eth_phy_reset_pin>;
+	};
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pinctrl {
+	gpio-leds {
+		lan_led_pin: lan-led-pin {
+			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		power_led_pin: power-led-pin {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wan_led_pin: wan-led-pin {
+			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	gmac {
+		eth_phy_reset_pin: eth-phy-reset-pin {
+			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pcie {
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rockchip-key {
+		reset_button_pin: reset-button-pin {
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	rtc {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	status = "okay";
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_1v8>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	no-sdio;
+	no-mmc;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	sd-uhs-sdr50;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
-- 
2.47.0

Re: [PATCH 1/7] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
> Ethernet ports designed and developed by FriendlyElec for IoT
> applications.
>
> Specification:
> - Rockchip RK3566
> - 2GB LPDDR4X RAM
> - optional 32GB eMMC module
> - SD card slot
> - 2x 1000 Base-T
> - 3x LEDs (POWER, LAN, WAN)
> - 2x Buttons (Reset, MaskROM)
> - 1x USB 3.0 Port
> - Type-C 5V 2A Power
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 50decd493c8394c52d04561fe4ede34df27a46ba ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   .../src/arm64/rockchip/rk3566-nanopi-r3s.dts  | 554 ++++++++++++++++++
>   1 file changed, 554 insertions(+)
>   create mode 100644 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> new file mode 100644
> index 0000000000..a7a55d68db
> --- /dev/null
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -0,0 +1,554 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
> +/*
> + * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
> + *
> + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
> + * (http://www.friendlyarm.com)
> + *
> + * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
> + */
> +
> +/dts-v1/;
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/soc/rockchip,vop2.h>
> +#include "rk3566.dtsi"
> +
> +/ {
> +	model = "FriendlyARM NanoPi R3S";
> +	compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
> +
> +	aliases {
> +		ethernet0 = &gmac1;
> +		mmc0 = &sdmmc0;
> +		mmc1 = &sdhci;
> +	};
> +
> +	chosen: chosen {
> +		stdout-path = "serial2:1500000n8";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&reset_button_pin>;
> +
> +		button-reset {
> +			label = "reset";
> +			gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_RESTART>;
> +			debounce-interval = <50>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
> +
> +		power_led: led-0 {
> +			color = <LED_COLOR_ID_RED>;
> +			function = LED_FUNCTION_POWER;
> +			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
> +			default-state = "on";
> +		};
> +
> +		lan_led: led-1 {
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_LAN;
> +			gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
> +		};
> +
> +		wan_led: led-2 {
> +			color = <LED_COLOR_ID_GREEN>;
> +			function = LED_FUNCTION_WAN;
> +			gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	vcc3v3_sys: regulator-vcc3v3-sys {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc3v3_sys";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		vin-supply = <&vcc5v0_sys>;
> +	};
> +
> +	vcc5v0_sys: regulator-vcc5v0-sys {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc5v0_sys";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		vin-supply = <&vdd_usbc>;
> +	};
> +
> +	vcc5v0_usb: regulator-vcc5v0_usb {
> +		compatible = "regulator-fixed";
> +		enable-active-high;
> +		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&vcc5v0_usb_host_en>;
> +		regulator-name = "vcc5v0_usb";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		vin-supply = <&vcc5v0_sys>;
> +	};
> +
> +	vdd_usbc: regulator-vdd-usbc {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vdd_usbc";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +	};
> +};
> +
> +&combphy1 {
> +	status = "okay";
> +};
> +
> +&combphy2 {
> +	status = "okay";
> +};
> +
> +&cpu0 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu1 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu2 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&cpu3 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&gmac1 {
> +	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
> +	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
> +	assigned-clock-rates = <0>, <125000000>;
> +	clock_in_out = "output";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&rgmii_phy1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&gmac1m0_miim
> +		     &gmac1m0_tx_bus2_level3
> +		     &gmac1m0_rx_bus2
> +		     &gmac1m0_rgmii_clk_level2
> +		     &gmac1m0_rgmii_bus_level3>;
> +	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
> +	snps,reset-active-low;
> +	/* Reset time is 20ms, 100ms for rtl8211f */
> +	snps,reset-delays-us = <0 20000 100000>;
> +	status = "okay";
> +};
> +
> +&gpu {
> +	mali-supply = <&vdd_gpu>;
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	vdd_cpu: regulator@1c {
> +		compatible = "tcs,tcs4525";
> +		reg = <0x1c>;
> +		fcs,suspend-voltage-selector = <1>;
> +		regulator-name = "vdd_cpu";
> +		regulator-always-on;
> +		regulator-boot-on;
> +		regulator-min-microvolt = <800000>;
> +		regulator-max-microvolt = <1150000>;
> +		regulator-ramp-delay = <2300>;
> +		vin-supply = <&vcc5v0_sys>;
> +
> +		regulator-state-mem {
> +			regulator-off-in-suspend;
> +		};
> +	};
> +
> +	rk809: pmic@20 {
> +		compatible = "rockchip,rk809";
> +		reg = <0x20>;
> +		interrupt-parent = <&gpio0>;
> +		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
> +		#clock-cells = <1>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pmic_int>;
> +		system-power-controller;
> +		vcc1-supply = <&vcc3v3_sys>;
> +		vcc2-supply = <&vcc3v3_sys>;
> +		vcc3-supply = <&vcc3v3_sys>;
> +		vcc4-supply = <&vcc3v3_sys>;
> +		vcc5-supply = <&vcc3v3_sys>;
> +		vcc6-supply = <&vcc3v3_sys>;
> +		vcc7-supply = <&vcc3v3_sys>;
> +		vcc8-supply = <&vcc3v3_sys>;
> +		vcc9-supply = <&vcc3v3_sys>;
> +		wakeup-source;
> +
> +		regulators {
> +			vdd_logic: DCDC_REG1 {
> +				regulator-name = "vdd_logic";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-initial-mode = <0x2>;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1350000>;
> +				regulator-ramp-delay = <6001>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vdd_gpu: DCDC_REG2 {
> +				regulator-name = "vdd_gpu";
> +				regulator-always-on;
> +				regulator-initial-mode = <0x2>;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1350000>;
> +				regulator-ramp-delay = <6001>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcc_ddr: DCDC_REG3 {
> +				regulator-name = "vcc_ddr";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-initial-mode = <0x2>;
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +
> +			vdd_npu: DCDC_REG4 {
> +				regulator-name = "vdd_npu";
> +				regulator-initial-mode = <0x2>;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1350000>;
> +				regulator-ramp-delay = <6001>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcc_1v8: DCDC_REG5 {
> +				regulator-name = "vcc_1v8";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vdda0v9_image: LDO_REG1 {
> +				regulator-name = "vdda0v9_image";
> +				regulator-min-microvolt = <950000>;
> +				regulator-max-microvolt = <950000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vdda_0v9: LDO_REG2 {
> +				regulator-name = "vdda_0v9";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <900000>;
> +				regulator-max-microvolt = <900000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vdda0v9_pmu: LDO_REG3 {
> +				regulator-name = "vdda0v9_pmu";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <900000>;
> +				regulator-max-microvolt = <900000>;
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-suspend-microvolt = <900000>;
> +				};
> +			};
> +
> +			vccio_acodec: LDO_REG4 {
> +				regulator-name = "vccio_acodec";
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vccio_sd: LDO_REG5 {
> +				regulator-name = "vccio_sd";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcc3v3_pmu: LDO_REG6 {
> +				regulator-name = "vcc3v3_pmu";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-suspend-microvolt = <3300000>;
> +				};
> +			};
> +
> +			vcca_1v8: LDO_REG7 {
> +				regulator-name = "vcca_1v8";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcca1v8_pmu: LDO_REG8 {
> +				regulator-name = "vcca1v8_pmu";
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-suspend-microvolt = <1800000>;
> +				};
> +			};
> +
> +			vcca1v8_image: LDO_REG9 {
> +				regulator-name = "vcca1v8_image";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcc_3v3: SWITCH_REG1 {
> +				regulator-name = "vcc_3v3";
> +				regulator-always-on;
> +				regulator-boot-on;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +
> +			vcc3v3_sd: SWITCH_REG2 {
> +				regulator-name = "vcc3v3_sd";
> +				regulator-always-on;
> +				regulator-boot-on;
> +
> +				regulator-state-mem {
> +					regulator-off-in-suspend;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +
> +	hym8563: rtc@51 {
> +		compatible = "haoyu,hym8563";
> +		reg = <0x51>;
> +		#clock-cells = <0>;
> +		clock-output-names = "hym8563";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&hym8563_int>;
> +		interrupt-parent = <&gpio0>;
> +		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
> +		wakeup-source;
> +	};
> +};
> +
> +&mdio1 {
> +	rgmii_phy1: ethernet-phy@1 {
> +		compatible = "ethernet-phy-ieee802.3-c22";
> +		reg = <1>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&eth_phy_reset_pin>;
> +	};
> +};
> +
> +&pcie2x1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_reset_h>;
> +	reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&pinctrl {
> +	gpio-leds {
> +		lan_led_pin: lan-led-pin {
> +			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		power_led_pin: power-led-pin {
> +			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +
> +		wan_led_pin: wan-led-pin {
> +			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
> +
> +	gmac {
> +		eth_phy_reset_pin: eth-phy-reset-pin {
> +			rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
> +	};
> +
> +	pcie {
> +		pcie_reset_h: pcie-reset-h {
> +			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
> +		};
> +	};
> +
> +	pmic {
> +		pmic_int: pmic-int {
> +			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
> +	};
> +
> +	rockchip-key {
> +		reset_button_pin: reset-button-pin {
> +			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
> +	};
> +
> +	rtc {
> +		hym8563_int: hym8563-int {
> +			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
> +		};
> +	};
> +
> +	usb {
> +		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
> +			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> +		};
> +	};
> +};
> +
> +&pmu_io_domains {
> +	status = "okay";
> +	pmuio1-supply = <&vcc3v3_pmu>;
> +	pmuio2-supply = <&vcc3v3_pmu>;
> +	vccio1-supply = <&vccio_acodec>;
> +	vccio2-supply = <&vcc_1v8>;
> +	vccio3-supply = <&vccio_sd>;
> +	vccio4-supply = <&vcc_3v3>;
> +	vccio5-supply = <&vcc_1v8>;
> +	vccio6-supply = <&vcc_3v3>;
> +	vccio7-supply = <&vcc_3v3>;
> +};
> +
> +&sdhci {
> +	bus-width = <8>;
> +	max-frequency = <200000000>;
> +	non-removable;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
> +	status = "okay";
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	cap-mmc-highspeed;
> +	cap-sd-highspeed;
> +	disable-wp;
> +	no-sdio;
> +	no-mmc;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
> +	sd-uhs-sdr50;
> +	vmmc-supply = <&vcc3v3_sd>;
> +	vqmmc-supply = <&vccio_sd>;
> +	status = "okay";
> +};
> +
> +&tsadc {
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
> +
> +&usb2phy0 {
> +	status = "okay";
> +};
> +
> +&usb2phy0_host {
> +	phy-supply = <&vcc5v0_usb>;
> +	status = "okay";
> +};
> +
> +&usb2phy0_otg {
> +	status = "okay";
> +};
> +
> +&usb_host0_xhci {
> +	extcon = <&usb2phy0>;
> +	status = "okay";
> +};
> +
> +&usb_host1_xhci {
> +	status = "okay";
> +};
> +
> +&vop {
> +	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
> +	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
> +	status = "okay";
> +};
> +
> +&vop_mmu {
> +	status = "okay";
> +};

[PATCH 2/7] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S

[Tianling Shen]

Use the marketing name for model name, this matches the dt-binding.
Also update the website url in copyright.

Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: b5bf84206a5c77528f9dd4cbca4e72caa063c102 ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
index a7a55d68db..6bc17f755b 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -3,7 +3,7 @@
  * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
  *
  * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
- * (http://www.friendlyarm.com)
+ * (http://www.friendlyelec.com)
  *
  * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
  */
@@ -17,7 +17,7 @@
 #include "rk3566.dtsi"
 
 / {
-	model = "FriendlyARM NanoPi R3S";
+	model = "FriendlyElec NanoPi R3S";
 	compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
 
 	aliases {
-- 
2.47.0

Re: [PATCH 2/7] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> Use the marketing name for model name, this matches the dt-binding.
> Also update the website url in copyright.
>
> Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: b5bf84206a5c77528f9dd4cbca4e72caa063c102 ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> index a7a55d68db..6bc17f755b 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -3,7 +3,7 @@
>    * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
>    *
>    * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
> - * (http://www.friendlyarm.com)
> + * (http://www.friendlyelec.com)
>    *
>    * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
>    */
> @@ -17,7 +17,7 @@
>   #include "rk3566.dtsi"
>   
>   / {
> -	model = "FriendlyARM NanoPi R3S";
> +	model = "FriendlyElec NanoPi R3S";
>   	compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
>   
>   	aliases {

[PATCH 3/7] arm64: dts: rockchip: replace deprecated snps, reset props for NanoPi R3S

[Tianling Shen]

Replace deprecated snps,reset props and move them to the PHY node.

Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 82b2868937883b65732da498b26366d34db61510 ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
index 6bc17f755b..66a00cddda 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -149,10 +149,6 @@
 		     &gmac1m0_rx_bus2
 		     &gmac1m0_rgmii_clk_level2
 		     &gmac1m0_rgmii_bus_level3>;
-	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	/* Reset time is 20ms, 100ms for rtl8211f */
-	snps,reset-delays-us = <0 20000 100000>;
 	status = "okay";
 };
 
@@ -414,6 +410,9 @@
 		interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&eth_phy_reset_pin>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
 	};
 };
 
-- 
2.47.0

Re: [PATCH 3/7] arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> Replace deprecated snps,reset props and move them to the PHY node.
>
> Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 82b2868937883b65732da498b26366d34db61510 ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 7 +++----
>   1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> index 6bc17f755b..66a00cddda 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -149,10 +149,6 @@
>   		     &gmac1m0_rx_bus2
>   		     &gmac1m0_rgmii_clk_level2
>   		     &gmac1m0_rgmii_bus_level3>;
> -	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
> -	snps,reset-active-low;
> -	/* Reset time is 20ms, 100ms for rtl8211f */
> -	snps,reset-delays-us = <0 20000 100000>;
>   	status = "okay";
>   };
>   
> @@ -414,6 +410,9 @@
>   		interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
>   		pinctrl-names = "default";
>   		pinctrl-0 = <&eth_phy_reset_pin>;
> +		reset-assert-us = <20000>;
> +		reset-deassert-us = <100000>;
> +		reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
>   	};
>   };
>   

[PATCH 4/7] arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S

[Tianling Shen]

The status prop is typically the last prop.

Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 17e150fdd983c7e59b9240e34a166285f3c3fb39 ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
index 66a00cddda..243574f8da 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -476,7 +476,6 @@
 };
 
 &pmu_io_domains {
-	status = "okay";
 	pmuio1-supply = <&vcc3v3_pmu>;
 	pmuio2-supply = <&vcc3v3_pmu>;
 	vccio1-supply = <&vccio_acodec>;
@@ -486,6 +485,7 @@
 	vccio5-supply = <&vcc_1v8>;
 	vccio6-supply = <&vcc_3v3>;
 	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
 };
 
 &sdhci {
-- 
2.47.0

Re: [PATCH 4/7] arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> The status prop is typically the last prop.
>
> Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 17e150fdd983c7e59b9240e34a166285f3c3fb39 ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> index 66a00cddda..243574f8da 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -476,7 +476,6 @@
>   };
>   
>   &pmu_io_domains {
> -	status = "okay";
>   	pmuio1-supply = <&vcc3v3_pmu>;
>   	pmuio2-supply = <&vcc3v3_pmu>;
>   	vccio1-supply = <&vccio_acodec>;
> @@ -486,6 +485,7 @@
>   	vccio5-supply = <&vcc_1v8>;
>   	vccio6-supply = <&vcc_3v3>;
>   	vccio7-supply = <&vcc_3v3>;
> +	status = "okay";
>   };
>   
>   &sdhci {

[PATCH 5/7] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S

[Tianling Shen]

It is required to boot from eMMC without additional patch in u-boot.

Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 1b5365034410f1ca21adadadd492b99bdf4f2c55 ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
index 243574f8da..03a2f90f62 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -491,6 +491,7 @@
 &sdhci {
 	bus-width = <8>;
 	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
 	non-removable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-- 
2.47.0

Re: [PATCH 5/7] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> It is required to boot from eMMC without additional patch in u-boot.
>
> Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 1b5365034410f1ca21adadadd492b99bdf4f2c55 ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> index 243574f8da..03a2f90f62 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -491,6 +491,7 @@
>   &sdhci {
>   	bus-width = <8>;
>   	max-frequency = <200000000>;
> +	mmc-hs200-1_8v;
>   	non-removable;
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;

[PATCH 6/7] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S

[Tianling Shen]

Typically any non-removable storage (emmc) is listed before removable
storage (sd-card) options. Also U-Boot will try to override and use
mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.

Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: b7cd1115456d312f8c5e60c80fdc35fd35ea6eab ]

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
index 03a2f90f62..fb1f65c868 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
@@ -22,8 +22,8 @@
 
 	aliases {
 		ethernet0 = &gmac1;
-		mmc0 = &sdmmc0;
-		mmc1 = &sdhci;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
 	};
 
 	chosen: chosen {
-- 
2.47.0

Re: [PATCH 6/7] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> Typically any non-removable storage (emmc) is listed before removable
> storage (sd-card) options. Also U-Boot will try to override and use
> mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
>
> Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: b7cd1115456d312f8c5e60c80fdc35fd35ea6eab ]
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> index 03a2f90f62..fb1f65c868 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts
> @@ -22,8 +22,8 @@
>   
>   	aliases {
>   		ethernet0 = &gmac1;
> -		mmc0 = &sdmmc0;
> -		mmc1 = &sdhci;
> +		mmc0 = &sdhci;
> +		mmc1 = &sdmmc0;
>   	};
>   
>   	chosen: chosen {

[PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.

Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
 board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
 configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
 doc/board/rockchip/rockchip.rst            |  1 +
 4 files changed, 90 insertions(+)
 create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
 create mode 100644 configs/nanopi-r3s-rk3566_defconfig

diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
new file mode 100644
index 0000000000..b66e5015d6
--- /dev/null
+++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rk356x-u-boot.dtsi"
+
+&vcc5v0_usb {
+	/delete-property/ regulator-always-on;
+	/delete-property/ regulator-boot-on;
+};
diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
index 588134ecb2..b2780401a3 100644
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -28,6 +28,13 @@ F:	configs/lubancat-2-rk3568_defconfig
 F:	arch/arm/dts/rk3568-lubancat-2.dts
 F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
 
+NANOPI-R3S
+M:	Tianling Shen <cnsztl@gmail.com>
+R:	Jonas Karlman <jonas@kwiboo.se>
+S:	Maintained
+F:	configs/nanopi-r3s-rk3566_defconfig
+F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
+
 NANOPI-R5C
 M:	Tianling Shen <cnsztl@gmail.com>
 R:	Jonas Karlman <jonas@kwiboo.se>
diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig
new file mode 100644
index 0000000000..f21c703ca7
--- /dev/null
+++ b/configs/nanopi-r3s-rk3566_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9bab86d234..02d7a4b124 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -99,6 +99,7 @@ List of mainline supported Rockchip boards:
 
 * rk3566
      - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
+     - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
      - Hardkernel ODROID-M1S (odroid-m1s-rk3566)
      - Pine64 PineTab2 (pinetab2-rk3566)
      - Pine64 Quartz64-A Board (quartz64-a-rk3566)
-- 
2.47.0

Re: [PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Kever Yang]

On 2024/12/26 17:20, Tianling Shen wrote:
> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
> Ethernet ports designed and developed by FriendlyElec for IoT
> applications.
>
> Specification:
> - Rockchip RK3566
> - 2GB LPDDR4X RAM
> - optional 32GB eMMC module
> - SD card slot
> - 2x 1000 Base-T
> - 3x LEDs (POWER, LAN, WAN)
> - 2x Buttons (Reset, MaskROM)
> - 1x USB 3.0 Port
> - Type-C 5V 2A Power
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
>   board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
>   configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
>   doc/board/rockchip/rockchip.rst            |  1 +
>   4 files changed, 90 insertions(+)
>   create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>   create mode 100644 configs/nanopi-r3s-rk3566_defconfig
>
> diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> new file mode 100644
> index 0000000000..b66e5015d6
> --- /dev/null
> +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include "rk356x-u-boot.dtsi"
> +
> +&vcc5v0_usb {
> +	/delete-property/ regulator-always-on;
> +	/delete-property/ regulator-boot-on;
> +};
> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
> index 588134ecb2..b2780401a3 100644
> --- a/board/rockchip/evb_rk3568/MAINTAINERS
> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> @@ -28,6 +28,13 @@ F:	configs/lubancat-2-rk3568_defconfig
>   F:	arch/arm/dts/rk3568-lubancat-2.dts
>   F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>   
> +NANOPI-R3S
> +M:	Tianling Shen <cnsztl@gmail.com>
> +R:	Jonas Karlman <jonas@kwiboo.se>
> +S:	Maintained
> +F:	configs/nanopi-r3s-rk3566_defconfig
> +F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> +
>   NANOPI-R5C
>   M:	Tianling Shen <cnsztl@gmail.com>
>   R:	Jonas Karlman <jonas@kwiboo.se>
> diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig
> new file mode 100644
> index 0000000000..f21c703ca7
> --- /dev/null
> +++ b/configs/nanopi-r3s-rk3566_defconfig
> @@ -0,0 +1,74 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
> +CONFIG_ROCKCHIP_RK3568=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFE660000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_PCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_ATF=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_RTL8169=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_SPL_RAM=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 9bab86d234..02d7a4b124 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards:
>   
>   * rk3566
>        - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
> +     - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
>        - Hardkernel ODROID-M1S (odroid-m1s-rk3566)
>        - Pine64 PineTab2 (pinetab2-rk3566)
>        - Pine64 Quartz64-A Board (quartz64-a-rk3566)

Re: [PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Kever Yang]

Hi Tianling.

You will need add below config for CONFIG_RTL8169:

CONFIG_SYS_HAS_NONCACHED_MEMORY=y


Or else we will get below error in CI:

    aarch64:  +   nanopi-r3s-rk3566
+drivers/net/rtl8169.c:320:2: error: #warning cache-line size is larger 
than descriptor size [-Werror=cpp]
+  320 | #warning cache-line size is larger than descriptor size
+      |  ^~~~~~~
+cc1: all warnings being treated as errors
+make[3]: *** [scripts/Makefile.build:257: drivers/net/rtl8169.o] Error 1
+make[2]: *** [scripts/Makefile.build:398: drivers/net] Error 2
+make[1]: *** [Makefile:1906: drivers] Error 2
+make: *** [Makefile:177: sub-make] Error 2

https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/jobs/988639


Thanks,

- Kever

On 2024/12/26 17:20, Tianling Shen wrote:
> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
> Ethernet ports designed and developed by FriendlyElec for IoT
> applications.
>
> Specification:
> - Rockchip RK3566
> - 2GB LPDDR4X RAM
> - optional 32GB eMMC module
> - SD card slot
> - 2x 1000 Base-T
> - 3x LEDs (POWER, LAN, WAN)
> - 2x Buttons (Reset, MaskROM)
> - 1x USB 3.0 Port
> - Type-C 5V 2A Power
>
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> ---
>   arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
>   board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
>   configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
>   doc/board/rockchip/rockchip.rst            |  1 +
>   4 files changed, 90 insertions(+)
>   create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>   create mode 100644 configs/nanopi-r3s-rk3566_defconfig
>
> diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> new file mode 100644
> index 0000000000..b66e5015d6
> --- /dev/null
> +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include "rk356x-u-boot.dtsi"
> +
> +&vcc5v0_usb {
> +	/delete-property/ regulator-always-on;
> +	/delete-property/ regulator-boot-on;
> +};
> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
> index 588134ecb2..b2780401a3 100644
> --- a/board/rockchip/evb_rk3568/MAINTAINERS
> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> @@ -28,6 +28,13 @@ F:	configs/lubancat-2-rk3568_defconfig
>   F:	arch/arm/dts/rk3568-lubancat-2.dts
>   F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>   
> +NANOPI-R3S
> +M:	Tianling Shen <cnsztl@gmail.com>
> +R:	Jonas Karlman <jonas@kwiboo.se>
> +S:	Maintained
> +F:	configs/nanopi-r3s-rk3566_defconfig
> +F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> +
>   NANOPI-R5C
>   M:	Tianling Shen <cnsztl@gmail.com>
>   R:	Jonas Karlman <jonas@kwiboo.se>
> diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig
> new file mode 100644
> index 0000000000..f21c703ca7
> --- /dev/null
> +++ b/configs/nanopi-r3s-rk3566_defconfig
> @@ -0,0 +1,74 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
> +CONFIG_ROCKCHIP_RK3568=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFE660000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_PCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_ATF=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_RTL8169=y
> +CONFIG_NVME_PCI=y
> +CONFIG_PCIE_DW_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_SPL_RAM=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 9bab86d234..02d7a4b124 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards:
>   
>   * rk3566
>        - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
> +     - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
>        - Hardkernel ODROID-M1S (odroid-m1s-rk3566)
>        - Pine64 PineTab2 (pinetab2-rk3566)
>        - Pine64 Quartz64-A Board (quartz64-a-rk3566)

Re: [PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

Hi Kever,

在 2025/1/6 11:06, Kever Yang 写道:
> Hi Tianling.
> 
> You will need add below config for CONFIG_RTL8169:
> 
> CONFIG_SYS_HAS_NONCACHED_MEMORY=y
> 

Thank you for fixing the issue and sorry for my mistake.
I will be more careful next time.

Thanks,
Tianling.

> 
> Or else we will get below error in CI:
> 
>     aarch64:  +   nanopi-r3s-rk3566
> +drivers/net/rtl8169.c:320:2: error: #warning cache-line size is larger 
> than descriptor size [-Werror=cpp]
> +  320 | #warning cache-line size is larger than descriptor size
> +      |  ^~~~~~~
> +cc1: all warnings being treated as errors
> +make[3]: *** [scripts/Makefile.build:257: drivers/net/rtl8169.o] Error 1
> +make[2]: *** [scripts/Makefile.build:398: drivers/net] Error 2
> +make[1]: *** [Makefile:1906: drivers] Error 2
> +make: *** [Makefile:177: sub-make] Error 2
> 
> https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/jobs/988639
> 
> 
> Thanks,
> 
> - Kever
> 
> On 2024/12/26 17:20, Tianling Shen wrote:
>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>> Ethernet ports designed and developed by FriendlyElec for IoT
>> applications.
>>
>> Specification:
>> - Rockchip RK3566
>> - 2GB LPDDR4X RAM
>> - optional 32GB eMMC module
>> - SD card slot
>> - 2x 1000 Base-T
>> - 3x LEDs (POWER, LAN, WAN)
>> - 2x Buttons (Reset, MaskROM)
>> - 1x USB 3.0 Port
>> - Type-C 5V 2A Power
>>
>> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
>> ---
>>   arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
>>   board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
>>   configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
>>   doc/board/rockchip/rockchip.rst            |  1 +
>>   4 files changed, 90 insertions(+)
>>   create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>>   create mode 100644 configs/nanopi-r3s-rk3566_defconfig
>>
>> diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/ 
>> dts/rk3566-nanopi-r3s-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..b66e5015d6
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>> @@ -0,0 +1,8 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +
>> +#include "rk356x-u-boot.dtsi"
>> +
>> +&vcc5v0_usb {
>> +    /delete-property/ regulator-always-on;
>> +    /delete-property/ regulator-boot-on;
>> +};
>> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/ 
>> evb_rk3568/MAINTAINERS
>> index 588134ecb2..b2780401a3 100644
>> --- a/board/rockchip/evb_rk3568/MAINTAINERS
>> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
>> @@ -28,6 +28,13 @@ F:    configs/lubancat-2-rk3568_defconfig
>>   F:    arch/arm/dts/rk3568-lubancat-2.dts
>>   F:    arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>> +NANOPI-R3S
>> +M:    Tianling Shen <cnsztl@gmail.com>
>> +R:    Jonas Karlman <jonas@kwiboo.se>
>> +S:    Maintained
>> +F:    configs/nanopi-r3s-rk3566_defconfig
>> +F:    arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>> +
>>   NANOPI-R5C
>>   M:    Tianling Shen <cnsztl@gmail.com>
>>   R:    Jonas Karlman <jonas@kwiboo.se>
>> diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s- 
>> rk3566_defconfig
>> new file mode 100644
>> index 0000000000..f21c703ca7
>> --- /dev/null
>> +++ b/configs/nanopi-r3s-rk3566_defconfig
>> @@ -0,0 +1,74 @@
>> +CONFIG_ARM=y
>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>> +CONFIG_COUNTER_FREQUENCY=24000000
>> +CONFIG_ARCH_ROCKCHIP=y
>> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
>> +CONFIG_ROCKCHIP_RK3568=y
>> +CONFIG_SPL_SERIAL=y
>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>> +CONFIG_DEBUG_UART_BASE=0xFE660000
>> +CONFIG_DEBUG_UART_CLOCK=24000000
>> +CONFIG_PCI=y
>> +CONFIG_DEBUG_UART=y
>> +CONFIG_FIT=y
>> +CONFIG_FIT_VERBOSE=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>> +CONFIG_SPL_MAX_SIZE=0x40000
>> +CONFIG_SPL_PAD_TO=0x7f8000
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +CONFIG_SPL_ATF=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_PCI=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_PMIC=y
>> +CONFIG_CMD_REGULATOR=y
>> +# CONFIG_SPL_DOS_PARTITION is not set
>> +CONFIG_SPL_OF_CONTROL=y
>> +CONFIG_OF_LIVE=y
>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned- 
>> clocks assigned-clock-rates assigned-clock-parents"
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> +CONFIG_SPL_REGMAP=y
>> +CONFIG_SPL_SYSCON=y
>> +CONFIG_SPL_CLK=y
>> +CONFIG_ROCKCHIP_GPIO=y
>> +CONFIG_SYS_I2C_ROCKCHIP=y
>> +CONFIG_LED=y
>> +CONFIG_LED_GPIO=y
>> +CONFIG_MISC=y
>> +CONFIG_SUPPORT_EMMC_RPMB=y
>> +CONFIG_MMC_DW=y
>> +CONFIG_MMC_DW_ROCKCHIP=y
>> +CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_SDMA=y
>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>> +CONFIG_PHY_REALTEK=y
>> +CONFIG_DWC_ETH_QOS=y
>> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
>> +CONFIG_RTL8169=y
>> +CONFIG_NVME_PCI=y
>> +CONFIG_PCIE_DW_ROCKCHIP=y
>> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
>> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
>> +CONFIG_SPL_PINCTRL=y
>> +CONFIG_DM_PMIC=y
>> +CONFIG_PMIC_RK8XX=y
>> +CONFIG_REGULATOR_RK8XX=y
>> +CONFIG_PWM_ROCKCHIP=y
>> +CONFIG_SPL_RAM=y
>> +CONFIG_BAUDRATE=1500000
>> +CONFIG_DEBUG_UART_SHIFT=2
>> +CONFIG_SYS_NS16550_MEM32=y
>> +CONFIG_SYSRESET=y
>> +CONFIG_USB=y
>> +CONFIG_USB_XHCI_HCD=y
>> +CONFIG_USB_DWC3=y
>> +CONFIG_USB_DWC3_GENERIC=y
>> +CONFIG_ERRNO_STR=y
>> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/ 
>> rockchip.rst
>> index 9bab86d234..02d7a4b124 100644
>> --- a/doc/board/rockchip/rockchip.rst
>> +++ b/doc/board/rockchip/rockchip.rst
>> @@ -99,6 +99,7 @@ List of mainline supported Rockchip boards:
>>   * rk3566
>>        - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
>> +     - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
>>        - Hardkernel ODROID-M1S (odroid-m1s-rk3566)
>>        - Pine64 PineTab2 (pinetab2-rk3566)
>>        - Pine64 Quartz64-A Board (quartz64-a-rk3566)

Re: [PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Quentin Schulz]

Hi Tianling,

On 12/26/24 10:20 AM, Tianling Shen wrote:
> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
> Ethernet ports designed and developed by FriendlyElec for IoT
> applications.
> 
> Specification:
> - Rockchip RK3566
> - 2GB LPDDR4X RAM
> - optional 32GB eMMC module
> - SD card slot
> - 2x 1000 Base-T
> - 3x LEDs (POWER, LAN, WAN)
> - 2x Buttons (Reset, MaskROM)
> - 1x USB 3.0 Port
> - Type-C 5V 2A Power
> 
> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
> ---
>   arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
>   board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
>   configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
>   doc/board/rockchip/rockchip.rst            |  1 +
>   4 files changed, 90 insertions(+)
>   create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>   create mode 100644 configs/nanopi-r3s-rk3566_defconfig
> 
> diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> new file mode 100644
> index 0000000000..b66e5015d6
> --- /dev/null
> +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +#include "rk356x-u-boot.dtsi"
> +
> +&vcc5v0_usb {
> +	/delete-property/ regulator-always-on;
> +	/delete-property/ regulator-boot-on;
> +};

Please justify this change, this seems very odd.

> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS
> index 588134ecb2..b2780401a3 100644
> --- a/board/rockchip/evb_rk3568/MAINTAINERS
> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
> @@ -28,6 +28,13 @@ F:	configs/lubancat-2-rk3568_defconfig
>   F:	arch/arm/dts/rk3568-lubancat-2.dts
>   F:	arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>   
> +NANOPI-R3S
> +M:	Tianling Shen <cnsztl@gmail.com>
> +R:	Jonas Karlman <jonas@kwiboo.se>
> +S:	Maintained
> +F:	configs/nanopi-r3s-rk3566_defconfig
> +F:	arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
> +
>   NANOPI-R5C
>   M:	Tianling Shen <cnsztl@gmail.com>
>   R:	Jonas Karlman <jonas@kwiboo.se>
> diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig
> new file mode 100644
> index 0000000000..f21c703ca7
> --- /dev/null
> +++ b/configs/nanopi-r3s-rk3566_defconfig
> @@ -0,0 +1,74 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
> +CONFIG_ROCKCHIP_RK3568=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFE660000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_PCI=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_ATF=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_RTL8169=y
> +CONFIG_NVME_PCI=y

I didn't see any PCIe connector for an NVMe on the R3S[1]? Did I miss 
something? The wiki seems to indicate there may be an NVME but that 
could be just a bad copy-pasting[2]?

[1] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R3S
[2] 
https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R3S#Expand_Docker_Storage

Cheers,
Quentin

Re: [PATCH 7/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

Hi Quentin,

On 2025/1/14 22:48, Quentin Schulz wrote:
> Hi Tianling,
> 
> On 12/26/24 10:20 AM, Tianling Shen wrote:
>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>> Ethernet ports designed and developed by FriendlyElec for IoT
>> applications.
>>
>> Specification:
>> - Rockchip RK3566
>> - 2GB LPDDR4X RAM
>> - optional 32GB eMMC module
>> - SD card slot
>> - 2x 1000 Base-T
>> - 3x LEDs (POWER, LAN, WAN)
>> - 2x Buttons (Reset, MaskROM)
>> - 1x USB 3.0 Port
>> - Type-C 5V 2A Power
>>
>> Signed-off-by: Tianling Shen <cnsztl@gmail.com>
>> ---
>>   arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi |  8 +++
>>   board/rockchip/evb_rk3568/MAINTAINERS      |  7 ++
>>   configs/nanopi-r3s-rk3566_defconfig        | 74 ++++++++++++++++++++++
>>   doc/board/rockchip/rockchip.rst            |  1 +
>>   4 files changed, 90 insertions(+)
>>   create mode 100644 arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>>   create mode 100644 configs/nanopi-r3s-rk3566_defconfig
>>
>> diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/ 
>> dts/rk3566-nanopi-r3s-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..b66e5015d6
>> --- /dev/null
>> +++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>> @@ -0,0 +1,8 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +
>> +#include "rk356x-u-boot.dtsi"
>> +
>> +&vcc5v0_usb {
>> +    /delete-property/ regulator-always-on;
>> +    /delete-property/ regulator-boot-on;
>> +};
> 
> Please justify this change, this seems very odd.

This change is based on commit 5b155997d445 "rockchip: rk3568-nanopi-r5: 
Update defconfig for NanoPi R5C and R5S" and it's copy&paste.

And another commit a9e9445ea2bb "rockchip: rk3568-nanopi-r5: Enable PCIe 
on NanoPi R5C and R5S" removes the vpcie3v3-supply prop, not sure why.

> 
>> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/ 
>> evb_rk3568/MAINTAINERS
>> index 588134ecb2..b2780401a3 100644
>> --- a/board/rockchip/evb_rk3568/MAINTAINERS
>> +++ b/board/rockchip/evb_rk3568/MAINTAINERS
>> @@ -28,6 +28,13 @@ F:    configs/lubancat-2-rk3568_defconfig
>>   F:    arch/arm/dts/rk3568-lubancat-2.dts
>>   F:    arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi
>> +NANOPI-R3S
>> +M:    Tianling Shen <cnsztl@gmail.com>
>> +R:    Jonas Karlman <jonas@kwiboo.se>
>> +S:    Maintained
>> +F:    configs/nanopi-r3s-rk3566_defconfig
>> +F:    arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi
>> +
>>   NANOPI-R5C
>>   M:    Tianling Shen <cnsztl@gmail.com>
>>   R:    Jonas Karlman <jonas@kwiboo.se>
>> diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s- 
>> rk3566_defconfig
>> new file mode 100644
>> index 0000000000..f21c703ca7
>> --- /dev/null
>> +++ b/configs/nanopi-r3s-rk3566_defconfig
>> @@ -0,0 +1,74 @@
>> +CONFIG_ARM=y
>> +CONFIG_SKIP_LOWLEVEL_INIT=y
>> +CONFIG_COUNTER_FREQUENCY=24000000
>> +CONFIG_ARCH_ROCKCHIP=y
>> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s"
>> +CONFIG_ROCKCHIP_RK3568=y
>> +CONFIG_SPL_SERIAL=y
>> +CONFIG_SYS_LOAD_ADDR=0xc00800
>> +CONFIG_DEBUG_UART_BASE=0xFE660000
>> +CONFIG_DEBUG_UART_CLOCK=24000000
>> +CONFIG_PCI=y
>> +CONFIG_DEBUG_UART=y
>> +CONFIG_FIT=y
>> +CONFIG_FIT_VERBOSE=y
>> +CONFIG_SPL_FIT_SIGNATURE=y
>> +CONFIG_SPL_LOAD_FIT=y
>> +CONFIG_LEGACY_IMAGE_FORMAT=y
>> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
>> +# CONFIG_DISPLAY_CPUINFO is not set
>> +CONFIG_DISPLAY_BOARDINFO_LATE=y
>> +CONFIG_SPL_MAX_SIZE=0x40000
>> +CONFIG_SPL_PAD_TO=0x7f8000
>> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
>> +CONFIG_SPL_ATF=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_GPT=y
>> +CONFIG_CMD_I2C=y
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_PCI=y
>> +CONFIG_CMD_USB=y
>> +CONFIG_CMD_PMIC=y
>> +CONFIG_CMD_REGULATOR=y
>> +# CONFIG_SPL_DOS_PARTITION is not set
>> +CONFIG_SPL_OF_CONTROL=y
>> +CONFIG_OF_LIVE=y
>> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned- 
>> clocks assigned-clock-rates assigned-clock-parents"
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> +CONFIG_SPL_REGMAP=y
>> +CONFIG_SPL_SYSCON=y
>> +CONFIG_SPL_CLK=y
>> +CONFIG_ROCKCHIP_GPIO=y
>> +CONFIG_SYS_I2C_ROCKCHIP=y
>> +CONFIG_LED=y
>> +CONFIG_LED_GPIO=y
>> +CONFIG_MISC=y
>> +CONFIG_SUPPORT_EMMC_RPMB=y
>> +CONFIG_MMC_DW=y
>> +CONFIG_MMC_DW_ROCKCHIP=y
>> +CONFIG_MMC_SDHCI=y
>> +CONFIG_MMC_SDHCI_SDMA=y
>> +CONFIG_MMC_SDHCI_ROCKCHIP=y
>> +CONFIG_PHY_REALTEK=y
>> +CONFIG_DWC_ETH_QOS=y
>> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
>> +CONFIG_RTL8169=y
>> +CONFIG_NVME_PCI=y
> 
> I didn't see any PCIe connector for an NVMe on the R3S[1]? Did I miss 
> something? The wiki seems to indicate there may be an NVME but that 
> could be just a bad copy-pasting[2]?

Yes, I checked this board and it does not have NVMe slot. I will send a 
new patch to disable it.

Thanks,
Tianling.

> 
> [1] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R3S
> [2] https://wiki.friendlyelec.com/wiki/index.php/ 
> NanoPi_R3S#Expand_Docker_Storage
> 
> Cheers,
> Quentin

Re: [PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Quentin Schulz]

Hi Tianling,

On 12/26/24 10:20 AM, Tianling Shen wrote:
> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
> Ethernet ports designed and developed by FriendlyElec for IoT
> applications.
> 
> Tianling Shen (7):
>    arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
>    arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
>    arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi
>      R3S
>    arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
>    arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
>    arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S

How did you backport the above patches?

./tools/update-subtree.sh pick dts <commit>

is the tool to be used, it should have added a

(cherry picked from commit ...)

in the commit log.

Cheers,
Quentin

Re: [PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

Hi Quentin,

On 2025/1/14 22:39, Quentin Schulz wrote:
> Hi Tianling,
> 
> On 12/26/24 10:20 AM, Tianling Shen wrote:
>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>> Ethernet ports designed and developed by FriendlyElec for IoT
>> applications.
>>
>> Tianling Shen (7):
>>    arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
>>    arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
>>    arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi
>>      R3S
>>    arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi R3S
>>    arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
>>    arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
> 
> How did you backport the above patches?
> 
> ./tools/update-subtree.sh pick dts <commit>
> 
> is the tool to be used, it should have added a
> 

Thank you for the tip! I did not know there's such a script and
I just copy&paste the commit message from linux tree manually.

Thanks,
Tianling.

> (cherry picked from commit ...)
> 
> in the commit log.
> 
> Cheers,
> Quentin

Re: [PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Quentin Schulz]

Hi Tianling,

On 1/14/25 3:49 PM, Tianling Shen wrote:
> Hi Quentin,
> 
> On 2025/1/14 22:39, Quentin Schulz wrote:
>> Hi Tianling,
>>
>> On 12/26/24 10:20 AM, Tianling Shen wrote:
>>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>>> Ethernet ports designed and developed by FriendlyElec for IoT
>>> applications.
>>>
>>> Tianling Shen (7):
>>>    arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
>>>    arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
>>>    arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi
>>>      R3S
>>>    arm64: dts: rockchip: sort props in pmu_io_domains node for NanoPi 
>>> R3S
>>>    arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
>>>    arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
>>
>> How did you backport the above patches?
>>
>> ./tools/update-subtree.sh pick dts <commit>
>>
>> is the tool to be used, it should have added a
>>
> 
> Thank you for the tip! I did not know there's such a script and
> I just copy&paste the commit message from linux tree manually.
> 

Mmmm, how did you apply the patch in your tree then? Trying to figure 
out how we can avoid this in the future.

I'm wondering if we shouldn't have tooling in place to detect when 
things aren't done the proper way (for maintainers I mean). We 
**really** want to have dts/upstream be upstream + some patches that 
were already merged in devicetree-rebasing tree. I don't know enough 
about subtree merges that Tom does when updating to a new tagged release 
to know if it's actually safe or if the possible mistake made when 
applying a commit by hand can persist without us noticing. I guess a 
mistake made in a manually applied patch would be caught by Tom during 
the merge from the next release with a merge conflict, but then that's 
pain for him to debug.

Cheers,
Quentin

Re: [PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Tianling Shen]

Hi Quentin,

On 2025/1/14 23:21, Quentin Schulz wrote:
> Hi Tianling,
> 
> On 1/14/25 3:49 PM, Tianling Shen wrote:
>> Hi Quentin,
>>
>> On 2025/1/14 22:39, Quentin Schulz wrote:
>>> Hi Tianling,
>>>
>>> On 12/26/24 10:20 AM, Tianling Shen wrote:
>>>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>>>> Ethernet ports designed and developed by FriendlyElec for IoT
>>>> applications.
>>>>
>>>> Tianling Shen (7):
>>>>    arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
>>>>    arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
>>>>    arm64: dts: rockchip: replace deprecated snps,reset props for NanoPi
>>>>      R3S
>>>>    arm64: dts: rockchip: sort props in pmu_io_domains node for 
>>>> NanoPi R3S
>>>>    arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
>>>>    arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
>>>
>>> How did you backport the above patches?
>>>
>>> ./tools/update-subtree.sh pick dts <commit>
>>>
>>> is the tool to be used, it should have added a
>>>
>>
>> Thank you for the tip! I did not know there's such a script and
>> I just copy&paste the commit message from linux tree manually.
>>
> 
> Mmmm, how did you apply the patch in your tree then? Trying to figure 
> out how we can avoid this in the future.

I fetched the patches[1] as-is from kernel and applied them by `git am 
-3` with path correction, then maually added the line "[ upstream 
commit: xxxxxx ]" to commit message.

1. 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=50decd493c8394c52d04561fe4ede34df27a46ba
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=b5bf84206a5c77528f9dd4cbca4e72caa063c102
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=82b2868937883b65732da498b26366d34db61510
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=17e150fdd983c7e59b9240e34a166285f3c3fb39
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=1b5365034410f1ca21adadadd492b99bdf4f2c55
  
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/patch/?id=b7cd1115456d312f8c5e60c80fdc35fd35ea6eab

> 
> I'm wondering if we shouldn't have tooling in place to detect when 
> things aren't done the proper way (for maintainers I mean). We 
> **really** want to have dts/upstream be upstream + some patches that 
> were already merged in devicetree-rebasing tree. I don't know enough 
> about subtree merges that Tom does when updating to a new tagged release 
> to know if it's actually safe or if the possible mistake made when 
> applying a commit by hand can persist without us noticing. I guess a 
> mistake made in a manually applied patch would be caught by Tom during 
> the merge from the next release with a merge conflict, but then that's 
> pain for him to debug.

I'm really sorry for that. All of those commits were already landed on 
devicetree-rebasing tree so hope everything would be fine.

Thanks,
Tianling.

> 
> Cheers,
> Quentin

Re: [PATCH 0/7] board: rockchip: add FriendlyElec NanoPi R3S

[Quentin Schulz]

Hi Tianling,

On 1/14/25 5:14 PM, Tianling Shen wrote:
> Hi Quentin,
> 
> On 2025/1/14 23:21, Quentin Schulz wrote:
>> Hi Tianling,
>>
>> On 1/14/25 3:49 PM, Tianling Shen wrote:
>>> Hi Quentin,
>>>
>>> On 2025/1/14 22:39, Quentin Schulz wrote:
>>>> Hi Tianling,
>>>>
>>>> On 12/26/24 10:20 AM, Tianling Shen wrote:
>>>>> The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
>>>>> Ethernet ports designed and developed by FriendlyElec for IoT
>>>>> applications.
>>>>>
>>>>> Tianling Shen (7):
>>>>>    arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
>>>>>    arm64: dts: rockchip: fix model name for FriendlyElec NanoPi R3S
>>>>>    arm64: dts: rockchip: replace deprecated snps,reset props for 
>>>>> NanoPi
>>>>>      R3S
>>>>>    arm64: dts: rockchip: sort props in pmu_io_domains node for 
>>>>> NanoPi R3S
>>>>>    arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
>>>>>    arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
>>>>
>>>> How did you backport the above patches?
>>>>
>>>> ./tools/update-subtree.sh pick dts <commit>
>>>>
>>>> is the tool to be used, it should have added a
>>>>
>>>
>>> Thank you for the tip! I did not know there's such a script and
>>> I just copy&paste the commit message from linux tree manually.
>>>
>>
>> Mmmm, how did you apply the patch in your tree then? Trying to figure 
>> out how we can avoid this in the future.
> 
> I fetched the patches[1] as-is from kernel and applied them by `git am 
> -3` with path correction, then maually added the line "[ upstream 
> commit: xxxxxx ]" to commit message.
> 
> 1. https://eur02.safelinks.protection.outlook.com/? 
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Thanks for explaining!

>>
>> I'm wondering if we shouldn't have tooling in place to detect when 
>> things aren't done the proper way (for maintainers I mean). We 
>> **really** want to have dts/upstream be upstream + some patches that 
>> were already merged in devicetree-rebasing tree. I don't know enough 
>> about subtree merges that Tom does when updating to a new tagged 
>> release to know if it's actually safe or if the possible mistake made 
>> when applying a commit by hand can persist without us noticing. I 
>> guess a mistake made in a manually applied patch would be caught by 
>> Tom during the merge from the next release with a merge conflict, but 
>> then that's pain for him to debug.
> 
> I'm really sorry for that. All of those commits were already landed on 
> devicetree-rebasing tree so hope everything would be fine.
> 

Nothing to feel sorry for, we should have caught that before merging the 
patches, so the blame is rather on reviewers/maintainers :) If someone 
made the mistake once, it'll happen a second time. I'm glad it was 
caught now, so at least we're aware it's a possibility and we should 
either be more vigilant or write tooling for that.

For what it's worth, the documentation is here on how to cherry pick 
device tree changes: 
https://docs.u-boot.org/en/latest/develop/devicetree/control.html#resyncing-with-devicetree-rebasing

I'm not too sure if there's tooling we could write to check that the 
patches to dts/upstream, were done the proper way. I'm not sure anyone 
wants to touch the checkpatch Perl script and that would still not 
necessarily be run by the maintainer(s) when merging (don't know what's 
the process there). If merge requests are always coming from a GitLab 
tree, maybe there's something we could do from GitLab CI for any change 
made in dts/upstream/ subtree? (like remove the commit, reapply the 
patch on its parent with ./tools/update-subtree.sh pick dts pick <> and 
see if the commit log and content is the same?).

+Cc Tom for at least awareness, hope you don't mind.

Maybe I'm also making this a bigger problem than it is as I am no 
maintainer :)

Cheers,
Quentin