* Re: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
@ 2024-12-31 3:10 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2024-12-31 3:10 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp, Dan Carpenter
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
In-Reply-To: <20241229145027.3984542-12-dario.binacchi@amarulasolutions.com>
References: <20241229145027.3984542-12-dario.binacchi@amarulasolutions.com>
TO: Dario Binacchi <dario.binacchi@amarulasolutions.com>
TO: linux-kernel@vger.kernel.org
CC: linux-amarula@amarulasolutions.com
CC: Dario Binacchi <dario.binacchi@amarulasolutions.com>
CC: Abel Vesa <abelvesa@kernel.org>
CC: Fabio Estevam <festevam@gmail.com>
CC: Michael Turquette <mturquette@baylibre.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Pengutronix Kernel Team <kernel@pengutronix.de>
CC: Sascha Hauer <s.hauer@pengutronix.de>
CC: Shawn Guo <shawnguo@kernel.org>
CC: Stephen Boyd <sboyd@kernel.org>
CC: imx@lists.linux.dev
CC: linux-arm-kernel@lists.infradead.org
CC: linux-clk@vger.kernel.org
Hi Dario,
kernel test robot noticed the following build warnings:
[auto build test WARNING on shawnguo/for-next]
[also build test WARNING on clk/clk-next linus/master v6.13-rc5 next-20241220]
[cannot apply to abelvesa/clk/imx]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dario-Binacchi/dt-bindings-clock-imx8mm-add-VIDEO_PLL-clocks/20241229-225716
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
patch link: https://lore.kernel.org/r/20241229145027.3984542-12-dario.binacchi%40amarulasolutions.com
patch subject: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
:::::: branch date: 2 days ago
:::::: commit date: 2 days ago
config: arm-randconfig-r071-20241231 (https://download.01.org/0day-ci/archive/20241231/202412311031.781qvq8q-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Closes: https://lore.kernel.org/r/202412311031.781qvq8q-lkp@intel.com/
smatch warnings:
drivers/clk/imx/clk-imx8mn-anatop.c:244 imx8mn_anatop_clocks_probe() error: buffer overflow 'hws' 62 <= 62
vim +/hws +244 drivers/clk/imx/clk-imx8mn-anatop.c
87df58feb5834e Dario Binacchi 2024-12-29 39
87df58feb5834e Dario Binacchi 2024-12-29 40 static int imx8mn_anatop_clocks_probe(struct platform_device *pdev)
87df58feb5834e Dario Binacchi 2024-12-29 41 {
87df58feb5834e Dario Binacchi 2024-12-29 42 struct device *dev = &pdev->dev;
87df58feb5834e Dario Binacchi 2024-12-29 43 struct device_node *np = dev->of_node;
87df58feb5834e Dario Binacchi 2024-12-29 44 void __iomem *base;
87df58feb5834e Dario Binacchi 2024-12-29 45 int ret;
87df58feb5834e Dario Binacchi 2024-12-29 46
87df58feb5834e Dario Binacchi 2024-12-29 47 base = devm_platform_ioremap_resource(pdev, 0);
87df58feb5834e Dario Binacchi 2024-12-29 48 if (IS_ERR(base)) {
87df58feb5834e Dario Binacchi 2024-12-29 49 dev_err(dev, "failed to get base address\n");
87df58feb5834e Dario Binacchi 2024-12-29 50 return PTR_ERR(base);
87df58feb5834e Dario Binacchi 2024-12-29 51 }
87df58feb5834e Dario Binacchi 2024-12-29 52
87df58feb5834e Dario Binacchi 2024-12-29 53 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
87df58feb5834e Dario Binacchi 2024-12-29 54 IMX8MN_ANATOP_CLK_END),
87df58feb5834e Dario Binacchi 2024-12-29 55 GFP_KERNEL);
87df58feb5834e Dario Binacchi 2024-12-29 56 if (WARN_ON(!clk_hw_data))
87df58feb5834e Dario Binacchi 2024-12-29 57 return -ENOMEM;
87df58feb5834e Dario Binacchi 2024-12-29 58
87df58feb5834e Dario Binacchi 2024-12-29 59 clk_hw_data->num = IMX8MN_ANATOP_CLK_END;
87df58feb5834e Dario Binacchi 2024-12-29 60 hws = clk_hw_data->hws;
87df58feb5834e Dario Binacchi 2024-12-29 61
87df58feb5834e Dario Binacchi 2024-12-29 62 hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
87df58feb5834e Dario Binacchi 2024-12-29 63 hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
87df58feb5834e Dario Binacchi 2024-12-29 64 hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
87df58feb5834e Dario Binacchi 2024-12-29 65
87df58feb5834e Dario Binacchi 2024-12-29 66 hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 67 imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 68 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 69 hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 70 imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 71 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 72 hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 73 imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 74 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 75 hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 76 imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 77 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 78 hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 79 imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 80 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 81 hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 82 imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 83 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 84 hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 85 imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 86 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 87 hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 88 imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 89 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 90
87df58feb5834e Dario Binacchi 2024-12-29 91 hws[IMX8MN_ANATOP_AUDIO_PLL1] =
87df58feb5834e Dario Binacchi 2024-12-29 92 imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 93 base, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 94 hws[IMX8MN_ANATOP_AUDIO_PLL2] =
87df58feb5834e Dario Binacchi 2024-12-29 95 imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 96 base + 0x14, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 97 hws[IMX8MN_ANATOP_VIDEO_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 98 imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 99 base + 0x28, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 100 hws[IMX8MN_ANATOP_DRAM_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 101 imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
87df58feb5834e Dario Binacchi 2024-12-29 102 &imx_1443x_dram_pll);
87df58feb5834e Dario Binacchi 2024-12-29 103 hws[IMX8MN_ANATOP_GPU_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 104 imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64,
87df58feb5834e Dario Binacchi 2024-12-29 105 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 106 hws[IMX8MN_ANATOP_M7_ALT_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 107 imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 108 base + 0x74, &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 109 hws[IMX8MN_ANATOP_ARM_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 110 imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
87df58feb5834e Dario Binacchi 2024-12-29 111 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 112 hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
87df58feb5834e Dario Binacchi 2024-12-29 113 hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
87df58feb5834e Dario Binacchi 2024-12-29 114 hws[IMX8MN_ANATOP_SYS_PLL3] =
87df58feb5834e Dario Binacchi 2024-12-29 115 imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
87df58feb5834e Dario Binacchi 2024-12-29 116 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 117
87df58feb5834e Dario Binacchi 2024-12-29 118 /* PLL bypass out */
87df58feb5834e Dario Binacchi 2024-12-29 119 hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 120 imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 121 audio_pll1_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 122 ARRAY_SIZE(audio_pll1_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 123 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 124 hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 125 imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 126 audio_pll2_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 127 ARRAY_SIZE(audio_pll2_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 128 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 129 hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 130 imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 131 video_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 132 ARRAY_SIZE(video_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 133 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 134 hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 135 imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 136 dram_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 137 ARRAY_SIZE(dram_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 138 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 139 hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 140 imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 141 gpu_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 142 ARRAY_SIZE(gpu_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 143 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 144 hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 145 imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 146 m7_alt_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 147 ARRAY_SIZE(m7_alt_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 148 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 149 hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 150 imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 151 arm_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 152 ARRAY_SIZE(arm_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 153 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 154 hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 155 imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 156 sys_pll3_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 157 ARRAY_SIZE(sys_pll3_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 158 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 159
87df58feb5834e Dario Binacchi 2024-12-29 160 /* PLL out gate */
87df58feb5834e Dario Binacchi 2024-12-29 161 hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 162 imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 163 base, 13);
87df58feb5834e Dario Binacchi 2024-12-29 164 hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 165 imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 166 base + 0x14, 13);
87df58feb5834e Dario Binacchi 2024-12-29 167 hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 168 imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 169 base + 0x28, 13);
87df58feb5834e Dario Binacchi 2024-12-29 170 hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 171 imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 172 base + 0x50, 13);
87df58feb5834e Dario Binacchi 2024-12-29 173 hws[IMX8MN_ANATOP_GPU_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 174 imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 175 base + 0x64, 11);
87df58feb5834e Dario Binacchi 2024-12-29 176 hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 177 imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 178 base + 0x74, 11);
87df58feb5834e Dario Binacchi 2024-12-29 179 hws[IMX8MN_ANATOP_ARM_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 180 imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 181 base + 0x84, 11);
87df58feb5834e Dario Binacchi 2024-12-29 182 hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 183 imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 184 base + 0x114, 11);
87df58feb5834e Dario Binacchi 2024-12-29 185
87df58feb5834e Dario Binacchi 2024-12-29 186 /* SYS PLL1 fixed output */
87df58feb5834e Dario Binacchi 2024-12-29 187 hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 188 imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
87df58feb5834e Dario Binacchi 2024-12-29 189 hws[IMX8MN_ANATOP_SYS_PLL1_40M] =
87df58feb5834e Dario Binacchi 2024-12-29 190 imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
87df58feb5834e Dario Binacchi 2024-12-29 191 hws[IMX8MN_ANATOP_SYS_PLL1_80M] =
87df58feb5834e Dario Binacchi 2024-12-29 192 imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
87df58feb5834e Dario Binacchi 2024-12-29 193 hws[IMX8MN_ANATOP_SYS_PLL1_100M] =
87df58feb5834e Dario Binacchi 2024-12-29 194 imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
87df58feb5834e Dario Binacchi 2024-12-29 195 hws[IMX8MN_ANATOP_SYS_PLL1_133M] =
87df58feb5834e Dario Binacchi 2024-12-29 196 imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
87df58feb5834e Dario Binacchi 2024-12-29 197 hws[IMX8MN_ANATOP_SYS_PLL1_160M] =
87df58feb5834e Dario Binacchi 2024-12-29 198 imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
87df58feb5834e Dario Binacchi 2024-12-29 199 hws[IMX8MN_ANATOP_SYS_PLL1_200M] =
87df58feb5834e Dario Binacchi 2024-12-29 200 imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
87df58feb5834e Dario Binacchi 2024-12-29 201 hws[IMX8MN_ANATOP_SYS_PLL1_266M] =
87df58feb5834e Dario Binacchi 2024-12-29 202 imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
87df58feb5834e Dario Binacchi 2024-12-29 203 hws[IMX8MN_ANATOP_SYS_PLL1_400M] =
87df58feb5834e Dario Binacchi 2024-12-29 204 imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
87df58feb5834e Dario Binacchi 2024-12-29 205 hws[IMX8MN_ANATOP_SYS_PLL1_800M] =
87df58feb5834e Dario Binacchi 2024-12-29 206 imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
87df58feb5834e Dario Binacchi 2024-12-29 207
87df58feb5834e Dario Binacchi 2024-12-29 208 /* SYS PLL2 fixed output */
87df58feb5834e Dario Binacchi 2024-12-29 209 hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 210 imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
87df58feb5834e Dario Binacchi 2024-12-29 211 hws[IMX8MN_ANATOP_SYS_PLL2_50M] =
87df58feb5834e Dario Binacchi 2024-12-29 212 imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
87df58feb5834e Dario Binacchi 2024-12-29 213 hws[IMX8MN_ANATOP_SYS_PLL2_100M] =
87df58feb5834e Dario Binacchi 2024-12-29 214 imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
87df58feb5834e Dario Binacchi 2024-12-29 215 hws[IMX8MN_ANATOP_SYS_PLL2_125M] =
87df58feb5834e Dario Binacchi 2024-12-29 216 imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
87df58feb5834e Dario Binacchi 2024-12-29 217 hws[IMX8MN_ANATOP_SYS_PLL2_166M] =
87df58feb5834e Dario Binacchi 2024-12-29 218 imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
87df58feb5834e Dario Binacchi 2024-12-29 219 hws[IMX8MN_ANATOP_SYS_PLL2_200M] =
87df58feb5834e Dario Binacchi 2024-12-29 220 imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
87df58feb5834e Dario Binacchi 2024-12-29 221 hws[IMX8MN_ANATOP_SYS_PLL2_250M] =
87df58feb5834e Dario Binacchi 2024-12-29 222 imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
87df58feb5834e Dario Binacchi 2024-12-29 223 hws[IMX8MN_ANATOP_SYS_PLL2_333M] =
87df58feb5834e Dario Binacchi 2024-12-29 224 imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
87df58feb5834e Dario Binacchi 2024-12-29 225 hws[IMX8MN_ANATOP_SYS_PLL2_500M] =
87df58feb5834e Dario Binacchi 2024-12-29 226 imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
87df58feb5834e Dario Binacchi 2024-12-29 227 hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =
87df58feb5834e Dario Binacchi 2024-12-29 228 imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
87df58feb5834e Dario Binacchi 2024-12-29 229
87df58feb5834e Dario Binacchi 2024-12-29 230 hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 231 imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
87df58feb5834e Dario Binacchi 2024-12-29 232 clkout_sels, ARRAY_SIZE(clkout_sels));
87df58feb5834e Dario Binacchi 2024-12-29 233 hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =
87df58feb5834e Dario Binacchi 2024-12-29 234 imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128,
87df58feb5834e Dario Binacchi 2024-12-29 235 0, 4);
87df58feb5834e Dario Binacchi 2024-12-29 236 hws[IMX8MN_ANATOP_CLK_CLKOUT1] =
87df58feb5834e Dario Binacchi 2024-12-29 237 imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
87df58feb5834e Dario Binacchi 2024-12-29 238 hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 239 imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
87df58feb5834e Dario Binacchi 2024-12-29 240 clkout_sels, ARRAY_SIZE(clkout_sels));
87df58feb5834e Dario Binacchi 2024-12-29 241 hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =
87df58feb5834e Dario Binacchi 2024-12-29 242 imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
87df58feb5834e Dario Binacchi 2024-12-29 243 16, 4);
87df58feb5834e Dario Binacchi 2024-12-29 @244 hws[IMX8MN_ANATOP_CLK_CLKOUT2] =
87df58feb5834e Dario Binacchi 2024-12-29 245 imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
87df58feb5834e Dario Binacchi 2024-12-29 246
87df58feb5834e Dario Binacchi 2024-12-29 247 imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END);
87df58feb5834e Dario Binacchi 2024-12-29 248
87df58feb5834e Dario Binacchi 2024-12-29 249 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
87df58feb5834e Dario Binacchi 2024-12-29 250 if (ret < 0) {
87df58feb5834e Dario Binacchi 2024-12-29 251 imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END);
87df58feb5834e Dario Binacchi 2024-12-29 252 return dev_err_probe(dev, ret,
87df58feb5834e Dario Binacchi 2024-12-29 253 "failed to register anatop clock provider\n");
87df58feb5834e Dario Binacchi 2024-12-29 254 }
87df58feb5834e Dario Binacchi 2024-12-29 255
87df58feb5834e Dario Binacchi 2024-12-29 256 dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n");
87df58feb5834e Dario Binacchi 2024-12-29 257 return 0;
87df58feb5834e Dario Binacchi 2024-12-29 258 }
87df58feb5834e Dario Binacchi 2024-12-29 259
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs
@ 2024-12-29 14:49 Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
0 siblings, 1 reply; 4+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Conor Dooley,
Fabio Estevam, Krzysztof Kozlowski, Michael Turquette, Peng Fan,
Pengutronix Kernel Team, Rob Herring, Sascha Hauer, Shawn Guo,
Stephen Boyd, devicetree, imx, linux-arm-kernel, linux-clk
The series adds support for spread spectrum clocking for i.MX8MN
PLLs (audio, video and DRAM). It has been tested for the video PLL on
a board using i.MX8MN.
The patches added in version 4, such as the dt-bindings and the driver
for anatop, were inspired by the extensive email exchange from version 3:
https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@amarulasolutions.com/
The series added spectrum spread support for the imx8mn platform only,
but in case it was merged, confirming that the directives and suggestions
made by the maintainers were correctly understood and implemented, I will
extend this support to the imx8mm and imx8mp platforms as well.
Changes in v8:
- Drop the patches added in version 7:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v7:
- Add and manage fsl,anatop property as phandle to the anatop node with
the new patches:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v6:
- Merge patches:
10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop
11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop
12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop
to
05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names
now renamed
05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
- Split the patch
15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch
into
12/18 dt-bindings: clock: imx8m-clock: add PLLs
16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking
Changes in v5:
- Fix compilation errors.
- Separate driver code from dt-bindings
Changes in v4:
- Add dt-bindings for anatop
- Add anatop driver
- Drop fsl,ssc-clocks from spread spectrum dt-bindings
Changes in v3:
- Patches 1/8 has been added in version 3. The dt-bindings have
been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The
anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a
syscon, so it represents a memory area accessible by ccm
(imx8m-clock.yaml) to setup the PLLs.
- Patches {3,5}/8 have been added in version 3.
- Patches {4,6,8}/8 use ccm device node instead of the anatop one.
Changes in v2:
- Add "allOf:" and place it after "required:" block, like in the
example schema.
- Move the properties definition to the top-level.
- Drop unit types as requested by the "make dt_binding_check" command.
Dario Binacchi (18):
dt-bindings: clock: imx8mm: add VIDEO_PLL clocks
clk: imx8mm: rename video_pll1 to video_pll
dt-bindings: clock: imx8mp: add VIDEO_PLL clocks
clk: imx8mp: rename video_pll1 to video_pll
dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
arm64: dts: imx8mm: add anatop clocks
arm64: dts: imx8mn: add anatop clocks
arm64: dts: imx8mp: add anatop clocks
arm64: dts: imx8mq: add anatop clocks
clk: imx: add hw API imx_anatop_get_clk_hw
clk: imx: add support for i.MX8MN anatop clock driver
dt-bindings: clock: imx8m-clock: add PLLs
arm64: dts: imx8mm: add PLLs to clock controller module (CCM)
arm64: dts: imx8mn: add PLLs to clock controller module (CCM)
arm64: dts: imx8mp: add PLLs to clock controller module (CCM)
dt-bindings: clock: imx8m-clock: support spread spectrum clocking
clk: imx: pll14xx: support spread spectrum clock generation
clk: imx8mn: support spread spectrum clock generation
.../bindings/clock/fsl,imx8m-anatop.yaml | 53 +++-
.../bindings/clock/imx8m-clock.yaml | 74 ++++-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +-
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mm.c | 102 +++----
drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++
drivers/clk/imx/clk-imx8mn.c | 196 ++++++------
drivers/clk/imx/clk-imx8mp.c | 118 ++++----
drivers/clk/imx/clk-pll14xx.c | 134 +++++++++
drivers/clk/imx/clk.c | 15 +
drivers/clk/imx/clk.h | 18 ++
include/dt-bindings/clock/imx8mm-clock.h | 76 ++++-
include/dt-bindings/clock/imx8mn-clock.h | 64 ++++
include/dt-bindings/clock/imx8mp-clock.h | 80 ++++-
17 files changed, 1015 insertions(+), 235 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c
--
2.43.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver 2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi @ 2024-12-29 14:49 ` Dario Binacchi 2025-01-06 9:05 ` Peng Fan 2025-01-06 11:06 ` Dan Carpenter 0 siblings, 2 replies; 4+ messages in thread From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw) To: linux-kernel Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam, Michael Turquette, Peng Fan, Pengutronix Kernel Team, Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> --- Changes in v8: - Drop call of of_parse_phandle() to get the anatop's device node. Changes in v7: - Update the code based on the changes made to the imx8m_anatop_get_clk_hw(): - Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw - Add device_node type parameter - Call of_parse_phandle() to get the anatop's device node. Changes in v6: - Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben removed from include/dt-bindings/clock/imx8mn-clock.h. Changes in v4: - New drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mn.c | 183 ++++++++---------- 3 files changed, 364 insertions(+), 104 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..f0f1d01c68f8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -26,7 +26,7 @@ mxc-clk-objs += clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) += mxc-clk.o obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o -obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o +obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8mn-anatop.c new file mode 100644 index 000000000000..895569d886f4 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mn-anatop.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver + * + * Copyright (c) 2024 Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +#include <dt-bindings/clock/imx8mn-clock.h> + +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/of_platform.h> + +#include "clk.h" + +#define IMX8MN_ANATOP_CLK_END IMX8MN_ANATOP_CLK_CLKOUT2 + +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; +static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "dummy", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MN_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = IMX8MN_ANATOP_CLK_END; + hws = clk_hw_data->hws; + + hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] = + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] = + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] = + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] = + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] = + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] = + imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] = + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] = + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_ANATOP_AUDIO_PLL1] = + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MN_ANATOP_AUDIO_PLL2] = + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MN_ANATOP_VIDEO_PLL] = + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MN_ANATOP_DRAM_PLL] = + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, + &imx_1443x_dram_pll); + hws[IMX8MN_ANATOP_GPU_PLL] = + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_M7_ALT_PLL] = + imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ANATOP_ARM_PLL] = + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, + &imx_1416x_pll); + hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MN_ANATOP_SYS_PLL3] = + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, + &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] = + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] = + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] = + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] = + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] = + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] = + imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, + m7_alt_pll_bypass_sels, + ARRAY_SIZE(m7_alt_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] = + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] = + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] = + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] = + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] = + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MN_ANATOP_DRAM_PLL_OUT] = + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MN_ANATOP_GPU_PLL_OUT] = + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] = + imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", + base + 0x74, 11); + hws[IMX8MN_ANATOP_ARM_PLL_OUT] = + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MN_ANATOP_SYS_PLL3_OUT] = + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL1_OUT] = + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); + hws[IMX8MN_ANATOP_SYS_PLL1_40M] = + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL1_80M] = + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL1_100M] = + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL1_133M] = + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL1_160M] = + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL1_200M] = + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL1_266M] = + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL1_400M] = + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL1_800M] = + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MN_ANATOP_SYS_PLL2_OUT] = + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); + hws[IMX8MN_ANATOP_SYS_PLL2_50M] = + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_ANATOP_SYS_PLL2_100M] = + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_ANATOP_SYS_PLL2_125M] = + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_ANATOP_SYS_PLL2_166M] = + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_ANATOP_SYS_PLL2_200M] = + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_ANATOP_SYS_PLL2_250M] = + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_ANATOP_SYS_PLL2_333M] = + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_ANATOP_SYS_PLL2_500M] = + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MN_ANATOP_SYS_PLL2_1000M] = + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] = + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] = + imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, + 0, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT1] = + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] = + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] = + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MN_ANATOP_CLK_CLKOUT2] = + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mn_anatop_clk_of_match[] = { + { .compatible = "fsl,imx8mn-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match); + +static struct platform_driver imx8mn_anatop_clk_driver = { + .probe = imx8mn_anatop_clocks_probe, + .driver = { + .name = "imx8mn-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs = true, + .of_match_table = imx8mn_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mn_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>"); +MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..c3a3d063d58e 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -24,16 +24,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; -static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; -static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; -static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; -static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", }; -static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; -static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; -static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", }; -static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; -static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; - static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; -static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "dummy", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; static int imx8mn_clocks_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; + struct device_node *np = dev->of_node, *anp; void __iomem *base; int ret; + base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MN_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -331,99 +320,90 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MN_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); - hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); + anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MN_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DUMMY); + hws[IMX8MN_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M); + hws[IMX8MN_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K); hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4"); - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base = devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret = PTR_ERR(base); - goto unregister_hws; - } - - hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); - hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL); + hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_REF_SEL); + hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_REF_SEL); + hws[IMX8MN_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_REF_SEL); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL); + hws[IMX8MN_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_REF_SEL); + hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL); + + hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1); + hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2); + hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL); + hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL); + hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL); + hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL); + hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL); + hws[IMX8MN_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1); + hws[IMX8MN_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2); + hws[IMX8MN_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3); /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_BYPASS); + hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_BYPASS); + hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_BYPASS); + hws[IMX8MN_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_BYPASS); + hws[IMX8MN_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_BYPASS); + hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_BYPASS); + hws[IMX8MN_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_BYPASS); + hws[IMX8MN_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_BYPASS); /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_OUT); + hws[IMX8MN_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_OUT); + hws[IMX8MN_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_OUT); + hws[IMX8MN_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_OUT); + hws[IMX8MN_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_OUT); + hws[IMX8MN_M7_ALT_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_OUT); + hws[IMX8MN_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_OUT); + hws[IMX8MN_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_OUT); /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); - hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + hws[IMX8MN_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_OUT); + hws[IMX8MN_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_40M); + hws[IMX8MN_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_80M); + hws[IMX8MN_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_100M); + hws[IMX8MN_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_133M); + hws[IMX8MN_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_160M); + hws[IMX8MN_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_200M); + hws[IMX8MN_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_266M); + hws[IMX8MN_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_400M); + hws[IMX8MN_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_800M); /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); - hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); - - hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4); - hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); - hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4); - hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); - - np = dev->of_node; - base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) { - ret = PTR_ERR(base); - goto unregister_hws; - } + hws[IMX8MN_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_OUT); + hws[IMX8MN_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_50M); + hws[IMX8MN_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_100M); + hws[IMX8MN_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_125M); + hws[IMX8MN_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_166M); + hws[IMX8MN_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_200M); + hws[IMX8MN_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_250M); + hws[IMX8MN_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_333M); + hws[IMX8MN_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_500M); + hws[IMX8MN_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_1000M); + + hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_SEL); + hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_DIV); + hws[IMX8MN_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1); + hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_SEL); + hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_DIV); + hws[IMX8MN_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2); /* CORE */ hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000); @@ -599,18 +579,15 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); if (ret < 0) { - dev_err(dev, "failed to register hws for i.MX8MN\n"); - goto unregister_hws; + imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); + return dev_err_probe(dev, ret, + "failed to register hws for i.MX8MN\n"); } imx_register_uart_clocks(); + dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n"); return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); - - return ret; } static const struct of_device_id imx8mn_clk_of_match[] = { -- 2.43.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver 2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi @ 2025-01-06 9:05 ` Peng Fan 2025-01-06 11:06 ` Dan Carpenter 1 sibling, 0 replies; 4+ messages in thread From: Peng Fan @ 2025-01-06 9:05 UTC (permalink / raw) To: Dario Binacchi Cc: linux-kernel, linux-amarula, Abel Vesa, Fabio Estevam, Michael Turquette, Peng Fan, Pengutronix Kernel Team, Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk On Sun, Dec 29, 2024 at 03:49:35PM +0100, Dario Binacchi wrote: >Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. >By doing so, we also simplify the CCM driver code. The changes are >backward compatible. > >Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> > Reviewed-by: Peng Fan <peng.fan@nxp.com> ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver 2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi 2025-01-06 9:05 ` Peng Fan @ 2025-01-06 11:06 ` Dan Carpenter 1 sibling, 0 replies; 4+ messages in thread From: Dan Carpenter @ 2025-01-06 11:06 UTC (permalink / raw) To: oe-kbuild, Dario Binacchi, linux-kernel Cc: lkp, oe-kbuild-all, linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam, Michael Turquette, Peng Fan, Pengutronix Kernel Team, Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk Hi Dario, kernel test robot noticed the following build warnings: https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Dario-Binacchi/dt-bindings-clock-imx8mm-add-VIDEO_PLL-clocks/20241229-225716 base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next patch link: https://lore.kernel.org/r/20241229145027.3984542-12-dario.binacchi%40amarulasolutions.com patch subject: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver config: arm-randconfig-r071-20241231 (https://download.01.org/0day-ci/archive/20241231/202412311031.781qvq8q-lkp@intel.com/config) compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Reported-by: Dan Carpenter <dan.carpenter@linaro.org> | Closes: https://lore.kernel.org/r/202412311031.781qvq8q-lkp@intel.com/ smatch warnings: drivers/clk/imx/clk-imx8mn-anatop.c:244 imx8mn_anatop_clocks_probe() error: buffer overflow 'hws' 62 <= 62 vim +/hws +244 drivers/clk/imx/clk-imx8mn-anatop.c 87df58feb5834e Dario Binacchi 2024-12-29 40 static int imx8mn_anatop_clocks_probe(struct platform_device *pdev) 87df58feb5834e Dario Binacchi 2024-12-29 41 { 87df58feb5834e Dario Binacchi 2024-12-29 42 struct device *dev = &pdev->dev; 87df58feb5834e Dario Binacchi 2024-12-29 43 struct device_node *np = dev->of_node; 87df58feb5834e Dario Binacchi 2024-12-29 44 void __iomem *base; 87df58feb5834e Dario Binacchi 2024-12-29 45 int ret; 87df58feb5834e Dario Binacchi 2024-12-29 46 87df58feb5834e Dario Binacchi 2024-12-29 47 base = devm_platform_ioremap_resource(pdev, 0); 87df58feb5834e Dario Binacchi 2024-12-29 48 if (IS_ERR(base)) { 87df58feb5834e Dario Binacchi 2024-12-29 49 dev_err(dev, "failed to get base address\n"); 87df58feb5834e Dario Binacchi 2024-12-29 50 return PTR_ERR(base); 87df58feb5834e Dario Binacchi 2024-12-29 51 } 87df58feb5834e Dario Binacchi 2024-12-29 52 87df58feb5834e Dario Binacchi 2024-12-29 53 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, 87df58feb5834e Dario Binacchi 2024-12-29 54 IMX8MN_ANATOP_CLK_END), IMX8MN_ANATOP_CLK_END is IMX8MN_ANATOP_CLK_CLKOUT2 87df58feb5834e Dario Binacchi 2024-12-29 55 GFP_KERNEL); 87df58feb5834e Dario Binacchi 2024-12-29 56 if (WARN_ON(!clk_hw_data)) 87df58feb5834e Dario Binacchi 2024-12-29 57 return -ENOMEM; 87df58feb5834e Dario Binacchi 2024-12-29 58 87df58feb5834e Dario Binacchi 2024-12-29 59 clk_hw_data->num = IMX8MN_ANATOP_CLK_END; 87df58feb5834e Dario Binacchi 2024-12-29 60 hws = clk_hw_data->hws; 87df58feb5834e Dario Binacchi 2024-12-29 61 87df58feb5834e Dario Binacchi 2024-12-29 62 hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); 87df58feb5834e Dario Binacchi 2024-12-29 63 hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); 87df58feb5834e Dario Binacchi 2024-12-29 64 hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); 87df58feb5834e Dario Binacchi 2024-12-29 65 87df58feb5834e Dario Binacchi 2024-12-29 66 hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 67 imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 68 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 69 hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 70 imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 71 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 72 hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 73 imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 74 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 75 hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 76 imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 77 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 78 hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 79 imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 80 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 81 hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 82 imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 83 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 84 hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 85 imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 86 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 87 hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 88 imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, 87df58feb5834e Dario Binacchi 2024-12-29 89 pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 90 87df58feb5834e Dario Binacchi 2024-12-29 91 hws[IMX8MN_ANATOP_AUDIO_PLL1] = 87df58feb5834e Dario Binacchi 2024-12-29 92 imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", 87df58feb5834e Dario Binacchi 2024-12-29 93 base, &imx_1443x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 94 hws[IMX8MN_ANATOP_AUDIO_PLL2] = 87df58feb5834e Dario Binacchi 2024-12-29 95 imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", 87df58feb5834e Dario Binacchi 2024-12-29 96 base + 0x14, &imx_1443x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 97 hws[IMX8MN_ANATOP_VIDEO_PLL] = 87df58feb5834e Dario Binacchi 2024-12-29 98 imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", 87df58feb5834e Dario Binacchi 2024-12-29 99 base + 0x28, &imx_1443x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 100 hws[IMX8MN_ANATOP_DRAM_PLL] = 87df58feb5834e Dario Binacchi 2024-12-29 101 imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, 87df58feb5834e Dario Binacchi 2024-12-29 102 &imx_1443x_dram_pll); 87df58feb5834e Dario Binacchi 2024-12-29 103 hws[IMX8MN_ANATOP_GPU_PLL] = 87df58feb5834e Dario Binacchi 2024-12-29 104 imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, 87df58feb5834e Dario Binacchi 2024-12-29 105 &imx_1416x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 106 hws[IMX8MN_ANATOP_M7_ALT_PLL] = 87df58feb5834e Dario Binacchi 2024-12-29 107 imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", 87df58feb5834e Dario Binacchi 2024-12-29 108 base + 0x74, &imx_1416x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 109 hws[IMX8MN_ANATOP_ARM_PLL] = 87df58feb5834e Dario Binacchi 2024-12-29 110 imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, 87df58feb5834e Dario Binacchi 2024-12-29 111 &imx_1416x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 112 hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000); 87df58feb5834e Dario Binacchi 2024-12-29 113 hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000); 87df58feb5834e Dario Binacchi 2024-12-29 114 hws[IMX8MN_ANATOP_SYS_PLL3] = 87df58feb5834e Dario Binacchi 2024-12-29 115 imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, 87df58feb5834e Dario Binacchi 2024-12-29 116 &imx_1416x_pll); 87df58feb5834e Dario Binacchi 2024-12-29 117 87df58feb5834e Dario Binacchi 2024-12-29 118 /* PLL bypass out */ 87df58feb5834e Dario Binacchi 2024-12-29 119 hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 120 imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, 87df58feb5834e Dario Binacchi 2024-12-29 121 audio_pll1_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 122 ARRAY_SIZE(audio_pll1_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 123 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 124 hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 125 imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, 87df58feb5834e Dario Binacchi 2024-12-29 126 audio_pll2_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 127 ARRAY_SIZE(audio_pll2_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 128 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 129 hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 130 imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, 87df58feb5834e Dario Binacchi 2024-12-29 131 video_pll_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 132 ARRAY_SIZE(video_pll_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 133 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 134 hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 135 imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, 87df58feb5834e Dario Binacchi 2024-12-29 136 dram_pll_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 137 ARRAY_SIZE(dram_pll_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 138 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 139 hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 140 imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, 87df58feb5834e Dario Binacchi 2024-12-29 141 gpu_pll_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 142 ARRAY_SIZE(gpu_pll_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 143 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 144 hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 145 imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, 87df58feb5834e Dario Binacchi 2024-12-29 146 m7_alt_pll_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 147 ARRAY_SIZE(m7_alt_pll_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 148 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 149 hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 150 imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, 87df58feb5834e Dario Binacchi 2024-12-29 151 arm_pll_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 152 ARRAY_SIZE(arm_pll_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 153 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 154 hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] = 87df58feb5834e Dario Binacchi 2024-12-29 155 imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, 87df58feb5834e Dario Binacchi 2024-12-29 156 sys_pll3_bypass_sels, 87df58feb5834e Dario Binacchi 2024-12-29 157 ARRAY_SIZE(sys_pll3_bypass_sels), 87df58feb5834e Dario Binacchi 2024-12-29 158 CLK_SET_RATE_PARENT); 87df58feb5834e Dario Binacchi 2024-12-29 159 87df58feb5834e Dario Binacchi 2024-12-29 160 /* PLL out gate */ 87df58feb5834e Dario Binacchi 2024-12-29 161 hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 162 imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 163 base, 13); 87df58feb5834e Dario Binacchi 2024-12-29 164 hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 165 imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 166 base + 0x14, 13); 87df58feb5834e Dario Binacchi 2024-12-29 167 hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 168 imx_clk_hw_gate("video_pll_out", "video_pll_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 169 base + 0x28, 13); 87df58feb5834e Dario Binacchi 2024-12-29 170 hws[IMX8MN_ANATOP_DRAM_PLL_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 171 imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 172 base + 0x50, 13); 87df58feb5834e Dario Binacchi 2024-12-29 173 hws[IMX8MN_ANATOP_GPU_PLL_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 174 imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 175 base + 0x64, 11); 87df58feb5834e Dario Binacchi 2024-12-29 176 hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 177 imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 178 base + 0x74, 11); 87df58feb5834e Dario Binacchi 2024-12-29 179 hws[IMX8MN_ANATOP_ARM_PLL_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 180 imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 181 base + 0x84, 11); 87df58feb5834e Dario Binacchi 2024-12-29 182 hws[IMX8MN_ANATOP_SYS_PLL3_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 183 imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", 87df58feb5834e Dario Binacchi 2024-12-29 184 base + 0x114, 11); 87df58feb5834e Dario Binacchi 2024-12-29 185 87df58feb5834e Dario Binacchi 2024-12-29 186 /* SYS PLL1 fixed output */ 87df58feb5834e Dario Binacchi 2024-12-29 187 hws[IMX8MN_ANATOP_SYS_PLL1_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 188 imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); 87df58feb5834e Dario Binacchi 2024-12-29 189 hws[IMX8MN_ANATOP_SYS_PLL1_40M] = 87df58feb5834e Dario Binacchi 2024-12-29 190 imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); 87df58feb5834e Dario Binacchi 2024-12-29 191 hws[IMX8MN_ANATOP_SYS_PLL1_80M] = 87df58feb5834e Dario Binacchi 2024-12-29 192 imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); 87df58feb5834e Dario Binacchi 2024-12-29 193 hws[IMX8MN_ANATOP_SYS_PLL1_100M] = 87df58feb5834e Dario Binacchi 2024-12-29 194 imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); 87df58feb5834e Dario Binacchi 2024-12-29 195 hws[IMX8MN_ANATOP_SYS_PLL1_133M] = 87df58feb5834e Dario Binacchi 2024-12-29 196 imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); 87df58feb5834e Dario Binacchi 2024-12-29 197 hws[IMX8MN_ANATOP_SYS_PLL1_160M] = 87df58feb5834e Dario Binacchi 2024-12-29 198 imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); 87df58feb5834e Dario Binacchi 2024-12-29 199 hws[IMX8MN_ANATOP_SYS_PLL1_200M] = 87df58feb5834e Dario Binacchi 2024-12-29 200 imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); 87df58feb5834e Dario Binacchi 2024-12-29 201 hws[IMX8MN_ANATOP_SYS_PLL1_266M] = 87df58feb5834e Dario Binacchi 2024-12-29 202 imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); 87df58feb5834e Dario Binacchi 2024-12-29 203 hws[IMX8MN_ANATOP_SYS_PLL1_400M] = 87df58feb5834e Dario Binacchi 2024-12-29 204 imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); 87df58feb5834e Dario Binacchi 2024-12-29 205 hws[IMX8MN_ANATOP_SYS_PLL1_800M] = 87df58feb5834e Dario Binacchi 2024-12-29 206 imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); 87df58feb5834e Dario Binacchi 2024-12-29 207 87df58feb5834e Dario Binacchi 2024-12-29 208 /* SYS PLL2 fixed output */ 87df58feb5834e Dario Binacchi 2024-12-29 209 hws[IMX8MN_ANATOP_SYS_PLL2_OUT] = 87df58feb5834e Dario Binacchi 2024-12-29 210 imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); 87df58feb5834e Dario Binacchi 2024-12-29 211 hws[IMX8MN_ANATOP_SYS_PLL2_50M] = 87df58feb5834e Dario Binacchi 2024-12-29 212 imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); 87df58feb5834e Dario Binacchi 2024-12-29 213 hws[IMX8MN_ANATOP_SYS_PLL2_100M] = 87df58feb5834e Dario Binacchi 2024-12-29 214 imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); 87df58feb5834e Dario Binacchi 2024-12-29 215 hws[IMX8MN_ANATOP_SYS_PLL2_125M] = 87df58feb5834e Dario Binacchi 2024-12-29 216 imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); 87df58feb5834e Dario Binacchi 2024-12-29 217 hws[IMX8MN_ANATOP_SYS_PLL2_166M] = 87df58feb5834e Dario Binacchi 2024-12-29 218 imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); 87df58feb5834e Dario Binacchi 2024-12-29 219 hws[IMX8MN_ANATOP_SYS_PLL2_200M] = 87df58feb5834e Dario Binacchi 2024-12-29 220 imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); 87df58feb5834e Dario Binacchi 2024-12-29 221 hws[IMX8MN_ANATOP_SYS_PLL2_250M] = 87df58feb5834e Dario Binacchi 2024-12-29 222 imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); 87df58feb5834e Dario Binacchi 2024-12-29 223 hws[IMX8MN_ANATOP_SYS_PLL2_333M] = 87df58feb5834e Dario Binacchi 2024-12-29 224 imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); 87df58feb5834e Dario Binacchi 2024-12-29 225 hws[IMX8MN_ANATOP_SYS_PLL2_500M] = 87df58feb5834e Dario Binacchi 2024-12-29 226 imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); 87df58feb5834e Dario Binacchi 2024-12-29 227 hws[IMX8MN_ANATOP_SYS_PLL2_1000M] = 87df58feb5834e Dario Binacchi 2024-12-29 228 imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); 87df58feb5834e Dario Binacchi 2024-12-29 229 87df58feb5834e Dario Binacchi 2024-12-29 230 hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 231 imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, 87df58feb5834e Dario Binacchi 2024-12-29 232 clkout_sels, ARRAY_SIZE(clkout_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 233 hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] = 87df58feb5834e Dario Binacchi 2024-12-29 234 imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 87df58feb5834e Dario Binacchi 2024-12-29 235 0, 4); 87df58feb5834e Dario Binacchi 2024-12-29 236 hws[IMX8MN_ANATOP_CLK_CLKOUT1] = 87df58feb5834e Dario Binacchi 2024-12-29 237 imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); 87df58feb5834e Dario Binacchi 2024-12-29 238 hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] = 87df58feb5834e Dario Binacchi 2024-12-29 239 imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, 87df58feb5834e Dario Binacchi 2024-12-29 240 clkout_sels, ARRAY_SIZE(clkout_sels)); 87df58feb5834e Dario Binacchi 2024-12-29 241 hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] = 87df58feb5834e Dario Binacchi 2024-12-29 242 imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 87df58feb5834e Dario Binacchi 2024-12-29 243 16, 4); 87df58feb5834e Dario Binacchi 2024-12-29 @244 hws[IMX8MN_ANATOP_CLK_CLKOUT2] = ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Corruption. 87df58feb5834e Dario Binacchi 2024-12-29 245 imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); 87df58feb5834e Dario Binacchi 2024-12-29 246 87df58feb5834e Dario Binacchi 2024-12-29 247 imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END); 87df58feb5834e Dario Binacchi 2024-12-29 248 87df58feb5834e Dario Binacchi 2024-12-29 249 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 87df58feb5834e Dario Binacchi 2024-12-29 250 if (ret < 0) { 87df58feb5834e Dario Binacchi 2024-12-29 251 imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END); 87df58feb5834e Dario Binacchi 2024-12-29 252 return dev_err_probe(dev, ret, 87df58feb5834e Dario Binacchi 2024-12-29 253 "failed to register anatop clock provider\n"); 87df58feb5834e Dario Binacchi 2024-12-29 254 } 87df58feb5834e Dario Binacchi 2024-12-29 255 87df58feb5834e Dario Binacchi 2024-12-29 256 dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n"); 87df58feb5834e Dario Binacchi 2024-12-29 257 return 0; 87df58feb5834e Dario Binacchi 2024-12-29 258 } -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-01-06 11:06 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-31 3:10 [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver kernel test robot -- strict thread matches above, loose matches on Subject: below -- 2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi 2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi 2025-01-06 9:05 ` Peng Fan 2025-01-06 11:06 ` Dan Carpenter
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