* [PATCH v8 01/18] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 02/18] clk: imx8mm: rename video_pll1 to video_pll Dario Binacchi
` (16 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's add the IMX8MM_VIDEO_PLL[_*]
definitions to be consistent with the RM and avoid misunderstandings.
The IMX8MM_VIDEO_PLL1* constants have not been removed to ensure
backward compatibility of the patch.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v6)
Changes in v6:
- Add 'Acked-by' tag of Krzysztof Kozlowski
Changes in v5:
- New
include/dt-bindings/clock/imx8mm-clock.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 1f768b2eeb1a..102d8a6cdb55 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -16,7 +16,8 @@
#define IMX8MM_CLK_EXT4 7
#define IMX8MM_AUDIO_PLL1_REF_SEL 8
#define IMX8MM_AUDIO_PLL2_REF_SEL 9
-#define IMX8MM_VIDEO_PLL1_REF_SEL 10
+#define IMX8MM_VIDEO_PLL_REF_SEL 10
+#define IMX8MM_VIDEO_PLL1_REF_SEL IMX8MM_VIDEO_PLL_REF_SEL
#define IMX8MM_DRAM_PLL_REF_SEL 11
#define IMX8MM_GPU_PLL_REF_SEL 12
#define IMX8MM_VPU_PLL_REF_SEL 13
@@ -26,7 +27,8 @@
#define IMX8MM_SYS_PLL3_REF_SEL 17
#define IMX8MM_AUDIO_PLL1 18
#define IMX8MM_AUDIO_PLL2 19
-#define IMX8MM_VIDEO_PLL1 20
+#define IMX8MM_VIDEO_PLL 20
+#define IMX8MM_VIDEO_PLL1 IMX8MM_VIDEO_PLL
#define IMX8MM_DRAM_PLL 21
#define IMX8MM_GPU_PLL 22
#define IMX8MM_VPU_PLL 23
@@ -36,7 +38,8 @@
#define IMX8MM_SYS_PLL3 27
#define IMX8MM_AUDIO_PLL1_BYPASS 28
#define IMX8MM_AUDIO_PLL2_BYPASS 29
-#define IMX8MM_VIDEO_PLL1_BYPASS 30
+#define IMX8MM_VIDEO_PLL_BYPASS 30
+#define IMX8MM_VIDEO_PLL1_BYPASS IMX8MM_VIDEO_PLL_BYPASS
#define IMX8MM_DRAM_PLL_BYPASS 31
#define IMX8MM_GPU_PLL_BYPASS 32
#define IMX8MM_VPU_PLL_BYPASS 33
@@ -46,7 +49,8 @@
#define IMX8MM_SYS_PLL3_BYPASS 37
#define IMX8MM_AUDIO_PLL1_OUT 38
#define IMX8MM_AUDIO_PLL2_OUT 39
-#define IMX8MM_VIDEO_PLL1_OUT 40
+#define IMX8MM_VIDEO_PLL_OUT 40
+#define IMX8MM_VIDEO_PLL1_OUT IMX8MM_VIDEO_PLL_OUT
#define IMX8MM_DRAM_PLL_OUT 41
#define IMX8MM_GPU_PLL_OUT 42
#define IMX8MM_VPU_PLL_OUT 43
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 02/18] clk: imx8mm: rename video_pll1 to video_pll
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 01/18] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 03/18] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Dario Binacchi
` (15 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
The patch, which simply replaces video_pll1 with video_pll, highlights
many warnings raised by checkpatch.pl. These are not generated by the
changes made but are inherited from how the module was originally
written. Fixing them would have meant "obscuring" the actual changes
introduced.
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v5:
- Split the patch dropping the dt-bindings changes.
Changes in v4:
- New
drivers/clk/imx/clk-imx8mm.c | 102 +++++++++++++++++------------------
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 342049b847b9..8a1fc7e17ba2 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -28,7 +28,7 @@ static u32 share_count_nand;
static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+static const char *video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -42,22 +42,22 @@ static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m
static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m",
- "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+ "sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
static const char *imx8mm_vpu_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "vpu_pll_out", };
static const char *imx8mm_gpu3d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", "sys_pll3_out",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m",
- "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",};
+ "sys_pll2_1000m", "audio_pll1_out", "video_pll_out", "sys_pll1_100m",};
static const char *imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
- "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+ "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
static const char *imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
"sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
@@ -72,28 +72,28 @@ static const char *imx8mm_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pl
"sys_pll1_40m", "audio_pll2_out", "clk_ext1", "clk_ext3", };
static const char *imx8mm_disp_rtrm_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll2_200m", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "clk_ext2", "clk_ext3", };
+ "audio_pll1_out", "video_pll_out", "clk_ext2", "clk_ext3", };
static const char *imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_100m",
"sys_pll2_200m", "clk_ext2", "clk_ext4", "audio_pll2_out", };
static const char *imx8mm_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", "sys_pll3_out", "sys_pll2_1000m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", "sys_pll2_1000m", "sys_pll2_500m",
- "audio_pll1_out", "video_pll1_out", "audio_pll2_out", };
+ "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_noc_apb_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", "sys_pll2_333m", "sys_pll2_200m",
- "sys_pll1_800m", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll1_800m", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
- "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+ "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", };
static const char *imx8mm_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll3_out", "audio_pll1_out", "sys_pll1_266m", };
@@ -108,10 +108,10 @@ static const char *imx8mm_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
"sys_pll1_100m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", };
static const char *imx8mm_disp_dtrc_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
+ "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", };
static const char *imx8mm_disp_dc8000_sels[] = {"osc_24m", "dummy", "sys_pll1_800m", "sys_pll2_1000m",
- "sys_pll1_160m", "video_pll1_out", "sys_pll3_out", "audio_pll2_out", };
+ "sys_pll1_160m", "video_pll_out", "sys_pll3_out", "audio_pll2_out", };
static const char *imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
"sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
@@ -122,47 +122,47 @@ static const char *imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_p
static const char *imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
"sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
-static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_dc_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out",
+static const char *imx8mm_lcdif_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out", "audio_pll1_out",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
-static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
-static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
-static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext1", "clk_ext2", };
-static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
-static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext2", "clk_ext3", };
-static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char *imx8mm_spdif2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", "video_pll_out",
"sys_pll1_133m", "osc_hdmi", "clk_ext3", "clk_ext4", };
static const char *imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
- "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
+ "sys_pll1_160m", "audio_pll1_out", "video_pll_out", "clk_ext4", };
static const char *imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4", "video_pll1_out", };
+ "clk_ext3", "clk_ext4", "video_pll_out", };
static const char *imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
- "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
+ "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
static const char *imx8mm_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", "sys_pll1_400m",
- "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll1_out", };
+ "audio_pll2_out", "sys_pll3_out", "sys_pll2_250m", "video_pll_out", };
static const char *imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
@@ -174,16 +174,16 @@ static const char *imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
static const char *imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+ "video_pll_out", "audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mm_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", "sys_pll2_100m",
"sys_pll3_out", "clk_ext2", "clk_ext4", "audio_pll2_out", };
@@ -213,19 +213,19 @@ static const char *imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1
"sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
- "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", };
static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
- "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
+ "video_pll_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
"sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
@@ -234,31 +234,31 @@ static const char *imx8mm_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_ou
"sys_pll1_266m", "sys_pll2_500m", "sys_pll1_100m", };
static const char *imx8mm_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
static const char *imx8mm_csi1_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi1_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
static const char *imx8mm_csi2_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", "sys_pll1_800m",
- "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "sys_pll3_out", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", "sys_pll1_800m",
- "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
+ "sys_pll2_1000m", "clk_ext2", "audio_pll2_out", "video_pll_out", };
static const char *imx8mm_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext3", "audio_pll2_out", };
@@ -286,9 +286,9 @@ static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
"audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", };
-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
@@ -327,7 +327,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MM_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -336,7 +336,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MM_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
+ hws[IMX8MM_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
@@ -348,7 +348,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
/* PLL bypass out */
hws[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MM_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MM_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MM_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
@@ -358,7 +358,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
/* PLL out gate */
hws[IMX8MM_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
hws[IMX8MM_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MM_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
+ hws[IMX8MM_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
hws[IMX8MM_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
hws[IMX8MM_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
hws[IMX8MM_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 03/18] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 01/18] dt-bindings: clock: imx8mm: add VIDEO_PLL clocks Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 02/18] clk: imx8mm: rename video_pll1 to video_pll Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 04/18] clk: imx8mp: rename video_pll1 to video_pll Dario Binacchi
` (14 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's add the IMX8MP_VIDEO_PLL[_*]
definitions to be consistent with the RM and avoid misunderstandings.
The IMX8MP_VIDEO_PLL1* constants have not been removed to ensure
backward compatibility of the patch.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v6)
Changes in v6:
- Add 'Acked-by' tag of Krzysztof Kozlowski
Changes in v5:
- New
include/dt-bindings/clock/imx8mp-clock.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 7da4243984b2..3235d7de3b62 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -16,7 +16,8 @@
#define IMX8MP_CLK_EXT4 7
#define IMX8MP_AUDIO_PLL1_REF_SEL 8
#define IMX8MP_AUDIO_PLL2_REF_SEL 9
-#define IMX8MP_VIDEO_PLL1_REF_SEL 10
+#define IMX8MP_VIDEO_PLL_REF_SEL 10
+#define IMX8MP_VIDEO_PLL1_REF_SEL IMX8MP_VIDEO_PLL_REF_SEL
#define IMX8MP_DRAM_PLL_REF_SEL 11
#define IMX8MP_GPU_PLL_REF_SEL 12
#define IMX8MP_VPU_PLL_REF_SEL 13
@@ -26,7 +27,8 @@
#define IMX8MP_SYS_PLL3_REF_SEL 17
#define IMX8MP_AUDIO_PLL1 18
#define IMX8MP_AUDIO_PLL2 19
-#define IMX8MP_VIDEO_PLL1 20
+#define IMX8MP_VIDEO_PLL 20
+#define IMX8MP_VIDEO_PLL1 IMX8MP_VIDEO_PLL
#define IMX8MP_DRAM_PLL 21
#define IMX8MP_GPU_PLL 22
#define IMX8MP_VPU_PLL 23
@@ -36,7 +38,8 @@
#define IMX8MP_SYS_PLL3 27
#define IMX8MP_AUDIO_PLL1_BYPASS 28
#define IMX8MP_AUDIO_PLL2_BYPASS 29
-#define IMX8MP_VIDEO_PLL1_BYPASS 30
+#define IMX8MP_VIDEO_PLL_BYPASS 30
+#define IMX8MP_VIDEO_PLL1_BYPASS IMX8MP_VIDEO_PLL_BYPASS
#define IMX8MP_DRAM_PLL_BYPASS 31
#define IMX8MP_GPU_PLL_BYPASS 32
#define IMX8MP_VPU_PLL_BYPASS 33
@@ -46,7 +49,8 @@
#define IMX8MP_SYS_PLL3_BYPASS 37
#define IMX8MP_AUDIO_PLL1_OUT 38
#define IMX8MP_AUDIO_PLL2_OUT 39
-#define IMX8MP_VIDEO_PLL1_OUT 40
+#define IMX8MP_VIDEO_PLL_OUT 40
+#define IMX8MP_VIDEO_PLL1_OUT IMX8MP_VIDEO_PLL_OUT
#define IMX8MP_DRAM_PLL_OUT 41
#define IMX8MP_GPU_PLL_OUT 42
#define IMX8MP_VPU_PLL_OUT 43
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 04/18] clk: imx8mp: rename video_pll1 to video_pll
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (2 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 03/18] dt-bindings: clock: imx8mp: add VIDEO_PLL clocks Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 05/18] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Dario Binacchi
` (13 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
The patch, which simply replaces video_pll1 with video_pll, highlights
many warnings raised by checkpatch.pl. These are not generated by the
changes made but are inherited from how the module was originally
written. Fixing them would have meant "obscuring" the actual changes
introduced.
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v5:
- Split the patch dropping the dt-bindings changes.
Changes in v4:
- New
drivers/clk/imx/clk-imx8mp.c | 118 +++++++++++++++++------------------
1 file changed, 59 insertions(+), 59 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 516dbd170c8a..e96460534e7d 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -23,7 +23,7 @@ static u32 share_count_audio;
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -40,27 +40,27 @@ static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out"
static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m",
"vpu_pll_out", "sys_pll1_800m", "audio_pll1_out",
- "video_pll1_out", "sys_pll3_out", };
+ "video_pll_out", "sys_pll3_out", };
static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
@@ -72,11 +72,11 @@ static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m"
static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "sys_pll1_100m",};
+ "video_pll_out", "sys_pll1_100m",};
static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
- "video_pll1_out", "sys_pll3_out", };
+ "video_pll_out", "sys_pll3_out", };
static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
@@ -96,35 +96,35 @@ static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m",
static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_800m", "sys_pll2_1000m",
@@ -159,56 +159,56 @@ static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m",
"sys_pll1_160m", "sys_pll1_200m", };
static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext1", "clk_ext2", };
static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext2", "clk_ext3", };
static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
- "video_pll1_out", "clk_ext4", };
+ "video_pll_out", "clk_ext4", };
static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
- "clk_ext4", "video_pll1_out", };
+ "clk_ext4", "video_pll_out", };
static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
- "video_pll1_out", "clk_ext4", };
+ "video_pll_out", "clk_ext4", };
static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
- "clk_ext4", "video_pll1_out", };
+ "clk_ext4", "video_pll_out", };
static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
- "video_pll1_out", "audio_pll2_out", };
+ "video_pll_out", "audio_pll2_out", };
static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
- "sys_pll2_250m", "video_pll1_out", };
+ "sys_pll2_250m", "video_pll_out", };
static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
@@ -223,19 +223,19 @@ static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s
"audio_pll2_out", "sys_pll1_100m", };
static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
@@ -276,42 +276,42 @@ static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s
static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
- "sys_pll1_80m", "video_pll1_out", };
+ "sys_pll1_80m", "video_pll_out", };
static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1" };
static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext2" };
static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext3" };
static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext1" };
static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext2" };
static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
- "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
+ "sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
"audio_pll1_out", "clk_ext3" };
static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
@@ -328,19 +328,19 @@ static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800
static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
"sys_pll1_166m", "sys_pll3_out", "audio_pll1_out",
- "video_pll1_out", "osc_32k" };
+ "video_pll_out", "osc_32k" };
static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
- "audio_pll2_out", "video_pll1_out", };
+ "audio_pll2_out", "video_pll_out", };
static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
- "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
+ "sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out",
"sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m",
- "audio_pll1_out", "video_pll1_out", };
+ "audio_pll1_out", "video_pll_out", };
static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
@@ -349,26 +349,26 @@ static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s
static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m",
"clk_ext2", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
-static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
+static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out",
"audio_pll1_out", "sys_pll1_800m",
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
"sys_pll1_800m", "sys_pll2_1000m",
"sys_pll3_out", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_media_ldb_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
"sys_pll1_800m", "sys_pll2_1000m",
"clk_ext2", "audio_pll2_out",
- "video_pll1_out", };
+ "video_pll_out", };
static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
@@ -392,12 +392,12 @@ static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out",
"sys_pll3_out", "audio_pll1_out", };
static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
- "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
+ "video_pll_out", "sys_pll1_133m", "osc_hdmi",
"clk_ext3", "clk_ext4", };
static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
-static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
+static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
@@ -440,7 +440,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MP_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@@ -451,7 +451,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll);
hws[IMX8MP_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll);
- hws[IMX8MP_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
+ hws[IMX8MP_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", anatop_base + 0x28, &imx_1443x_pll);
hws[IMX8MP_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll);
hws[IMX8MP_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll);
hws[IMX8MP_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll);
@@ -462,7 +462,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MP_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
hws[IMX8MP_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
@@ -473,7 +473,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13);
hws[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13);
- hws[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13);
+ hws[IMX8MP_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", anatop_base + 0x28, 13);
hws[IMX8MP_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13);
hws[IMX8MP_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11);
hws[IMX8MP_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11);
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 05/18] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (3 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 04/18] clk: imx8mp: rename video_pll1 to video_pll Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 06/18] arm64: dts: imx8mm: add anatop clocks Dario Binacchi
` (12 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Though adding clocks and clock-names properties will break the ABI,
it is required to accurately describe the hardware. Indeed, the anatop
module uses the input oscillators to generate various PLLs. In turn,
the Clock Control Module (CCM) receives clocks from the PLLs and
oscillators and generates clocks for on-chip peripherals.
Furthermore, as agreed in [1], this change represents the first step
toward the implementation of the anatop driver. Currently, in fact,
there is no dedicated anatop driver, but the CCM driver parses the
anatop node and registers the PLLs it produces.
[1] https://lore.kernel.org/imx/20241106090549.3684963-1-dario.binacchi@amarulasolutions.com/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- Improve commit message
- Merge it with patch 10, 11, and 12:
- 10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop
- 11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop
- 12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop
Changes in v4:
- New
.../bindings/clock/fsl,imx8m-anatop.yaml | 53 ++++++++++++++-
include/dt-bindings/clock/imx8mm-clock.h | 64 +++++++++++++++++
include/dt-bindings/clock/imx8mn-clock.h | 64 +++++++++++++++++
include/dt-bindings/clock/imx8mp-clock.h | 68 +++++++++++++++++++
4 files changed, 248 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
index bbd22e95b319..f439b0a94ce2 100644
--- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml
@@ -30,22 +30,73 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
'#clock-cells':
const: 1
required:
- compatible
- reg
+ - clocks
+ - clock-names
- '#clock-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-anatop
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 25m osc
+ - description: 27m osc
+ clock-names:
+ items:
+ - const: ckil
+ - const: osc_25m
+ - const: osc_27m
+ else:
+ properties:
+ clocks:
+ items:
+ - description: 32k osc
+ - description: 24m osc
+
+ clock-names:
+ items:
+ - const: osc_32k
+ - const: osc_24m
+
additionalProperties: false
examples:
- |
- anatop: clock-controller@30360000 {
+ clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>;
+ clock-names = "osc_32k", "osc_24m";
+ };
+
+ - |
+ clock-controller@30360000 {
+ compatible = "fsl,imx8mq-anatop";
+ reg = <0x30360000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>;
+ clock-names = "ckil", "osc_25m", "osc_27m";
};
...
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 102d8a6cdb55..017c06e48430 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -287,4 +287,68 @@
#define IMX8MM_CLK_END 258
+#define IMX8MM_ANATOP_CLK_DUMMY 0
+#define IMX8MM_ANATOP_CLK_32K 1
+#define IMX8MM_ANATOP_CLK_24M 2
+#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8
+#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10
+#define IMX8MM_ANATOP_AUDIO_PLL1 11
+#define IMX8MM_ANATOP_AUDIO_PLL2 12
+#define IMX8MM_ANATOP_VIDEO_PLL 13
+#define IMX8MM_ANATOP_DRAM_PLL 14
+#define IMX8MM_ANATOP_GPU_PLL 15
+#define IMX8MM_ANATOP_VPU_PLL 16
+#define IMX8MM_ANATOP_ARM_PLL 17
+#define IMX8MM_ANATOP_SYS_PLL1 18
+#define IMX8MM_ANATOP_SYS_PLL2 19
+#define IMX8MM_ANATOP_SYS_PLL3 20
+#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21
+#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22
+#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23
+#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24
+#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25
+#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26
+#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27
+#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28
+#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29
+#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30
+#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31
+#define IMX8MM_ANATOP_DRAM_PLL_OUT 32
+#define IMX8MM_ANATOP_GPU_PLL_OUT 33
+#define IMX8MM_ANATOP_VPU_PLL_OUT 34
+#define IMX8MM_ANATOP_ARM_PLL_OUT 35
+#define IMX8MM_ANATOP_SYS_PLL3_OUT 36
+#define IMX8MM_ANATOP_SYS_PLL1_OUT 37
+#define IMX8MM_ANATOP_SYS_PLL1_40M 38
+#define IMX8MM_ANATOP_SYS_PLL1_80M 39
+#define IMX8MM_ANATOP_SYS_PLL1_100M 40
+#define IMX8MM_ANATOP_SYS_PLL1_133M 41
+#define IMX8MM_ANATOP_SYS_PLL1_160M 42
+#define IMX8MM_ANATOP_SYS_PLL1_200M 43
+#define IMX8MM_ANATOP_SYS_PLL1_266M 44
+#define IMX8MM_ANATOP_SYS_PLL1_400M 45
+#define IMX8MM_ANATOP_SYS_PLL1_800M 46
+#define IMX8MM_ANATOP_SYS_PLL2_OUT 47
+#define IMX8MM_ANATOP_SYS_PLL2_50M 48
+#define IMX8MM_ANATOP_SYS_PLL2_100M 49
+#define IMX8MM_ANATOP_SYS_PLL2_125M 50
+#define IMX8MM_ANATOP_SYS_PLL2_166M 51
+#define IMX8MM_ANATOP_SYS_PLL2_200M 52
+#define IMX8MM_ANATOP_SYS_PLL2_250M 53
+#define IMX8MM_ANATOP_SYS_PLL2_333M 54
+#define IMX8MM_ANATOP_SYS_PLL2_500M 55
+#define IMX8MM_ANATOP_SYS_PLL2_1000M 56
+#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57
+#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58
+#define IMX8MM_ANATOP_CLK_CLKOUT1 59
+#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60
+#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61
+#define IMX8MM_ANATOP_CLK_CLKOUT2 62
+
#endif
diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h
index 04809edab33c..b2fa73803d45 100644
--- a/include/dt-bindings/clock/imx8mn-clock.h
+++ b/include/dt-bindings/clock/imx8mn-clock.h
@@ -267,4 +267,68 @@
#define IMX8MN_CLK_END 235
+#define IMX8MN_ANATOP_CLK_DUMMY 0
+#define IMX8MN_ANATOP_CLK_32K 1
+#define IMX8MN_ANATOP_CLK_24M 2
+#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8
+#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10
+#define IMX8MN_ANATOP_AUDIO_PLL1 11
+#define IMX8MN_ANATOP_AUDIO_PLL2 12
+#define IMX8MN_ANATOP_VIDEO_PLL 13
+#define IMX8MN_ANATOP_DRAM_PLL 14
+#define IMX8MN_ANATOP_GPU_PLL 15
+#define IMX8MN_ANATOP_M7_ALT_PLL 16
+#define IMX8MN_ANATOP_ARM_PLL 17
+#define IMX8MN_ANATOP_SYS_PLL1 18
+#define IMX8MN_ANATOP_SYS_PLL2 19
+#define IMX8MN_ANATOP_SYS_PLL3 20
+#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21
+#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22
+#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23
+#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24
+#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25
+#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26
+#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27
+#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28
+#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29
+#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30
+#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31
+#define IMX8MN_ANATOP_DRAM_PLL_OUT 32
+#define IMX8MN_ANATOP_GPU_PLL_OUT 33
+#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34
+#define IMX8MN_ANATOP_ARM_PLL_OUT 35
+#define IMX8MN_ANATOP_SYS_PLL3_OUT 36
+#define IMX8MN_ANATOP_SYS_PLL1_OUT 37
+#define IMX8MN_ANATOP_SYS_PLL1_40M 38
+#define IMX8MN_ANATOP_SYS_PLL1_80M 39
+#define IMX8MN_ANATOP_SYS_PLL1_100M 40
+#define IMX8MN_ANATOP_SYS_PLL1_133M 41
+#define IMX8MN_ANATOP_SYS_PLL1_160M 42
+#define IMX8MN_ANATOP_SYS_PLL1_200M 43
+#define IMX8MN_ANATOP_SYS_PLL1_266M 44
+#define IMX8MN_ANATOP_SYS_PLL1_400M 45
+#define IMX8MN_ANATOP_SYS_PLL1_800M 46
+#define IMX8MN_ANATOP_SYS_PLL2_OUT 47
+#define IMX8MN_ANATOP_SYS_PLL2_50M 48
+#define IMX8MN_ANATOP_SYS_PLL2_100M 49
+#define IMX8MN_ANATOP_SYS_PLL2_125M 50
+#define IMX8MN_ANATOP_SYS_PLL2_166M 51
+#define IMX8MN_ANATOP_SYS_PLL2_200M 52
+#define IMX8MN_ANATOP_SYS_PLL2_250M 53
+#define IMX8MN_ANATOP_SYS_PLL2_333M 54
+#define IMX8MN_ANATOP_SYS_PLL2_500M 55
+#define IMX8MN_ANATOP_SYS_PLL2_1000M 56
+#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57
+#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58
+#define IMX8MN_ANATOP_CLK_CLKOUT1 59
+#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60
+#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61
+#define IMX8MN_ANATOP_CLK_CLKOUT2 62
+
#endif
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 3235d7de3b62..8c076225fd9e 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -402,4 +402,72 @@
#define IMX8MP_CLK_AUDIOMIX_END 59
+#define IMX8MP_ANATOP_CLK_DUMMY 0
+#define IMX8MP_ANATOP_CLK_24M 1
+#define IMX8MP_ANATOP_CLK_32K 2
+#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3
+#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4
+#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5
+#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6
+#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7
+#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8
+#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9
+#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10
+#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11
+#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12
+#define IMX8MP_ANATOP_AUDIO_PLL1 13
+#define IMX8MP_ANATOP_AUDIO_PLL2 14
+#define IMX8MP_ANATOP_VIDEO_PLL 15
+#define IMX8MP_ANATOP_DRAM_PLL 16
+#define IMX8MP_ANATOP_GPU_PLL 17
+#define IMX8MP_ANATOP_VPU_PLL 18
+#define IMX8MP_ANATOP_ARM_PLL 19
+#define IMX8MP_ANATOP_SYS_PLL1 20
+#define IMX8MP_ANATOP_SYS_PLL2 21
+#define IMX8MP_ANATOP_SYS_PLL3 22
+#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23
+#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24
+#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25
+#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26
+#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27
+#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28
+#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29
+#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30
+#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31
+#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32
+#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33
+#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34
+#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35
+#define IMX8MP_ANATOP_DRAM_PLL_OUT 36
+#define IMX8MP_ANATOP_GPU_PLL_OUT 37
+#define IMX8MP_ANATOP_VPU_PLL_OUT 38
+#define IMX8MP_ANATOP_ARM_PLL_OUT 39
+#define IMX8MP_ANATOP_SYS_PLL3_OUT 40
+#define IMX8MP_ANATOP_SYS_PLL1_OUT 41
+#define IMX8MP_ANATOP_SYS_PLL1_40M 42
+#define IMX8MP_ANATOP_SYS_PLL1_80M 43
+#define IMX8MP_ANATOP_SYS_PLL1_100M 44
+#define IMX8MP_ANATOP_SYS_PLL1_133M 45
+#define IMX8MP_ANATOP_SYS_PLL1_160M 46
+#define IMX8MP_ANATOP_SYS_PLL1_200M 47
+#define IMX8MP_ANATOP_SYS_PLL1_266M 48
+#define IMX8MP_ANATOP_SYS_PLL1_400M 49
+#define IMX8MP_ANATOP_SYS_PLL1_800M 50
+#define IMX8MP_ANATOP_SYS_PLL2_OUT 51
+#define IMX8MP_ANATOP_SYS_PLL2_50M 52
+#define IMX8MP_ANATOP_SYS_PLL2_100M 53
+#define IMX8MP_ANATOP_SYS_PLL2_125M 54
+#define IMX8MP_ANATOP_SYS_PLL2_166M 55
+#define IMX8MP_ANATOP_SYS_PLL2_200M 56
+#define IMX8MP_ANATOP_SYS_PLL2_250M 57
+#define IMX8MP_ANATOP_SYS_PLL2_333M 58
+#define IMX8MP_ANATOP_SYS_PLL2_500M 59
+#define IMX8MP_ANATOP_SYS_PLL2_1000M 60
+#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61
+#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62
+#define IMX8MP_ANATOP_CLK_CLKOUT1 63
+#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64
+#define IMX8MP_ANATOP_CLK_CLKOUT2_DIV 65
+#define IMX8MP_ANATOP_CLK_CLKOUT2 66
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 06/18] arm64: dts: imx8mm: add anatop clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (4 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 05/18] dt-bindings: clock: imx8m-anatop: add oscillators and PLLs Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 07/18] arm64: dts: imx8mn: " Dario Binacchi
` (11 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add clocks to anatop node.
Add the bindings definitions for the anatop node. The patch is
preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 4de3bf22902b..597041a05073 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -600,6 +600,8 @@ anatop: clock-controller@30360000 {
compatible = "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>;
+ clock-names = "osc_32k", "osc_24m";
};
snvs: snvs@30370000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 07/18] arm64: dts: imx8mn: add anatop clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (5 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 06/18] arm64: dts: imx8mm: add anatop clocks Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 08/18] arm64: dts: imx8mp: " Dario Binacchi
` (10 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add clocks to anatop node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a5f9cfb46e5d..49be492b5687 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -606,6 +606,8 @@ anatop: clock-controller@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>;
+ clock-names = "osc_32k", "osc_24m";
};
snvs: snvs@30370000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 08/18] arm64: dts: imx8mp: add anatop clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (6 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 07/18] arm64: dts: imx8mn: " Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 09/18] arm64: dts: imx8mq: " Dario Binacchi
` (9 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add clocks to anatop node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index e0d3b8cba221..0b928e173f29 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -709,6 +709,8 @@ anatop: clock-controller@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>;
+ clock-names = "osc_32k", "osc_24m";
};
snvs: snvs@30370000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 09/18] arm64: dts: imx8mq: add anatop clocks
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (7 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 08/18] arm64: dts: imx8mp: " Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 10/18] clk: imx: add hw API imx_anatop_get_clk_hw Dario Binacchi
` (8 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add clocks to anatop node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d51de8d899b2..1d1424a136f0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -817,6 +817,8 @@ anatop: clock-controller@30360000 {
reg = <0x30360000 0x10000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
+ clocks = <&ckil>, <&osc_25m>, <&osc_27m>;
+ clock-names = "ckil", "osc_25m", "osc_27m";
};
snvs: snvs@30370000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 10/18] clk: imx: add hw API imx_anatop_get_clk_hw
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (8 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 09/18] arm64: dts: imx8mq: " Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2025-01-06 9:04 ` Peng Fan
2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
` (7 subsequent siblings)
17 siblings, 1 reply; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Get the hw of a clock registered by the anatop module. This function is
preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v7)
Changes in v7:
- Add device_node type parameter to imx8m_anatop_get_clk_hw()
- Rename imx8m_anatop_get_clk_hw() to imx_anatop_get_clk_hw()
- Drop the gaurding macros so the code can be used also by i.MX9
Changes in v5:
- Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors
Changes in v4:
- New
drivers/clk/imx/clk.c | 15 +++++++++++++++
drivers/clk/imx/clk.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index df83bd939492..a906d3cd960b 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -128,6 +128,21 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
}
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
+struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id)
+{
+ struct of_phandle_args args;
+ struct clk_hw *hw;
+
+ args.np = np;
+ args.args_count = 1;
+ args.args[0] = id;
+
+ hw = __clk_get_hw(of_clk_get_from_provider(&args));
+ pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw));
+ return hw;
+}
+EXPORT_SYMBOL_GPL(imx_anatop_get_clk_hw);
+
/*
* This fixups the register CCM_CSCMR1 write value.
* The write/read/divider values of the aclk_podf field
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa5202f284f3..50e407cf48d9 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -487,4 +487,6 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
u32 reg, const char **parent_names,
u8 num_parents, const u32 *mux_table, u32 mask);
+struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id);
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v8 10/18] clk: imx: add hw API imx_anatop_get_clk_hw
2024-12-29 14:49 ` [PATCH v8 10/18] clk: imx: add hw API imx_anatop_get_clk_hw Dario Binacchi
@ 2025-01-06 9:04 ` Peng Fan
0 siblings, 0 replies; 24+ messages in thread
From: Peng Fan @ 2025-01-06 9:04 UTC (permalink / raw)
To: Dario Binacchi
Cc: linux-kernel, linux-amarula, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
On Sun, Dec 29, 2024 at 03:49:34PM +0100, Dario Binacchi wrote:
>Get the hw of a clock registered by the anatop module. This function is
>preparatory for future developments.
>
>Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (9 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 10/18] clk: imx: add hw API imx_anatop_get_clk_hw Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2025-01-06 9:05 ` Peng Fan
2025-01-06 11:06 ` Dan Carpenter
2024-12-29 14:49 ` [PATCH v8 12/18] dt-bindings: clock: imx8m-clock: add PLLs Dario Binacchi
` (6 subsequent siblings)
17 siblings, 2 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root.
By doing so, we also simplify the CCM driver code. The changes are
backward compatible.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
Changes in v8:
- Drop call of of_parse_phandle() to get the anatop's device node.
Changes in v7:
- Update the code based on the changes made to the
imx8m_anatop_get_clk_hw():
- Rename imx8m_anatop_get_clk_hw to imx_anatop_get_clk_hw
- Add device_node type parameter
- Call of_parse_phandle() to get the anatop's device node.
Changes in v6:
- Define IMX8MN_ANATOP_CLK_END inside the driver after it has ben
removed from include/dt-bindings/clock/imx8mn-clock.h.
Changes in v4:
- New
drivers/clk/imx/Makefile | 2 +-
drivers/clk/imx/clk-imx8mn-anatop.c | 283 ++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8mn.c | 183 ++++++++----------
3 files changed, 364 insertions(+), 104 deletions(-)
create mode 100644 drivers/clk/imx/clk-imx8mn-anatop.c
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 03f2b2a1ab63..f0f1d01c68f8 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -26,7 +26,7 @@ mxc-clk-objs += clk-gpr-mux.o
obj-$(CONFIG_MXC_CLK) += mxc-clk.o
obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
-obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
+obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn-anatop.o clk-imx8mn.o
obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
diff --git a/drivers/clk/imx/clk-imx8mn-anatop.c b/drivers/clk/imx/clk-imx8mn-anatop.c
new file mode 100644
index 000000000000..895569d886f4
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mn-anatop.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * clk-imx8mn-anatop.c - NXP i.MX8MN anatop clock driver
+ *
+ * Copyright (c) 2024 Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ */
+
+#include <dt-bindings/clock/imx8mn-clock.h>
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+
+#include "clk.h"
+
+#define IMX8MN_ANATOP_CLK_END IMX8MN_ANATOP_CLK_CLKOUT2
+
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
+static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
+static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
+static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
+static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
+static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
+static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
+ "dummy", "dummy", "gpu_pll_out", "dummy",
+ "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
+ "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
+
+static struct clk_hw_onecell_data *clk_hw_data;
+static struct clk_hw **hws;
+
+static int imx8mn_anatop_clocks_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(dev, "failed to get base address\n");
+ return PTR_ERR(base);
+ }
+
+ clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
+ IMX8MN_ANATOP_CLK_END),
+ GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMX8MN_ANATOP_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
+ hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
+
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =
+ imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =
+ imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =
+ imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =
+ imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =
+ imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =
+ imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =
+ imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+ hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =
+ imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+ pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
+
+ hws[IMX8MN_ANATOP_AUDIO_PLL1] =
+ imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
+ base, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2] =
+ imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
+ base + 0x14, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_VIDEO_PLL] =
+ imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
+ base + 0x28, &imx_1443x_pll);
+ hws[IMX8MN_ANATOP_DRAM_PLL] =
+ imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
+ &imx_1443x_dram_pll);
+ hws[IMX8MN_ANATOP_GPU_PLL] =
+ imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64,
+ &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL] =
+ imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel",
+ base + 0x74, &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_ARM_PLL] =
+ imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
+ &imx_1416x_pll);
+ hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
+ hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
+ hws[IMX8MN_ANATOP_SYS_PLL3] =
+ imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
+ &imx_1416x_pll);
+
+ /* PLL bypass out */
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
+ audio_pll1_bypass_sels,
+ ARRAY_SIZE(audio_pll1_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =
+ imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1,
+ audio_pll2_bypass_sels,
+ ARRAY_SIZE(audio_pll2_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
+ video_pll_bypass_sels,
+ ARRAY_SIZE(video_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1,
+ dram_pll_bypass_sels,
+ ARRAY_SIZE(dram_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1,
+ gpu_pll_bypass_sels,
+ ARRAY_SIZE(gpu_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1,
+ m7_alt_pll_bypass_sels,
+ ARRAY_SIZE(m7_alt_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =
+ imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1,
+ arm_pll_bypass_sels,
+ ARRAY_SIZE(arm_pll_bypass_sels),
+ CLK_SET_RATE_PARENT);
+ hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =
+ imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1,
+ sys_pll3_bypass_sels,
+ ARRAY_SIZE(sys_pll3_bypass_sels),
+ CLK_SET_RATE_PARENT);
+
+ /* PLL out gate */
+ hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =
+ imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
+ base, 13);
+ hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =
+ imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
+ base + 0x14, 13);
+ hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =
+ imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
+ base + 0x28, 13);
+ hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =
+ imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
+ base + 0x50, 13);
+ hws[IMX8MN_ANATOP_GPU_PLL_OUT] =
+ imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
+ base + 0x64, 11);
+ hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =
+ imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass",
+ base + 0x74, 11);
+ hws[IMX8MN_ANATOP_ARM_PLL_OUT] =
+ imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
+ base + 0x84, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =
+ imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
+ base + 0x114, 11);
+
+ /* SYS PLL1 fixed output */
+ hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =
+ imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL1_40M] =
+ imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
+ hws[IMX8MN_ANATOP_SYS_PLL1_80M] =
+ imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
+ hws[IMX8MN_ANATOP_SYS_PLL1_100M] =
+ imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
+ hws[IMX8MN_ANATOP_SYS_PLL1_133M] =
+ imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
+ hws[IMX8MN_ANATOP_SYS_PLL1_160M] =
+ imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
+ hws[IMX8MN_ANATOP_SYS_PLL1_200M] =
+ imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
+ hws[IMX8MN_ANATOP_SYS_PLL1_266M] =
+ imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
+ hws[IMX8MN_ANATOP_SYS_PLL1_400M] =
+ imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
+ hws[IMX8MN_ANATOP_SYS_PLL1_800M] =
+ imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+
+ /* SYS PLL2 fixed output */
+ hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =
+ imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
+ hws[IMX8MN_ANATOP_SYS_PLL2_50M] =
+ imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
+ hws[IMX8MN_ANATOP_SYS_PLL2_100M] =
+ imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
+ hws[IMX8MN_ANATOP_SYS_PLL2_125M] =
+ imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
+ hws[IMX8MN_ANATOP_SYS_PLL2_166M] =
+ imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
+ hws[IMX8MN_ANATOP_SYS_PLL2_200M] =
+ imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
+ hws[IMX8MN_ANATOP_SYS_PLL2_250M] =
+ imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
+ hws[IMX8MN_ANATOP_SYS_PLL2_333M] =
+ imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
+ hws[IMX8MN_ANATOP_SYS_PLL2_500M] =
+ imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
+ hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =
+ imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
+
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =
+ imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =
+ imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128,
+ 0, 4);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT1] =
+ imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =
+ imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
+ clkout_sels, ARRAY_SIZE(clkout_sels));
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =
+ imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
+ 16, 4);
+ hws[IMX8MN_ANATOP_CLK_CLKOUT2] =
+ imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
+
+ imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register anatop clock provider\n");
+ }
+
+ dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n");
+ return 0;
+}
+
+static const struct of_device_id imx8mn_anatop_clk_of_match[] = {
+ { .compatible = "fsl,imx8mn-anatop" },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mn_anatop_clk_of_match);
+
+static struct platform_driver imx8mn_anatop_clk_driver = {
+ .probe = imx8mn_anatop_clocks_probe,
+ .driver = {
+ .name = "imx8mn-anatop",
+ /*
+ * Disable bind attributes: clocks are not removed and
+ * reloading the driver will crash or break devices.
+ */
+ .suppress_bind_attrs = true,
+ .of_match_table = imx8mn_anatop_clk_of_match,
+ },
+};
+
+module_platform_driver(imx8mn_anatop_clk_driver);
+
+MODULE_AUTHOR("Dario Binacchi <dario.binacchi@amarulasolutions.com>");
+MODULE_DESCRIPTION("NXP i.MX8MN anatop clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ab77e148e70c..c3a3d063d58e 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -24,16 +24,6 @@ static u32 share_count_disp;
static u32 share_count_pdm;
static u32 share_count_nand;
-static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
-static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
-static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
-static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
-static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
-static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
-static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
-static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
-static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
-
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
"audio_pll1_out", "sys_pll3_out", };
@@ -308,21 +298,20 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
"video_pll_out", "osc_32k", };
-static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
- "dummy", "dummy", "gpu_pll_out", "dummy",
- "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
- "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
-
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
static int imx8mn_clocks_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
+ struct device_node *np = dev->of_node, *anp;
void __iomem *base;
int ret;
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(base)))
+ return PTR_ERR(base);
+
clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
IMX8MN_CLK_END), GFP_KERNEL);
if (WARN_ON(!clk_hw_data))
@@ -331,99 +320,90 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
clk_hw_data->num = IMX8MN_CLK_END;
hws = clk_hw_data->hws;
- hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
- hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
- hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
+ if (!anp)
+ return dev_err_probe(dev, -ENODEV, "missing anatop\n");
+
+ of_node_put(anp);
+
+ hws[IMX8MN_CLK_DUMMY] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_DUMMY);
+ hws[IMX8MN_CLK_24M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_24M);
+ hws[IMX8MN_CLK_32K] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_32K);
hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
- base = devm_of_iomap(dev, np, 0, NULL);
- of_node_put(np);
- if (WARN_ON(IS_ERR(base))) {
- ret = PTR_ERR(base);
- goto unregister_hws;
- }
-
- hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
- hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
- hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
- hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
- hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
- hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll);
- hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
- hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
- hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
- hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
+ hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL);
+ hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL);
+ hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_REF_SEL);
+ hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_REF_SEL);
+ hws[IMX8MN_GPU_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_REF_SEL);
+ hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL);
+ hws[IMX8MN_ARM_PLL_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_REF_SEL);
+ hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL);
+
+ hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1);
+ hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2);
+ hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL);
+ hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL);
+ hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL);
+ hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL);
+ hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL);
+ hws[IMX8MN_SYS_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1);
+ hws[IMX8MN_SYS_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2);
+ hws[IMX8MN_SYS_PLL3] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3);
/* PLL bypass out */
- hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
+ hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_BYPASS);
+ hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_BYPASS);
+ hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_BYPASS);
+ hws[IMX8MN_DRAM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_BYPASS);
+ hws[IMX8MN_GPU_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_BYPASS);
+ hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_BYPASS);
+ hws[IMX8MN_ARM_PLL_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_BYPASS);
+ hws[IMX8MN_SYS_PLL3_BYPASS] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_BYPASS);
/* PLL out gate */
- hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
- hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
- hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
- hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
- hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
- hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11);
- hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
- hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
+ hws[IMX8MN_AUDIO_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1_OUT);
+ hws[IMX8MN_AUDIO_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2_OUT);
+ hws[IMX8MN_VIDEO_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL_OUT);
+ hws[IMX8MN_DRAM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL_OUT);
+ hws[IMX8MN_GPU_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL_OUT);
+ hws[IMX8MN_M7_ALT_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL_OUT);
+ hws[IMX8MN_ARM_PLL_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL_OUT);
+ hws[IMX8MN_SYS_PLL3_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_OUT);
/* SYS PLL1 fixed output */
- hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
- hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
- hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
- hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
- hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
- hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
- hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
- hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
- hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
- hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
+ hws[IMX8MN_SYS_PLL1_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_OUT);
+ hws[IMX8MN_SYS_PLL1_40M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_40M);
+ hws[IMX8MN_SYS_PLL1_80M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_80M);
+ hws[IMX8MN_SYS_PLL1_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_100M);
+ hws[IMX8MN_SYS_PLL1_133M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_133M);
+ hws[IMX8MN_SYS_PLL1_160M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_160M);
+ hws[IMX8MN_SYS_PLL1_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_200M);
+ hws[IMX8MN_SYS_PLL1_266M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_266M);
+ hws[IMX8MN_SYS_PLL1_400M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_400M);
+ hws[IMX8MN_SYS_PLL1_800M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL1_800M);
/* SYS PLL2 fixed output */
- hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
- hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
- hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
- hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
- hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
- hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
- hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
- hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
- hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
- hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
-
- hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
- hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
- hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
- hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
- hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
-
- np = dev->of_node;
- base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(base))) {
- ret = PTR_ERR(base);
- goto unregister_hws;
- }
+ hws[IMX8MN_SYS_PLL2_OUT] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_OUT);
+ hws[IMX8MN_SYS_PLL2_50M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_50M);
+ hws[IMX8MN_SYS_PLL2_100M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_100M);
+ hws[IMX8MN_SYS_PLL2_125M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_125M);
+ hws[IMX8MN_SYS_PLL2_166M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_166M);
+ hws[IMX8MN_SYS_PLL2_200M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_200M);
+ hws[IMX8MN_SYS_PLL2_250M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_250M);
+ hws[IMX8MN_SYS_PLL2_333M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_333M);
+ hws[IMX8MN_SYS_PLL2_500M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_500M);
+ hws[IMX8MN_SYS_PLL2_1000M] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL2_1000M);
+
+ hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_SEL);
+ hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1_DIV);
+ hws[IMX8MN_CLK_CLKOUT1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT1);
+ hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_SEL);
+ hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2_DIV);
+ hws[IMX8MN_CLK_CLKOUT2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_CLK_CLKOUT2);
/* CORE */
hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
@@ -599,18 +579,15 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
if (ret < 0) {
- dev_err(dev, "failed to register hws for i.MX8MN\n");
- goto unregister_hws;
+ imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
+ return dev_err_probe(dev, ret,
+ "failed to register hws for i.MX8MN\n");
}
imx_register_uart_clocks();
+ dev_info(dev, "NXP i.MX8MN ccm clock driver probed\n");
return 0;
-
-unregister_hws:
- imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
-
- return ret;
}
static const struct of_device_id imx8mn_clk_of_match[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
@ 2025-01-06 9:05 ` Peng Fan
2025-01-06 11:06 ` Dan Carpenter
1 sibling, 0 replies; 24+ messages in thread
From: Peng Fan @ 2025-01-06 9:05 UTC (permalink / raw)
To: Dario Binacchi
Cc: linux-kernel, linux-amarula, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
On Sun, Dec 29, 2024 at 03:49:35PM +0100, Dario Binacchi wrote:
>Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root.
>By doing so, we also simplify the CCM driver code. The changes are
>backward compatible.
>
>Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
2025-01-06 9:05 ` Peng Fan
@ 2025-01-06 11:06 ` Dan Carpenter
1 sibling, 0 replies; 24+ messages in thread
From: Dan Carpenter @ 2025-01-06 11:06 UTC (permalink / raw)
To: oe-kbuild, Dario Binacchi, linux-kernel
Cc: lkp, oe-kbuild-all, linux-amarula, Dario Binacchi, Abel Vesa,
Fabio Estevam, Michael Turquette, Peng Fan,
Pengutronix Kernel Team, Sascha Hauer, Shawn Guo, Stephen Boyd,
imx, linux-arm-kernel, linux-clk
Hi Dario,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Dario-Binacchi/dt-bindings-clock-imx8mm-add-VIDEO_PLL-clocks/20241229-225716
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
patch link: https://lore.kernel.org/r/20241229145027.3984542-12-dario.binacchi%40amarulasolutions.com
patch subject: [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver
config: arm-randconfig-r071-20241231 (https://download.01.org/0day-ci/archive/20241231/202412311031.781qvq8q-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202412311031.781qvq8q-lkp@intel.com/
smatch warnings:
drivers/clk/imx/clk-imx8mn-anatop.c:244 imx8mn_anatop_clocks_probe() error: buffer overflow 'hws' 62 <= 62
vim +/hws +244 drivers/clk/imx/clk-imx8mn-anatop.c
87df58feb5834e Dario Binacchi 2024-12-29 40 static int imx8mn_anatop_clocks_probe(struct platform_device *pdev)
87df58feb5834e Dario Binacchi 2024-12-29 41 {
87df58feb5834e Dario Binacchi 2024-12-29 42 struct device *dev = &pdev->dev;
87df58feb5834e Dario Binacchi 2024-12-29 43 struct device_node *np = dev->of_node;
87df58feb5834e Dario Binacchi 2024-12-29 44 void __iomem *base;
87df58feb5834e Dario Binacchi 2024-12-29 45 int ret;
87df58feb5834e Dario Binacchi 2024-12-29 46
87df58feb5834e Dario Binacchi 2024-12-29 47 base = devm_platform_ioremap_resource(pdev, 0);
87df58feb5834e Dario Binacchi 2024-12-29 48 if (IS_ERR(base)) {
87df58feb5834e Dario Binacchi 2024-12-29 49 dev_err(dev, "failed to get base address\n");
87df58feb5834e Dario Binacchi 2024-12-29 50 return PTR_ERR(base);
87df58feb5834e Dario Binacchi 2024-12-29 51 }
87df58feb5834e Dario Binacchi 2024-12-29 52
87df58feb5834e Dario Binacchi 2024-12-29 53 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
87df58feb5834e Dario Binacchi 2024-12-29 54 IMX8MN_ANATOP_CLK_END),
IMX8MN_ANATOP_CLK_END is IMX8MN_ANATOP_CLK_CLKOUT2
87df58feb5834e Dario Binacchi 2024-12-29 55 GFP_KERNEL);
87df58feb5834e Dario Binacchi 2024-12-29 56 if (WARN_ON(!clk_hw_data))
87df58feb5834e Dario Binacchi 2024-12-29 57 return -ENOMEM;
87df58feb5834e Dario Binacchi 2024-12-29 58
87df58feb5834e Dario Binacchi 2024-12-29 59 clk_hw_data->num = IMX8MN_ANATOP_CLK_END;
87df58feb5834e Dario Binacchi 2024-12-29 60 hws = clk_hw_data->hws;
87df58feb5834e Dario Binacchi 2024-12-29 61
87df58feb5834e Dario Binacchi 2024-12-29 62 hws[IMX8MN_ANATOP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
87df58feb5834e Dario Binacchi 2024-12-29 63 hws[IMX8MN_ANATOP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
87df58feb5834e Dario Binacchi 2024-12-29 64 hws[IMX8MN_ANATOP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
87df58feb5834e Dario Binacchi 2024-12-29 65
87df58feb5834e Dario Binacchi 2024-12-29 66 hws[IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 67 imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 68 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 69 hws[IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 70 imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 71 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 72 hws[IMX8MN_ANATOP_VIDEO_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 73 imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 74 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 75 hws[IMX8MN_ANATOP_DRAM_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 76 imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 77 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 78 hws[IMX8MN_ANATOP_GPU_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 79 imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 80 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 81 hws[IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 82 imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 83 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 84 hws[IMX8MN_ANATOP_ARM_PLL_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 85 imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 86 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 87 hws[IMX8MN_ANATOP_SYS_PLL3_REF_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 88 imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
87df58feb5834e Dario Binacchi 2024-12-29 89 pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
87df58feb5834e Dario Binacchi 2024-12-29 90
87df58feb5834e Dario Binacchi 2024-12-29 91 hws[IMX8MN_ANATOP_AUDIO_PLL1] =
87df58feb5834e Dario Binacchi 2024-12-29 92 imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 93 base, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 94 hws[IMX8MN_ANATOP_AUDIO_PLL2] =
87df58feb5834e Dario Binacchi 2024-12-29 95 imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 96 base + 0x14, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 97 hws[IMX8MN_ANATOP_VIDEO_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 98 imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 99 base + 0x28, &imx_1443x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 100 hws[IMX8MN_ANATOP_DRAM_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 101 imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
87df58feb5834e Dario Binacchi 2024-12-29 102 &imx_1443x_dram_pll);
87df58feb5834e Dario Binacchi 2024-12-29 103 hws[IMX8MN_ANATOP_GPU_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 104 imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64,
87df58feb5834e Dario Binacchi 2024-12-29 105 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 106 hws[IMX8MN_ANATOP_M7_ALT_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 107 imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel",
87df58feb5834e Dario Binacchi 2024-12-29 108 base + 0x74, &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 109 hws[IMX8MN_ANATOP_ARM_PLL] =
87df58feb5834e Dario Binacchi 2024-12-29 110 imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
87df58feb5834e Dario Binacchi 2024-12-29 111 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 112 hws[IMX8MN_ANATOP_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
87df58feb5834e Dario Binacchi 2024-12-29 113 hws[IMX8MN_ANATOP_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
87df58feb5834e Dario Binacchi 2024-12-29 114 hws[IMX8MN_ANATOP_SYS_PLL3] =
87df58feb5834e Dario Binacchi 2024-12-29 115 imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
87df58feb5834e Dario Binacchi 2024-12-29 116 &imx_1416x_pll);
87df58feb5834e Dario Binacchi 2024-12-29 117
87df58feb5834e Dario Binacchi 2024-12-29 118 /* PLL bypass out */
87df58feb5834e Dario Binacchi 2024-12-29 119 hws[IMX8MN_ANATOP_AUDIO_PLL1_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 120 imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 121 audio_pll1_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 122 ARRAY_SIZE(audio_pll1_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 123 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 124 hws[IMX8MN_ANATOP_AUDIO_PLL2_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 125 imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 126 audio_pll2_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 127 ARRAY_SIZE(audio_pll2_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 128 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 129 hws[IMX8MN_ANATOP_VIDEO_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 130 imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 131 video_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 132 ARRAY_SIZE(video_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 133 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 134 hws[IMX8MN_ANATOP_DRAM_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 135 imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1,
87df58feb5834e Dario Binacchi 2024-12-29 136 dram_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 137 ARRAY_SIZE(dram_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 138 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 139 hws[IMX8MN_ANATOP_GPU_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 140 imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 141 gpu_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 142 ARRAY_SIZE(gpu_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 143 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 144 hws[IMX8MN_ANATOP_M7_ALT_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 145 imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 146 m7_alt_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 147 ARRAY_SIZE(m7_alt_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 148 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 149 hws[IMX8MN_ANATOP_ARM_PLL_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 150 imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 151 arm_pll_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 152 ARRAY_SIZE(arm_pll_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 153 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 154 hws[IMX8MN_ANATOP_SYS_PLL3_BYPASS] =
87df58feb5834e Dario Binacchi 2024-12-29 155 imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1,
87df58feb5834e Dario Binacchi 2024-12-29 156 sys_pll3_bypass_sels,
87df58feb5834e Dario Binacchi 2024-12-29 157 ARRAY_SIZE(sys_pll3_bypass_sels),
87df58feb5834e Dario Binacchi 2024-12-29 158 CLK_SET_RATE_PARENT);
87df58feb5834e Dario Binacchi 2024-12-29 159
87df58feb5834e Dario Binacchi 2024-12-29 160 /* PLL out gate */
87df58feb5834e Dario Binacchi 2024-12-29 161 hws[IMX8MN_ANATOP_AUDIO_PLL1_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 162 imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 163 base, 13);
87df58feb5834e Dario Binacchi 2024-12-29 164 hws[IMX8MN_ANATOP_AUDIO_PLL2_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 165 imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 166 base + 0x14, 13);
87df58feb5834e Dario Binacchi 2024-12-29 167 hws[IMX8MN_ANATOP_VIDEO_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 168 imx_clk_hw_gate("video_pll_out", "video_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 169 base + 0x28, 13);
87df58feb5834e Dario Binacchi 2024-12-29 170 hws[IMX8MN_ANATOP_DRAM_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 171 imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 172 base + 0x50, 13);
87df58feb5834e Dario Binacchi 2024-12-29 173 hws[IMX8MN_ANATOP_GPU_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 174 imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 175 base + 0x64, 11);
87df58feb5834e Dario Binacchi 2024-12-29 176 hws[IMX8MN_ANATOP_M7_ALT_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 177 imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 178 base + 0x74, 11);
87df58feb5834e Dario Binacchi 2024-12-29 179 hws[IMX8MN_ANATOP_ARM_PLL_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 180 imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 181 base + 0x84, 11);
87df58feb5834e Dario Binacchi 2024-12-29 182 hws[IMX8MN_ANATOP_SYS_PLL3_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 183 imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass",
87df58feb5834e Dario Binacchi 2024-12-29 184 base + 0x114, 11);
87df58feb5834e Dario Binacchi 2024-12-29 185
87df58feb5834e Dario Binacchi 2024-12-29 186 /* SYS PLL1 fixed output */
87df58feb5834e Dario Binacchi 2024-12-29 187 hws[IMX8MN_ANATOP_SYS_PLL1_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 188 imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
87df58feb5834e Dario Binacchi 2024-12-29 189 hws[IMX8MN_ANATOP_SYS_PLL1_40M] =
87df58feb5834e Dario Binacchi 2024-12-29 190 imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
87df58feb5834e Dario Binacchi 2024-12-29 191 hws[IMX8MN_ANATOP_SYS_PLL1_80M] =
87df58feb5834e Dario Binacchi 2024-12-29 192 imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
87df58feb5834e Dario Binacchi 2024-12-29 193 hws[IMX8MN_ANATOP_SYS_PLL1_100M] =
87df58feb5834e Dario Binacchi 2024-12-29 194 imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
87df58feb5834e Dario Binacchi 2024-12-29 195 hws[IMX8MN_ANATOP_SYS_PLL1_133M] =
87df58feb5834e Dario Binacchi 2024-12-29 196 imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
87df58feb5834e Dario Binacchi 2024-12-29 197 hws[IMX8MN_ANATOP_SYS_PLL1_160M] =
87df58feb5834e Dario Binacchi 2024-12-29 198 imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
87df58feb5834e Dario Binacchi 2024-12-29 199 hws[IMX8MN_ANATOP_SYS_PLL1_200M] =
87df58feb5834e Dario Binacchi 2024-12-29 200 imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
87df58feb5834e Dario Binacchi 2024-12-29 201 hws[IMX8MN_ANATOP_SYS_PLL1_266M] =
87df58feb5834e Dario Binacchi 2024-12-29 202 imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
87df58feb5834e Dario Binacchi 2024-12-29 203 hws[IMX8MN_ANATOP_SYS_PLL1_400M] =
87df58feb5834e Dario Binacchi 2024-12-29 204 imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
87df58feb5834e Dario Binacchi 2024-12-29 205 hws[IMX8MN_ANATOP_SYS_PLL1_800M] =
87df58feb5834e Dario Binacchi 2024-12-29 206 imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
87df58feb5834e Dario Binacchi 2024-12-29 207
87df58feb5834e Dario Binacchi 2024-12-29 208 /* SYS PLL2 fixed output */
87df58feb5834e Dario Binacchi 2024-12-29 209 hws[IMX8MN_ANATOP_SYS_PLL2_OUT] =
87df58feb5834e Dario Binacchi 2024-12-29 210 imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
87df58feb5834e Dario Binacchi 2024-12-29 211 hws[IMX8MN_ANATOP_SYS_PLL2_50M] =
87df58feb5834e Dario Binacchi 2024-12-29 212 imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
87df58feb5834e Dario Binacchi 2024-12-29 213 hws[IMX8MN_ANATOP_SYS_PLL2_100M] =
87df58feb5834e Dario Binacchi 2024-12-29 214 imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
87df58feb5834e Dario Binacchi 2024-12-29 215 hws[IMX8MN_ANATOP_SYS_PLL2_125M] =
87df58feb5834e Dario Binacchi 2024-12-29 216 imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
87df58feb5834e Dario Binacchi 2024-12-29 217 hws[IMX8MN_ANATOP_SYS_PLL2_166M] =
87df58feb5834e Dario Binacchi 2024-12-29 218 imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
87df58feb5834e Dario Binacchi 2024-12-29 219 hws[IMX8MN_ANATOP_SYS_PLL2_200M] =
87df58feb5834e Dario Binacchi 2024-12-29 220 imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
87df58feb5834e Dario Binacchi 2024-12-29 221 hws[IMX8MN_ANATOP_SYS_PLL2_250M] =
87df58feb5834e Dario Binacchi 2024-12-29 222 imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
87df58feb5834e Dario Binacchi 2024-12-29 223 hws[IMX8MN_ANATOP_SYS_PLL2_333M] =
87df58feb5834e Dario Binacchi 2024-12-29 224 imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
87df58feb5834e Dario Binacchi 2024-12-29 225 hws[IMX8MN_ANATOP_SYS_PLL2_500M] =
87df58feb5834e Dario Binacchi 2024-12-29 226 imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
87df58feb5834e Dario Binacchi 2024-12-29 227 hws[IMX8MN_ANATOP_SYS_PLL2_1000M] =
87df58feb5834e Dario Binacchi 2024-12-29 228 imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
87df58feb5834e Dario Binacchi 2024-12-29 229
87df58feb5834e Dario Binacchi 2024-12-29 230 hws[IMX8MN_ANATOP_CLK_CLKOUT1_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 231 imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4,
87df58feb5834e Dario Binacchi 2024-12-29 232 clkout_sels, ARRAY_SIZE(clkout_sels));
87df58feb5834e Dario Binacchi 2024-12-29 233 hws[IMX8MN_ANATOP_CLK_CLKOUT1_DIV] =
87df58feb5834e Dario Binacchi 2024-12-29 234 imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128,
87df58feb5834e Dario Binacchi 2024-12-29 235 0, 4);
87df58feb5834e Dario Binacchi 2024-12-29 236 hws[IMX8MN_ANATOP_CLK_CLKOUT1] =
87df58feb5834e Dario Binacchi 2024-12-29 237 imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
87df58feb5834e Dario Binacchi 2024-12-29 238 hws[IMX8MN_ANATOP_CLK_CLKOUT2_SEL] =
87df58feb5834e Dario Binacchi 2024-12-29 239 imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4,
87df58feb5834e Dario Binacchi 2024-12-29 240 clkout_sels, ARRAY_SIZE(clkout_sels));
87df58feb5834e Dario Binacchi 2024-12-29 241 hws[IMX8MN_ANATOP_CLK_CLKOUT2_DIV] =
87df58feb5834e Dario Binacchi 2024-12-29 242 imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128,
87df58feb5834e Dario Binacchi 2024-12-29 243 16, 4);
87df58feb5834e Dario Binacchi 2024-12-29 @244 hws[IMX8MN_ANATOP_CLK_CLKOUT2] =
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Corruption.
87df58feb5834e Dario Binacchi 2024-12-29 245 imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
87df58feb5834e Dario Binacchi 2024-12-29 246
87df58feb5834e Dario Binacchi 2024-12-29 247 imx_check_clk_hws(hws, IMX8MN_ANATOP_CLK_END);
87df58feb5834e Dario Binacchi 2024-12-29 248
87df58feb5834e Dario Binacchi 2024-12-29 249 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
87df58feb5834e Dario Binacchi 2024-12-29 250 if (ret < 0) {
87df58feb5834e Dario Binacchi 2024-12-29 251 imx_unregister_hw_clocks(hws, IMX8MN_ANATOP_CLK_END);
87df58feb5834e Dario Binacchi 2024-12-29 252 return dev_err_probe(dev, ret,
87df58feb5834e Dario Binacchi 2024-12-29 253 "failed to register anatop clock provider\n");
87df58feb5834e Dario Binacchi 2024-12-29 254 }
87df58feb5834e Dario Binacchi 2024-12-29 255
87df58feb5834e Dario Binacchi 2024-12-29 256 dev_info(dev, "NXP i.MX8MN anatop clock driver probed\n");
87df58feb5834e Dario Binacchi 2024-12-29 257 return 0;
87df58feb5834e Dario Binacchi 2024-12-29 258 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v8 12/18] dt-bindings: clock: imx8m-clock: add PLLs
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (10 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 11/18] clk: imx: add support for i.MX8MN anatop clock driver Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 13/18] arm64: dts: imx8mm: add PLLs to clock controller module (CCM) Dario Binacchi
` (5 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
Though adding the PLLs to clocks and clock-names properties will break
the ABI, it is required to accurately describe the hardware. Indeed,
the Clock Control Module (CCM) receives clocks from the PLLs and
oscillators and generates clocks for on-chip peripherals.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- New
.../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++-----
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
index c643d4a81478..d96570bf60dc 100644
--- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
@@ -29,12 +29,12 @@ properties:
maxItems: 2
clocks:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
clock-names:
- minItems: 6
- maxItems: 7
+ minItems: 7
+ maxItems: 10
'#clock-cells':
const: 1
@@ -86,6 +86,10 @@ allOf:
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
+ - description: audio1 PLL input
+ - description: audio2 PLL input
+ - description: dram PLL input
+ - description: video PLL input
clock-names:
items:
@@ -95,20 +99,31 @@ allOf:
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
+ - const: audio_pll1
+ - const: audio_pll2
+ - const: dram_pll
+ - const: video_pll
additionalProperties: false
examples:
# Clock Control Module node:
- |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+
clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL2>,
+ <&anatop IMX8MM_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MM_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
};
- |
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 13/18] arm64: dts: imx8mm: add PLLs to clock controller module (CCM)
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (11 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 12/18] dt-bindings: clock: imx8m-clock: add PLLs Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 14/18] arm64: dts: imx8mn: " Dario Binacchi
` (4 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add the PLLs generated by anatop to the clock list of the Clock
Controller Module (CCM) node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 597041a05073..79f4c1ae7d8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -642,9 +642,14 @@ clk: clock-controller@30380000 {
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MM_ANATOP_AUDIO_PLL2>,
+ <&anatop IMX8MM_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MM_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
<&clk IMX8MM_CLK_A53_CORE>,
<&clk IMX8MM_CLK_NOC>,
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 14/18] arm64: dts: imx8mn: add PLLs to clock controller module (CCM)
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (12 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 13/18] arm64: dts: imx8mm: add PLLs to clock controller module (CCM) Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 15/18] arm64: dts: imx8mp: " Dario Binacchi
` (3 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add the PLLs generated by anatop to the clock list of the Clock
Controller Module (CCM) node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 49be492b5687..01013c1fd61d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -643,9 +643,14 @@ clk: clock-controller@30380000 {
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MN_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MN_ANATOP_AUDIO_PLL2>,
+ <&anatop IMX8MN_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MN_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
<&clk IMX8MN_CLK_A53_CORE>,
<&clk IMX8MN_CLK_NOC>,
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 15/18] arm64: dts: imx8mp: add PLLs to clock controller module (CCM)
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (13 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 14/18] arm64: dts: imx8mn: " Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 16/18] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Dario Binacchi
` (2 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Conor Dooley, Fabio Estevam,
Krzysztof Kozlowski, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, devicetree, imx, linux-arm-kernel
Add the PLLs generated by anatop to the clock list of the Clock
Controller Module (CCM) node.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- New
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 0b928e173f29..eab05170442d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -751,9 +751,14 @@ clk: clock-controller@30380000 {
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
+ <&clk_ext3>, <&clk_ext4>,
+ <&anatop IMX8MP_ANATOP_AUDIO_PLL1>,
+ <&anatop IMX8MP_ANATOP_AUDIO_PLL2>,
+ <&anatop IMX8MP_ANATOP_DRAM_PLL>,
+ <&anatop IMX8MP_ANATOP_VIDEO_PLL>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
+ "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
+ "dram_pll", "video_pll";
assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
<&clk IMX8MP_CLK_A53_CORE>,
<&clk IMX8MP_CLK_NOC>,
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 16/18] dt-bindings: clock: imx8m-clock: support spread spectrum clocking
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (14 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 15/18] arm64: dts: imx8mp: " Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 17/18] clk: imx: pll14xx: support spread spectrum clock generation Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 18/18] clk: imx8mn: " Dario Binacchi
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Krzysztof Kozlowski, Abel Vesa,
Conor Dooley, Fabio Estevam, Krzysztof Kozlowski,
Michael Turquette, Peng Fan, Pengutronix Kernel Team, Rob Herring,
Sascha Hauer, Shawn Guo, Stephen Boyd, devicetree, imx,
linux-arm-kernel, linux-clk
The addition of DT bindings for enabling and tuning spread spectrum
clocking generation can be applied specifically to the PLLs.
The "" value for the fsl,ssc-method property is specifically intended to
specify a "no SSC" case, as in the example, when you don't want to
configure spread spectrum for one of the PLLs, thus avoiding the use of
a method that would only make sense if SSC were being set.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
(no changes since v7)
Changes in v7:
- List the PLLs to strictly define the setup order for each of the
added properties
- Drop maxItems from "fsl,ssc-modfreq-hz" and "fsl,ssc-modrate-percent"
properties
- Add 'Reviewed-by' tag of Krzysztof Kozlowski
Changes in v6:
- Improve the commit message
- change minItems from 7 to 1 for all the ssc properties added
- change maxItems from 10 to 4 for alle the ssc properties added
- update the DTS example
Changes in v4:
- Drop "fsl,ssc-clocks" property. The other added properties now refer
to the clock list.
- Updated minItems and maxItems of
- clocks
- clock-names
- fsl,ssc-modfreq-hz
- fsl,ssc-modrate-percent
- fsl,ssc-modmethod
- Updated the dts examples
Changes in v3:
- Added in v3
- The dt-bindings have been moved from fsl,imx8m-anatop.yaml to
imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is
indeed more or less a syscon, so it represents a memory area
accessible by ccm (imx8m-clock.yaml) to setup the PLLs.
Changes in v2:
- Add "allOf:" and place it after "required:" block, like in the
example schema.
- Move the properties definition to the top-level.
- Drop unit types as requested by the "make dt_binding_check" command.
.../bindings/clock/imx8m-clock.yaml | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
index d96570bf60dc..d347d630764a 100644
--- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml
@@ -43,6 +43,46 @@ properties:
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
for the full list of i.MX8M clock IDs.
+ fsl,ssc-modfreq-hz:
+ description:
+ The values of modulation frequency (Hz unit) for each clock
+ supporting spread spectrum.
+ minItems: 1
+ items:
+ - description: audio_pll1
+ - description: audio_pll2
+ - description: dram_pll
+ - description: video_pll
+
+ fsl,ssc-modrate-percent:
+ description:
+ The percentage values of modulation rate for each clock
+ supporting spread spectrum.
+ minItems: 1
+ items:
+ - description: audio_pll1
+ - description: audio_pll2
+ - description: dram_pll
+ - description: video_pll
+
+ fsl,ssc-modmethod:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description: |
+ The modulation techniques for each clock supporting spread
+ spectrum in this order::
+ - audio_pll1
+ - audio_pll2
+ - dram_pll
+ - video_pll
+ minItems: 1
+ maxItems: 4
+ items:
+ enum:
+ - ""
+ - down-spread
+ - up-spread
+ - center-spread
+
required:
- compatible
- reg
@@ -76,6 +116,10 @@ allOf:
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
+ fsl,ssc-modfreq-hz: false
+ fsl,ssc-modrate-percent: false
+ fsl,ssc-modmethod: false
+
else:
properties:
clocks:
@@ -124,6 +168,9 @@ examples:
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2",
"dram_pll", "video_pll";
+ fsl,ssc-modfreq-hz = <6818>, <0>, <0>, <2419>;
+ fsl,ssc-modrate-percent = <3>, <0>, <0>, <7>;
+ fsl,ssc-modmethod = "down-spread", "", "", "center-spread";
};
- |
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 17/18] clk: imx: pll14xx: support spread spectrum clock generation
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (15 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 16/18] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2024-12-29 14:49 ` [PATCH v8 18/18] clk: imx8mn: " Dario Binacchi
17 siblings, 0 replies; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Peng Fan, Abel Vesa, Fabio Estevam,
Michael Turquette, Pengutronix Kernel Team, Sascha Hauer,
Shawn Guo, Stephen Boyd, imx, linux-arm-kernel, linux-clk
Add support for spread spectrum clock (SSC) generation to the pll14xxx
driver.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
(no changes since v7)
Changes in v7:
- Add 'Reviewed-by' tag of Peng Fan
Changes in v6:
- Update the code based on the changes made to the DT bindings
drivers/clk/imx/clk-pll14xx.c | 134 ++++++++++++++++++++++++++++++++++
drivers/clk/imx/clk.h | 16 ++++
2 files changed, 150 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index d63564dbb12c..c20f1ade9dff 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -20,6 +20,8 @@
#define GNRL_CTL 0x0
#define DIV_CTL0 0x4
#define DIV_CTL1 0x8
+#define SSCG_CTRL 0xc
+
#define LOCK_STATUS BIT(31)
#define LOCK_SEL_MASK BIT(29)
#define CLKE_MASK BIT(11)
@@ -31,6 +33,10 @@
#define KDIV_MASK GENMASK(15, 0)
#define KDIV_MIN SHRT_MIN
#define KDIV_MAX SHRT_MAX
+#define SSCG_ENABLE BIT(31)
+#define MFREQ_CTL_MASK GENMASK(19, 12)
+#define MRAT_CTL_MASK GENMASK(9, 4)
+#define SEL_PF_MASK GENMASK(1, 0)
#define LOCK_TIMEOUT_US 10000
@@ -40,6 +46,8 @@ struct clk_pll14xx {
enum imx_pll14xx_type type;
const struct imx_pll14xx_rate_table *rate_table;
int rate_count;
+ bool ssc_enable;
+ struct imx_pll14xx_ssc ssc_conf;
};
#define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
@@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
return 0;
}
+static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long parent_rate,
+ unsigned int pdiv, unsigned int mdiv)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(hw);
+ struct imx_pll14xx_ssc *conf = &pll->ssc_conf;
+ u32 sscg_ctrl, mfr, mrr;
+
+ sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL);
+ sscg_ctrl &=
+ ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK);
+
+ mfr = parent_rate / (conf->mod_freq * pdiv * (1 << 5));
+ mrr = (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr);
+
+ sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) |
+ FIELD_PREP(MRAT_CTL_MASK, mrr) |
+ FIELD_PREP(SEL_PF_MASK, conf->mod_type);
+
+ writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL);
+}
+
static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
unsigned long prate)
{
@@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv),
pll->base + DIV_CTL1);
+ if (pll->ssc_enable)
+ clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv);
+
return 0;
}
@@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
gnrl_ctl &= ~BYPASS_MASK;
writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
+ if (pll->ssc_enable)
+ clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv);
+
return 0;
}
@@ -542,3 +577,102 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
return hw;
}
EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);
+
+void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf)
+{
+ struct clk_pll14xx *pll = to_clk_pll14xx(hw);
+
+ pll->ssc_enable = true;
+ memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf));
+}
+EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc);
+
+static int clk_pll14xx_ssc_mod_type(const char *name,
+ enum imx_pll14xx_ssc_mod_type *mod_type)
+{
+ int i;
+ struct {
+ const char *name;
+ enum imx_pll14xx_ssc_mod_type id;
+ } mod_types[] = {
+ { .name = "down-spread", .id = IMX_PLL14XX_SSC_DOWN_SPREAD },
+ { .name = "up-spread", .id = IMX_PLL14XX_SSC_UP_SPREAD },
+ { .name = "center-spread", .id = IMX_PLL14XX_SSC_CENTER_SPREAD }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mod_types); i++) {
+ if (!strcmp(name, mod_types[i].name)) {
+ *mod_type = mod_types[i].id;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int clk_pll14xx_ssc_index(const char *pll_name)
+{
+ static const char *const pll_names[] = {
+ "audio_pll1",
+ "audio_pll2",
+ "dram_pll",
+ "video_pll"
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pll_names); i++) {
+ if (!strcmp(pll_names[i], pll_name))
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name,
+ struct imx_pll14xx_ssc *conf)
+{
+ int index, ret;
+ const char *s;
+
+ if (!conf)
+ return -EINVAL;
+
+ index = clk_pll14xx_ssc_index(pll_name);
+ if (index < 0)
+ return index;
+
+ ret = of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", index,
+ &conf->mod_freq);
+ if (ret)
+ return ret;
+
+ ret = of_property_read_u32_index(np, "fsl,ssc-modrate-percent", index,
+ &conf->mod_rate);
+ if (ret) {
+ pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n",
+ np);
+ return ret;
+ }
+
+ ret = of_property_read_string_index(np, "fsl,ssc-modmethod", index, &s);
+ if (ret) {
+ pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n",
+ np);
+ return ret;
+ }
+
+ if (strlen(s) == 0)
+ return -ENODEV;
+
+ ret = clk_pll14xx_ssc_mod_type(s, &conf->mod_type);
+ if (ret) {
+ pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np);
+ return ret;
+ }
+
+ pr_debug("%s: SSC %s settings: mod_freq: %d, mod_rate: %d: mod_method: %s [%d]\n",
+ __func__, pll_name, conf->mod_freq, conf->mod_rate, s, conf->mod_type);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 50e407cf48d9..38e4a4cf253d 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -69,6 +69,18 @@ struct imx_pll14xx_clk {
int flags;
};
+enum imx_pll14xx_ssc_mod_type {
+ IMX_PLL14XX_SSC_DOWN_SPREAD,
+ IMX_PLL14XX_SSC_UP_SPREAD,
+ IMX_PLL14XX_SSC_CENTER_SPREAD,
+};
+
+struct imx_pll14xx_ssc {
+ unsigned int mod_freq;
+ unsigned int mod_rate;
+ enum imx_pll14xx_ssc_mod_type mod_type;
+};
+
extern struct imx_pll14xx_clk imx_1416x_pll;
extern struct imx_pll14xx_clk imx_1443x_pll;
extern struct imx_pll14xx_clk imx_1443x_dram_pll;
@@ -489,4 +501,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,
struct clk_hw *imx_anatop_get_clk_hw(struct device_node *np, int id);
+void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf);
+int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name,
+ struct imx_pll14xx_ssc *conf);
+
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v8 18/18] clk: imx8mn: support spread spectrum clock generation
2024-12-29 14:49 [PATCH v8 00/18] Support spread spectrum clocking for i.MX8N PLLs Dario Binacchi
` (16 preceding siblings ...)
2024-12-29 14:49 ` [PATCH v8 17/18] clk: imx: pll14xx: support spread spectrum clock generation Dario Binacchi
@ 2024-12-29 14:49 ` Dario Binacchi
2025-01-06 9:06 ` Peng Fan
17 siblings, 1 reply; 24+ messages in thread
From: Dario Binacchi @ 2024-12-29 14:49 UTC (permalink / raw)
To: linux-kernel
Cc: linux-amarula, Dario Binacchi, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
Add support for spread spectrum clock generation for the audio, video,
and DRAM PLLs.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
Changes in v8:
- Drop the patches added in version 7:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v7:
- Add and manage fsl,anatop property as phandle to the anatop node with
the new patches:
- 10/23 dt-bindings: clock: imx8m-clock: add phandle to the anatop
- 11/23 arm64: dts: imx8mm: add phandle to anatop within CCM
- 12/23 arm64: dts: imx8mn: add phandle to anatop within CCM
- 13/23 arm64: dts: imx8mp: add phandle to anatop within CCM
- 14/23 arm64: dts: imx8mq: add phandle to anatop within CCM
Changes in v6:
- Merge patches:
10/20 dt-bindings: clock: imx8mm: add binding definitions for anatop
11/20 dt-bindings: clock: imx8mn: add binding definitions for anatop
12/20 dt-bindings: clock: imx8mp: add binding definitions for anatop
to
05/20 dt-bindings: clock: imx8m-anatop: define clocks/clock-names
now renamed
05/18 dt-bindings: clock: imx8m-anatop: add oscillators and PLLs
- Split the patch
15/20 dt-bindings-clock-imx8m-clock-support-spread-spectru.patch
into
12/18 dt-bindings: clock: imx8m-clock: add PLLs
16/18 dt-bindings: clock: imx8m-clock: support spread spectrum clocking
Changes in v5:
- Fix compilation errors.
- Separate driver code from dt-bindings
Changes in v4:
- Add dt-bindings for anatop
- Add anatop driver
- Drop fsl,ssc-clocks from spread spectrum dt-bindings
Changes in v3:
- Patches 1/8 has been added in version 3. The dt-bindings have
been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The
anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a
syscon, so it represents a memory area accessible by ccm
(imx8m-clock.yaml) to setup the PLLs.
- Patches {3,5}/8 have been added in version 3.
- Patches {4,6,8}/8 use ccm device node instead of the anatop one.
Changes in v2:
- Add "allOf:" and place it after "required:" block, like in the
example schema.
- Move the properties definition to the top-level.
- Drop unit types as requested by the "make dt_binding_check" command.
drivers/clk/imx/clk-imx8mn.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index c3a3d063d58e..090b5924fa01 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -306,6 +306,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node, *anp;
void __iomem *base;
+ struct imx_pll14xx_ssc ssc_conf;
int ret;
base = devm_platform_ioremap_resource(pdev, 0);
@@ -344,9 +345,21 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_SYS_PLL3_REF_SEL);
hws[IMX8MN_AUDIO_PLL1] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL1);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll1", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL1], &ssc_conf);
+
hws[IMX8MN_AUDIO_PLL2] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_AUDIO_PLL2);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "audio_pll2", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_AUDIO_PLL2], &ssc_conf);
+
hws[IMX8MN_VIDEO_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_VIDEO_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "video_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_VIDEO_PLL], &ssc_conf);
+
hws[IMX8MN_DRAM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_DRAM_PLL);
+ if (!imx_clk_pll14xx_ssc_parse_dt(np, "dram_pll", &ssc_conf))
+ imx_clk_pll14xx_enable_ssc(hws[IMX8MN_DRAM_PLL], &ssc_conf);
+
hws[IMX8MN_GPU_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_GPU_PLL);
hws[IMX8MN_M7_ALT_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_M7_ALT_PLL);
hws[IMX8MN_ARM_PLL] = imx_anatop_get_clk_hw(anp, IMX8MN_ANATOP_ARM_PLL);
--
2.43.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v8 18/18] clk: imx8mn: support spread spectrum clock generation
2024-12-29 14:49 ` [PATCH v8 18/18] clk: imx8mn: " Dario Binacchi
@ 2025-01-06 9:06 ` Peng Fan
0 siblings, 0 replies; 24+ messages in thread
From: Peng Fan @ 2025-01-06 9:06 UTC (permalink / raw)
To: Dario Binacchi
Cc: linux-kernel, linux-amarula, Abel Vesa, Fabio Estevam,
Michael Turquette, Peng Fan, Pengutronix Kernel Team,
Sascha Hauer, Shawn Guo, Stephen Boyd, imx, linux-arm-kernel,
linux-clk
On Sun, Dec 29, 2024 at 03:49:42PM +0100, Dario Binacchi wrote:
>Add support for spread spectrum clock generation for the audio, video,
>and DRAM PLLs.
>
>Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 24+ messages in thread