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From: Rob Herring <robh@kernel.org>
To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Cc: Anup Patel <anup@brainfault.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: interrupt-controller: add risc-v,aplic hart indexes
Date: Fri, 10 Jan 2025 10:20:43 -0600	[thread overview]
Message-ID: <20250110162043.GA2975507-robh@kernel.org> (raw)
In-Reply-To: <20250109113814.3254448-2-vladimir.kondratiev@mobileye.com>

On Thu, Jan 09, 2025 at 01:38:13PM +0200, Vladimir Kondratiev wrote:
> Document optional property "riscv,hart-indexes"
> 
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
>  .../bindings/interrupt-controller/riscv,aplic.yaml        | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> index 190a6499c932..bef00521d5da 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> @@ -91,6 +91,14 @@ properties:
>        Firmware must configure interrupt delegation registers based on
>        interrupt delegation list.
>  
> +  riscv,hart-indexes:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 1
> +    maxItems: 16384
> +    description:
> +      A list of hart indexes that APLIC should use to address each hart
> +      that is mentioned in the "interrupts-extended"

Wouldn't using the 'cpus' property linking to each cpu/hart node work?

Rob

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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Cc: Anup Patel <anup@brainfault.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: interrupt-controller: add risc-v,aplic hart indexes
Date: Fri, 10 Jan 2025 10:20:43 -0600	[thread overview]
Message-ID: <20250110162043.GA2975507-robh@kernel.org> (raw)
In-Reply-To: <20250109113814.3254448-2-vladimir.kondratiev@mobileye.com>

On Thu, Jan 09, 2025 at 01:38:13PM +0200, Vladimir Kondratiev wrote:
> Document optional property "riscv,hart-indexes"
> 
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
>  .../bindings/interrupt-controller/riscv,aplic.yaml        | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> index 190a6499c932..bef00521d5da 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
> @@ -91,6 +91,14 @@ properties:
>        Firmware must configure interrupt delegation registers based on
>        interrupt delegation list.
>  
> +  riscv,hart-indexes:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 1
> +    maxItems: 16384
> +    description:
> +      A list of hart indexes that APLIC should use to address each hart
> +      that is mentioned in the "interrupts-extended"

Wouldn't using the 'cpus' property linking to each cpu/hart node work?

Rob

  reply	other threads:[~2025-01-10 17:37 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-09 11:38 [PATCH v4 0/2] riscv,aplic: support for hart indexes Vladimir Kondratiev
2025-01-09 11:38 ` Vladimir Kondratiev
2025-01-09 11:38 ` [PATCH v4 1/2] dt-bindings: interrupt-controller: add risc-v,aplic " Vladimir Kondratiev
2025-01-09 11:38   ` Vladimir Kondratiev
2025-01-10 16:20   ` Rob Herring [this message]
2025-01-10 16:20     ` Rob Herring
2025-01-12  7:47     ` Vladimir Kondratiev
2025-01-12  7:47       ` Vladimir Kondratiev
2025-01-10 16:22   ` Rob Herring
2025-01-10 16:22     ` Rob Herring
2025-01-12  8:38     ` Vladimir Kondratiev
2025-01-12  8:38       ` Vladimir Kondratiev
2025-01-27 17:52       ` Thomas Gleixner
2025-01-27 17:52         ` Thomas Gleixner
2025-01-29  9:16         ` [PATCH v5 0/2] riscv,aplic: support for " Vladimir Kondratiev
2025-01-29  9:16           ` Vladimir Kondratiev
2025-01-29  9:16           ` [PATCH v5 1/2] dt-bindings: interrupt-controller: add risc-v,aplic " Vladimir Kondratiev
2025-01-29  9:16             ` Vladimir Kondratiev
2025-01-29 16:40             ` Rob Herring (Arm)
2025-01-29 16:40               ` Rob Herring (Arm)
2025-02-03 13:37             ` [tip: irq/core] dt-bindings: interrupt-controller: Add " tip-bot2 for Vladimir Kondratiev
2025-01-29  9:16           ` [PATCH v5 2/2] irqchip/riscv-aplic: add support for " Vladimir Kondratiev
2025-01-29  9:16             ` Vladimir Kondratiev
2025-02-03 13:37             ` [tip: irq/core] irqchip/riscv-aplic: Add " tip-bot2 for Vladimir Kondratiev
2025-01-09 11:38 ` [PATCH v4 2/2] irqchip/riscv-aplic: add " Vladimir Kondratiev
2025-01-09 11:38   ` Vladimir Kondratiev
2025-01-20  9:57 ` [PATCH v4 0/2] riscv,aplic: " Vladimir Kondratiev
2025-01-20  9:57   ` Vladimir Kondratiev

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