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From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Fabiano Rosas" <farosas@suse.de>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Andrey Smirnov" <andrew.smirnov@gmail.com>,
	qemu-arm@nongnu.org,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	"Laurent Vivier" <lvivier@redhat.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	qemu-block@nongnu.org, "Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v2 08/13] hw/char/imx_serial: Turn some DPRINTF() statements into trace events
Date: Sat, 11 Jan 2025 19:37:06 +0100	[thread overview]
Message-ID: <20250111183711.2338-9-shentey@gmail.com> (raw)
In-Reply-To: <20250111183711.2338-1-shentey@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/char/imx_serial.c | 58 +++++++++++++++++++++++++++++---------------
 hw/char/trace-events |  5 ++++
 2 files changed, 44 insertions(+), 19 deletions(-)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index be06f39a4d..38b4865157 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -27,6 +27,7 @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qemu/fifo32.h"
+#include "trace.h"
 
 #ifndef DEBUG_IMX_UART
 #define DEBUG_IMX_UART 0
@@ -185,10 +186,10 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
                                 unsigned size)
 {
     IMXSerialState *s = (IMXSerialState *)opaque;
+    Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
     uint32_t c, rx_used;
     uint8_t rxtl = s->ufcr & TL_MASK;
-
-    DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
+    uint64_t value;
 
     switch (offset >> 2) {
     case 0x0: /* URXD */
@@ -209,49 +210,67 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
             imx_serial_rx_fifo_ageing_timer_restart(s);
             qemu_chr_fe_accept_input(&s->chr);
         }
-        return c;
+        value = c;
+        break;
 
     case 0x20: /* UCR1 */
-        return s->ucr1;
+        value = s->ucr1;
+        break;
 
     case 0x21: /* UCR2 */
-        return s->ucr2;
+        value = s->ucr2;
+        break;
 
     case 0x25: /* USR1 */
-        return s->usr1;
+        value = s->usr1;
+        break;
 
     case 0x26: /* USR2 */
-        return s->usr2;
+        value = s->usr2;
+        break;
 
     case 0x2A: /* BRM Modulator */
-        return s->ubmr;
+        value = s->ubmr;
+        break;
 
     case 0x2B: /* Baud Rate Count */
-        return s->ubrc;
+        value = s->ubrc;
+        break;
 
     case 0x2d: /* Test register */
-        return s->uts1;
+        value = s->uts1;
+        break;
 
     case 0x24: /* UFCR */
-        return s->ufcr;
+        value = s->ufcr;
+        break;
 
     case 0x2c:
-        return s->onems;
+        value = s->onems;
+        break;
 
     case 0x22: /* UCR3 */
-        return s->ucr3;
+        value = s->ucr3;
+        break;
 
     case 0x23: /* UCR4 */
-        return s->ucr4;
+        value = s->ucr4;
+        break;
 
     case 0x29: /* BRM Incremental */
-        return 0x0; /* TODO */
+        value = 0x0; /* TODO */
+        break;
 
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
-        return 0;
+        value = 0;
+        break;
     }
+
+    trace_imx_serial_read(chr ? chr->label : "NODEV", offset, value);
+
+    return value;
 }
 
 static void imx_serial_write(void *opaque, hwaddr offset,
@@ -261,8 +280,7 @@ static void imx_serial_write(void *opaque, hwaddr offset,
     Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
     unsigned char ch;
 
-    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
-            offset, (unsigned int)value, chr ? chr->label : "NODEV");
+    trace_imx_serial_write(chr ? chr->label : "NODEV", offset, value);
 
     switch (offset >> 2) {
     case 0x10: /* UTXD */
@@ -374,9 +392,11 @@ static int imx_can_receive(void *opaque)
 static void imx_put_data(void *opaque, uint32_t value)
 {
     IMXSerialState *s = (IMXSerialState *)opaque;
+    Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
     uint8_t rxtl = s->ufcr & TL_MASK;
 
-    DPRINTF("received char\n");
+    trace_imx_serial_put_data(chr ? chr->label : "NODEV", value);
+
     imx_serial_rx_fifo_push(s, value);
     if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
         s->usr1 |= USR1_RRDY;
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 59e1f734a7..92e002da7a 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -52,6 +52,11 @@ escc_sunkbd_event_out(int ch) "Translated keycode 0x%2.2x"
 escc_kbd_command(int val) "Command %d"
 escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%01x"
 
+# imx_serial.c
+imx_serial_read(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] -> 0x%08" PRIx64
+imx_serial_write(const char *chrname, uint64_t addr, uint64_t value) "%s:[0x%03" PRIu64 "] <- 0x%08" PRIx64
+imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32
+
 # pl011.c
 pl011_irq_state(int level) "irq state %d"
 pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
-- 
2.48.0


  parent reply	other threads:[~2025-01-11 18:37 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-11 18:36 [PATCH v2 00/13] i.MX and SDHCI improvements Bernhard Beschow
2025-01-11 18:36 ` [PATCH v2 01/13] hw/sd/sdhci: Set SDHC_NIS_DMA bit when appropriate Bernhard Beschow
2025-01-15 12:55   ` Michael Tokarev
2025-01-16 23:39     ` Bernhard Beschow
2025-01-17  7:11       ` Michael Tokarev
2025-01-11 18:37 ` [PATCH v2 02/13] hw/char/imx_serial: Fix reset value of UFCR register Bernhard Beschow
2025-01-27 13:18   ` Peter Maydell
2025-01-11 18:37 ` [PATCH v2 03/13] hw/char/imx_serial: Update all state before restarting ageing timer Bernhard Beschow
2025-01-27 13:19   ` Peter Maydell
2025-01-11 18:37 ` [PATCH v2 04/13] hw/pci-host/designware: Expose MSI IRQ Bernhard Beschow
2025-01-27 13:30   ` Peter Maydell
2025-01-11 18:37 ` [PATCH v2 05/13] hw/gpio/imx_gpio: Don't clear input GPIO values upon reset Bernhard Beschow
2025-01-27 13:47   ` Peter Maydell
2025-01-11 18:37 ` [PATCH v2 06/13] hw/sd/sd: Remove legacy sd_set_cb() in favor of GPIOs Bernhard Beschow
2025-01-27 13:24   ` Peter Maydell
2025-01-27 23:11     ` Bernhard Beschow
2025-01-28 10:34       ` Peter Maydell
2025-01-28 22:45         ` Bernhard Beschow
2025-01-11 18:37 ` [PATCH v2 07/13] hw/sd/sd: Allow for inverting polarities of presence and write-protect GPIOs Bernhard Beschow
2025-01-15 17:32   ` Philippe Mathieu-Daudé
2025-01-17  9:29     ` Bernhard Beschow
2025-01-11 18:37 ` Bernhard Beschow [this message]
2025-01-11 18:37 ` [PATCH v2 09/13] hw/timer/imx_gpt: Remove unused define Bernhard Beschow
2025-01-11 18:37 ` [PATCH v2 10/13] tests/qtest/libqos: Reuse TYPE_IMX_I2C define Bernhard Beschow
2025-01-11 18:37 ` [PATCH v2 11/13] hw/i2c/imx_i2c: Convert DPRINTF() to trace events Bernhard Beschow
2025-01-14 13:34   ` Corey Minyard
2025-01-11 18:37 ` [PATCH v2 12/13] hw/misc/imx6_src: " Bernhard Beschow
2025-01-11 18:37 ` [PATCH v2 13/13] hw/gpio/imx_gpio: Turn DPRINTF() into " Bernhard Beschow
2025-01-14 12:46 ` [PATCH v2 00/13] i.MX and SDHCI improvements Bernhard Beschow
2025-01-27 13:54 ` Peter Maydell

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