* [PATCH v3 0/2] MediaTek pinctrl patch on mt8196 @ 2025-01-15 6:35 Cathy Xu 2025-01-15 6:35 ` [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 Cathy Xu 2025-01-15 6:35 ` [PATCH v3 2/2] pinctrl: mediatek: add mt8196 driver Cathy Xu 0 siblings, 2 replies; 17+ messages in thread From: Cathy Xu @ 2025-01-15 6:35 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang, Lei Xue, wenbin.mei Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Cathy Xu Changes in v3: - remove drive-strength-microamp & rsel-resistence-in-si-unit related description in mediatek,mt8196-pinctrl.yaml. - use pm_sleep_ptr() in pinctrl-mt8196.c to fix build error. Changes in v2: - fix driver file's coding style. - add pinctrl binding document. Changes in v1: - add mt8196 pinctrl driver. - add pinmux definition file. Cathy Xu (2): dt-bindings: pinctrl: mediatek: add support for mt8196 pinctrl: mediatek: add mt8196 driver .../pinctrl/mediatek,mt8196-pinctrl.yaml | 244 ++ drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8196.c | 1764 +++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h | 2789 +++++++++++++++++ include/dt-bindings/pinctrl/mt8196-pinfunc.h | 1572 ++++++++++ 6 files changed, 6382 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8196.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h create mode 100644 include/dt-bindings/pinctrl/mt8196-pinfunc.h -- 2.34.1 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-15 6:35 [PATCH v3 0/2] MediaTek pinctrl patch on mt8196 Cathy Xu @ 2025-01-15 6:35 ` Cathy Xu 2025-01-15 9:50 ` Krzysztof Kozlowski 2025-01-15 6:35 ` [PATCH v3 2/2] pinctrl: mediatek: add mt8196 driver Cathy Xu 1 sibling, 1 reply; 17+ messages in thread From: Cathy Xu @ 2025-01-15 6:35 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang, Lei Xue, wenbin.mei Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Cathy Xu, Guodong Liu 1.Add the new binding document for pinctrl on MediaTek mt8196. 2.Add the pinctrl header file on MediaTek mt8196. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com> --- .../pinctrl/mediatek,mt8196-pinctrl.yaml | 244 +++ include/dt-bindings/pinctrl/mt8196-pinfunc.h | 1572 +++++++++++++++++ 2 files changed, 1816 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/mt8196-pinfunc.h diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml new file mode 100644 index 000000000000..56a2d2de7ec1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 Pin Controller + +maintainers: + - Lei Xue <lei.xue@mediatek.com> + - Cathy Xu <ot_cathy.xu@mediatek.com> + +description: + The MediaTek's MT8196 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8196-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + reg: + items: + - description: gpio registers base address + - description: rt group io configuration registers base address + - description: rm1 group io configuration registers base address + - description: rm2 group io configuration registers base address + - description: rb group io configuration registers base address + - description: bm1 group io configuration registers base address + - description: bm2 group io configuration registers base address + - description: bm3 group io configuration registers base address + - description: lt group io configuration registers base address + - description: lm1 group io configuration registers base address + - description: lm2 group io configuration registers base address + - description: lb1 group io configuration registers base address + - description: lb2 group io configuration registers base address + - description: tm1 group io configuration registers base address + - description: tm2 group io configuration registers base address + - description: tm3 group io configuration registers base address + + reg-names: + items: + - const: iocfg0 + - const: iocfg_rt + - const: iocfg_rm1 + - const: iocfg_rm2 + - const: iocfg_rb + - const: iocfg_bm1 + - const: iocfg_bm2 + - const: iocfg_bm3 + - const: iocfg_lt + - const: iocfg_lm1 + - const: iocfg_lm2 + - const: iocfg_lb1 + - const: iocfg_lb2 + - const: iocfg_tm1 + - const: iocfg_tm2 + - const: iocfg_tm3 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/mt8196-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8196 pull down RSEL type define value. + description: | + For pull down type is normal, it doesn't need add RSEL & R1R0. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull down type is PD/RSEL, it can add RSEL define to set + different resistance. It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8196. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8196 pull up RSEL type define value. + description: | + For pull up type is normal, it don't need add RSEL & R1R0. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull up type is PU/RSEL, it can add RSEL define to set + different resistance. It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8196. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt8196-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8196-pinctrl"; + reg = <0x1002d000 0x1000>, + <0x12000000 0x1000>, + <0x12020000 0x1000>, + <0x12040000 0x1000>, + <0x12060000 0x1000>, + <0x12820000 0x1000>, + <0x12840000 0x1000>, + <0x12860000 0x1000>, + <0x13000000 0x1000>, + <0x13020000 0x1000>, + <0x13040000 0x1000>, + <0x130f0000 0x1000>, + <0x13110000 0x1000>, + <0x13800000 0x1000>, + <0x13820000 0x1000>, + <0x13860000 0x1000>; + reg-names = "iocfg0", "iocfg_rt", + "iocfg_rm1", "iocfg_rm2", "iocfg_rb", + "iocfg_bm1", "iocfg_bm2", "iocfg_bm3", + "iocfg_lt", "iocfg_lm1", "iocfg_lm2", + "iocfg_lb1", "iocfg_lb2", "iocfg_tm1", + "iocfg_tm2", "iocfg_tm3"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 271>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO110__FUNC_SPI1_CLK>, + <PINMUX_GPIO111__FUNC_SPI1_CSB>, + <PINMUX_GPIO112__FUNC_SPI1_MO>; + drive-strength = <6>; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO113__FUNC_SPI1_MI>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-disable; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h b/include/dt-bindings/pinctrl/mt8196-pinfunc.h new file mode 100644 index 000000000000..bf0c8374407c --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h @@ -0,0 +1,1572 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2025 Mediatek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + */ + +#ifndef __MT8196_PINFUNC_H +#define __MT8196_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_DMIC1_DAT (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SRCLKENAI1 (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_SPI3_A_MI (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_FMI2S_B_DI (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO15_AO (MTK_PIN_NO(1) | 6) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_PWM_VLP (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_DSI_HSYNC (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_RG_TSFDC_LDO_EN (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO8_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_MD_INT0 (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_DSI1_HSYNC (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_DA_TSFDC_LDO_MODE (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO9_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(4) | 2) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_LCM1_RST (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_SPI7_A_CLK (MTK_PIN_NO(5) | 2) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_DSI1_TE (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI7_A_CSB (MTK_PIN_NO(6) | 2) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI7_A_MO (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_GPS_PPS0 (MTK_PIN_NO(7) | 3) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SPI7_A_MI (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_EDP_TX_HPD (MTK_PIN_NO(8) | 3) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_I2SIN1_LRCK (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_RG_TSFDC_LDO_REFSEL0 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_I2SOUT1_DO (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_RG_TSFDC_LDO_REFSEL1 (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_FMI2S_B_BCK (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_DBG_MON_A30 (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2SIN1_DI_B (MTK_PIN_NO(12) | 3) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_EDP_TX_HPD (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_GPS_PPS1 (MTK_PIN_NO(13) | 2) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_SRCLKENA2 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_DSI2_TE (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_MD_INT3 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_TP_GPIO8_AO (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_SRCLKENAI0 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_UCTS0 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_MD_INT4 (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_I2SOUT2_DO (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_TP_GPIO9_AO (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_DP_TX_HPD (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_URTS0 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_KPROW2 (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_TP_GPIO10_AO (MTK_PIN_NO(16) | 6) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_MD_INT0 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_DP_OC_EN (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_UCTS1 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_MD_NTN_URXD1 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_KPCOL2 (MTK_PIN_NO(17) | 5) +#define PINMUX_GPIO17__FUNC_TP_GPIO11_AO (MTK_PIN_NO(17) | 6) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_DMIC1_CLK (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_URTS1 (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_MD_NTN_UTXD1 (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_I2SIN2_DI (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_TP_UTXD_GNSS_VLP (MTK_PIN_NO(18) | 6) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_DMIC1_DAT (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_CLKM3_A (MTK_PIN_NO(19) | 4) +#define PINMUX_GPIO19__FUNC_I2SIN2_BCK (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_TP_URXD_GNSS_VLP (MTK_PIN_NO(19) | 6) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_IDDIG (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_LCM2_RST (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_GPS_PPS1 (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_CLKM2_A (MTK_PIN_NO(20) | 4) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_BPI_BUS11 (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_PCIE_PERSTN_1P (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_DSI1_TE (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_DMIC_CLK (MTK_PIN_NO(21) | 4) +#define PINMUX_GPIO21__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(21) | 5) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_BPI_BUS12 (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_PCIE_CLKREQN_1P (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_DSI2_TE (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_DMIC_DAT (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(22) | 5) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_BPI_BUS13 (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_PCIE_WAKEN_1P (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_DSI3_TE (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_DMIC1_CLK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(23) | 5) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_BPI_BUS14 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_LCM1_RST (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_AGPS_SYNC (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_DMIC1_DAT (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_DISP_PWM1 (MTK_PIN_NO(24) | 6) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_BPI_BUS15 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_LCM2_RST (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SRCLKENAI1 (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_DMIC2_CLK (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DISP_PWM2 (MTK_PIN_NO(25) | 6) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_BPI_BUS16 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_LCM3_RST (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_DMIC2_DAT (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_DISP_PWM3 (MTK_PIN_NO(26) | 6) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_BPI_BUS17 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_UTXD4 (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_DISP_PWM4 (MTK_PIN_NO(27) | 6) +#define PINMUX_GPIO27__FUNC_DBG_MON_A20 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_BPI_BUS18 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_URXD4 (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI2_A_MI (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_CLKM0_A (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_DBG_MON_A21 (MTK_PIN_NO(28) | 7) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_BPI_BUS19 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_MD_NTN_UTXD1 (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SPI2_A_MO (MTK_PIN_NO(29) | 3) +#define PINMUX_GPIO29__FUNC_CLKM1_A (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_UCTS4 (MTK_PIN_NO(29) | 6) +#define PINMUX_GPIO29__FUNC_DBG_MON_A17 (MTK_PIN_NO(29) | 7) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_BPI_BUS20 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_MD_NTN_URXD1 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_SPI2_A_CLK (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_CLKM2_A (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_DSI3_HSYNC (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_URTS4 (MTK_PIN_NO(30) | 6) +#define PINMUX_GPIO30__FUNC_DBG_MON_A18 (MTK_PIN_NO(30) | 7) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_BPI_BUS21 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_SPI2_A_CSB (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_CLKM3_A (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_EDP_TX_HPD (MTK_PIN_NO(31) | 6) +#define PINMUX_GPIO31__FUNC_DBG_MON_A19 (MTK_PIN_NO(31) | 7) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_LCM4_RST (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_DP_TX_HPD (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_SSPM_JTAG_TCK_VLP (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_SCP_JTAG0_TCK_VLP (MTK_PIN_NO(32) | 5) +#define PINMUX_GPIO32__FUNC_SPU0_TCK (MTK_PIN_NO(32) | 6) +#define PINMUX_GPIO32__FUNC_IO_JTAG_TCK (MTK_PIN_NO(32) | 7) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_DSI4_TE (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_DP_OC_EN (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_SSPM_JTAG_TRSTN_VLP (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_SCP_JTAG0_TRSTN_VLP (MTK_PIN_NO(33) | 5) +#define PINMUX_GPIO33__FUNC_SPU0_NTRST (MTK_PIN_NO(33) | 6) +#define PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(33) | 7) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_UCTS5 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SSPM_JTAG_TDI_VLP (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_SCP_JTAG0_TDI_VLP (MTK_PIN_NO(34) | 5) +#define PINMUX_GPIO34__FUNC_SPU0_TDI (MTK_PIN_NO(34) | 6) +#define PINMUX_GPIO34__FUNC_IO_JTAG_TDI (MTK_PIN_NO(34) | 7) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_URTS5 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SSPM_JTAG_TDO_VLP (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_SCP_JTAG0_TDO_VLP (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_SPU0_TDO (MTK_PIN_NO(35) | 6) +#define PINMUX_GPIO35__FUNC_IO_JTAG_TDO (MTK_PIN_NO(35) | 7) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_UTXD5 (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_SSPM_JTAG_TMS_VLP (MTK_PIN_NO(36) | 3) +#define PINMUX_GPIO36__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SCP_JTAG0_TMS_VLP (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_SPU0_TMS (MTK_PIN_NO(36) | 6) +#define PINMUX_GPIO36__FUNC_IO_JTAG_TMS (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_URXD5 (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_MD_INT3 (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_CLKM0_B (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_TP_GPIO5_AO (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_SPU0_UTX (MTK_PIN_NO(37) | 6) +#define PINMUX_GPIO37__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPMI_P_TRIG_FLAG (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_MD_INT4 (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_CLKM1_B (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_TP_GPIO6_AO (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_SPU0_URX (MTK_PIN_NO(38) | 6) +#define PINMUX_GPIO38__FUNC_DAP_MD32_SWD (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_I2S_MCK0 (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_GPS_PPS0 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_DBG_MON_B12 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_I2SIN6_0_BCK (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SPI4_B_CLK (MTK_PIN_NO(40) | 3) +#define PINMUX_GPIO40__FUNC_UCTS2 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_CCU1_UTXD (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_DBG_MON_B13 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_I2SIN6_0_LRCK (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SPI4_B_CSB (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_URTS2 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_CCU1_URXD (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_DBG_MON_B14 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_I2SIN6_0_DI (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_SPI4_B_MI (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_URXD2 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_CCU1_URTS (MTK_PIN_NO(42) | 5) +#define PINMUX_GPIO42__FUNC_MD32_0_RXD (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_B15 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_I2SOUT6_0_DO (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_SPI4_B_MO (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_UTXD2 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_CCU1_UCTS (MTK_PIN_NO(43) | 5) +#define PINMUX_GPIO43__FUNC_MD32_0_TXD (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_B16 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_SPI3_A_CLK (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_TP_GPIO10_AO (MTK_PIN_NO(44) | 6) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_DSI2_HSYNC (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_SPI3_A_CSB (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_PWM_VLP (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_TP_GPIO11_AO (MTK_PIN_NO(45) | 6) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SCP_SCL4 (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_PWM_VLP (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_SCP_ILDO_DTEST1_VLP (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_TP_GPIO0_AO (MTK_PIN_NO(46) | 6) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SCP_SDA4 (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_ILDO_DTEST2_VLP (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_TP_GPIO1_AO (MTK_PIN_NO(47) | 6) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SCP_SCL5 (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_PWM_VLP (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_CCU0_UTXD (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_SCP_ILDO_DTEST3_VLP (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_TP_GPIO2_AO (MTK_PIN_NO(48) | 6) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SCP_SDA5 (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_CCU0_URXD (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_SCP_ILDO_DTEST4_VLP (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_TP_GPIO3_AO (MTK_PIN_NO(49) | 6) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SCP_SCL6 (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_PWM_VLP (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_CCU0_URTS (MTK_PIN_NO(50) | 3) +#define PINMUX_GPIO50__FUNC_DSI_HSYNC (MTK_PIN_NO(50) | 4) +#define PINMUX_GPIO50__FUNC_TP_GPIO4_AO (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SCP_SDA6 (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_CCU0_UCTS (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_DSI1_HSYNC (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_TP_GPIO5_AO (MTK_PIN_NO(51) | 6) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SCP_SCL1 (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_TDM_DATA2 (MTK_PIN_NO(52) | 3) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SCP_SDA1 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_TDM_DATA3 (MTK_PIN_NO(53) | 3) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_TDM_MCK (MTK_PIN_NO(54) | 3) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_AUD_CLK_MISO (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_I2SOUT2_BCK (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_TDM_BCK (MTK_PIN_NO(55) | 3) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_I2SOUT2_LRCK (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_TDM_LRCK (MTK_PIN_NO(56) | 3) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_I2SOUT2_DO (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_TDM_DATA0 (MTK_PIN_NO(57) | 3) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_TDM_DATA1 (MTK_PIN_NO(58) | 3) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_I2SIN1_BCK (MTK_PIN_NO(59) | 3) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_KPCOL0 (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_TP_GPIO13_AO (MTK_PIN_NO(60) | 6) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_MCU_M_PMIC_POC_I (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_MCU_B_PMIC_POC_I (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_MFG_PMIC_POC_I (MTK_PIN_NO(63) | 1) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_PRE_UVLO (MTK_PIN_NO(64) | 1) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_DPM2PMIC (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_SRCLKENA1 (MTK_PIN_NO(65) | 2) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_WATCHDOG (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_SRCLKENA0 (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_RTC32K_CK (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_CMFLASH0 (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_DCXO_FPM_LPM (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_SPMI_M_SCL (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_SPMI_M_SDA (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_SPMI_P_SCL (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_SPMI_P_SDA (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_CMMCLK0 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_MD_INT4 (MTK_PIN_NO(79) | 2) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_CMMCLK1 (MTK_PIN_NO(80) | 1) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_SCP_SPI0_CK (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_SPI6_B_CLK (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_PWM_VLP (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_I2SOUT5_BCK (MTK_PIN_NO(81) | 4) +#define PINMUX_GPIO81__FUNC_TP_GPIO0_AO (MTK_PIN_NO(81) | 6) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_SCP_SPI0_CS (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_SPI6_B_CSB (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_I2SOUT5_LRCK (MTK_PIN_NO(82) | 4) +#define PINMUX_GPIO82__FUNC_TP_GPIO1_AO (MTK_PIN_NO(82) | 6) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_SCP_SPI0_MO (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_SPI6_B_MO (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_I2SOUT5_DATA0 (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_TP_GPIO2_AO (MTK_PIN_NO(83) | 6) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_SCP_SPI0_MI (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_SPI6_B_MI (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_I2SOUT5_DATA1 (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_TP_GPIO3_AO (MTK_PIN_NO(84) | 6) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_SCP_SPI1_CK (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_SPI7_B_CLK (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_I2SIN5_DATA0 (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_PWM_VLP (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_TP_GPIO4_AO (MTK_PIN_NO(85) | 6) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_SCP_SPI1_CS (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_SPI7_B_CSB (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_I2SIN5_DATA1 (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_TP_GPIO5_AO (MTK_PIN_NO(86) | 6) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_SCP_SPI1_MO (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_SPI7_B_MO (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_I2SIN5_BCK (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_TP_GPIO6_AO (MTK_PIN_NO(87) | 6) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_SCP_SPI1_MI (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_SPI7_B_MI (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_I2SIN5_LRCK (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_TP_GPIO7_AO (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_DSI_TE (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_DSI1_TE (MTK_PIN_NO(89) | 2) +#define PINMUX_GPIO89__FUNC_DBG_MON_B30 (MTK_PIN_NO(89) | 7) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_LCM_RST (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_LCM1_RST (MTK_PIN_NO(90) | 2) +#define PINMUX_GPIO90__FUNC_DBG_MON_B31 (MTK_PIN_NO(90) | 7) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_CMFLASH2 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_SF_D0 (MTK_PIN_NO(91) | 2) +#define PINMUX_GPIO91__FUNC_SRCLKENAI1 (MTK_PIN_NO(91) | 3) +#define PINMUX_GPIO91__FUNC_KPCOL2 (MTK_PIN_NO(91) | 5) +#define PINMUX_GPIO91__FUNC_TP_GPIO11_AO (MTK_PIN_NO(91) | 6) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_CMFLASH3 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_SF_D1 (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_DISP_PWM1 (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_TP_GPIO12_AO (MTK_PIN_NO(92) | 6) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_CMFLASH1 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_SF_D2 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_SRCLKENAI0 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_KPROW2 (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_TP_GPIO13_AO (MTK_PIN_NO(93) | 6) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_I2S_MCK1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_SF_D3 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_CLKM0_A (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_TP_GPIO14_AO (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_DBG_MON_B18 (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_I2SIN1_BCK (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_I2SIN4_BCK (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_SPI6_A_CLK (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_MD32_1_GPIO0 (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_CLKM1_A (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_TP_GPIO15_AO (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_DBG_MON_B19 (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_I2SIN1_LRCK (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_I2SIN4_LRCK (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_SPI6_A_CSB (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_MD32_2_GPIO0 (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_CLKM2_A (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_DBG_MON_B20 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_I2SIN1_DI_A (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_I2SIN4_DATA0 (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_SPI6_A_MO (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_MD32_3_GPIO0 (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_CLKM3_A (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_DBG_MON_B21 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_I2SOUT1_DO (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I2SOUT4_DATA0 (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_SPI6_A_MI (MTK_PIN_NO(98) | 3) +#define PINMUX_GPIO98__FUNC_DBG_MON_B22 (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_LCM2_RST (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_SPU0_SCL (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_DBG_MON_B24 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_DSI2_TE (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_SPU0_SDA (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_DBG_MON_B25 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_SCL10 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_SF_CS (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_I2SIN5_DATA2 (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_SCP_SCL_OIS (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_TP_GPIO10_AO (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_DBG_MON_B28 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_SDA10 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_SF_CK (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_SCP_DMIC1_DAT (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_I2SIN5_DATA3 (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_SCP_SDA_OIS (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_TP_GPIO11_AO (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DBG_MON_B29 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_DISP_PWM (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_DSI1_TE (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_I2S_MCK0 (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_DBG_MON_B23 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SCL6 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_SPU1_SCL (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_I2S_MCK1 (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_IDDIG_2P (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_DBG_MON_B26 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SDA6 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_SPU1_SDA (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_DISP_PWM2 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_VBUSVALID_2P (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_I2S_MCK2 (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_VBUSVALID_3P (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_DBG_MON_B27 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SCP_SPI3_CK (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_SPI3_B_CLK (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_MD_UTXD0 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_CONN_BG_GPS_MCU_UART0_TXD (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_TP_GPIO6_AO (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_DBG_MON_B0 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_SCP_SPI3_CS (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_SPI3_B_CSB (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_MD_URXD0 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_TP_URXD1_VLP (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_CONN_BG_GPS_MCU_UART0_RXD (MTK_PIN_NO(107) | 5) +#define PINMUX_GPIO107__FUNC_TP_GPIO7_AO (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_DBG_MON_B1 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_SCP_SPI3_MO (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_SPI3_B_MO (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_MD_UTXD1 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_MD32PCM_UTXD_AO_VLP (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_CONN_BG_GPS_MCU_UART1_TXD (MTK_PIN_NO(108) | 5) +#define PINMUX_GPIO108__FUNC_TP_GPIO8_AO (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_DBG_MON_B2 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_SCP_SPI3_MI (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_SPI3_B_MI (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_MD_URXD1 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_MD32PCM_URXD_AO_VLP (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_CONN_BG_GPS_MCU_UART1_RXD (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_TP_GPIO9_AO (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DBG_MON_B3 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_SPI1_CLK (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_PWM_0 (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_MD_UCTS0 (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_TP_UCTS1_VLP (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_SPU0_GPIO_O (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_DBG_MON_B4 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_SPI1_CSB (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_PWM_1 (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_MD_URTS0 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_TP_URTS1_VLP (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_SPU0_GPIO_I (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_DBG_MON_B5 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_SPI1_MO (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_PWM_2 (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_MD_UCTS1 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_SPU1_GPIO_O (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_DBG_MON_B6 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_SPI1_MI (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_PWM_3 (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_MD_URTS1 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_SPU1_GPIO_I (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_DBG_MON_B7 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_SPI0_SPU_CLK (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SPI4_A_CLK (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_CONN_BG_GPS_MCU_DBG_UART_TXD (MTK_PIN_NO(114) | 5) +#define PINMUX_GPIO114__FUNC_DBG_MON_B8 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_SPI0_SPU_CSB (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SPI4_A_CSB (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_DBG_MON_B9 (MTK_PIN_NO(115) | 7) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_SPI0_SPU_MO (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_SPI4_A_MO (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_LCM1_RST (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_DBG_MON_B10 (MTK_PIN_NO(116) | 7) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_SPI0_SPU_MI (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_SPI4_A_MI (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_DSI1_TE (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_DBG_MON_B11 (MTK_PIN_NO(117) | 7) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_SPI5_CLK (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_USB_DRVVBUS (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_DP_TX_HPD (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_AD_ILDO_DTEST0 (MTK_PIN_NO(118) | 4) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_SPI5_CSB (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_VBUSVALID (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DP_OC_EN (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_AD_ILDO_DTEST1 (MTK_PIN_NO(119) | 4) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_SPI5_MO (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_LCM2_RST (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_DP_RAUX_SBU1 (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_AD_ILDO_DTEST2 (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_IDDIG_3P (MTK_PIN_NO(120) | 6) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SPI5_MI (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_DSI2_TE (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DP_RAUX_SBU2 (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_AD_ILDO_DTEST3 (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_USB_DRVVBUS_3P (MTK_PIN_NO(121) | 6) +#define PINMUX_GPIO121__FUNC_DBG_MON_B17 (MTK_PIN_NO(121) | 7) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_AP_GOOD (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(122) | 2) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_SCL3 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_I2SIN2_LRCK (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_TP_UTXD_MD_VCORE (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_SDA3 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_TP_URXD_MD_VCORE (MTK_PIN_NO(124) | 6) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_MSDC1_CLK (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_HFRP_JTAG0_TCK (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_UDI_TCK (MTK_PIN_NO(125) | 4) +#define PINMUX_GPIO125__FUNC_CONN_BGF_DSP_L1_JCK (MTK_PIN_NO(125) | 5) +#define PINMUX_GPIO125__FUNC_SCP_JTAG_LITTLE_TCK_VLP (MTK_PIN_NO(125) | 6) +#define PINMUX_GPIO125__FUNC_JTCK2_SEL1 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_MSDC1_CMD (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_HFRP_JTAG0_TMS (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_UDI_TMS (MTK_PIN_NO(126) | 4) +#define PINMUX_GPIO126__FUNC_CONN_BGF_DSP_L1_JMS (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_SCP_JTAG_LITTLE_TMS_VLP (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_JTMS2_SEL1 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_MSDC1_DAT0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_HFRP_JTAG0_TDI (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_UDI_TDI_0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_CONN_BGF_DSP_L1_JDI (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_SCP_JTAG_LITTLE_TDI_VLP (MTK_PIN_NO(127) | 6) +#define PINMUX_GPIO127__FUNC_JTDI2_SEL1 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_MSDC1_DAT1 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_HFRP_JTAG0_TDO (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_UDI_TDO_0 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_CONN_BGF_DSP_L1_JDO (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_SCP_JTAG_LITTLE_TDO_VLP (MTK_PIN_NO(128) | 6) +#define PINMUX_GPIO128__FUNC_JTDO2_SEL1 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_MSDC1_DAT2 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_DSI2_HSYNC (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_HFRP_JTAG0_TRSTN (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_UDI_NTRST (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_JTAG_LITTLE_TRSTN_VLP (MTK_PIN_NO(129) | 6) +#define PINMUX_GPIO129__FUNC_JTRSTN2_SEL1 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_MSDC1_DAT3 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_DSI3_HSYNC (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_CONN_BGF_DSP_L1_JINTP (MTK_PIN_NO(130) | 5) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_CLKM0_A (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_CONN_BGF_DSP_L5_JDI (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_TSFDC_SCK (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI_VCORE (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_CLKM1_B (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_CONN_BGF_DSP_L5_JMS (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_TSFDC_SDI (MTK_PIN_NO(132) | 6) +#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS_VCORE (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_CONN_BGF_DSP_L5_JDO (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_TSFDC_SCF (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TDO_VCORE (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(134) | 2) +#define PINMUX_GPIO134__FUNC_TSFDC_26M (MTK_PIN_NO(134) | 6) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_CONN_BGF_DSP_L5_JCK (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_TSFDC_SDO (MTK_PIN_NO(135) | 6) +#define PINMUX_GPIO135__FUNC_SCP_JTAG0_TCK_VCORE (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_CONN_BGF_DSP_L5_JINTP (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_TSFDC_FOUT (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_SCP_JTAG0_TRSTN_VCORE (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_BPI_BUS16 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_DBG_MON_A0 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_BPI_BUS17 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_PCM0_LRCK (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SPM_JTAG_TCK_VCORE (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_DBG_MON_A1 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_BPI_BUS18 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_MD_GPS_BLANK (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_SPM_JTAG_TMS_VCORE (MTK_PIN_NO(139) | 6) +#define PINMUX_GPIO139__FUNC_DBG_MON_A2 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_BPI_BUS19 (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_MD_URXD1_CONN (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_SPM_JTAG_TDO_VCORE (MTK_PIN_NO(140) | 6) +#define PINMUX_GPIO140__FUNC_DBG_MON_A3 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_BPI_BUS20 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_SPM_JTAG_TDI_VCORE (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_DBG_MON_A4 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_BPI_BUS21 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_SSPM_JTAG_TRSTN_VCORE (MTK_PIN_NO(142) | 6) +#define PINMUX_GPIO142__FUNC_DBG_MON_A5 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_MIPI3_D_SCLK (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_BPI_BUS22 (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_TP_UTXD_GNSS_VLP (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_SSPM_JTAG_TCK_VCORE (MTK_PIN_NO(143) | 6) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_MIPI3_D_SDATA (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_BPI_BUS23 (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_TP_URXD_GNSS_VLP (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_MD_URXD1_CONN (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_SSPM_JTAG_TMS_VCORE (MTK_PIN_NO(144) | 6) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_BPI_BUS0 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_PCIE_WAKEN_1P (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_SSPM_JTAG_TDO_VCORE (MTK_PIN_NO(145) | 6) +#define PINMUX_GPIO145__FUNC_DBG_MON_A10 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_BPI_BUS1 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_PCIE_PERSTN_1P (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_SSPM_JTAG_TDI_VCORE (MTK_PIN_NO(146) | 6) +#define PINMUX_GPIO146__FUNC_DBG_MON_A11 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_BPI_BUS2 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_PCIE_CLKREQN_1P (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_SCP_JTAG_LITTLE_TRSTN_VCORE (MTK_PIN_NO(147) | 6) +#define PINMUX_GPIO147__FUNC_DBG_MON_A12 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_BPI_BUS3 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_AUD_DAC_26M_CLK (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_TP_UTXD_MD_VLP (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_TP_GPIO0_AO (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_SCP_JTAG_LITTLE_TCK_VCORE (MTK_PIN_NO(148) | 6) +#define PINMUX_GPIO148__FUNC_DBG_MON_A13 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_BPI_BUS4 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_TP_URXD_MD_VLP (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_TP_GPIO1_AO (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_SCP_JTAG_LITTLE_TMS_VCORE (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_DBG_MON_A14 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_BPI_BUS5 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_GPS_PPS0 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_TP_GPIO2_AO (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_SCP_JTAG_LITTLE_TDO_VCORE (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_DBG_MON_A15 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_BPI_BUS6 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_GPS_PPS1 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_TP_GPIO3_AO (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_SCP_JTAG_LITTLE_TDI_VCORE (MTK_PIN_NO(151) | 6) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_BPI_BUS7 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_EDP_TX_HPD (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_AGPS_SYNC (MTK_PIN_NO(152) | 5) +#define PINMUX_GPIO152__FUNC_SSPM_UTXD_AO_VCORE (MTK_PIN_NO(152) | 6) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_TP_URTS1_VCORE (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_DBG_MON_A8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_DIGRF_IRQ (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_TP_UCTS1_VCORE (MTK_PIN_NO(154) | 6) +#define PINMUX_GPIO154__FUNC_DBG_MON_A9 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_MIPI_M_SCLK (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_UCTS2 (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_TP_UTXD_CONSYS_VCORE (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_A6 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_MIPI_M_SDATA (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_URTS2 (MTK_PIN_NO(156) | 4) +#define PINMUX_GPIO156__FUNC_TP_URXD_CONSYS_VCORE (MTK_PIN_NO(156) | 6) +#define PINMUX_GPIO156__FUNC_DBG_MON_A7 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_BPI_BUS8 (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_UTXD2 (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_CLKM0_A (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_SSPM_URXD_AO_VCORE (MTK_PIN_NO(157) | 6) +#define PINMUX_GPIO157__FUNC_DBG_MON_A16 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_BPI_BUS9 (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_URXD2 (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_CLKM1_A (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_TP_UTXD1_VCORE (MTK_PIN_NO(158) | 6) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_BPI_BUS10 (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_MD_INT0 (MTK_PIN_NO(159) | 2) +#define PINMUX_GPIO159__FUNC_SRCLKENAI1 (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_CLKM2_A (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_TP_URXD1_VCORE (MTK_PIN_NO(159) | 6) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_UTXD0 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_MD_UTXD1 (MTK_PIN_NO(160) | 2) +#define PINMUX_GPIO160__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(160) | 5) +#define PINMUX_GPIO160__FUNC_CONN_BG_GPS_MCU_DBG_UART_TXD (MTK_PIN_NO(160) | 6) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_URXD0 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_MD_URXD1 (MTK_PIN_NO(161) | 2) +#define PINMUX_GPIO161__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(161) | 5) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_UTXD1 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_MD_UTXD0 (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_TP_UTXD1_VLP (MTK_PIN_NO(162) | 3) +#define PINMUX_GPIO162__FUNC_ADSP_UTXD0 (MTK_PIN_NO(162) | 4) +#define PINMUX_GPIO162__FUNC_SSPM_UTXD_AO_VLP (MTK_PIN_NO(162) | 5) +#define PINMUX_GPIO162__FUNC_HFRP_UTXD1 (MTK_PIN_NO(162) | 6) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_URXD1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_MD_URXD0 (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_TP_URXD1_VLP (MTK_PIN_NO(163) | 3) +#define PINMUX_GPIO163__FUNC_ADSP_URXD0 (MTK_PIN_NO(163) | 4) +#define PINMUX_GPIO163__FUNC_SSPM_URXD_AO_VLP (MTK_PIN_NO(163) | 5) +#define PINMUX_GPIO163__FUNC_HFRP_URXD1 (MTK_PIN_NO(163) | 6) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_SCP_SCL0 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_TP_GPIO0_AO (MTK_PIN_NO(164) | 6) +#define PINMUX_GPIO164__FUNC_DBG_MON_A22 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_SCP_SDA0 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_TP_GPIO1_AO (MTK_PIN_NO(165) | 6) +#define PINMUX_GPIO165__FUNC_DBG_MON_A23 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_SCP_SCL2 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_TP_GPIO2_AO (MTK_PIN_NO(166) | 6) +#define PINMUX_GPIO166__FUNC_DBG_MON_A24 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_SCP_SDA2 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_TP_GPIO3_AO (MTK_PIN_NO(167) | 6) +#define PINMUX_GPIO167__FUNC_DBG_MON_A25 (MTK_PIN_NO(167) | 7) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_SCP_SPI2_CK (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_SPI2_B_CLK (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_PWM_VLP (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_SCP_SCL2 (MTK_PIN_NO(168) | 4) +#define PINMUX_GPIO168__FUNC_DBG_MON_A26 (MTK_PIN_NO(168) | 7) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_SCP_SPI2_CS (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_SPI2_B_CSB (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_DBG_MON_A27 (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_SCP_SPI2_MO (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_SPI2_B_MO (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_SCP_SDA2 (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_DBG_MON_A28 (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_SCP_SPI2_MI (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_SPI2_B_MI (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_DBG_MON_A29 (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(172) | 1) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_CMFLASH3 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_PWM_3 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_CLKM1_A (MTK_PIN_NO(173) | 4) +#define PINMUX_GPIO173__FUNC_DBG_MON_A31 (MTK_PIN_NO(173) | 7) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CMFLASH0 (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_PWM_0 (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_VBUSVALID_1P (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_MD32_2_RXD (MTK_PIN_NO(174) | 4) +#define PINMUX_GPIO174__FUNC_DISP_PWM3 (MTK_PIN_NO(174) | 5) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CMFLASH1 (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_PWM_1 (MTK_PIN_NO(175) | 2) +#define PINMUX_GPIO175__FUNC_EDP_TX_HPD (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_MD32_2_TXD (MTK_PIN_NO(175) | 4) +#define PINMUX_GPIO175__FUNC_DISP_PWM4 (MTK_PIN_NO(175) | 5) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_SCL5 (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_LCM3_RST (MTK_PIN_NO(176) | 2) +#define PINMUX_GPIO176__FUNC_MD_URXD1_CONN (MTK_PIN_NO(176) | 4) +#define PINMUX_GPIO176__FUNC_TP_UTXD_GNSS_VCORE (MTK_PIN_NO(176) | 6) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_SDA5 (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_DSI3_TE (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_MD_UTXD1_CONN (MTK_PIN_NO(177) | 4) +#define PINMUX_GPIO177__FUNC_TP_URXD_GNSS_VCORE (MTK_PIN_NO(177) | 6) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_DMIC_CLK (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_SCP_DMIC_CLK (MTK_PIN_NO(178) | 2) +#define PINMUX_GPIO178__FUNC_SRCLKENAI0 (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_CLKM2_B (MTK_PIN_NO(178) | 4) +#define PINMUX_GPIO178__FUNC_TP_GPIO7_AO (MTK_PIN_NO(178) | 5) +#define PINMUX_GPIO178__FUNC_SPU1_UTX (MTK_PIN_NO(178) | 6) +#define PINMUX_GPIO178__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(178) | 7) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_DMIC_DAT (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_SCP_DMIC_DAT (MTK_PIN_NO(179) | 2) +#define PINMUX_GPIO179__FUNC_SRCLKENAI1 (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_CLKM3_B (MTK_PIN_NO(179) | 4) +#define PINMUX_GPIO179__FUNC_TP_GPIO8_AO (MTK_PIN_NO(179) | 5) +#define PINMUX_GPIO179__FUNC_SPU1_URX (MTK_PIN_NO(179) | 6) +#define PINMUX_GPIO179__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(179) | 7) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_IDDIG_1P (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_CMVREF0 (MTK_PIN_NO(180) | 2) +#define PINMUX_GPIO180__FUNC_GPS_PPS1 (MTK_PIN_NO(180) | 3) +#define PINMUX_GPIO180__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(180) | 4) +#define PINMUX_GPIO180__FUNC_DISP_PWM1 (MTK_PIN_NO(180) | 5) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_CMVREF1 (MTK_PIN_NO(181) | 2) +#define PINMUX_GPIO181__FUNC_MFG_EB_JTAG_TRSTN (MTK_PIN_NO(181) | 3) +#define PINMUX_GPIO181__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(181) | 4) +#define PINMUX_GPIO181__FUNC_HFRP_JTAG1_TRSTN (MTK_PIN_NO(181) | 5) +#define PINMUX_GPIO181__FUNC_SPU1_NTRST (MTK_PIN_NO(181) | 6) +#define PINMUX_GPIO181__FUNC_CONN_BG_GPS_MCU_TRST_B (MTK_PIN_NO(181) | 7) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_SCL11 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_CMVREF2 (MTK_PIN_NO(182) | 2) +#define PINMUX_GPIO182__FUNC_MFG_EB_JTAG_TCK (MTK_PIN_NO(182) | 3) +#define PINMUX_GPIO182__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(182) | 4) +#define PINMUX_GPIO182__FUNC_HFRP_JTAG1_TCK (MTK_PIN_NO(182) | 5) +#define PINMUX_GPIO182__FUNC_SPU1_TCK (MTK_PIN_NO(182) | 6) +#define PINMUX_GPIO182__FUNC_CONN_BG_GPS_MCU_TCK (MTK_PIN_NO(182) | 7) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_SDA11 (MTK_PIN_NO(183) | 1) +#define PINMUX_GPIO183__FUNC_CMVREF3 (MTK_PIN_NO(183) | 2) +#define PINMUX_GPIO183__FUNC_MFG_EB_JTAG_TMS (MTK_PIN_NO(183) | 3) +#define PINMUX_GPIO183__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(183) | 4) +#define PINMUX_GPIO183__FUNC_HFRP_JTAG1_TMS (MTK_PIN_NO(183) | 5) +#define PINMUX_GPIO183__FUNC_SPU1_TMS (MTK_PIN_NO(183) | 6) +#define PINMUX_GPIO183__FUNC_CONN_BG_GPS_MCU_TMS (MTK_PIN_NO(183) | 7) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_SCL12 (MTK_PIN_NO(184) | 1) +#define PINMUX_GPIO184__FUNC_CMVREF4 (MTK_PIN_NO(184) | 2) +#define PINMUX_GPIO184__FUNC_MFG_EB_JTAG_TDO (MTK_PIN_NO(184) | 3) +#define PINMUX_GPIO184__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(184) | 4) +#define PINMUX_GPIO184__FUNC_HFRP_JTAG1_TDO (MTK_PIN_NO(184) | 5) +#define PINMUX_GPIO184__FUNC_SPU1_TDO (MTK_PIN_NO(184) | 6) +#define PINMUX_GPIO184__FUNC_CONN_BG_GPS_MCU_TDO (MTK_PIN_NO(184) | 7) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_SDA12 (MTK_PIN_NO(185) | 1) +#define PINMUX_GPIO185__FUNC_CMVREF5 (MTK_PIN_NO(185) | 2) +#define PINMUX_GPIO185__FUNC_MFG_EB_JTAG_TDI (MTK_PIN_NO(185) | 3) +#define PINMUX_GPIO185__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(185) | 4) +#define PINMUX_GPIO185__FUNC_HFRP_JTAG1_TDI (MTK_PIN_NO(185) | 5) +#define PINMUX_GPIO185__FUNC_SPU1_TDI (MTK_PIN_NO(185) | 6) +#define PINMUX_GPIO185__FUNC_CONN_BG_GPS_MCU_TDI (MTK_PIN_NO(185) | 7) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_MD_GPS_L1_BLANK (MTK_PIN_NO(186) | 1) +#define PINMUX_GPIO186__FUNC_PMSR_SMAP (MTK_PIN_NO(186) | 2) +#define PINMUX_GPIO186__FUNC_TP_GPIO2_AO (MTK_PIN_NO(186) | 3) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_MD_GPS_L5_BLANK (MTK_PIN_NO(187) | 1) +#define PINMUX_GPIO187__FUNC_TP_GPIO4_AO (MTK_PIN_NO(187) | 3) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_SCL2 (MTK_PIN_NO(188) | 1) +#define PINMUX_GPIO188__FUNC_SCP_SCL8 (MTK_PIN_NO(188) | 2) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_SDA2 (MTK_PIN_NO(189) | 1) +#define PINMUX_GPIO189__FUNC_SCP_SDA8 (MTK_PIN_NO(189) | 2) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_SCL4 (MTK_PIN_NO(190) | 1) +#define PINMUX_GPIO190__FUNC_SCP_SCL9 (MTK_PIN_NO(190) | 2) +#define PINMUX_GPIO190__FUNC_UDI_TDI_6 (MTK_PIN_NO(190) | 6) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_SDA4 (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_SCP_SDA9 (MTK_PIN_NO(191) | 2) +#define PINMUX_GPIO191__FUNC_UDI_TDI_7 (MTK_PIN_NO(191) | 6) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_CMMCLK2 (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_MD32_3_RXD (MTK_PIN_NO(192) | 4) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_CLKM0_B (MTK_PIN_NO(193) | 3) +#define PINMUX_GPIO193__FUNC_MD32_3_TXD (MTK_PIN_NO(193) | 4) +#define PINMUX_GPIO193__FUNC_UDI_TDO_7 (MTK_PIN_NO(193) | 6) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_SCL7 (MTK_PIN_NO(194) | 1) +#define PINMUX_GPIO194__FUNC_MD32_3_GPIO0 (MTK_PIN_NO(194) | 2) +#define PINMUX_GPIO194__FUNC_CLKM2_B (MTK_PIN_NO(194) | 3) +#define PINMUX_GPIO194__FUNC_UDI_TDI_2 (MTK_PIN_NO(194) | 6) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_SDA7 (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_CLKM3_B (MTK_PIN_NO(195) | 3) +#define PINMUX_GPIO195__FUNC_UDI_TDI_3 (MTK_PIN_NO(195) | 6) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_CMMCLK3 (MTK_PIN_NO(196) | 1) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_CLKM1_B (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_UDI_TDI_1 (MTK_PIN_NO(197) | 6) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_SCL8 (MTK_PIN_NO(198) | 1) +#define PINMUX_GPIO198__FUNC_UDI_TDI_4 (MTK_PIN_NO(198) | 6) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_SDA8 (MTK_PIN_NO(199) | 1) +#define PINMUX_GPIO199__FUNC_UDI_TDI_5 (MTK_PIN_NO(199) | 6) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_SCL1 (MTK_PIN_NO(200) | 1) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_SDA1 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_TSFDC_BG_COMP (MTK_PIN_NO(201) | 7) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_SCL9 (MTK_PIN_NO(202) | 1) +#define PINMUX_GPIO202__FUNC_SCP_SCL7 (MTK_PIN_NO(202) | 2) +#define PINMUX_GPIO202__FUNC_TP_GPIO15_AO (MTK_PIN_NO(202) | 6) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define PINMUX_GPIO203__FUNC_SDA9 (MTK_PIN_NO(203) | 1) +#define PINMUX_GPIO203__FUNC_SCP_SDA7 (MTK_PIN_NO(203) | 2) +#define PINMUX_GPIO203__FUNC_TP_GPIO9_AO (MTK_PIN_NO(203) | 6) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define PINMUX_GPIO204__FUNC_SCL13 (MTK_PIN_NO(204) | 1) +#define PINMUX_GPIO204__FUNC_CMVREF6 (MTK_PIN_NO(204) | 2) +#define PINMUX_GPIO204__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(204) | 3) +#define PINMUX_GPIO204__FUNC_CLKM2_B (MTK_PIN_NO(204) | 5) +#define PINMUX_GPIO204__FUNC_TP_GPIO12_AO (MTK_PIN_NO(204) | 6) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define PINMUX_GPIO205__FUNC_SDA13 (MTK_PIN_NO(205) | 1) +#define PINMUX_GPIO205__FUNC_CMVREF7 (MTK_PIN_NO(205) | 2) +#define PINMUX_GPIO205__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(205) | 3) +#define PINMUX_GPIO205__FUNC_CLKM3_B (MTK_PIN_NO(205) | 5) +#define PINMUX_GPIO205__FUNC_TP_GPIO13_AO (MTK_PIN_NO(205) | 6) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define PINMUX_GPIO206__FUNC_MD32_2_GPIO0 (MTK_PIN_NO(206) | 2) +#define PINMUX_GPIO206__FUNC_VBUSVALID (MTK_PIN_NO(206) | 5) +#define PINMUX_GPIO206__FUNC_UDI_TDO_3 (MTK_PIN_NO(206) | 6) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define PINMUX_GPIO207__FUNC_PCIE_WAKEN_2P (MTK_PIN_NO(207) | 1) +#define PINMUX_GPIO207__FUNC_PMSR_SMAP_MAX (MTK_PIN_NO(207) | 2) +#define PINMUX_GPIO207__FUNC_FMI2S_A_BCK (MTK_PIN_NO(207) | 4) +#define PINMUX_GPIO207__FUNC_UDI_TDO_4 (MTK_PIN_NO(207) | 6) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define PINMUX_GPIO208__FUNC_PCIE_CLKREQN_2P (MTK_PIN_NO(208) | 1) +#define PINMUX_GPIO208__FUNC_PMSR_SMAP_MAX_W (MTK_PIN_NO(208) | 2) +#define PINMUX_GPIO208__FUNC_FMI2S_A_LRCK (MTK_PIN_NO(208) | 4) +#define PINMUX_GPIO208__FUNC_CLKM0_B (MTK_PIN_NO(208) | 5) +#define PINMUX_GPIO208__FUNC_UDI_TDO_5 (MTK_PIN_NO(208) | 6) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define PINMUX_GPIO209__FUNC_PCIE_PERSTN_2P (MTK_PIN_NO(209) | 1) +#define PINMUX_GPIO209__FUNC_PMSR_SMAP (MTK_PIN_NO(209) | 2) +#define PINMUX_GPIO209__FUNC_FMI2S_A_DI (MTK_PIN_NO(209) | 4) +#define PINMUX_GPIO209__FUNC_CLKM1_B (MTK_PIN_NO(209) | 5) +#define PINMUX_GPIO209__FUNC_UDI_TDO_6 (MTK_PIN_NO(209) | 6) + +#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define PINMUX_GPIO210__FUNC_CMMCLK4 (MTK_PIN_NO(210) | 1) + +#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define PINMUX_GPIO211__FUNC_CMMCLK5 (MTK_PIN_NO(211) | 1) +#define PINMUX_GPIO211__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(211) | 2) + +#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define PINMUX_GPIO212__FUNC_CMMCLK6 (MTK_PIN_NO(212) | 1) +#define PINMUX_GPIO212__FUNC_TP_GPIO10_AO (MTK_PIN_NO(212) | 2) +#define PINMUX_GPIO212__FUNC_IDDIG (MTK_PIN_NO(212) | 5) +#define PINMUX_GPIO212__FUNC_UDI_TDO_1 (MTK_PIN_NO(212) | 6) + +#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define PINMUX_GPIO213__FUNC_CMMCLK7 (MTK_PIN_NO(213) | 1) +#define PINMUX_GPIO213__FUNC_TP_GPIO11_AO (MTK_PIN_NO(213) | 2) +#define PINMUX_GPIO213__FUNC_USB_DRVVBUS (MTK_PIN_NO(213) | 5) +#define PINMUX_GPIO213__FUNC_UDI_TDO_2 (MTK_PIN_NO(213) | 6) + +#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define PINMUX_GPIO214__FUNC_SCP_SCL3 (MTK_PIN_NO(214) | 1) +#define PINMUX_GPIO214__FUNC_SDA14_E1 (MTK_PIN_NO(214) | 2) +#define PINMUX_GPIO214__FUNC_SCL14_E2 (MTK_PIN_NO(214) | 2) +#define PINMUX_GPIO214__FUNC_GBE1_MDC (MTK_PIN_NO(214) | 6) +#define PINMUX_GPIO214__FUNC_GBE0_MDC (MTK_PIN_NO(214) | 7) + +#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define PINMUX_GPIO215__FUNC_SCP_SDA3 (MTK_PIN_NO(215) | 1) +#define PINMUX_GPIO215__FUNC_SCL14_E1 (MTK_PIN_NO(215) | 2) +#define PINMUX_GPIO215__FUNC_SDA14_E2 (MTK_PIN_NO(215) | 2) +#define PINMUX_GPIO215__FUNC_GBE1_MDIO (MTK_PIN_NO(215) | 6) +#define PINMUX_GPIO215__FUNC_GBE0_MDIO (MTK_PIN_NO(215) | 7) + +#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define PINMUX_GPIO216__FUNC_GPS_PPS0 (MTK_PIN_NO(216) | 1) + +#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define PINMUX_GPIO217__FUNC_KPROW0 (MTK_PIN_NO(217) | 1) +#define PINMUX_GPIO217__FUNC_TP_GPIO12_AO (MTK_PIN_NO(217) | 6) + +#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define PINMUX_GPIO218__FUNC_KPROW1 (MTK_PIN_NO(218) | 1) +#define PINMUX_GPIO218__FUNC_SPI0_WP (MTK_PIN_NO(218) | 2) +#define PINMUX_GPIO218__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(218) | 3) +#define PINMUX_GPIO218__FUNC_GPS_L5_ELNA_EN (MTK_PIN_NO(218) | 5) +#define PINMUX_GPIO218__FUNC_TP_GPIO14_AO (MTK_PIN_NO(218) | 6) + +#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define PINMUX_GPIO219__FUNC_KPCOL1 (MTK_PIN_NO(219) | 1) +#define PINMUX_GPIO219__FUNC_SPI0_HOLD (MTK_PIN_NO(219) | 2) +#define PINMUX_GPIO219__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(219) | 3) +#define PINMUX_GPIO219__FUNC_SPMI_M_TRIG_FLAG (MTK_PIN_NO(219) | 4) +#define PINMUX_GPIO219__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(219) | 5) +#define PINMUX_GPIO219__FUNC_SPM_JTAG_TRSTN_VLP (MTK_PIN_NO(219) | 6) +#define PINMUX_GPIO219__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(219) | 7) + +#define PINMUX_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +#define PINMUX_GPIO220__FUNC_SPI0_CLK (MTK_PIN_NO(220) | 1) +#define PINMUX_GPIO220__FUNC_SPM_JTAG_TCK_VLP (MTK_PIN_NO(220) | 6) +#define PINMUX_GPIO220__FUNC_JTCK_SEL1 (MTK_PIN_NO(220) | 7) + +#define PINMUX_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +#define PINMUX_GPIO221__FUNC_SPI0_CSB (MTK_PIN_NO(221) | 1) +#define PINMUX_GPIO221__FUNC_SPM_JTAG_TMS_VLP (MTK_PIN_NO(221) | 6) +#define PINMUX_GPIO221__FUNC_JTMS_SEL1 (MTK_PIN_NO(221) | 7) + +#define PINMUX_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +#define PINMUX_GPIO222__FUNC_SPI0_MO (MTK_PIN_NO(222) | 1) +#define PINMUX_GPIO222__FUNC_SCP_SCL7 (MTK_PIN_NO(222) | 2) +#define PINMUX_GPIO222__FUNC_SPM_JTAG_TDO_VLP (MTK_PIN_NO(222) | 6) +#define PINMUX_GPIO222__FUNC_JTDO_SEL1 (MTK_PIN_NO(222) | 7) + +#define PINMUX_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +#define PINMUX_GPIO223__FUNC_SPI0_MI (MTK_PIN_NO(223) | 1) +#define PINMUX_GPIO223__FUNC_SCP_SDA7 (MTK_PIN_NO(223) | 2) +#define PINMUX_GPIO223__FUNC_SPM_JTAG_TDI_VLP (MTK_PIN_NO(223) | 6) +#define PINMUX_GPIO223__FUNC_JTDI_SEL1 (MTK_PIN_NO(223) | 7) + +#define PINMUX_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +#define PINMUX_GPIO224__FUNC_MSDC2_CLK (MTK_PIN_NO(224) | 1) +#define PINMUX_GPIO224__FUNC_DMIC2_CLK (MTK_PIN_NO(224) | 2) +#define PINMUX_GPIO224__FUNC_GBE0_AUX_PPS0 (MTK_PIN_NO(224) | 3) +#define PINMUX_GPIO224__FUNC_GBE0_TXER (MTK_PIN_NO(224) | 4) +#define PINMUX_GPIO224__FUNC_GBE1_TXER (MTK_PIN_NO(224) | 5) +#define PINMUX_GPIO224__FUNC_GBE1_AUX_PPS0 (MTK_PIN_NO(224) | 6) +#define PINMUX_GPIO224__FUNC_MD32_1_TXD (MTK_PIN_NO(224) | 7) + +#define PINMUX_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +#define PINMUX_GPIO225__FUNC_MSDC2_CMD (MTK_PIN_NO(225) | 1) +#define PINMUX_GPIO225__FUNC_DMIC2_DAT (MTK_PIN_NO(225) | 2) +#define PINMUX_GPIO225__FUNC_GBE0_AUX_PPS1 (MTK_PIN_NO(225) | 3) +#define PINMUX_GPIO225__FUNC_GBE0_RXER (MTK_PIN_NO(225) | 4) +#define PINMUX_GPIO225__FUNC_GBE1_RXER (MTK_PIN_NO(225) | 5) +#define PINMUX_GPIO225__FUNC_GBE1_AUX_PPS1 (MTK_PIN_NO(225) | 6) +#define PINMUX_GPIO225__FUNC_MD32_1_RXD (MTK_PIN_NO(225) | 7) + +#define PINMUX_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +#define PINMUX_GPIO226__FUNC_MSDC2_DAT0 (MTK_PIN_NO(226) | 1) +#define PINMUX_GPIO226__FUNC_I2SIN3_BCK (MTK_PIN_NO(226) | 2) +#define PINMUX_GPIO226__FUNC_GBE0_AUX_PPS2 (MTK_PIN_NO(226) | 3) +#define PINMUX_GPIO226__FUNC_GBE0_COL (MTK_PIN_NO(226) | 4) +#define PINMUX_GPIO226__FUNC_GBE1_COL (MTK_PIN_NO(226) | 5) +#define PINMUX_GPIO226__FUNC_GBE1_AUX_PPS2 (MTK_PIN_NO(226) | 6) +#define PINMUX_GPIO226__FUNC_GBE1_MDC (MTK_PIN_NO(226) | 7) + +#define PINMUX_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +#define PINMUX_GPIO227__FUNC_MSDC2_DAT1 (MTK_PIN_NO(227) | 1) +#define PINMUX_GPIO227__FUNC_I2SIN3_LRCK (MTK_PIN_NO(227) | 2) +#define PINMUX_GPIO227__FUNC_GBE0_AUX_PPS3 (MTK_PIN_NO(227) | 3) +#define PINMUX_GPIO227__FUNC_GBE0_INTR (MTK_PIN_NO(227) | 4) +#define PINMUX_GPIO227__FUNC_GBE1_INTR (MTK_PIN_NO(227) | 5) +#define PINMUX_GPIO227__FUNC_GBE1_AUX_PPS3 (MTK_PIN_NO(227) | 6) +#define PINMUX_GPIO227__FUNC_GBE1_MDIO (MTK_PIN_NO(227) | 7) + +#define PINMUX_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +#define PINMUX_GPIO228__FUNC_MSDC2_DAT2 (MTK_PIN_NO(228) | 1) +#define PINMUX_GPIO228__FUNC_I2SIN3_DI (MTK_PIN_NO(228) | 2) +#define PINMUX_GPIO228__FUNC_GBE0_MDC (MTK_PIN_NO(228) | 3) +#define PINMUX_GPIO228__FUNC_GBE1_MDC (MTK_PIN_NO(228) | 4) +#define PINMUX_GPIO228__FUNC_CONN_BG_GPS_MCU_AICE_TCKC (MTK_PIN_NO(228) | 5) + +#define PINMUX_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +#define PINMUX_GPIO229__FUNC_MSDC2_DAT3 (MTK_PIN_NO(229) | 1) +#define PINMUX_GPIO229__FUNC_I2SOUT3_DO (MTK_PIN_NO(229) | 2) +#define PINMUX_GPIO229__FUNC_GBE0_MDIO (MTK_PIN_NO(229) | 3) +#define PINMUX_GPIO229__FUNC_GBE1_MDIO (MTK_PIN_NO(229) | 4) +#define PINMUX_GPIO229__FUNC_CONN_BG_GPS_MCU_AICE_TMSC (MTK_PIN_NO(229) | 5) +#define PINMUX_GPIO229__FUNC_AVB_CLK2 (MTK_PIN_NO(229) | 7) + +#define PINMUX_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +#define PINMUX_GPIO230__FUNC_CONN_TOP_CLK (MTK_PIN_NO(230) | 1) + +#define PINMUX_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +#define PINMUX_GPIO231__FUNC_CONN_TOP_DATA (MTK_PIN_NO(231) | 1) + +#define PINMUX_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0) +#define PINMUX_GPIO232__FUNC_CONN_HRST_B (MTK_PIN_NO(232) | 1) + +#define PINMUX_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0) +#define PINMUX_GPIO233__FUNC_I2SIN0_BCK (MTK_PIN_NO(233) | 1) + +#define PINMUX_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0) +#define PINMUX_GPIO234__FUNC_I2SIN0_LRCK (MTK_PIN_NO(234) | 1) + +#define PINMUX_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0) +#define PINMUX_GPIO235__FUNC_I2SIN0_DI (MTK_PIN_NO(235) | 1) + +#define PINMUX_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +#define PINMUX_GPIO236__FUNC_I2SOUT0_DO (MTK_PIN_NO(236) | 1) + +#define PINMUX_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +#define PINMUX_GPIO237__FUNC_CONN_UARTHUB_UART_TX (MTK_PIN_NO(237) | 1) +#define PINMUX_GPIO237__FUNC_UTXD3 (MTK_PIN_NO(237) | 3) + +#define PINMUX_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +#define PINMUX_GPIO238__FUNC_CONN_UARTHUB_UART_RX (MTK_PIN_NO(238) | 1) +#define PINMUX_GPIO238__FUNC_URXD3 (MTK_PIN_NO(238) | 3) + +#define PINMUX_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +#define PINMUX_GPIO239__FUNC_TP_UTXD_CONSYS_VLP (MTK_PIN_NO(239) | 1) +#define PINMUX_GPIO239__FUNC_TP_URXD_CONSYS_VLP (MTK_PIN_NO(239) | 2) + +#define PINMUX_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +#define PINMUX_GPIO240__FUNC_TP_URXD_CONSYS_VLP (MTK_PIN_NO(240) | 1) +#define PINMUX_GPIO240__FUNC_TP_UTXD_CONSYS_VLP (MTK_PIN_NO(240) | 2) + +#define PINMUX_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +#define PINMUX_GPIO241__FUNC_PCIE_PERSTN (MTK_PIN_NO(241) | 1) + +#define PINMUX_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +#define PINMUX_GPIO242__FUNC_PCIE_WAKEN (MTK_PIN_NO(242) | 1) + +#define PINMUX_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +#define PINMUX_GPIO243__FUNC_PCIE_CLKREQN (MTK_PIN_NO(243) | 1) + +#define PINMUX_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +#define PINMUX_GPIO244__FUNC_CONN_RST (MTK_PIN_NO(244) | 1) + +#define PINMUX_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) + +#define PINMUX_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) +#define PINMUX_GPIO246__FUNC_CONN_PTA_TXD0 (MTK_PIN_NO(246) | 1) + +#define PINMUX_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +#define PINMUX_GPIO247__FUNC_CONN_PTA_RXD0 (MTK_PIN_NO(247) | 1) + +#define PINMUX_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +#define PINMUX_GPIO248__FUNC_UCTS3 (MTK_PIN_NO(248) | 3) + +#define PINMUX_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0) +#define PINMUX_GPIO249__FUNC_URTS3 (MTK_PIN_NO(249) | 3) + +#define PINMUX_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0) + +#define PINMUX_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0) +#define PINMUX_GPIO251__FUNC_IDDIG_1P (MTK_PIN_NO(251) | 1) + +#define PINMUX_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0) +#define PINMUX_GPIO252__FUNC_USB_DRVVBUS_1P (MTK_PIN_NO(252) | 1) + +#define PINMUX_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0) +#define PINMUX_GPIO253__FUNC_VBUSVALID_1P (MTK_PIN_NO(253) | 1) + +#define PINMUX_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0) +#define PINMUX_GPIO254__FUNC_IDDIG_2P (MTK_PIN_NO(254) | 1) + +#define PINMUX_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0) +#define PINMUX_GPIO255__FUNC_USB_DRVVBUS_2P (MTK_PIN_NO(255) | 1) + +#define PINMUX_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0) +#define PINMUX_GPIO256__FUNC_VBUSVALID_2P (MTK_PIN_NO(256) | 1) + +#define PINMUX_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0) +#define PINMUX_GPIO257__FUNC_VBUSVALID_3P (MTK_PIN_NO(257) | 1) + +#define PINMUX_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0) +#define PINMUX_GPIO258__FUNC_AVB_CLK1 (MTK_PIN_NO(258) | 7) + +#define PINMUX_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0) +#define PINMUX_GPIO259__FUNC_GBE0_TXD0 (MTK_PIN_NO(259) | 1) +#define PINMUX_GPIO259__FUNC_GBE1_TXD0 (MTK_PIN_NO(259) | 2) + +#define PINMUX_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0) +#define PINMUX_GPIO260__FUNC_GBE0_TXD1 (MTK_PIN_NO(260) | 1) +#define PINMUX_GPIO260__FUNC_GBE1_TXD1 (MTK_PIN_NO(260) | 2) + +#define PINMUX_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +#define PINMUX_GPIO261__FUNC_GBE0_TXC (MTK_PIN_NO(261) | 1) +#define PINMUX_GPIO261__FUNC_GBE1_TXC (MTK_PIN_NO(261) | 2) + +#define PINMUX_GPIO262__FUNC_GPIO262 (MTK_PIN_NO(262) | 0) +#define PINMUX_GPIO262__FUNC_GBE0_TXEN (MTK_PIN_NO(262) | 1) +#define PINMUX_GPIO262__FUNC_GBE1_TXEN (MTK_PIN_NO(262) | 2) + +#define PINMUX_GPIO263__FUNC_GPIO263 (MTK_PIN_NO(263) | 0) +#define PINMUX_GPIO263__FUNC_GBE0_RXD0 (MTK_PIN_NO(263) | 1) +#define PINMUX_GPIO263__FUNC_GBE1_RXD0 (MTK_PIN_NO(263) | 2) +#define PINMUX_GPIO263__FUNC_GBE0_AUX_PPS0 (MTK_PIN_NO(263) | 3) + +#define PINMUX_GPIO264__FUNC_GPIO264 (MTK_PIN_NO(264) | 0) +#define PINMUX_GPIO264__FUNC_GBE0_RXD1 (MTK_PIN_NO(264) | 1) +#define PINMUX_GPIO264__FUNC_GBE1_RXD1 (MTK_PIN_NO(264) | 2) +#define PINMUX_GPIO264__FUNC_GBE0_AUX_PPS1 (MTK_PIN_NO(264) | 3) + +#define PINMUX_GPIO265__FUNC_GPIO265 (MTK_PIN_NO(265) | 0) +#define PINMUX_GPIO265__FUNC_GBE0_RXC (MTK_PIN_NO(265) | 1) +#define PINMUX_GPIO265__FUNC_GBE1_RXC (MTK_PIN_NO(265) | 2) +#define PINMUX_GPIO265__FUNC_GBE0_AUX_PPS2 (MTK_PIN_NO(265) | 3) + +#define PINMUX_GPIO266__FUNC_GPIO266 (MTK_PIN_NO(266) | 0) +#define PINMUX_GPIO266__FUNC_GBE0_RXDV (MTK_PIN_NO(266) | 1) +#define PINMUX_GPIO266__FUNC_GBE1_RXDV (MTK_PIN_NO(266) | 2) +#define PINMUX_GPIO266__FUNC_GBE0_AUX_PPS3 (MTK_PIN_NO(266) | 3) + +#define PINMUX_GPIO267__FUNC_GPIO267 (MTK_PIN_NO(267) | 0) +#define PINMUX_GPIO267__FUNC_GBE0_TXD2 (MTK_PIN_NO(267) | 1) +#define PINMUX_GPIO267__FUNC_GBE1_TXD2 (MTK_PIN_NO(267) | 2) +#define PINMUX_GPIO267__FUNC_GBE0_RXER (MTK_PIN_NO(267) | 3) +#define PINMUX_GPIO267__FUNC_GBE1_RXER (MTK_PIN_NO(267) | 4) + +#define PINMUX_GPIO268__FUNC_GPIO268 (MTK_PIN_NO(268) | 0) +#define PINMUX_GPIO268__FUNC_GBE0_TXD3 (MTK_PIN_NO(268) | 1) +#define PINMUX_GPIO268__FUNC_GBE1_TXD3 (MTK_PIN_NO(268) | 2) + +#define PINMUX_GPIO269__FUNC_GPIO269 (MTK_PIN_NO(269) | 0) +#define PINMUX_GPIO269__FUNC_GBE0_RXD2 (MTK_PIN_NO(269) | 1) +#define PINMUX_GPIO269__FUNC_GBE1_RXD2 (MTK_PIN_NO(269) | 2) +#define PINMUX_GPIO269__FUNC_GBE0_MDC (MTK_PIN_NO(269) | 3) + +#define PINMUX_GPIO270__FUNC_GPIO270 (MTK_PIN_NO(270) | 0) +#define PINMUX_GPIO270__FUNC_GBE0_RXD3 (MTK_PIN_NO(270) | 1) +#define PINMUX_GPIO270__FUNC_GBE1_RXD3 (MTK_PIN_NO(270) | 2) +#define PINMUX_GPIO270__FUNC_GBE0_MDIO (MTK_PIN_NO(270) | 3) + +#endif /* __MT8196_PINFUNC_H */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-15 6:35 ` [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 Cathy Xu @ 2025-01-15 9:50 ` Krzysztof Kozlowski 2025-01-16 2:20 ` Cathy Xu (许华婷) 0 siblings, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2025-01-15 9:50 UTC (permalink / raw) To: Cathy Xu Cc: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang, Lei Xue, wenbin.mei, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Guodong Liu On Wed, Jan 15, 2025 at 02:35:38PM +0800, Cathy Xu wrote: > + > + properties: > + pinmux: > + description: > + Integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are > + defined as macros in dt-bindings/pinctrl/mt8196-pinfunc.h > + directly, for this SoC. > + > + drive-strength: > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > + > + bias-pull-down: > + oneOf: > + - type: boolean > + - enum: [100, 101, 102, 103] > + description: mt8196 pull down PUPD/R0/R1 type define value. > + - enum: [200, 201, 202, 203, 204, 205, 206, 207] > + description: mt8196 pull down RSEL type define value. Not much improved. > + description: | > + For pull down type is normal, it doesn't need add RSEL & R1R0. > + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to > + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & > + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > + For pull down type is PD/RSEL, it can add RSEL define to set > + different resistance. It can support > + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & > + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & > + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & > + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in > + mt8196. > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > new file mode 100644 > index 000000000000..bf0c8374407c > --- /dev/null > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > @@ -0,0 +1,1572 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +/* > + * Copyright (C) 2025 Mediatek Inc. > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > + */ > + > +#ifndef __MT8196_PINFUNC_H > +#define __MT8196_PINFUNC_H > + > +#include <dt-bindings/pinctrl/mt65xx.h> > + > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) I do not see how you resolved my comment from v1. In v2 I reminded about it, so you responded that yopu will change something, but I do not see any changes. So explain: how did you resolve my comment? These two examples where you claim you will change something, but send the same. I skipped the rest of the patch. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-15 9:50 ` Krzysztof Kozlowski @ 2025-01-16 2:20 ` Cathy Xu (许华婷) 2025-01-16 7:28 ` Krzysztof Kozlowski 0 siblings, 1 reply; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-01-16 2:20 UTC (permalink / raw) To: krzk@kernel.org Cc: linux-kernel@vger.kernel.org, Lei Xue (薛磊), linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Wed, 2025-01-15 at 10:50 +0100, Krzysztof Kozlowski wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Wed, Jan 15, 2025 at 02:35:38PM +0800, Cathy Xu wrote: > > + > > + properties: > > + pinmux: > > + description: > > + Integer array, represents gpio pin number and mux > > setting. > > + Supported pin number and mux varies for different > > SoCs, and are > > + defined as macros in dt-bindings/pinctrl/mt8196- > > pinfunc.h > > + directly, for this SoC. > > + > > + drive-strength: > > + enum: [2, 4, 6, 8, 10, 12, 14, 16] > > + > > + bias-pull-down: > > + oneOf: > > + - type: boolean > > + - enum: [100, 101, 102, 103] > > + description: mt8196 pull down PUPD/R0/R1 type > > define value. > > + - enum: [200, 201, 202, 203, 204, 205, 206, 207] > > + description: mt8196 pull down RSEL type define > > value. > > Not much improved. I have removed the content related to 'resistance value', we use 'RSEL' instead of 'resistance value'. > > > > + description: | > > + For pull down type is normal, it doesn't need add > > RSEL & R1R0. > > + For pull down type is PUPD/R0/R1 type, it can add > > R1R0 define to > > + set different resistance. It can support > > "MTK_PUPD_SET_R1R0_00" & > > + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > + For pull down type is PD/RSEL, it can add RSEL > > define to set > > + different resistance. It can support > > + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & > > + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & > > + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & > > + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" > > define in > > + mt8196. > > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > new file mode 100644 > > index 000000000000..bf0c8374407c > > --- /dev/null > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > @@ -0,0 +1,1572 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > > +/* > > + * Copyright (C) 2025 Mediatek Inc. > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > + */ > > + > > +#ifndef __MT8196_PINFUNC_H > > +#define __MT8196_PINFUNC_H > > + > > +#include <dt-bindings/pinctrl/mt65xx.h> > > + > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) > > I do not see how you resolved my comment from v1. In v2 I reminded > about > it, so you responded that yopu will change something, but I do not > see > any changes. > > So explain: how did you resolve my comment? > > These two examples where you claim you will change something, but > send > the same. I skipped the rest of the patch. Thank you for your patient response, here is my explanation for you question: In v1, I undertand that you meant I didn't sent a real binding, and the bindings should be separated from driver. In addition, I should run scripts/checkpatch.pl and scripts/get_maintainers.pl. So in v2, I sent a real binding(mediatek,mt8196-pinctrl.yaml), and sent two separate patches, one for driver and one for bindings, also ran scripts/get_maintainers.pl get necessary people and sent to them. In v2, I understand that I need refer to git history to modify the commit msgs, so I made the changes in v3. Then you asked me about the difference between 'RSEL' and 'resistance value'. I replied that the 'resistance value' method is no longer use, so in v3, I removed all content about it(include entire 'rsel-resistance-in-si-unit' property and the parts mentioned in bias-pull-up/down). I may not have correctly undertand your meaning, so I didn't make the changes you wanted. If that is the case, please point it out. Thank you. > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 2:20 ` Cathy Xu (许华婷) @ 2025-01-16 7:28 ` Krzysztof Kozlowski 2025-01-16 8:18 ` Cathy Xu (许华婷) 0 siblings, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2025-01-16 7:28 UTC (permalink / raw) To: Cathy Xu (许华婷) Cc: linux-kernel@vger.kernel.org, Lei Xue (薛磊), linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: >>> + bias-pull-down: >>> + oneOf: >>> + - type: boolean >>> + - enum: [100, 101, 102, 103] >>> + description: mt8196 pull down PUPD/R0/R1 type >>> define value. >>> + - enum: [200, 201, 202, 203, 204, 205, 206, 207] >>> + description: mt8196 pull down RSEL type define >>> value. >> >> Not much improved. > I have removed the content related to 'resistance value', we use > 'RSEL' instead of 'resistance value'. So the value in Ohms was removed? I assume above do not have known value in Ohms? > >> >> >>> + description: | >>> + For pull down type is normal, it doesn't need add >>> RSEL & R1R0. >>> + For pull down type is PUPD/R0/R1 type, it can add >>> R1R0 define to >>> + set different resistance. It can support >>> "MTK_PUPD_SET_R1R0_00" & >>> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & >>> + "MTK_PUPD_SET_R1R0_11" define in mt8196. >>> + For pull down type is PD/RSEL, it can add RSEL >>> define to set >>> + different resistance. It can support >>> + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & >>> + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & >>> + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & >>> + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" >>> define in >>> + mt8196. >>> diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>> b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>> new file mode 100644 >>> index 000000000000..bf0c8374407c >>> --- /dev/null >>> +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>> @@ -0,0 +1,1572 @@ >>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ >>> +/* >>> + * Copyright (C) 2025 Mediatek Inc. >>> + * Author: Guodong Liu <Guodong.Liu@mediatek.com> >>> + */ >>> + >>> +#ifndef __MT8196_PINFUNC_H >>> +#define __MT8196_PINFUNC_H >>> + >>> +#include <dt-bindings/pinctrl/mt65xx.h> >>> + >>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) >>> +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) >>> +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) >>> +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) >>> +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) >>> +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) >> >> I do not see how you resolved my comment from v1. In v2 I reminded >> about >> it, so you responded that yopu will change something, but I do not >> see >> any changes. >> >> So explain: how did you resolve my comment? >> >> These two examples where you claim you will change something, but >> send >> the same. I skipped the rest of the patch. > > Thank you for your patient response, here is my explanation for you > question: > > In v1, I undertand that you meant I didn't sent a real binding, and The comment is under specific lines, so I said these defines are not a real binding. You sent them again, but they are still not bindings, because they are not used in the driver. Maybe the usage is convoluted, so which part of implementation are these connecting with DTS? IOW, which part of driver relies on the binding? > the bindings should be separated from driver. In addition, I should > run scripts/checkpatch.pl and scripts/get_maintainers.pl. So in v2, I > sent a real binding(mediatek,mt8196-pinctrl.yaml), and sent two > separate patches, one for driver and one for bindings, also ran > scripts/get_maintainers.pl get necessary people and sent to them. > > In v2, I understand that I need refer to git history to modify the > commit msgs, so I made the changes in v3. Then you asked me about the > difference between 'RSEL' and 'resistance value'. I replied that the > 'resistance value' method is no longer use, so in v3, I removed all > content about it(include entire 'rsel-resistance-in-si-unit' property > and the parts mentioned in bias-pull-up/down). Yes, thank you this I saw, the comments appear under specific places, so only these places are discussed. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 7:28 ` Krzysztof Kozlowski @ 2025-01-16 8:18 ` Cathy Xu (许华婷) 2025-01-16 8:33 ` Chen-Yu Tsai 2025-01-16 10:20 ` Krzysztof Kozlowski 0 siblings, 2 replies; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-01-16 8:18 UTC (permalink / raw) To: krzk@kernel.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > + bias-pull-down: > > > > + oneOf: > > > > + - type: boolean > > > > + - enum: [100, 101, 102, 103] > > > > + description: mt8196 pull down PUPD/R0/R1 type > > > > define value. > > > > + - enum: [200, 201, 202, 203, 204, 205, 206, 207] > > > > + description: mt8196 pull down RSEL type define > > > > value. > > > > > > Not much improved. > > > > I have removed the content related to 'resistance value', we use > > 'RSEL' instead of 'resistance value'. > > So the value in Ohms was removed? I assume above do not have known > value > in Ohms? Yes, value in Ohns was removed, no code have knowm value. > > > > > > > > > > > > > + description: | > > > > + For pull down type is normal, it doesn't need > > > > add > > > > RSEL & R1R0. > > > > + For pull down type is PUPD/R0/R1 type, it can > > > > add > > > > R1R0 define to > > > > + set different resistance. It can support > > > > "MTK_PUPD_SET_R1R0_00" & > > > > + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" > > > > & > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > + For pull down type is PD/RSEL, it can add RSEL > > > > define to set > > > > + different resistance. It can support > > > > + "MTK_PULL_SET_RSEL_000" & > > > > "MTK_PULL_SET_RSEL_001" & > > > > + "MTK_PULL_SET_RSEL_010" & > > > > "MTK_PULL_SET_RSEL_011" & > > > > + "MTK_PULL_SET_RSEL_100" & > > > > "MTK_PULL_SET_RSEL_101" & > > > > + "MTK_PULL_SET_RSEL_110" & > > > > "MTK_PULL_SET_RSEL_111" > > > > define in > > > > + mt8196. > > > > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > new file mode 100644 > > > > index 000000000000..bf0c8374407c > > > > --- /dev/null > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > @@ -0,0 +1,1572 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > > > > +/* > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > + */ > > > > + > > > > +#ifndef __MT8196_PINFUNC_H > > > > +#define __MT8196_PINFUNC_H > > > > + > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > + > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > reminded > > > about > > > it, so you responded that yopu will change something, but I do > > > not > > > see > > > any changes. > > > > > > So explain: how did you resolve my comment? > > > > > > These two examples where you claim you will change something, but > > > send > > > the same. I skipped the rest of the patch. > > > > Thank you for your patient response, here is my explanation for > > you > > question: > > > > In v1, I undertand that you meant I didn't sent a real binding, > > and > > > The comment is under specific lines, so I said these defines are not > a > real binding. You sent them again, but they are still not bindings, > because they are not used in the driver. Maybe the usage is > convoluted, > so which part of implementation are these connecting with DTS? IOW, > which part of driver relies on the binding? I got you. This binding define many macros, which will be used for 'pinmux' setting in the DTS. The usage like this: adsp_uart_pins: adsp-uart-pins { pins-tx-rx { pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>; }; }; > > > > > the bindings should be separated from driver. In addition, I should > > run scripts/checkpatch.pl and scripts/get_maintainers.pl. So in v2, > > I > > sent a real binding(mediatek,mt8196-pinctrl.yaml), and sent two > > separate patches, one for driver and one for bindings, also ran > > scripts/get_maintainers.pl get necessary people and sent to them. > > > > In v2, I understand that I need refer to git history to modify > > the > > commit msgs, so I made the changes in v3. Then you asked me about > > the > > difference between 'RSEL' and 'resistance value'. I replied that > > the > > 'resistance value' method is no longer use, so in v3, I removed all > > content about it(include entire 'rsel-resistance-in-si-unit' > > property > > and the parts mentioned in bias-pull-up/down). > > Yes, thank you this I saw, the comments appear under specific places, > so > only these places are discussed. ok, thank you, we can discuss if there are any issues. > > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 8:18 ` Cathy Xu (许华婷) @ 2025-01-16 8:33 ` Chen-Yu Tsai 2025-01-20 9:12 ` Cathy Xu (许华婷) 2025-01-16 10:20 ` Krzysztof Kozlowski 1 sibling, 1 reply; 17+ messages in thread From: Chen-Yu Tsai @ 2025-01-16 8:33 UTC (permalink / raw) To: Cathy Xu (许华婷) Cc: krzk@kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Thu, Jan 16, 2025 at 4:19 PM Cathy Xu (许华婷) <ot_cathy.xu@mediatek.com> wrote: > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > > you have verified the sender or the content. > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > + bias-pull-down: > > > > > + oneOf: > > > > > + - type: boolean > > > > > + - enum: [100, 101, 102, 103] > > > > > + description: mt8196 pull down PUPD/R0/R1 type > > > > > define value. > > > > > + - enum: [200, 201, 202, 203, 204, 205, 206, 207] > > > > > + description: mt8196 pull down RSEL type define > > > > > value. > > > > > > > > Not much improved. > > > > > > I have removed the content related to 'resistance value', we use > > > 'RSEL' instead of 'resistance value'. > > > > So the value in Ohms was removed? I assume above do not have known > > value > > in Ohms? > > Yes, value in Ohns was removed, no code have knowm value. That's sad. We went through a lot during the MT8195 cycle to get the paris driver library to support proper SI unit values [1] to replace the RSEL values (200 ~ 207). Why can't this be supported anymore? Also we never got around to getting rid the PUPD/R0/R1 values (100 ~ 103). > > > > > > > > > > > > > > > > > > + description: | > > > > > + For pull down type is normal, it doesn't need > > > > > add > > > > > RSEL & R1R0. > > > > > + For pull down type is PUPD/R0/R1 type, it can > > > > > add > > > > > R1R0 define to > > > > > + set different resistance. It can support > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" > > > > > & > > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > > + For pull down type is PD/RSEL, it can add RSEL > > > > > define to set > > > > > + different resistance. It can support > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > "MTK_PULL_SET_RSEL_111" > > > > > define in > > > > > + mt8196. > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > new file mode 100644 > > > > > index 000000000000..bf0c8374407c > > > > > --- /dev/null > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > @@ -0,0 +1,1572 @@ > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > > > > > +/* > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > + */ > > > > > + > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > +#define __MT8196_PINFUNC_H > > > > > + > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > + > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) > > > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > > reminded > > > > about > > > > it, so you responded that yopu will change something, but I do > > > > not > > > > see > > > > any changes. > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > These two examples where you claim you will change something, but > > > > send > > > > the same. I skipped the rest of the patch. > > > > > > Thank you for your patient response, here is my explanation for > > > you > > > question: > > > > > > In v1, I undertand that you meant I didn't sent a real binding, > > > and > > > > > > The comment is under specific lines, so I said these defines are not > > a > > real binding. You sent them again, but they are still not bindings, > > because they are not used in the driver. Maybe the usage is > > convoluted, > > so which part of implementation are these connecting with DTS? IOW, > > which part of driver relies on the binding? > > I got you. This binding define many macros, which will be used for > 'pinmux' setting in the DTS. The usage like this: > > adsp_uart_pins: adsp-uart-pins { > pins-tx-rx { > pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>; > }; > }; The only binding between the DT and the driver is the structure of the value, given as "(MTK_PIN_NO(<N>) | <function mux value>)". The whole list of "PINMUX_GPIOxxx__FUNC_xyz" macros is just a convenience table for developers, and not used by the driver. The driver simply takes the values from the two bit fields and uses them directly. That's why Krzysztof is saying the macros are not used in the driver and therefore not a binding. Please move the header file to under "arch/arm64/boot/dts/mediatek", and split it out as a separate commit with a subject like: arm64: dts: mediatek: mt8196: Add pinmux macro header file ChenYu > > > > > > > > > the bindings should be separated from driver. In addition, I should > > > run scripts/checkpatch.pl and scripts/get_maintainers.pl. So in v2, > > > I > > > sent a real binding(mediatek,mt8196-pinctrl.yaml), and sent two > > > separate patches, one for driver and one for bindings, also ran > > > scripts/get_maintainers.pl get necessary people and sent to them. > > > > > > In v2, I understand that I need refer to git history to modify > > > the > > > commit msgs, so I made the changes in v3. Then you asked me about > > > the > > > difference between 'RSEL' and 'resistance value'. I replied that > > > the > > > 'resistance value' method is no longer use, so in v3, I removed all > > > content about it(include entire 'rsel-resistance-in-si-unit' > > > property > > > and the parts mentioned in bias-pull-up/down). > > > > Yes, thank you this I saw, the comments appear under specific places, > > so > > only these places are discussed. > > ok, thank you, we can discuss if there are any issues. > > > > > > > > > Best regards, > > Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 8:33 ` Chen-Yu Tsai @ 2025-01-20 9:12 ` Cathy Xu (许华婷) 0 siblings, 0 replies; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-01-20 9:12 UTC (permalink / raw) To: wenst@chromium.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), krzk@kernel.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Thu, 2025-01-16 at 16:33 +0800, Chen-Yu Tsai wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Thu, Jan 16, 2025 at 4:19 PM Cathy Xu (许华婷) < > ot_cathy.xu@mediatek.com> wrote: > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > > > External email : Please do not click links or open attachments > > > until > > > you have verified the sender or the content. > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > + bias-pull-down: > > > > > > + oneOf: > > > > > > + - type: boolean > > > > > > + - enum: [100, 101, 102, 103] > > > > > > + description: mt8196 pull down PUPD/R0/R1 > > > > > > type > > > > > > define value. > > > > > > + - enum: [200, 201, 202, 203, 204, 205, 206, > > > > > > 207] > > > > > > + description: mt8196 pull down RSEL type > > > > > > define > > > > > > value. > > > > > > > > > > Not much improved. > > > > > > > > I have removed the content related to 'resistance value', we > > > > use > > > > 'RSEL' instead of 'resistance value'. > > > > > > So the value in Ohms was removed? I assume above do not have > > > known > > > value > > > in Ohms? > > > > Yes, value in Ohns was removed, no code have knowm value. > > That's sad. We went through a lot during the MT8195 cycle to get the > paris driver library to support proper SI unit values [1] to replace > the RSEL values (200 ~ 207). Why can't this be supported anymore? > > Also we never got around to getting rid the PUPD/R0/R1 values (100 ~ > 103). Sorry, I didn't see any parsing of 'mediatek,rsel-resistence-in-si- unit' in driver, and I noticed that in driver, the final value written to the rsel register is based on the value of RSEL(200 ~ 207). Additionally, I don't understand why we abandon the RSEL/R0/R1 values (200 ~ 207/100 ~ 103). Is it to prevent confusion? Perhaps adding some comments would help? > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > + For pull down type is normal, it doesn't > > > > > > need > > > > > > add > > > > > > RSEL & R1R0. > > > > > > + For pull down type is PUPD/R0/R1 type, it > > > > > > can > > > > > > add > > > > > > R1R0 define to > > > > > > + set different resistance. It can support > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > & > > > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > > > + For pull down type is PD/RSEL, it can add > > > > > > RSEL > > > > > > define to set > > > > > > + different resistance. It can support > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > define in > > > > > > + mt8196. > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > new file mode 100644 > > > > > > index 000000000000..bf0c8374407c > > > > > > --- /dev/null > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > @@ -0,0 +1,1572 @@ > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > > > > > */ > > > > > > +/* > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > + */ > > > > > > + > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > +#define __MT8196_PINFUNC_H > > > > > > + > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > + > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | > > > > > > 4) > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | > > > > > > 5) > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | > > > > > > 6) > > > > > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > > > reminded > > > > > about > > > > > it, so you responded that yopu will change something, but I > > > > > do > > > > > not > > > > > see > > > > > any changes. > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > These two examples where you claim you will change something, > > > > > but > > > > > send > > > > > the same. I skipped the rest of the patch. > > > > > > > > Thank you for your patient response, here is my explanation > > > > for > > > > you > > > > question: > > > > > > > > In v1, I undertand that you meant I didn't sent a real > > > > binding, > > > > and > > > > > > > > > The comment is under specific lines, so I said these defines are > > > not > > > a > > > real binding. You sent them again, but they are still not > > > bindings, > > > because they are not used in the driver. Maybe the usage is > > > convoluted, > > > so which part of implementation are these connecting with DTS? > > > IOW, > > > which part of driver relies on the binding? > > > > I got you. This binding define many macros, which will be used > > for > > 'pinmux' setting in the DTS. The usage like this: > > > > adsp_uart_pins: adsp-uart-pins { > > pins-tx-rx { > > pinmux = > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0 > > >; > > }; > > }; > > The only binding between the DT and the driver is the structure of > the value, given as "(MTK_PIN_NO(<N>) | <function mux value>)". > > The whole list of "PINMUX_GPIOxxx__FUNC_xyz" macros is just a > convenience > table for developers, and not used by the driver. The driver simply > takes > the values from the two bit fields and uses them directly. > > That's why Krzysztof is saying the macros are not used in the driver > and therefore not a binding. > > Please move the header file to under "arch/arm64/boot/dts/mediatek", > and split it out as a separate commit with a subject like: > > arm64: dts: mediatek: mt8196: Add pinmux macro header file ok, got it, I will fix in next version. However, the previous 'xxx- pinfunc.h' file were placed under binding. > > > ChenYu > > > > > > > > > > > > > > the bindings should be separated from driver. In addition, I > > > > should > > > > run scripts/checkpatch.pl and scripts/get_maintainers.pl. So in > > > > v2, > > > > I > > > > sent a real binding(mediatek,mt8196-pinctrl.yaml), and sent two > > > > separate patches, one for driver and one for bindings, also ran > > > > scripts/get_maintainers.pl get necessary people and sent to > > > > them. > > > > > > > > In v2, I understand that I need refer to git history to > > > > modify > > > > the > > > > commit msgs, so I made the changes in v3. Then you asked me > > > > about > > > > the > > > > difference between 'RSEL' and 'resistance value'. I replied > > > > that > > > > the > > > > 'resistance value' method is no longer use, so in v3, I removed > > > > all > > > > content about it(include entire 'rsel-resistance-in-si-unit' > > > > property > > > > and the parts mentioned in bias-pull-up/down). > > > > > > Yes, thank you this I saw, the comments appear under specific > > > places, > > > so > > > only these places are discussed. > > > > ok, thank you, we can discuss if there are any issues. > > > > > > > > > > > > > > Best regards, > > > Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 8:18 ` Cathy Xu (许华婷) 2025-01-16 8:33 ` Chen-Yu Tsai @ 2025-01-16 10:20 ` Krzysztof Kozlowski 2025-01-20 9:17 ` Cathy Xu (许华婷) 1 sibling, 1 reply; 17+ messages in thread From: Krzysztof Kozlowski @ 2025-01-16 10:20 UTC (permalink / raw) To: Cathy Xu (许华婷) Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> >> >> On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: >>>>> + bias-pull-down: >>>>> + oneOf: >>>>> + - type: boolean >>>>> + - enum: [100, 101, 102, 103] >>>>> + description: mt8196 pull down PUPD/R0/R1 type >>>>> define value. >>>>> + - enum: [200, 201, 202, 203, 204, 205, 206, 207] >>>>> + description: mt8196 pull down RSEL type define >>>>> value. >>>> >>>> Not much improved. >>> >>> I have removed the content related to 'resistance value', we use >>> 'RSEL' instead of 'resistance value'. >> >> So the value in Ohms was removed? I assume above do not have known >> value >> in Ohms? > > Yes, value in Ohns was removed, no code have knowm value. Does the hardware have known value in Ohms? > >> >>> >>>> >>>> >>>>> + description: | >>>>> + For pull down type is normal, it doesn't need >>>>> add >>>>> RSEL & R1R0. >>>>> + For pull down type is PUPD/R0/R1 type, it can >>>>> add >>>>> R1R0 define to >>>>> + set different resistance. It can support >>>>> "MTK_PUPD_SET_R1R0_00" & >>>>> + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" >>>>> & >>>>> + "MTK_PUPD_SET_R1R0_11" define in mt8196. >>>>> + For pull down type is PD/RSEL, it can add RSEL >>>>> define to set >>>>> + different resistance. It can support >>>>> + "MTK_PULL_SET_RSEL_000" & >>>>> "MTK_PULL_SET_RSEL_001" & >>>>> + "MTK_PULL_SET_RSEL_010" & >>>>> "MTK_PULL_SET_RSEL_011" & >>>>> + "MTK_PULL_SET_RSEL_100" & >>>>> "MTK_PULL_SET_RSEL_101" & >>>>> + "MTK_PULL_SET_RSEL_110" & >>>>> "MTK_PULL_SET_RSEL_111" >>>>> define in >>>>> + mt8196. >>>>> diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>> b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>> new file mode 100644 >>>>> index 000000000000..bf0c8374407c >>>>> --- /dev/null >>>>> +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>> @@ -0,0 +1,1572 @@ >>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ >>>>> +/* >>>>> + * Copyright (C) 2025 Mediatek Inc. >>>>> + * Author: Guodong Liu <Guodong.Liu@mediatek.com> >>>>> + */ >>>>> + >>>>> +#ifndef __MT8196_PINFUNC_H >>>>> +#define __MT8196_PINFUNC_H >>>>> + >>>>> +#include <dt-bindings/pinctrl/mt65xx.h> >>>>> + >>>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) >>>>> +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) >>>>> +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) >>>>> +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | 4) >>>>> +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | 5) >>>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | 6) >>>> >>>> I do not see how you resolved my comment from v1. In v2 I >>>> reminded >>>> about >>>> it, so you responded that yopu will change something, but I do >>>> not >>>> see >>>> any changes. >>>> >>>> So explain: how did you resolve my comment? >>>> >>>> These two examples where you claim you will change something, but >>>> send >>>> the same. I skipped the rest of the patch. >>> >>> Thank you for your patient response, here is my explanation for >>> you >>> question: >>> >>> In v1, I undertand that you meant I didn't sent a real binding, >>> and >> >> >> The comment is under specific lines, so I said these defines are not >> a >> real binding. You sent them again, but they are still not bindings, >> because they are not used in the driver. Maybe the usage is >> convoluted, >> so which part of implementation are these connecting with DTS? IOW, >> which part of driver relies on the binding? > > I got you. This binding define many macros, which will be used for > 'pinmux' setting in the DTS. The usage like this: > > adsp_uart_pins: adsp-uart-pins { > pins-tx-rx { > pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>; > }; > }; That's DTS, not driver, so not a binding. Drop the header from bindings. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-16 10:20 ` Krzysztof Kozlowski @ 2025-01-20 9:17 ` Cathy Xu (许华婷) 2025-01-20 12:42 ` AngeloGioacchino Del Regno 0 siblings, 1 reply; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-01-20 9:17 UTC (permalink / raw) To: krzk@kernel.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > > > External email : Please do not click links or open attachments > > > until > > > you have verified the sender or the content. > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > + bias-pull-down: > > > > > > + oneOf: > > > > > > + - type: boolean > > > > > > + - enum: [100, 101, 102, 103] > > > > > > + description: mt8196 pull down PUPD/R0/R1 > > > > > > type > > > > > > define value. > > > > > > + - enum: [200, 201, 202, 203, 204, 205, 206, > > > > > > 207] > > > > > > + description: mt8196 pull down RSEL type > > > > > > define > > > > > > value. > > > > > > > > > > Not much improved. > > > > > > > > I have removed the content related to 'resistance value', we > > > > use > > > > 'RSEL' instead of 'resistance value'. > > > > > > So the value in Ohms was removed? I assume above do not have > > > known > > > value > > > in Ohms? > > > > Yes, value in Ohns was removed, no code have knowm value. > > Does the hardware have known value in Ohms? What do you mean by 'hardware'? When writing to the rsel register, the value written is 0-7. > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > + For pull down type is normal, it doesn't > > > > > > need > > > > > > add > > > > > > RSEL & R1R0. > > > > > > + For pull down type is PUPD/R0/R1 type, it > > > > > > can > > > > > > add > > > > > > R1R0 define to > > > > > > + set different resistance. It can support > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > & > > > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > > > + For pull down type is PD/RSEL, it can add > > > > > > RSEL > > > > > > define to set > > > > > > + different resistance. It can support > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > define in > > > > > > + mt8196. > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > new file mode 100644 > > > > > > index 000000000000..bf0c8374407c > > > > > > --- /dev/null > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > @@ -0,0 +1,1572 @@ > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > > > > > */ > > > > > > +/* > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > + */ > > > > > > + > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > +#define __MT8196_PINFUNC_H > > > > > > + > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > + > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | > > > > > > 4) > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | > > > > > > 5) > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | > > > > > > 6) > > > > > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > > > reminded > > > > > about > > > > > it, so you responded that yopu will change something, but I > > > > > do > > > > > not > > > > > see > > > > > any changes. > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > These two examples where you claim you will change something, > > > > > but > > > > > send > > > > > the same. I skipped the rest of the patch. > > > > > > > > Thank you for your patient response, here is my explanation > > > > for > > > > you > > > > question: > > > > > > > > In v1, I undertand that you meant I didn't sent a real > > > > binding, > > > > and > > > > > > > > > The comment is under specific lines, so I said these defines are > > > not > > > a > > > real binding. You sent them again, but they are still not > > > bindings, > > > because they are not used in the driver. Maybe the usage is > > > convoluted, > > > so which part of implementation are these connecting with DTS? > > > IOW, > > > which part of driver relies on the binding? > > > > I got you. This binding define many macros, which will be used > > for > > 'pinmux' setting in the DTS. The usage like this: > > > > adsp_uart_pins: adsp-uart-pins { > > pins-tx-rx { > > pinmux = > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0 > > >; > > }; > > }; > > > That's DTS, not driver, so not a binding. Drop the header from > bindings. Sorry, I don't quite understand the relationship between binding and driver. Driver will parse this macro to get gpio number and function. > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-20 9:17 ` Cathy Xu (许华婷) @ 2025-01-20 12:42 ` AngeloGioacchino Del Regno 2025-01-21 9:56 ` Cathy Xu (许华婷) 0 siblings, 1 reply; 17+ messages in thread From: AngeloGioacchino Del Regno @ 2025-01-20 12:42 UTC (permalink / raw) To: Cathy Xu (许华婷), krzk@kernel.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> >> >> On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: >>> On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: >>>> External email : Please do not click links or open attachments >>>> until >>>> you have verified the sender or the content. >>>> >>>> >>>> On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: >>>>>>> + bias-pull-down: >>>>>>> + oneOf: >>>>>>> + - type: boolean >>>>>>> + - enum: [100, 101, 102, 103] >>>>>>> + description: mt8196 pull down PUPD/R0/R1 >>>>>>> type >>>>>>> define value. >>>>>>> + - enum: [200, 201, 202, 203, 204, 205, 206, >>>>>>> 207] >>>>>>> + description: mt8196 pull down RSEL type >>>>>>> define >>>>>>> value. >>>>>> >>>>>> Not much improved. >>>>> >>>>> I have removed the content related to 'resistance value', we >>>>> use >>>>> 'RSEL' instead of 'resistance value'. This is wrong. >>>> >>>> So the value in Ohms was removed? I assume above do not have >>>> known >>>> value >>>> in Ohms? >>> >>> Yes, value in Ohns was removed, no code have knowm value. >> >> Does the hardware have known value in Ohms? It does. > > What do you mean by 'hardware'? When writing to the rsel register, > the value written is 0-7. > Hardware means "the pin controller of the mt8196 SoC" :-) Anyway. The RSEL registers' function is to select a specific resistance value to pullup/down a pin, or a group of pins. Devicetree bindings require to specify values in known units, so in device tree you *need* to specify the RSEL resistance in Ohms. You cannot specify RSEL register value in device-tree. That's unacceptable. Regards, Angelo >> >> >>> >>>> >>>>> >>>>>> >>>>>> >>>>>>> + description: | >>>>>>> + For pull down type is normal, it doesn't >>>>>>> need >>>>>>> add >>>>>>> RSEL & R1R0. >>>>>>> + For pull down type is PUPD/R0/R1 type, it >>>>>>> can >>>>>>> add >>>>>>> R1R0 define to >>>>>>> + set different resistance. It can support >>>>>>> "MTK_PUPD_SET_R1R0_00" & >>>>>>> + "MTK_PUPD_SET_R1R0_01" & >>>>>>> "MTK_PUPD_SET_R1R0_10" >>>>>>> & >>>>>>> + "MTK_PUPD_SET_R1R0_11" define in mt8196. >>>>>>> + For pull down type is PD/RSEL, it can add >>>>>>> RSEL >>>>>>> define to set >>>>>>> + different resistance. It can support >>>>>>> + "MTK_PULL_SET_RSEL_000" & >>>>>>> "MTK_PULL_SET_RSEL_001" & >>>>>>> + "MTK_PULL_SET_RSEL_010" & >>>>>>> "MTK_PULL_SET_RSEL_011" & >>>>>>> + "MTK_PULL_SET_RSEL_100" & >>>>>>> "MTK_PULL_SET_RSEL_101" & >>>>>>> + "MTK_PULL_SET_RSEL_110" & >>>>>>> "MTK_PULL_SET_RSEL_111" >>>>>>> define in >>>>>>> + mt8196. >>>>>>> diff --git a/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>>>> b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>>>> new file mode 100644 >>>>>>> index 000000000000..bf0c8374407c >>>>>>> --- /dev/null >>>>>>> +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h >>>>>>> @@ -0,0 +1,1572 @@ >>>>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>>>>>> */ >>>>>>> +/* >>>>>>> + * Copyright (C) 2025 Mediatek Inc. >>>>>>> + * Author: Guodong Liu <Guodong.Liu@mediatek.com> >>>>>>> + */ >>>>>>> + >>>>>>> +#ifndef __MT8196_PINFUNC_H >>>>>>> +#define __MT8196_PINFUNC_H >>>>>>> + >>>>>>> +#include <dt-bindings/pinctrl/mt65xx.h> >>>>>>> + >>>>>>> +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) >>>>>>> +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | 1) >>>>>>> +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | 3) >>>>>>> +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) | >>>>>>> 4) >>>>>>> +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK (MTK_PIN_NO(0) | >>>>>>> 5) >>>>>>> +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) | >>>>>>> 6) >>>>>> >>>>>> I do not see how you resolved my comment from v1. In v2 I >>>>>> reminded >>>>>> about >>>>>> it, so you responded that yopu will change something, but I >>>>>> do >>>>>> not >>>>>> see >>>>>> any changes. >>>>>> >>>>>> So explain: how did you resolve my comment? >>>>>> >>>>>> These two examples where you claim you will change something, >>>>>> but >>>>>> send >>>>>> the same. I skipped the rest of the patch. >>>>> >>>>> Thank you for your patient response, here is my explanation >>>>> for >>>>> you >>>>> question: >>>>> >>>>> In v1, I undertand that you meant I didn't sent a real >>>>> binding, >>>>> and >>>> >>>> >>>> The comment is under specific lines, so I said these defines are >>>> not >>>> a >>>> real binding. You sent them again, but they are still not >>>> bindings, >>>> because they are not used in the driver. Maybe the usage is >>>> convoluted, >>>> so which part of implementation are these connecting with DTS? >>>> IOW, >>>> which part of driver relies on the binding? >>> >>> I got you. This binding define many macros, which will be used >>> for >>> 'pinmux' setting in the DTS. The usage like this: >>> >>> adsp_uart_pins: adsp-uart-pins { >>> pins-tx-rx { >>> pinmux = >>> <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, >>> <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0 >>>> ; >>> }; >>> }; >> >> >> That's DTS, not driver, so not a binding. Drop the header from >> bindings. > > Sorry, I don't quite understand the relationship between binding and > driver. Driver will parse this macro to get gpio number and function. > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-20 12:42 ` AngeloGioacchino Del Regno @ 2025-01-21 9:56 ` Cathy Xu (许华婷) 2025-01-21 10:03 ` Chen-Yu Tsai 0 siblings, 1 reply; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-01-21 9:56 UTC (permalink / raw) To: AngeloGioacchino Del Regno, krzk@kernel.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org On Mon, 2025-01-20 at 13:42 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: > > > External email : Please do not click links or open attachments > > > until > > > you have verified the sender or the content. > > > > > > > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > > > > > External email : Please do not click links or open > > > > > attachments > > > > > until > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > > > + bias-pull-down: > > > > > > > > + oneOf: > > > > > > > > + - type: boolean > > > > > > > > + - enum: [100, 101, 102, 103] > > > > > > > > + description: mt8196 pull down > > > > > > > > PUPD/R0/R1 > > > > > > > > type > > > > > > > > define value. > > > > > > > > + - enum: [200, 201, 202, 203, 204, 205, > > > > > > > > 206, > > > > > > > > 207] > > > > > > > > + description: mt8196 pull down RSEL > > > > > > > > type > > > > > > > > define > > > > > > > > value. > > > > > > > > > > > > > > Not much improved. > > > > > > > > > > > > I have removed the content related to 'resistance > > > > > > value', we > > > > > > use > > > > > > 'RSEL' instead of 'resistance value'. > > This is wrong. Sorry, I think I may not have expressed myself clearly. What I meant is that the attribute 'mediatek,rsel-resistance-in-si-unit' is not supported. In the dts, can write the resistance value, for example: bias-pull-up=<1000>, but can't use 'mediatek,rsel-resistance-in-si-unit = <xxx>'. > > > > > > > > > > > So the value in Ohms was removed? I assume above do not have > > > > > known > > > > > value > > > > > in Ohms? > > > > > > > > Yes, value in Ohns was removed, no code have knowm value. > > > > > > Does the hardware have known value in Ohms? > > It does. > > > > > What do you mean by 'hardware'? When writing to the rsel > > register, > > the value written is 0-7. > > > > Hardware means "the pin controller of the mt8196 SoC" :-) > > Anyway. > > The RSEL registers' function is to select a specific resistance value > to > pullup/down a pin, or a group of pins. > > Devicetree bindings require to specify values in known units, so in > device tree > you *need* to specify the RSEL resistance in Ohms. > > You cannot specify RSEL register value in device-tree. That's > unacceptable. > > Regards, > Angelo Yes, I understand what you mean. However, I was referring to writing the rsel register in the driver, not in dts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > > > + For pull down type is normal, it doesn't > > > > > > > > need > > > > > > > > add > > > > > > > > RSEL & R1R0. > > > > > > > > + For pull down type is PUPD/R0/R1 type, > > > > > > > > it > > > > > > > > can > > > > > > > > add > > > > > > > > R1R0 define to > > > > > > > > + set different resistance. It can support > > > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > > > & > > > > > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > > > > > + For pull down type is PD/RSEL, it can > > > > > > > > add > > > > > > > > RSEL > > > > > > > > define to set > > > > > > > > + different resistance. It can support > > > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > > > define in > > > > > > > > + mt8196. > > > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196- > > > > > > > > pinfunc.h > > > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > new file mode 100644 > > > > > > > > index 000000000000..bf0c8374407c > > > > > > > > --- /dev/null > > > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > @@ -0,0 +1,1572 @@ > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2- > > > > > > > > Clause > > > > > > > > */ > > > > > > > > +/* > > > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > > > + */ > > > > > > > > + > > > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > > > +#define __MT8196_PINFUNC_H > > > > > > > > + > > > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > > > + > > > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | > > > > > > > > 1) > > > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | > > > > > > > > 3) > > > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) > > > > > > > > | > > > > > > > > 4) > > > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > 5) > > > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) > > > > > > > > | > > > > > > > > 6) > > > > > > > > > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > > > > > reminded > > > > > > > about > > > > > > > it, so you responded that yopu will change something, but > > > > > > > I > > > > > > > do > > > > > > > not > > > > > > > see > > > > > > > any changes. > > > > > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > > > > > These two examples where you claim you will change > > > > > > > something, > > > > > > > but > > > > > > > send > > > > > > > the same. I skipped the rest of the patch. > > > > > > > > > > > > Thank you for your patient response, here is my > > > > > > explanation > > > > > > for > > > > > > you > > > > > > question: > > > > > > > > > > > > In v1, I undertand that you meant I didn't sent a real > > > > > > binding, > > > > > > and > > > > > > > > > > > > > > > The comment is under specific lines, so I said these defines > > > > > are > > > > > not > > > > > a > > > > > real binding. You sent them again, but they are still not > > > > > bindings, > > > > > because they are not used in the driver. Maybe the usage is > > > > > convoluted, > > > > > so which part of implementation are these connecting with > > > > > DTS? > > > > > IOW, > > > > > which part of driver relies on the binding? > > > > > > > > I got you. This binding define many macros, which will be > > > > used > > > > for > > > > 'pinmux' setting in the DTS. The usage like this: > > > > > > > > adsp_uart_pins: adsp-uart-pins { > > > > pins-tx-rx { > > > > pinmux = > > > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > > > <PINMUX_GPIO36__FUNC_I1_ADSP_ > > > > URXD0 > > > > > ; > > > > > > > > }; > > > > }; > > > > > > > > > That's DTS, not driver, so not a binding. Drop the header from > > > bindings. > > > > Sorry, I don't quite understand the relationship between binding > > and > > driver. Driver will parse this macro to get gpio number and > > function. > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-21 9:56 ` Cathy Xu (许华婷) @ 2025-01-21 10:03 ` Chen-Yu Tsai 2025-02-17 9:45 ` Cathy Xu (许华婷) 0 siblings, 1 reply; 17+ messages in thread From: Chen-Yu Tsai @ 2025-01-21 10:03 UTC (permalink / raw) To: Cathy Xu (许华婷) Cc: AngeloGioacchino Del Regno, krzk@kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org On Tue, Jan 21, 2025 at 5:58 PM Cathy Xu (许华婷) <ot_cathy.xu@mediatek.com> wrote: > > On Mon, 2025-01-20 at 13:42 +0100, AngeloGioacchino Del Regno wrote: > > External email : Please do not click links or open attachments until > > you have verified the sender or the content. > > > > > > Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > > > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: > > > > External email : Please do not click links or open attachments > > > > until > > > > you have verified the sender or the content. > > > > > > > > > > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski wrote: > > > > > > External email : Please do not click links or open > > > > > > attachments > > > > > > until > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > > > > + bias-pull-down: > > > > > > > > > + oneOf: > > > > > > > > > + - type: boolean > > > > > > > > > + - enum: [100, 101, 102, 103] > > > > > > > > > + description: mt8196 pull down > > > > > > > > > PUPD/R0/R1 > > > > > > > > > type > > > > > > > > > define value. > > > > > > > > > + - enum: [200, 201, 202, 203, 204, 205, > > > > > > > > > 206, > > > > > > > > > 207] > > > > > > > > > + description: mt8196 pull down RSEL > > > > > > > > > type > > > > > > > > > define > > > > > > > > > value. > > > > > > > > > > > > > > > > Not much improved. > > > > > > > > > > > > > > I have removed the content related to 'resistance > > > > > > > value', we > > > > > > > use > > > > > > > 'RSEL' instead of 'resistance value'. > > > > This is wrong. > > Sorry, I think I may not have expressed myself clearly. What I meant > is that the attribute 'mediatek,rsel-resistance-in-si-unit' is not > supported. In the dts, can write the resistance value, for example: > bias-pull-up=<1000>, but can't use 'mediatek,rsel-resistance-in-si-unit > = <xxx>'. `mediatek,rsel-resistance-in-si-unit` is supported in drivers/pinctrl/mediatek/pinctrl-paris.c Angelo is requesting that you continue that support and make it exclusive, i.e. not support the RSEL macro magic numbers, and _only_ support ohm values, in the device tree. ChenYu > > > > > > > > > > > > So the value in Ohms was removed? I assume above do not have > > > > > > known > > > > > > value > > > > > > in Ohms? > > > > > > > > > > Yes, value in Ohns was removed, no code have knowm value. > > > > > > > > Does the hardware have known value in Ohms? > > > > It does. > > > > > > > > What do you mean by 'hardware'? When writing to the rsel > > > register, > > > the value written is 0-7. > > > > > > > Hardware means "the pin controller of the mt8196 SoC" :-) > > > > Anyway. > > > > The RSEL registers' function is to select a specific resistance value > > to > > pullup/down a pin, or a group of pins. > > > > Devicetree bindings require to specify values in known units, so in > > device tree > > you *need* to specify the RSEL resistance in Ohms. > > > > You cannot specify RSEL register value in device-tree. That's > > unacceptable. > > > > Regards, > > Angelo > > Yes, I understand what you mean. However, I was referring to writing > the rsel register in the driver, not in dts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > > > > + For pull down type is normal, it doesn't > > > > > > > > > need > > > > > > > > > add > > > > > > > > > RSEL & R1R0. > > > > > > > > > + For pull down type is PUPD/R0/R1 type, > > > > > > > > > it > > > > > > > > > can > > > > > > > > > add > > > > > > > > > R1R0 define to > > > > > > > > > + set different resistance. It can support > > > > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > > > > & > > > > > > > > > + "MTK_PUPD_SET_R1R0_11" define in mt8196. > > > > > > > > > + For pull down type is PD/RSEL, it can > > > > > > > > > add > > > > > > > > > RSEL > > > > > > > > > define to set > > > > > > > > > + different resistance. It can support > > > > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > > > > define in > > > > > > > > > + mt8196. > > > > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196- > > > > > > > > > pinfunc.h > > > > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > new file mode 100644 > > > > > > > > > index 000000000000..bf0c8374407c > > > > > > > > > --- /dev/null > > > > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > @@ -0,0 +1,1572 @@ > > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2- > > > > > > > > > Clause > > > > > > > > > */ > > > > > > > > > +/* > > > > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > > > > + */ > > > > > > > > > + > > > > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > > > > +#define __MT8196_PINFUNC_H > > > > > > > > > + > > > > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > > > > + > > > > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) > > > > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK (MTK_PIN_NO(0) | > > > > > > > > > 1) > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO (MTK_PIN_NO(0) | > > > > > > > > > 3) > > > > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK (MTK_PIN_NO(0) > > > > > > > > > | > > > > > > > > > 4) > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > 5) > > > > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO (MTK_PIN_NO(0) > > > > > > > > > | > > > > > > > > > 6) > > > > > > > > > > > > > > > > I do not see how you resolved my comment from v1. In v2 I > > > > > > > > reminded > > > > > > > > about > > > > > > > > it, so you responded that yopu will change something, but > > > > > > > > I > > > > > > > > do > > > > > > > > not > > > > > > > > see > > > > > > > > any changes. > > > > > > > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > > > > > > > These two examples where you claim you will change > > > > > > > > something, > > > > > > > > but > > > > > > > > send > > > > > > > > the same. I skipped the rest of the patch. > > > > > > > > > > > > > > Thank you for your patient response, here is my > > > > > > > explanation > > > > > > > for > > > > > > > you > > > > > > > question: > > > > > > > > > > > > > > In v1, I undertand that you meant I didn't sent a real > > > > > > > binding, > > > > > > > and > > > > > > > > > > > > > > > > > > The comment is under specific lines, so I said these defines > > > > > > are > > > > > > not > > > > > > a > > > > > > real binding. You sent them again, but they are still not > > > > > > bindings, > > > > > > because they are not used in the driver. Maybe the usage is > > > > > > convoluted, > > > > > > so which part of implementation are these connecting with > > > > > > DTS? > > > > > > IOW, > > > > > > which part of driver relies on the binding? > > > > > > > > > > I got you. This binding define many macros, which will be > > > > > used > > > > > for > > > > > 'pinmux' setting in the DTS. The usage like this: > > > > > > > > > > adsp_uart_pins: adsp-uart-pins { > > > > > pins-tx-rx { > > > > > pinmux = > > > > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > > > > <PINMUX_GPIO36__FUNC_I1_ADSP_ > > > > > URXD0 > > > > > > ; > > > > > > > > > > }; > > > > > }; > > > > > > > > > > > > That's DTS, not driver, so not a binding. Drop the header from > > > > bindings. > > > > > > Sorry, I don't quite understand the relationship between binding > > > and > > > driver. Driver will parse this macro to get gpio number and > > > function. > > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-01-21 10:03 ` Chen-Yu Tsai @ 2025-02-17 9:45 ` Cathy Xu (许华婷) 2025-02-17 10:24 ` Chen-Yu Tsai 0 siblings, 1 reply; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-02-17 9:45 UTC (permalink / raw) To: wenst@chromium.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), krzk@kernel.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Tue, 2025-01-21 at 18:03 +0800, Chen-Yu Tsai wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Tue, Jan 21, 2025 at 5:58 PM Cathy Xu (许华婷) < > ot_cathy.xu@mediatek.com> wrote: > > > > On Mon, 2025-01-20 at 13:42 +0100, AngeloGioacchino Del Regno > > wrote: > > > External email : Please do not click links or open attachments > > > until > > > you have verified the sender or the content. > > > > > > > > > Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > > > > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: > > > > > External email : Please do not click links or open > > > > > attachments > > > > > until > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski > > > > > > wrote: > > > > > > > External email : Please do not click links or open > > > > > > > attachments > > > > > > > until > > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > > > > > + bias-pull-down: > > > > > > > > > > + oneOf: > > > > > > > > > > + - type: boolean > > > > > > > > > > + - enum: [100, 101, 102, 103] > > > > > > > > > > + description: mt8196 pull down > > > > > > > > > > PUPD/R0/R1 > > > > > > > > > > type > > > > > > > > > > define value. > > > > > > > > > > + - enum: [200, 201, 202, 203, 204, > > > > > > > > > > 205, > > > > > > > > > > 206, > > > > > > > > > > 207] > > > > > > > > > > + description: mt8196 pull down RSEL > > > > > > > > > > type > > > > > > > > > > define > > > > > > > > > > value. > > > > > > > > > > > > > > > > > > Not much improved. > > > > > > > > > > > > > > > > I have removed the content related to 'resistance > > > > > > > > value', we > > > > > > > > use > > > > > > > > 'RSEL' instead of 'resistance value'. > > > > > > This is wrong. > > > > Sorry, I think I may not have expressed myself clearly. What I > > meant > > is that the attribute 'mediatek,rsel-resistance-in-si-unit' is not > > supported. In the dts, can write the resistance value, for example: > > bias-pull-up=<1000>, but can't use 'mediatek,rsel-resistance-in-si- > > unit > > = <xxx>'. > > `mediatek,rsel-resistance-in-si-unit` is supported in > drivers/pinctrl/mediatek/pinctrl-paris.c > > Angelo is requesting that you continue that support and make it > exclusive, i.e. not support the RSEL macro magic numbers, and > _only_ support ohm values, in the device tree. > > ChenYu Thank you for your response. Can I understand that in next version, I should remove the RSEL macro magic numbers and add `mediatek,rsel- resistance-in-si-unit`? > > > > > > > > > > > > > > > So the value in Ohms was removed? I assume above do not > > > > > > > have > > > > > > > known > > > > > > > value > > > > > > > in Ohms? > > > > > > > > > > > > Yes, value in Ohns was removed, no code have knowm > > > > > > value. > > > > > > > > > > Does the hardware have known value in Ohms? > > > > > > It does. > > > > > > > > > > > What do you mean by 'hardware'? When writing to the rsel > > > > register, > > > > the value written is 0-7. > > > > > > > > > > Hardware means "the pin controller of the mt8196 SoC" :-) > > > > > > Anyway. > > > > > > The RSEL registers' function is to select a specific resistance > > > value > > > to > > > pullup/down a pin, or a group of pins. > > > > > > Devicetree bindings require to specify values in known units, so > > > in > > > device tree > > > you *need* to specify the RSEL resistance in Ohms. > > > > > > You cannot specify RSEL register value in device-tree. That's > > > unacceptable. > > > > > > Regards, > > > Angelo > > > > Yes, I understand what you mean. However, I was referring to > > writing > > the rsel register in the driver, not in dts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > > > > > + For pull down type is normal, it > > > > > > > > > > doesn't > > > > > > > > > > need > > > > > > > > > > add > > > > > > > > > > RSEL & R1R0. > > > > > > > > > > + For pull down type is PUPD/R0/R1 > > > > > > > > > > type, > > > > > > > > > > it > > > > > > > > > > can > > > > > > > > > > add > > > > > > > > > > R1R0 define to > > > > > > > > > > + set different resistance. It can > > > > > > > > > > support > > > > > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > > > > > & > > > > > > > > > > + "MTK_PUPD_SET_R1R0_11" define in > > > > > > > > > > mt8196. > > > > > > > > > > + For pull down type is PD/RSEL, it > > > > > > > > > > can > > > > > > > > > > add > > > > > > > > > > RSEL > > > > > > > > > > define to set > > > > > > > > > > + different resistance. It can support > > > > > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > > > > > define in > > > > > > > > > > + mt8196. > > > > > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196- > > > > > > > > > > pinfunc.h > > > > > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > > new file mode 100644 > > > > > > > > > > index 000000000000..bf0c8374407c > > > > > > > > > > --- /dev/null > > > > > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > > @@ -0,0 +1,1572 @@ > > > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2- > > > > > > > > > > Clause > > > > > > > > > > */ > > > > > > > > > > +/* > > > > > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > > > > > + */ > > > > > > > > > > + > > > > > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > > > > > +#define __MT8196_PINFUNC_H > > > > > > > > > > + > > > > > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > > > > > + > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | > > > > > > > > > > 0) > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > 1) > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > 3) > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 4) > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > 5) > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 6) > > > > > > > > > > > > > > > > > > I do not see how you resolved my comment from v1. In > > > > > > > > > v2 I > > > > > > > > > reminded > > > > > > > > > about > > > > > > > > > it, so you responded that yopu will change something, > > > > > > > > > but > > > > > > > > > I > > > > > > > > > do > > > > > > > > > not > > > > > > > > > see > > > > > > > > > any changes. > > > > > > > > > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > > > > > > > > > These two examples where you claim you will change > > > > > > > > > something, > > > > > > > > > but > > > > > > > > > send > > > > > > > > > the same. I skipped the rest of the patch. > > > > > > > > > > > > > > > > Thank you for your patient response, here is my > > > > > > > > explanation > > > > > > > > for > > > > > > > > you > > > > > > > > question: > > > > > > > > > > > > > > > > In v1, I undertand that you meant I didn't sent a > > > > > > > > real > > > > > > > > binding, > > > > > > > > and > > > > > > > > > > > > > > > > > > > > > The comment is under specific lines, so I said these > > > > > > > defines > > > > > > > are > > > > > > > not > > > > > > > a > > > > > > > real binding. You sent them again, but they are still not > > > > > > > bindings, > > > > > > > because they are not used in the driver. Maybe the usage > > > > > > > is > > > > > > > convoluted, > > > > > > > so which part of implementation are these connecting with > > > > > > > DTS? > > > > > > > IOW, > > > > > > > which part of driver relies on the binding? > > > > > > > > > > > > I got you. This binding define many macros, which will > > > > > > be > > > > > > used > > > > > > for > > > > > > 'pinmux' setting in the DTS. The usage like this: > > > > > > > > > > > > adsp_uart_pins: adsp-uart-pins { > > > > > > pins-tx-rx { > > > > > > pinmux = > > > > > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > > > > > <PINMUX_GPIO36__FUNC_I1_A > > > > > > DSP_ > > > > > > URXD0 > > > > > > > ; > > > > > > > > > > > > }; > > > > > > }; > > > > > > > > > > > > > > > That's DTS, not driver, so not a binding. Drop the header > > > > > from > > > > > bindings. > > > > > > > > Sorry, I don't quite understand the relationship between > > > > binding > > > > and > > > > driver. Driver will parse this macro to get gpio number and > > > > function. > > > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-02-17 9:45 ` Cathy Xu (许华婷) @ 2025-02-17 10:24 ` Chen-Yu Tsai 2025-02-19 8:54 ` Cathy Xu (许华婷) 0 siblings, 1 reply; 17+ messages in thread From: Chen-Yu Tsai @ 2025-02-17 10:24 UTC (permalink / raw) To: Cathy Xu (许华婷) Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), krzk@kernel.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, Guodong Liu (刘国栋), linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Mon, Feb 17, 2025 at 5:45 PM Cathy Xu (许华婷) <ot_cathy.xu@mediatek.com> wrote: > > On Tue, 2025-01-21 at 18:03 +0800, Chen-Yu Tsai wrote: > > External email : Please do not click links or open attachments until > > you have verified the sender or the content. > > > > > > On Tue, Jan 21, 2025 at 5:58 PM Cathy Xu (许华婷) < > > ot_cathy.xu@mediatek.com> wrote: > > > > > > On Mon, 2025-01-20 at 13:42 +0100, AngeloGioacchino Del Regno > > > wrote: > > > > External email : Please do not click links or open attachments > > > > until > > > > you have verified the sender or the content. > > > > > > > > > > > > Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > > > > > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski wrote: > > > > > > External email : Please do not click links or open > > > > > > attachments > > > > > > until > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > > > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski > > > > > > > wrote: > > > > > > > > External email : Please do not click links or open > > > > > > > > attachments > > > > > > > > until > > > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > > > > > > + bias-pull-down: > > > > > > > > > > > + oneOf: > > > > > > > > > > > + - type: boolean > > > > > > > > > > > + - enum: [100, 101, 102, 103] > > > > > > > > > > > + description: mt8196 pull down > > > > > > > > > > > PUPD/R0/R1 > > > > > > > > > > > type > > > > > > > > > > > define value. > > > > > > > > > > > + - enum: [200, 201, 202, 203, 204, > > > > > > > > > > > 205, > > > > > > > > > > > 206, > > > > > > > > > > > 207] > > > > > > > > > > > + description: mt8196 pull down RSEL > > > > > > > > > > > type > > > > > > > > > > > define > > > > > > > > > > > value. > > > > > > > > > > > > > > > > > > > > Not much improved. > > > > > > > > > > > > > > > > > > I have removed the content related to 'resistance > > > > > > > > > value', we > > > > > > > > > use > > > > > > > > > 'RSEL' instead of 'resistance value'. > > > > > > > > This is wrong. > > > > > > Sorry, I think I may not have expressed myself clearly. What I > > > meant > > > is that the attribute 'mediatek,rsel-resistance-in-si-unit' is not > > > supported. In the dts, can write the resistance value, for example: > > > bias-pull-up=<1000>, but can't use 'mediatek,rsel-resistance-in-si- > > > unit > > > = <xxx>'. > > > > `mediatek,rsel-resistance-in-si-unit` is supported in > > drivers/pinctrl/mediatek/pinctrl-paris.c > > > > Angelo is requesting that you continue that support and make it > > exclusive, i.e. not support the RSEL macro magic numbers, and > > _only_ support ohm values, in the device tree. > > > > ChenYu > > Thank you for your response. Can I understand that in next version, I > should remove the RSEL macro magic numbers and add `mediatek,rsel- > resistance-in-si-unit`? You should remove the RSEL macro magic numbers, and add an option to |struct mtk_pin_soc| so that the argument to "bias-pull-up" are always treated as values in SI units as if "mediatek,rsel-resistance-in-si-unit" was set in the DT. ChenYu > > > > > > > > > > > > > > > > > > So the value in Ohms was removed? I assume above do not > > > > > > > > have > > > > > > > > known > > > > > > > > value > > > > > > > > in Ohms? > > > > > > > > > > > > > > Yes, value in Ohns was removed, no code have knowm > > > > > > > value. > > > > > > > > > > > > Does the hardware have known value in Ohms? > > > > > > > > It does. > > > > > > > > > > > > > > What do you mean by 'hardware'? When writing to the rsel > > > > > register, > > > > > the value written is 0-7. > > > > > > > > > > > > > Hardware means "the pin controller of the mt8196 SoC" :-) > > > > > > > > Anyway. > > > > > > > > The RSEL registers' function is to select a specific resistance > > > > value > > > > to > > > > pullup/down a pin, or a group of pins. > > > > > > > > Devicetree bindings require to specify values in known units, so > > > > in > > > > device tree > > > > you *need* to specify the RSEL resistance in Ohms. > > > > > > > > You cannot specify RSEL register value in device-tree. That's > > > > unacceptable. > > > > > > > > Regards, > > > > Angelo > > > > > > Yes, I understand what you mean. However, I was referring to > > > writing > > > the rsel register in the driver, not in dts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > > > > > > + For pull down type is normal, it > > > > > > > > > > > doesn't > > > > > > > > > > > need > > > > > > > > > > > add > > > > > > > > > > > RSEL & R1R0. > > > > > > > > > > > + For pull down type is PUPD/R0/R1 > > > > > > > > > > > type, > > > > > > > > > > > it > > > > > > > > > > > can > > > > > > > > > > > add > > > > > > > > > > > R1R0 define to > > > > > > > > > > > + set different resistance. It can > > > > > > > > > > > support > > > > > > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > > > > > > & > > > > > > > > > > > + "MTK_PUPD_SET_R1R0_11" define in > > > > > > > > > > > mt8196. > > > > > > > > > > > + For pull down type is PD/RSEL, it > > > > > > > > > > > can > > > > > > > > > > > add > > > > > > > > > > > RSEL > > > > > > > > > > > define to set > > > > > > > > > > > + different resistance. It can support > > > > > > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > > > > > > define in > > > > > > > > > > > + mt8196. > > > > > > > > > > > diff --git a/include/dt-bindings/pinctrl/mt8196- > > > > > > > > > > > pinfunc.h > > > > > > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > > > new file mode 100644 > > > > > > > > > > > index 000000000000..bf0c8374407c > > > > > > > > > > > --- /dev/null > > > > > > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > > > @@ -0,0 +1,1572 @@ > > > > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2- > > > > > > > > > > > Clause > > > > > > > > > > > */ > > > > > > > > > > > +/* > > > > > > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > > > > > > + * Author: Guodong Liu <Guodong.Liu@mediatek.com> > > > > > > > > > > > + */ > > > > > > > > > > > + > > > > > > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > > > > > > +#define __MT8196_PINFUNC_H > > > > > > > > > > > + > > > > > > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > > > > > > + > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | > > > > > > > > > > > 0) > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > 1) > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > 3) > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK > > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 4) > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > 5) > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO > > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 6) > > > > > > > > > > > > > > > > > > > > I do not see how you resolved my comment from v1. In > > > > > > > > > > v2 I > > > > > > > > > > reminded > > > > > > > > > > about > > > > > > > > > > it, so you responded that yopu will change something, > > > > > > > > > > but > > > > > > > > > > I > > > > > > > > > > do > > > > > > > > > > not > > > > > > > > > > see > > > > > > > > > > any changes. > > > > > > > > > > > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > > > > > > > > > > > These two examples where you claim you will change > > > > > > > > > > something, > > > > > > > > > > but > > > > > > > > > > send > > > > > > > > > > the same. I skipped the rest of the patch. > > > > > > > > > > > > > > > > > > Thank you for your patient response, here is my > > > > > > > > > explanation > > > > > > > > > for > > > > > > > > > you > > > > > > > > > question: > > > > > > > > > > > > > > > > > > In v1, I undertand that you meant I didn't sent a > > > > > > > > > real > > > > > > > > > binding, > > > > > > > > > and > > > > > > > > > > > > > > > > > > > > > > > > The comment is under specific lines, so I said these > > > > > > > > defines > > > > > > > > are > > > > > > > > not > > > > > > > > a > > > > > > > > real binding. You sent them again, but they are still not > > > > > > > > bindings, > > > > > > > > because they are not used in the driver. Maybe the usage > > > > > > > > is > > > > > > > > convoluted, > > > > > > > > so which part of implementation are these connecting with > > > > > > > > DTS? > > > > > > > > IOW, > > > > > > > > which part of driver relies on the binding? > > > > > > > > > > > > > > I got you. This binding define many macros, which will > > > > > > > be > > > > > > > used > > > > > > > for > > > > > > > 'pinmux' setting in the DTS. The usage like this: > > > > > > > > > > > > > > adsp_uart_pins: adsp-uart-pins { > > > > > > > pins-tx-rx { > > > > > > > pinmux = > > > > > > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > > > > > > <PINMUX_GPIO36__FUNC_I1_A > > > > > > > DSP_ > > > > > > > URXD0 > > > > > > > > ; > > > > > > > > > > > > > > }; > > > > > > > }; > > > > > > > > > > > > > > > > > > That's DTS, not driver, so not a binding. Drop the header > > > > > > from > > > > > > bindings. > > > > > > > > > > Sorry, I don't quite understand the relationship between > > > > > binding > > > > > and > > > > > driver. Driver will parse this macro to get gpio number and > > > > > function. > > > > > > > ************* MEDIATEK Confidentiality Notice > ******************** > The information contained in this e-mail message (including any > attachments) may be confidential, proprietary, privileged, or otherwise > exempt from disclosure under applicable laws. It is intended to be > conveyed only to the designated recipient(s). Any use, dissemination, > distribution, printing, retaining or copying of this e-mail (including its > attachments) by unintended recipient(s) is strictly prohibited and may > be unlawful. If you are not an intended recipient of this e-mail, or believe > > that you have received this e-mail in error, please notify the sender > immediately (by replying to this e-mail), delete any and all copies of > this e-mail (including any attachments) from your system, and do not > disclose the content of this e-mail to any other person. Thank you! ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 2025-02-17 10:24 ` Chen-Yu Tsai @ 2025-02-19 8:54 ` Cathy Xu (许华婷) 0 siblings, 0 replies; 17+ messages in thread From: Cathy Xu (许华婷) @ 2025-02-19 8:54 UTC (permalink / raw) To: wenst@chromium.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Lei Xue (薛磊), krzk@kernel.org, devicetree@vger.kernel.org, Wenbin Mei (梅文彬), linus.walleij@linaro.org, linux-gpio@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org, sean.wang@kernel.org, linux-arm-kernel@lists.infradead.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno On Mon, 2025-02-17 at 18:24 +0800, Chen-Yu Tsai wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On Mon, Feb 17, 2025 at 5:45 PM Cathy Xu (许华婷) < > ot_cathy.xu@mediatek.com> wrote: > > > > On Tue, 2025-01-21 at 18:03 +0800, Chen-Yu Tsai wrote: > > > External email : Please do not click links or open attachments > > > until > > > you have verified the sender or the content. > > > > > > > > > On Tue, Jan 21, 2025 at 5:58 PM Cathy Xu (许华婷) < > > > ot_cathy.xu@mediatek.com> wrote: > > > > > > > > On Mon, 2025-01-20 at 13:42 +0100, AngeloGioacchino Del Regno > > > > wrote: > > > > > External email : Please do not click links or open > > > > > attachments > > > > > until > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > Il 20/01/25 10:17, Cathy Xu (许华婷) ha scritto: > > > > > > On Thu, 2025-01-16 at 11:20 +0100, Krzysztof Kozlowski > > > > > > wrote: > > > > > > > External email : Please do not click links or open > > > > > > > attachments > > > > > > > until > > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > > > > On 16/01/2025 09:18, Cathy Xu (许华婷) wrote: > > > > > > > > On Thu, 2025-01-16 at 08:28 +0100, Krzysztof Kozlowski > > > > > > > > wrote: > > > > > > > > > External email : Please do not click links or open > > > > > > > > > attachments > > > > > > > > > until > > > > > > > > > you have verified the sender or the content. > > > > > > > > > > > > > > > > > > > > > > > > > > > On 16/01/2025 03:20, Cathy Xu (许华婷) wrote: > > > > > > > > > > > > + bias-pull-down: > > > > > > > > > > > > + oneOf: > > > > > > > > > > > > + - type: boolean > > > > > > > > > > > > + - enum: [100, 101, 102, 103] > > > > > > > > > > > > + description: mt8196 pull down > > > > > > > > > > > > PUPD/R0/R1 > > > > > > > > > > > > type > > > > > > > > > > > > define value. > > > > > > > > > > > > + - enum: [200, 201, 202, 203, > > > > > > > > > > > > 204, > > > > > > > > > > > > 205, > > > > > > > > > > > > 206, > > > > > > > > > > > > 207] > > > > > > > > > > > > + description: mt8196 pull down > > > > > > > > > > > > RSEL > > > > > > > > > > > > type > > > > > > > > > > > > define > > > > > > > > > > > > value. > > > > > > > > > > > > > > > > > > > > > > Not much improved. > > > > > > > > > > > > > > > > > > > > I have removed the content related to > > > > > > > > > > 'resistance > > > > > > > > > > value', we > > > > > > > > > > use > > > > > > > > > > 'RSEL' instead of 'resistance value'. > > > > > > > > > > This is wrong. > > > > > > > > Sorry, I think I may not have expressed myself clearly. What > > > > I > > > > meant > > > > is that the attribute 'mediatek,rsel-resistance-in-si-unit' is > > > > not > > > > supported. In the dts, can write the resistance value, for > > > > example: > > > > bias-pull-up=<1000>, but can't use 'mediatek,rsel-resistance- > > > > in-si- > > > > unit > > > > = <xxx>'. > > > > > > `mediatek,rsel-resistance-in-si-unit` is supported in > > > drivers/pinctrl/mediatek/pinctrl-paris.c > > > > > > Angelo is requesting that you continue that support and make it > > > exclusive, i.e. not support the RSEL macro magic numbers, and > > > _only_ support ohm values, in the device tree. > > > > > > ChenYu > > > > Thank you for your response. Can I understand that in next > > version, I > > should remove the RSEL macro magic numbers and add `mediatek,rsel- > > resistance-in-si-unit`? > > You should remove the RSEL macro magic numbers, and add an option to > > struct mtk_pin_soc| so that the argument to "bias-pull-up" are > > always > > treated as values in SI units as if "mediatek,rsel-resistance-in-si- > unit" > was set in the DT. > > ChenYu Thank you for your support, it will be fixed in next version. > > > > > > > > > > > > > > > > > > > > > > So the value in Ohms was removed? I assume above do > > > > > > > > > not > > > > > > > > > have > > > > > > > > > known > > > > > > > > > value > > > > > > > > > in Ohms? > > > > > > > > > > > > > > > > Yes, value in Ohns was removed, no code have knowm > > > > > > > > value. > > > > > > > > > > > > > > Does the hardware have known value in Ohms? > > > > > > > > > > It does. > > > > > > > > > > > > > > > > > What do you mean by 'hardware'? When writing to the rsel > > > > > > register, > > > > > > the value written is 0-7. > > > > > > > > > > > > > > > > Hardware means "the pin controller of the mt8196 SoC" :-) > > > > > > > > > > Anyway. > > > > > > > > > > The RSEL registers' function is to select a specific > > > > > resistance > > > > > value > > > > > to > > > > > pullup/down a pin, or a group of pins. > > > > > > > > > > Devicetree bindings require to specify values in known units, > > > > > so > > > > > in > > > > > device tree > > > > > you *need* to specify the RSEL resistance in Ohms. > > > > > > > > > > You cannot specify RSEL register value in device-tree. That's > > > > > unacceptable. > > > > > > > > > > Regards, > > > > > Angelo > > > > > > > > Yes, I understand what you mean. However, I was referring to > > > > writing > > > > the rsel register in the driver, not in dts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > + description: | > > > > > > > > > > > > + For pull down type is normal, it > > > > > > > > > > > > doesn't > > > > > > > > > > > > need > > > > > > > > > > > > add > > > > > > > > > > > > RSEL & R1R0. > > > > > > > > > > > > + For pull down type is PUPD/R0/R1 > > > > > > > > > > > > type, > > > > > > > > > > > > it > > > > > > > > > > > > can > > > > > > > > > > > > add > > > > > > > > > > > > R1R0 define to > > > > > > > > > > > > + set different resistance. It can > > > > > > > > > > > > support > > > > > > > > > > > > "MTK_PUPD_SET_R1R0_00" & > > > > > > > > > > > > + "MTK_PUPD_SET_R1R0_01" & > > > > > > > > > > > > "MTK_PUPD_SET_R1R0_10" > > > > > > > > > > > > & > > > > > > > > > > > > + "MTK_PUPD_SET_R1R0_11" define in > > > > > > > > > > > > mt8196. > > > > > > > > > > > > + For pull down type is PD/RSEL, > > > > > > > > > > > > it > > > > > > > > > > > > can > > > > > > > > > > > > add > > > > > > > > > > > > RSEL > > > > > > > > > > > > define to set > > > > > > > > > > > > + different resistance. It can > > > > > > > > > > > > support > > > > > > > > > > > > + "MTK_PULL_SET_RSEL_000" & > > > > > > > > > > > > "MTK_PULL_SET_RSEL_001" & > > > > > > > > > > > > + "MTK_PULL_SET_RSEL_010" & > > > > > > > > > > > > "MTK_PULL_SET_RSEL_011" & > > > > > > > > > > > > + "MTK_PULL_SET_RSEL_100" & > > > > > > > > > > > > "MTK_PULL_SET_RSEL_101" & > > > > > > > > > > > > + "MTK_PULL_SET_RSEL_110" & > > > > > > > > > > > > "MTK_PULL_SET_RSEL_111" > > > > > > > > > > > > define in > > > > > > > > > > > > + mt8196. > > > > > > > > > > > > diff --git a/include/dt- > > > > > > > > > > > > bindings/pinctrl/mt8196- > > > > > > > > > > > > pinfunc.h > > > > > > > > > > > > b/include/dt-bindings/pinctrl/mt8196-pinfunc.h > > > > > > > > > > > > new file mode 100644 > > > > > > > > > > > > index 000000000000..bf0c8374407c > > > > > > > > > > > > --- /dev/null > > > > > > > > > > > > +++ b/include/dt-bindings/pinctrl/mt8196- > > > > > > > > > > > > pinfunc.h > > > > > > > > > > > > @@ -0,0 +1,1572 @@ > > > > > > > > > > > > +/* SPDX-License-Identifier: GPL-2.0-only OR > > > > > > > > > > > > BSD-2- > > > > > > > > > > > > Clause > > > > > > > > > > > > */ > > > > > > > > > > > > +/* > > > > > > > > > > > > + * Copyright (C) 2025 Mediatek Inc. > > > > > > > > > > > > + * Author: Guodong Liu < > > > > > > > > > > > > Guodong.Liu@mediatek.com> > > > > > > > > > > > > + */ > > > > > > > > > > > > + > > > > > > > > > > > > +#ifndef __MT8196_PINFUNC_H > > > > > > > > > > > > +#define __MT8196_PINFUNC_H > > > > > > > > > > > > + > > > > > > > > > > > > +#include <dt-bindings/pinctrl/mt65xx.h> > > > > > > > > > > > > + > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_GPIO0 > > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > > 0) > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_DMIC1_CLK > > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > > 1) > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SPI3_A_MO > > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > > 3) > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_FMI2S_B_LRCK > > > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 4) > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_SCP_DMIC1_CLK > > > > > > > > > > > > (MTK_PIN_NO(0) | > > > > > > > > > > > > 5) > > > > > > > > > > > > +#define PINMUX_GPIO0__FUNC_TP_GPIO14_AO > > > > > > > > > > > > (MTK_PIN_NO(0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 6) > > > > > > > > > > > > > > > > > > > > > > I do not see how you resolved my comment from v1. > > > > > > > > > > > In > > > > > > > > > > > v2 I > > > > > > > > > > > reminded > > > > > > > > > > > about > > > > > > > > > > > it, so you responded that yopu will change > > > > > > > > > > > something, > > > > > > > > > > > but > > > > > > > > > > > I > > > > > > > > > > > do > > > > > > > > > > > not > > > > > > > > > > > see > > > > > > > > > > > any changes. > > > > > > > > > > > > > > > > > > > > > > So explain: how did you resolve my comment? > > > > > > > > > > > > > > > > > > > > > > These two examples where you claim you will > > > > > > > > > > > change > > > > > > > > > > > something, > > > > > > > > > > > but > > > > > > > > > > > send > > > > > > > > > > > the same. I skipped the rest of the patch. > > > > > > > > > > > > > > > > > > > > Thank you for your patient response, here is my > > > > > > > > > > explanation > > > > > > > > > > for > > > > > > > > > > you > > > > > > > > > > question: > > > > > > > > > > > > > > > > > > > > In v1, I undertand that you meant I didn't sent > > > > > > > > > > a > > > > > > > > > > real > > > > > > > > > > binding, > > > > > > > > > > and > > > > > > > > > > > > > > > > > > > > > > > > > > > The comment is under specific lines, so I said these > > > > > > > > > defines > > > > > > > > > are > > > > > > > > > not > > > > > > > > > a > > > > > > > > > real binding. You sent them again, but they are still > > > > > > > > > not > > > > > > > > > bindings, > > > > > > > > > because they are not used in the driver. Maybe the > > > > > > > > > usage > > > > > > > > > is > > > > > > > > > convoluted, > > > > > > > > > so which part of implementation are these connecting > > > > > > > > > with > > > > > > > > > DTS? > > > > > > > > > IOW, > > > > > > > > > which part of driver relies on the binding? > > > > > > > > > > > > > > > > I got you. This binding define many macros, which > > > > > > > > will > > > > > > > > be > > > > > > > > used > > > > > > > > for > > > > > > > > 'pinmux' setting in the DTS. The usage like this: > > > > > > > > > > > > > > > > adsp_uart_pins: adsp-uart-pins { > > > > > > > > pins-tx-rx { > > > > > > > > pinmux = > > > > > > > > <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>, > > > > > > > > <PINMUX_GPIO36__FUNC_ > > > > > > > > I1_A > > > > > > > > DSP_ > > > > > > > > URXD0 > > > > > > > > > ; > > > > > > > > > > > > > > > > }; > > > > > > > > }; > > > > > > > > > > > > > > > > > > > > > That's DTS, not driver, so not a binding. Drop the header > > > > > > > from > > > > > > > bindings. > > > > > > > > > > > > Sorry, I don't quite understand the relationship between > > > > > > binding > > > > > > and > > > > > > driver. Driver will parse this macro to get gpio number and > > > > > > function. > > > > > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 2/2] pinctrl: mediatek: add mt8196 driver 2025-01-15 6:35 [PATCH v3 0/2] MediaTek pinctrl patch on mt8196 Cathy Xu 2025-01-15 6:35 ` [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 Cathy Xu @ 2025-01-15 6:35 ` Cathy Xu 1 sibling, 0 replies; 17+ messages in thread From: Cathy Xu @ 2025-01-15 6:35 UTC (permalink / raw) To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Sean Wang, Lei Xue, wenbin.mei Cc: linux-gpio, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Guodong Liu, kernel test robot, Cathy Xu From: Guodong Liu <guodong.liu@mediatek.com> Add pinctrl driver support for MediaTek Soc mt8196. Reported-by: kernel test robot <lkp@intel.com> Closes:https://lore.kernel.org/oe-kbuild-all/202501112005.DuwEi3Ig-lkp@intel.com/ Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com> --- drivers/pinctrl/mediatek/Kconfig | 12 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8196.c | 1764 +++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h | 2789 +++++++++++++++++ 4 files changed, 4566 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8196.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 58f32818a0e6..b59d94a0fe3b 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -263,6 +263,18 @@ config PINCTRL_MT8195 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8196 + bool "MediaTek MT8196 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + help + Say yes here to support pin controller and gpio driver + on MediaTek MT8196 SoC. + In MTK platform, we support virtual gpio and use it to + map specific eint which doesn't have real gpio pin. + config PINCTRL_MT8365 bool "MediaTek MT8365 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 721ae83476d0..08e7239fcd8b 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8196) += pinctrl-mt8196.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8196.c b/drivers/pinctrl/mediatek/pinctrl-mt8196.c new file mode 100644 index 000000000000..822ceb8dc268 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8196.c @@ -0,0 +1,1764 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Mediatek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + */ + +#include <linux/module.h> +#include "pinctrl-mtk-mt8196.h" +#include "pinctrl-paris.h" + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt8196_pin_mode_range[] = { + PIN_FIELD(0, 270, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8196_pin_dir_range[] = { + PIN_FIELD(0, 270, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_di_range[] = { + PIN_FIELD(0, 270, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_do_range[] = { + PIN_FIELD(0, 270, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(4, 4, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(5, 5, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(6, 6, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(7, 7, 11, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(8, 8, 11, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(9, 9, 9, 0x0120, 0x10, 13, 1), + PIN_FIELD_BASE(10, 10, 9, 0x0120, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x0120, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 3, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 2, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(22, 22, 2, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(23, 23, 2, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(24, 24, 2, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, 2, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(28, 28, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 2, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(31, 31, 2, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(32, 32, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(34, 34, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(35, 35, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(36, 36, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(38, 38, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(42, 42, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(43, 43, 8, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(44, 44, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 8, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(46, 46, 8, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(47, 47, 8, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(48, 48, 8, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 8, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(50, 50, 8, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(51, 51, 8, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(52, 52, 9, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x0120, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x0120, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0120, 0x10, 19, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0120, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0120, 0x10, 14, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0120, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0120, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x0120, 0x10, 16, 1), + PIN_FIELD_BASE(67, 67, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(69, 69, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(71, 71, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(72, 72, 9, 0x0120, 0x10, 18, 1), + PIN_FIELD_BASE(73, 73, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(74, 74, 9, 0x0120, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(82, 82, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(83, 83, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(84, 84, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(86, 86, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(88, 88, 11, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(89, 89, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(90, 90, 11, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(91, 91, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(92, 92, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, 12, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(94, 94, 12, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(96, 96, 12, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(97, 97, 12, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(98, 98, 12, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(99, 99, 12, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(100, 100, 12, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(101, 101, 12, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(102, 102, 12, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(103, 103, 12, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(104, 104, 12, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(105, 105, 12, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(106, 106, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(108, 108, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(109, 109, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(110, 110, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(112, 112, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(113, 113, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(114, 114, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(115, 115, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(116, 116, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(117, 117, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0120, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0120, 0x10, 7, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0120, 0x10, 9, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0120, 0x10, 8, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0120, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0120, 0x10, 4, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0120, 0x10, 5, 1), + PIN_FIELD_BASE(125, 125, 7, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(143, 143, 4, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(144, 144, 4, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(145, 145, 4, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(146, 146, 4, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(147, 147, 4, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(148, 148, 4, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(149, 149, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(150, 150, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(151, 151, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(152, 152, 4, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(153, 153, 4, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(154, 154, 4, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(155, 155, 4, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(156, 156, 4, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(157, 157, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(158, 158, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(159, 159, 2, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 3, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(162, 162, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(163, 163, 3, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(164, 164, 3, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(165, 165, 3, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(166, 166, 3, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(167, 167, 3, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(168, 168, 3, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(169, 169, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(170, 170, 3, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(171, 171, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(172, 172, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(173, 173, 3, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(175, 175, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(176, 176, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(179, 179, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(187, 187, 13, 0x0110, 0x10, 14, 1), + PIN_FIELD_BASE(188, 188, 13, 0x0110, 0x10, 4, 1), + PIN_FIELD_BASE(189, 189, 13, 0x0110, 0x10, 9, 1), + PIN_FIELD_BASE(190, 190, 13, 0x0110, 0x10, 5, 1), + PIN_FIELD_BASE(191, 191, 13, 0x0110, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 13, 0x0110, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x0110, 0x10, 15, 1), + PIN_FIELD_BASE(194, 194, 13, 0x0110, 0x10, 6, 1), + PIN_FIELD_BASE(195, 195, 13, 0x0110, 0x10, 11, 1), + PIN_FIELD_BASE(196, 196, 13, 0x0110, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x0110, 0x10, 16, 1), + PIN_FIELD_BASE(198, 198, 13, 0x0110, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 13, 0x0110, 0x10, 12, 1), + PIN_FIELD_BASE(200, 200, 13, 0x0110, 0x10, 19, 1), + PIN_FIELD_BASE(201, 201, 13, 0x0110, 0x10, 22, 1), + PIN_FIELD_BASE(202, 202, 13, 0x0110, 0x10, 8, 1), + PIN_FIELD_BASE(203, 203, 13, 0x0110, 0x10, 13, 1), + PIN_FIELD_BASE(204, 204, 13, 0x0110, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x0110, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x0110, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(208, 208, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(209, 209, 13, 0x0110, 0x10, 17, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0130, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0130, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0130, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0130, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x0110, 0x10, 20, 1), + PIN_FIELD_BASE(215, 215, 13, 0x0110, 0x10, 21, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(217, 217, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(218, 218, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(219, 219, 14, 0x0130, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0130, 0x10, 11, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0130, 0x10, 12, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0130, 0x10, 22, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0130, 0x10, 21, 1), + PIN_FIELD_BASE(224, 224, 14, 0x0130, 0x10, 5, 1), + PIN_FIELD_BASE(225, 225, 14, 0x0130, 0x10, 6, 1), + PIN_FIELD_BASE(226, 226, 14, 0x0130, 0x10, 7, 1), + PIN_FIELD_BASE(227, 227, 14, 0x0130, 0x10, 8, 1), + PIN_FIELD_BASE(228, 228, 14, 0x0130, 0x10, 9, 1), + PIN_FIELD_BASE(229, 229, 14, 0x0130, 0x10, 10, 1), + PIN_FIELD_BASE(230, 230, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(231, 231, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(232, 232, 15, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(233, 233, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(234, 234, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(235, 235, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(237, 237, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(238, 238, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(239, 239, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(240, 240, 15, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(241, 241, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(242, 242, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(243, 243, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(244, 244, 15, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(245, 245, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(246, 246, 15, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(247, 247, 15, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(248, 248, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(250, 250, 15, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(251, 251, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(252, 252, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(253, 253, 3, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(256, 256, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(257, 257, 3, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(258, 258, 3, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(259, 259, 14, 0x0130, 0x10, 13, 1), + PIN_FIELD_BASE(260, 260, 14, 0x0130, 0x10, 14, 1), + PIN_FIELD_BASE(261, 261, 14, 0x0130, 0x10, 15, 1), + PIN_FIELD_BASE(262, 262, 14, 0x0130, 0x10, 16, 1), + PIN_FIELD_BASE(263, 263, 14, 0x0130, 0x10, 17, 1), + PIN_FIELD_BASE(264, 264, 14, 0x0130, 0x10, 18, 1), + PIN_FIELD_BASE(265, 265, 14, 0x0130, 0x10, 19, 1), + PIN_FIELD_BASE(266, 266, 14, 0x0130, 0x10, 20, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00e0, 0x10, 7, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(60, 60, 9, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(61, 61, 9, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(68, 68, 9, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(69, 69, 9, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(74, 74, 9, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(217, 217, 14, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 14, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(219, 219, 14, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(224, 224, 14, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(225, 225, 14, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(226, 226, 14, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(227, 227, 14, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(228, 228, 14, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(229, 229, 14, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(259, 259, 14, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(260, 260, 14, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(261, 261, 14, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(262, 262, 14, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(263, 263, 14, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(264, 264, 14, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(265, 265, 14, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(266, 266, 14, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(267, 267, 15, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(268, 268, 15, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(269, 269, 15, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(270, 270, 15, 0x0040, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pupd_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x0080, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_r0_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00a0, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_r1_range[] = { + PIN_FIELD_BASE(60, 60, 9, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(127, 127, 7, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(128, 128, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(130, 130, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(131, 131, 7, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(132, 132, 7, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 7, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(135, 135, 7, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(136, 136, 7, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(144, 144, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(145, 145, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(146, 146, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(217, 217, 14, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(218, 218, 14, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(219, 219, 14, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(224, 224, 14, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(225, 225, 14, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(226, 226, 14, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(227, 227, 14, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(228, 228, 14, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(229, 229, 14, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(259, 259, 14, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(260, 260, 14, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(261, 261, 14, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(262, 262, 14, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(263, 263, 14, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(264, 264, 14, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(265, 265, 14, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(266, 266, 14, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(267, 267, 15, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(268, 268, 15, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(269, 269, 15, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(270, 270, 15, 0x00b0, 0x10, 1, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 9, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x00c0, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 9, 0x00c0, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(74, 74, 9, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x00d0, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x00d0, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x00d0, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x00d0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x00d0, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x00d0, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x00d0, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x00d0, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x00d0, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x00d0, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x00d0, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x00d0, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x00d0, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x00d0, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x00d0, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x00d0, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x00d0, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x00d0, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x00d0, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x00d0, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x00d0, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x00d0, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(221, 221, 14, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(222, 222, 14, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(223, 223, 14, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0090, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, 11, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(3, 3, 11, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, 11, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(5, 5, 11, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(6, 6, 11, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(7, 7, 11, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, 11, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, 9, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(10, 10, 9, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(11, 11, 8, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(12, 12, 9, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(17, 17, 6, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(18, 18, 6, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, 6, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 2, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(27, 27, 2, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, 2, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(29, 29, 2, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 2, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(31, 31, 2, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(36, 36, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(37, 37, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(38, 38, 1, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(39, 39, 8, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 8, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(44, 44, 8, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(45, 45, 8, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 8, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(47, 47, 8, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(48, 48, 8, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(49, 49, 8, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(50, 50, 8, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(51, 51, 8, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(52, 52, 9, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(53, 53, 9, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(54, 54, 9, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 9, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(56, 56, 9, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(57, 57, 9, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(58, 58, 9, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(59, 59, 9, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 9, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 9, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(63, 63, 9, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(64, 64, 9, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 9, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(66, 66, 9, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(67, 67, 9, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(68, 68, 9, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(69, 69, 9, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(70, 70, 9, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(71, 71, 9, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(72, 72, 9, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(73, 73, 9, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(74, 74, 9, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(75, 75, 10, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(76, 76, 10, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 10, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(78, 78, 10, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(79, 79, 10, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 10, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 11, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(82, 82, 11, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(83, 83, 11, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(84, 84, 11, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(85, 85, 11, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(86, 86, 11, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(87, 87, 11, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(88, 88, 11, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(89, 89, 11, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(90, 90, 11, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(91, 91, 12, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(92, 92, 12, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(93, 93, 12, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 12, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 12, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(96, 96, 12, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 12, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 12, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 12, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(100, 100, 12, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(101, 101, 12, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(102, 102, 12, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(103, 103, 12, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 12, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(105, 105, 12, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(106, 106, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(107, 107, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(109, 109, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(110, 110, 5, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(111, 111, 5, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(112, 112, 5, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 5, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(114, 114, 5, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 5, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(116, 116, 5, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 5, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 6, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(119, 119, 6, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(120, 120, 6, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(121, 121, 6, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(122, 122, 6, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, 6, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(124, 124, 6, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(161, 161, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(162, 162, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(163, 163, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(164, 164, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(166, 166, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(168, 168, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(169, 169, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(170, 170, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(171, 171, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(172, 172, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(173, 173, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(174, 174, 1, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(175, 175, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(176, 176, 1, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(177, 177, 1, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(178, 178, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(180, 180, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(181, 181, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(182, 182, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(184, 184, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(185, 185, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(186, 186, 13, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(187, 187, 13, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(188, 188, 13, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(189, 189, 13, 0x00c0, 0x10, 17, 1), + PIN_FIELD_BASE(190, 190, 13, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(191, 191, 13, 0x00c0, 0x10, 18, 1), + PIN_FIELD_BASE(192, 192, 13, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 13, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(194, 194, 13, 0x00c0, 0x10, 14, 1), + PIN_FIELD_BASE(195, 195, 13, 0x00c0, 0x10, 19, 1), + PIN_FIELD_BASE(196, 196, 13, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(197, 197, 13, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(198, 198, 13, 0x00c0, 0x10, 15, 1), + PIN_FIELD_BASE(199, 199, 13, 0x00c0, 0x10, 20, 1), + PIN_FIELD_BASE(200, 200, 13, 0x00c0, 0x10, 22, 1), + PIN_FIELD_BASE(201, 201, 13, 0x00c0, 0x10, 25, 1), + PIN_FIELD_BASE(202, 202, 13, 0x00c0, 0x10, 16, 1), + PIN_FIELD_BASE(203, 203, 13, 0x00c0, 0x10, 21, 1), + PIN_FIELD_BASE(204, 204, 13, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 13, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(206, 206, 13, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(207, 207, 13, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(208, 208, 13, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(209, 209, 13, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(210, 210, 14, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 14, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(212, 212, 14, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(213, 213, 14, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(214, 214, 13, 0x00c0, 0x10, 23, 1), + PIN_FIELD_BASE(215, 215, 13, 0x00c0, 0x10, 24, 1), + PIN_FIELD_BASE(216, 216, 14, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(220, 220, 14, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(221, 221, 14, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(222, 222, 14, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(223, 223, 14, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(230, 230, 15, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(231, 231, 15, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(232, 232, 15, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(233, 233, 15, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(234, 234, 15, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(235, 235, 15, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(236, 236, 15, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(237, 237, 15, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(238, 238, 15, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(239, 239, 15, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(240, 240, 15, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(241, 241, 15, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(242, 242, 15, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(243, 243, 15, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(244, 244, 15, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(245, 245, 15, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(246, 246, 15, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(247, 247, 15, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(248, 248, 15, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(249, 249, 15, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(250, 250, 15, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(251, 251, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(252, 252, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(253, 253, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(254, 254, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(255, 255, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(256, 256, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(257, 257, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(258, 258, 3, 0x0080, 0x10, 9, 1), +}; + +static const struct mtk_pin_field_calc mt8196_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(3, 3, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(4, 4, 11, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(5, 5, 11, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 11, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(7, 7, 11, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(8, 8, 11, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(9, 9, 9, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(10, 10, 9, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(11, 11, 8, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, 9, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(19, 19, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(20, 20, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(21, 21, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(22, 22, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(23, 23, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(24, 24, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(28, 28, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(31, 31, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(32, 32, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(33, 33, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(34, 34, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(36, 36, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(37, 37, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(38, 38, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(39, 39, 8, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(41, 41, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(42, 42, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(43, 43, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(44, 44, 8, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(45, 45, 8, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(46, 46, 8, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(54, 54, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(55, 55, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(57, 57, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(58, 58, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(59, 59, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(60, 60, 9, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(61, 61, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(62, 62, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(63, 63, 9, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(64, 64, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(65, 65, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(66, 66, 9, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(67, 67, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(68, 68, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(69, 69, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(70, 70, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(72, 72, 9, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(73, 73, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(74, 74, 9, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(75, 75, 10, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(76, 76, 10, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(77, 77, 10, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(78, 78, 10, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, 10, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(80, 80, 10, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(81, 81, 11, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(82, 82, 11, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(83, 83, 11, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(84, 84, 11, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(85, 85, 11, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(86, 86, 11, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(87, 87, 11, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(88, 88, 11, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(89, 89, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(90, 90, 11, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(91, 91, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(92, 92, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(93, 93, 12, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(94, 94, 12, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(95, 95, 12, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(96, 96, 12, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(97, 97, 12, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(98, 98, 12, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(99, 99, 12, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(100, 100, 12, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(101, 101, 12, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(102, 102, 12, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(103, 103, 12, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, 12, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(106, 106, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(107, 107, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(108, 108, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(109, 109, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(110, 110, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(111, 111, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(112, 112, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(113, 113, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(114, 114, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(115, 115, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(116, 116, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(117, 117, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(118, 118, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(119, 119, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(120, 120, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(121, 121, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(122, 122, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(125, 125, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(126, 126, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(127, 127, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(128, 128, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(129, 129, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(130, 130, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(131, 131, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(132, 132, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(133, 133, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(135, 135, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(136, 136, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(137, 137, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(144, 144, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(145, 145, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(146, 146, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(149, 149, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(150, 150, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(152, 152, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(153, 153, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(154, 154, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(155, 155, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(156, 156, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(157, 157, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(159, 159, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(160, 160, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(161, 161, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(163, 163, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(164, 164, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(165, 165, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(166, 166, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(167, 167, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(168, 168, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(169, 169, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(170, 170, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(171, 171, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(172, 172, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(173, 173, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(174, 174, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(175, 175, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(178, 178, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(179, 179, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(180, 180, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(181, 181, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(182, 182, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(183, 183, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(184, 184, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(185, 185, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(186, 186, 13, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(187, 187, 13, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(188, 188, 13, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(189, 189, 13, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(190, 190, 13, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(191, 191, 13, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(192, 192, 13, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(193, 193, 13, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(194, 194, 13, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(195, 195, 13, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(196, 196, 13, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(197, 197, 13, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(198, 198, 13, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(199, 199, 13, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(202, 202, 13, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(203, 203, 13, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(204, 204, 13, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(205, 205, 13, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(206, 206, 13, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(207, 207, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(208, 208, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(209, 209, 13, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(210, 210, 14, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(211, 211, 14, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(212, 212, 14, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(213, 213, 14, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(216, 216, 14, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(217, 217, 14, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(218, 218, 14, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(219, 219, 14, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(220, 220, 14, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(221, 221, 14, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(222, 222, 14, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(223, 223, 14, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(224, 224, 14, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(225, 225, 14, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(226, 226, 14, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(227, 227, 14, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(228, 228, 14, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(229, 229, 14, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(230, 230, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(231, 231, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(232, 232, 15, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(233, 233, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(234, 234, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(235, 235, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(236, 236, 15, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(237, 237, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(238, 238, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(239, 239, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(240, 240, 15, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(241, 241, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(242, 242, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(243, 243, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(244, 244, 15, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(245, 245, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(246, 246, 15, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(247, 247, 15, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(248, 248, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(249, 249, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(250, 250, 15, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(251, 251, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(252, 252, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(253, 253, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(254, 254, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(255, 255, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(256, 256, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(257, 257, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(258, 258, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(259, 259, 14, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(260, 260, 14, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(261, 261, 14, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(262, 262, 14, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(263, 263, 14, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(264, 264, 14, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(265, 265, 14, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(266, 266, 14, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(267, 267, 15, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(268, 268, 15, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(269, 269, 15, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(270, 270, 15, 0x0000, 0x10, 21, 3), +}; + +static const struct mtk_pin_field_calc mt8196_pin_drv_adv_range[] = { + PIN_FIELD_BASE(46, 46, 8, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x0030, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x0030, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(75, 75, 10, 0x0020, 0x10, 0, 5), + PIN_FIELD_BASE(76, 76, 10, 0x0020, 0x10, 5, 5), + PIN_FIELD_BASE(77, 77, 10, 0x0020, 0x10, 10, 5), + PIN_FIELD_BASE(78, 78, 10, 0x0020, 0x10, 15, 5), + PIN_FIELD_BASE(99, 99, 12, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 12, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(101, 101, 12, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(102, 102, 12, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 12, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(165, 165, 3, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 3, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 3, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 3, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 3, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(176, 176, 1, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(188, 188, 13, 0x0040, 0x10, 0, 3), + PIN_FIELD_BASE(189, 189, 13, 0x0040, 0x10, 15, 3), + PIN_FIELD_BASE(190, 190, 13, 0x0040, 0x10, 3, 3), + PIN_FIELD_BASE(191, 191, 13, 0x0040, 0x10, 18, 3), + PIN_FIELD_BASE(194, 194, 13, 0x0040, 0x10, 6, 3), + PIN_FIELD_BASE(195, 195, 13, 0x0040, 0x10, 21, 3), + PIN_FIELD_BASE(198, 198, 13, 0x0040, 0x10, 9, 3), + PIN_FIELD_BASE(199, 199, 13, 0x0040, 0x10, 24, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0050, 0x10, 0, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0050, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 13, 0x0040, 0x10, 12, 3), + PIN_FIELD_BASE(203, 203, 13, 0x0040, 0x10, 27, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0050, 0x10, 3, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0050, 0x10, 6, 3), +}; + +static const struct mtk_pin_field_calc mt8196_pin_rsel_range[] = { + PIN_FIELD_BASE(46, 46, 8, 0x00c0, 0x10, 0, 3), + PIN_FIELD_BASE(47, 47, 8, 0x00c0, 0x10, 9, 3), + PIN_FIELD_BASE(48, 48, 8, 0x00c0, 0x10, 3, 3), + PIN_FIELD_BASE(49, 49, 8, 0x00c0, 0x10, 12, 3), + PIN_FIELD_BASE(50, 50, 8, 0x00c0, 0x10, 6, 3), + PIN_FIELD_BASE(51, 51, 8, 0x00c0, 0x10, 15, 3), + PIN_FIELD_BASE(52, 52, 9, 0x0110, 0x10, 0, 3), + PIN_FIELD_BASE(53, 53, 9, 0x0110, 0x10, 3, 3), + PIN_FIELD_BASE(99, 99, 12, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(100, 100, 12, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(101, 101, 12, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(102, 102, 12, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(104, 104, 12, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 12, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 6, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(124, 124, 6, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 3, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(165, 165, 3, 0x00b0, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 3, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(167, 167, 3, 0x00b0, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 3, 0x00b0, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 3, 0x00b0, 0x10, 15, 3), + PIN_FIELD_BASE(176, 176, 1, 0x00b0, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 1, 0x00b0, 0x10, 3, 3), + PIN_FIELD_BASE(188, 188, 13, 0x00f0, 0x10, 0, 3), + PIN_FIELD_BASE(189, 189, 13, 0x00f0, 0x10, 15, 3), + PIN_FIELD_BASE(190, 190, 13, 0x00f0, 0x10, 3, 3), + PIN_FIELD_BASE(191, 191, 13, 0x00f0, 0x10, 18, 3), + PIN_FIELD_BASE(194, 194, 13, 0x00f0, 0x10, 6, 3), + PIN_FIELD_BASE(195, 195, 13, 0x00f0, 0x10, 21, 3), + PIN_FIELD_BASE(198, 198, 13, 0x00f0, 0x10, 9, 3), + PIN_FIELD_BASE(199, 199, 13, 0x00f0, 0x10, 24, 3), + PIN_FIELD_BASE(200, 200, 13, 0x0100, 0x10, 0, 3), + PIN_FIELD_BASE(201, 201, 13, 0x0100, 0x10, 9, 3), + PIN_FIELD_BASE(202, 202, 13, 0x00f0, 0x10, 12, 3), + PIN_FIELD_BASE(203, 203, 13, 0x00f0, 0x10, 27, 3), + PIN_FIELD_BASE(214, 214, 13, 0x0100, 0x10, 3, 3), + PIN_FIELD_BASE(215, 215, 13, 0x0100, 0x10, 6, 3), +}; + +static const unsigned int mt8196_pull_type[] = { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/ + MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/ + MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*46*/ MTK_PULL_PU_PD_RSEL_TYPE,/*47*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*48*/ MTK_PULL_PU_PD_RSEL_TYPE,/*49*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*50*/ MTK_PULL_PU_PD_RSEL_TYPE,/*51*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*52*/ MTK_PULL_PU_PD_RSEL_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PU_PD_TYPE,/*67*/ + MTK_PULL_PU_PD_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_RSEL_TYPE,/*99*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*100*/ MTK_PULL_PU_PD_RSEL_TYPE,/*101*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*104*/ MTK_PULL_PU_PD_RSEL_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/ + MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/ + MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_RSEL_TYPE,/*123*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*124*/ MTK_PULL_PUPD_R1R0_TYPE,/*125*/ + MTK_PULL_PUPD_R1R0_TYPE,/*126*/ MTK_PULL_PUPD_R1R0_TYPE,/*127*/ + MTK_PULL_PUPD_R1R0_TYPE,/*128*/ MTK_PULL_PUPD_R1R0_TYPE,/*129*/ + MTK_PULL_PUPD_R1R0_TYPE,/*130*/ MTK_PULL_PUPD_R1R0_TYPE,/*131*/ + MTK_PULL_PUPD_R1R0_TYPE,/*132*/ MTK_PULL_PUPD_R1R0_TYPE,/*133*/ + MTK_PULL_PUPD_R1R0_TYPE,/*134*/ MTK_PULL_PUPD_R1R0_TYPE,/*135*/ + MTK_PULL_PUPD_R1R0_TYPE,/*136*/ MTK_PULL_PUPD_R1R0_TYPE,/*137*/ + MTK_PULL_PUPD_R1R0_TYPE,/*138*/ MTK_PULL_PUPD_R1R0_TYPE,/*139*/ + MTK_PULL_PUPD_R1R0_TYPE,/*140*/ MTK_PULL_PUPD_R1R0_TYPE,/*141*/ + MTK_PULL_PUPD_R1R0_TYPE,/*142*/ MTK_PULL_PUPD_R1R0_TYPE,/*143*/ + MTK_PULL_PUPD_R1R0_TYPE,/*144*/ MTK_PULL_PUPD_R1R0_TYPE,/*145*/ + MTK_PULL_PUPD_R1R0_TYPE,/*146*/ MTK_PULL_PUPD_R1R0_TYPE,/*147*/ + MTK_PULL_PUPD_R1R0_TYPE,/*148*/ MTK_PULL_PUPD_R1R0_TYPE,/*149*/ + MTK_PULL_PUPD_R1R0_TYPE,/*150*/ MTK_PULL_PUPD_R1R0_TYPE,/*151*/ + MTK_PULL_PUPD_R1R0_TYPE,/*152*/ MTK_PULL_PUPD_R1R0_TYPE,/*153*/ + MTK_PULL_PUPD_R1R0_TYPE,/*154*/ MTK_PULL_PUPD_R1R0_TYPE,/*155*/ + MTK_PULL_PUPD_R1R0_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*164*/ MTK_PULL_PU_PD_RSEL_TYPE,/*165*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*166*/ MTK_PULL_PU_PD_RSEL_TYPE,/*167*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*176*/ MTK_PULL_PU_PD_RSEL_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/ + MTK_PULL_PU_PD_TYPE,/*184*/ MTK_PULL_PU_PD_TYPE,/*185*/ + MTK_PULL_PU_PD_TYPE,/*186*/ MTK_PULL_PU_PD_TYPE,/*187*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*188*/ MTK_PULL_PU_PD_RSEL_TYPE,/*189*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*190*/ MTK_PULL_PU_PD_RSEL_TYPE,/*191*/ + MTK_PULL_PU_PD_TYPE,/*192*/ MTK_PULL_PU_PD_TYPE,/*193*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*194*/ MTK_PULL_PU_PD_RSEL_TYPE,/*195*/ + MTK_PULL_PU_PD_TYPE,/*196*/ MTK_PULL_PU_PD_TYPE,/*197*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*198*/ MTK_PULL_PU_PD_RSEL_TYPE,/*199*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*200*/ MTK_PULL_PU_PD_RSEL_TYPE,/*201*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*202*/ MTK_PULL_PU_PD_RSEL_TYPE,/*203*/ + MTK_PULL_PU_PD_TYPE,/*204*/ MTK_PULL_PU_PD_TYPE,/*205*/ + MTK_PULL_PU_PD_TYPE,/*206*/ MTK_PULL_PU_PD_TYPE,/*207*/ + MTK_PULL_PU_PD_TYPE,/*208*/ MTK_PULL_PU_PD_TYPE,/*209*/ + MTK_PULL_PU_PD_TYPE,/*210*/ MTK_PULL_PU_PD_TYPE,/*211*/ + MTK_PULL_PU_PD_TYPE,/*212*/ MTK_PULL_PU_PD_TYPE,/*213*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*214*/ MTK_PULL_PU_PD_RSEL_TYPE,/*215*/ + MTK_PULL_PU_PD_TYPE,/*216*/ MTK_PULL_PUPD_R1R0_TYPE,/*217*/ + MTK_PULL_PUPD_R1R0_TYPE,/*218*/ MTK_PULL_PUPD_R1R0_TYPE,/*219*/ + MTK_PULL_PU_PD_TYPE,/*220*/ MTK_PULL_PU_PD_TYPE,/*221*/ + MTK_PULL_PU_PD_TYPE,/*222*/ MTK_PULL_PU_PD_TYPE,/*223*/ + MTK_PULL_PUPD_R1R0_TYPE,/*224*/ MTK_PULL_PUPD_R1R0_TYPE,/*225*/ + MTK_PULL_PUPD_R1R0_TYPE,/*226*/ MTK_PULL_PUPD_R1R0_TYPE,/*227*/ + MTK_PULL_PUPD_R1R0_TYPE,/*228*/ MTK_PULL_PUPD_R1R0_TYPE,/*229*/ + MTK_PULL_PU_PD_TYPE,/*230*/ MTK_PULL_PU_PD_TYPE,/*231*/ + MTK_PULL_PU_PD_TYPE,/*232*/ MTK_PULL_PU_PD_TYPE,/*233*/ + MTK_PULL_PU_PD_TYPE,/*234*/ MTK_PULL_PU_PD_TYPE,/*235*/ + MTK_PULL_PU_PD_TYPE,/*236*/ MTK_PULL_PU_PD_TYPE,/*237*/ + MTK_PULL_PU_PD_TYPE,/*238*/ MTK_PULL_PU_PD_TYPE,/*239*/ + MTK_PULL_PU_PD_TYPE,/*240*/ MTK_PULL_PU_PD_TYPE,/*241*/ + MTK_PULL_PU_PD_TYPE,/*242*/ MTK_PULL_PU_PD_TYPE,/*243*/ + MTK_PULL_PU_PD_TYPE,/*244*/ MTK_PULL_PU_PD_TYPE,/*245*/ + MTK_PULL_PU_PD_TYPE,/*246*/ MTK_PULL_PU_PD_TYPE,/*247*/ + MTK_PULL_PU_PD_TYPE,/*248*/ MTK_PULL_PU_PD_TYPE,/*249*/ + MTK_PULL_PU_PD_TYPE,/*250*/ MTK_PULL_PU_PD_TYPE,/*251*/ + MTK_PULL_PU_PD_TYPE,/*252*/ MTK_PULL_PU_PD_TYPE,/*253*/ + MTK_PULL_PU_PD_TYPE,/*254*/ MTK_PULL_PU_PD_TYPE,/*255*/ + MTK_PULL_PU_PD_TYPE,/*256*/ MTK_PULL_PU_PD_TYPE,/*257*/ + MTK_PULL_PU_PD_TYPE,/*258*/ MTK_PULL_PUPD_R1R0_TYPE,/*259*/ + MTK_PULL_PUPD_R1R0_TYPE,/*260*/ MTK_PULL_PUPD_R1R0_TYPE,/*261*/ + MTK_PULL_PUPD_R1R0_TYPE,/*262*/ MTK_PULL_PUPD_R1R0_TYPE,/*263*/ + MTK_PULL_PUPD_R1R0_TYPE,/*264*/ MTK_PULL_PUPD_R1R0_TYPE,/*265*/ + MTK_PULL_PUPD_R1R0_TYPE,/*266*/ MTK_PULL_PUPD_R1R0_TYPE,/*267*/ + MTK_PULL_PUPD_R1R0_TYPE,/*268*/ MTK_PULL_PUPD_R1R0_TYPE,/*269*/ + MTK_PULL_PUPD_R1R0_TYPE,/*270*/ +}; + +static const struct mtk_pin_reg_calc mt8196_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8196_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8196_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8196_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8196_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8196_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8196_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8196_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8196_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8196_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8196_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8196_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8196_pin_drv_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8196_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8196_pin_rsel_range), +}; + +static const char * const mt8196_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_rt", "iocfg_rm1", "iocfg_rm2", + "iocfg_rb", "iocfg_bm1", "iocfg_bm2", "iocfg_bm3", + "iocfg_lt", "iocfg_lm1", "iocfg_lm2", "iocfg_lb1", + "iocfg_lb2", "iocfg_tm1", "iocfg_tm2", "iocfg_tm3", +}; + +static const struct mtk_eint_hw mt8196_eint_hw = { + .port_mask = 0xf, + .ports = 3, + .ap_num = 293, + .db_cnt = 32, + .db_time = debounce_time_mt6765, +}; + +static const struct mtk_pin_soc mt8196_data = { + .reg_cal = mt8196_reg_cals, + .pins = mtk_pins_mt8196, + .npins = ARRAY_SIZE(mtk_pins_mt8196), + .ngrps = ARRAY_SIZE(mtk_pins_mt8196), + .eint_hw = &mt8196_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .base_names = mt8196_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8196_pinctrl_register_base_names), + .pull_type = mt8196_pull_type, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt8196_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8196-pinctrl", .data = &mt8196_data }, + { } +}; + +static struct platform_driver mt8196_pinctrl_driver = { + .driver = { + .name = "mt8196-pinctrl", + .of_match_table = mt8196_pinctrl_of_match, + .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops), + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt8196_pinctrl_init(void) +{ + return platform_driver_register(&mt8196_pinctrl_driver); +} +arch_initcall(mt8196_pinctrl_init); + +MODULE_DESCRIPTION("MediaTek MT8196 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h new file mode 100644 index 000000000000..d342d091672c --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h @@ -0,0 +1,2789 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Mediatek Inc. + * Author: Guodong Liu <Guodong.Liu@mediatek.com> + */ + +#ifndef __PINCTRL_MTK_MT8196_H +#define __PINCTRL_MTK_MT8196_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8196[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(3, "SPI3_A_MO"), + MTK_FUNCTION(4, "FMI2S_B_LRCK"), + MTK_FUNCTION(5, "SCP_DMIC1_CLK"), + MTK_FUNCTION(6, "TP_GPIO14_AO") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "DMIC1_DAT"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "SPI3_A_MI"), + MTK_FUNCTION(4, "FMI2S_B_DI"), + MTK_FUNCTION(5, "SCP_DMIC1_DAT"), + MTK_FUNCTION(6, "TP_GPIO15_AO") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "PWM_VLP"), + MTK_FUNCTION(2, "DSI_HSYNC"), + MTK_FUNCTION(5, "RG_TSFDC_LDO_EN"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "MD_INT0"), + MTK_FUNCTION(2, "DSI1_HSYNC"), + MTK_FUNCTION(5, "DA_TSFDC_LDO_MODE"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "DISP_PWM1"), + MTK_FUNCTION(2, "MD32_0_GPIO0") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "LCM1_RST"), + MTK_FUNCTION(2, "SPI7_A_CLK") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "DSI1_TE"), + MTK_FUNCTION(2, "SPI7_A_CSB") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(2, "SPI7_A_MO"), + MTK_FUNCTION(3, "GPS_PPS0") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(2, "SPI7_A_MI"), + MTK_FUNCTION(3, "EDP_TX_HPD") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(7, "RG_TSFDC_LDO_REFSEL0") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(3, "I2SOUT1_DO"), + MTK_FUNCTION(7, "RG_TSFDC_LDO_REFSEL1") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(4, "FMI2S_B_BCK"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(3, "I2SIN1_DI_B") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "EDP_TX_HPD"), + MTK_FUNCTION(2, "GPS_PPS1") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "SRCLKENA2"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(3, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(5, "MD_INT3"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "MD_INT4"), + MTK_FUNCTION(5, "I2SOUT2_DO"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "DP_TX_HPD"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "KPROW2"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "MD_INT0"), + MTK_FUNCTION(2, "DP_OC_EN"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "MD_NTN_URXD1"), + MTK_FUNCTION(5, "KPCOL2"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(2, "DP_RAUX_SBU1"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "MD_NTN_UTXD1"), + MTK_FUNCTION(5, "I2SIN2_DI"), + MTK_FUNCTION(6, "TP_UTXD_GNSS_VLP") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "DMIC1_DAT"), + MTK_FUNCTION(2, "DP_RAUX_SBU2"), + MTK_FUNCTION(3, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(4, "CLKM3_A"), + MTK_FUNCTION(5, "I2SIN2_BCK"), + MTK_FUNCTION(6, "TP_URXD_GNSS_VLP") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "GPS_PPS1"), + MTK_FUNCTION(4, "CLKM2_A") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(2, "PCIE_PERSTN_1P"), + MTK_FUNCTION(3, "DSI1_TE"), + MTK_FUNCTION(4, "DMIC_CLK"), + MTK_FUNCTION(5, "SCP_DMIC_CLK") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(2, "PCIE_CLKREQN_1P"), + MTK_FUNCTION(3, "DSI2_TE"), + MTK_FUNCTION(4, "DMIC_DAT"), + MTK_FUNCTION(5, "SCP_DMIC_DAT") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(2, "PCIE_WAKEN_1P"), + MTK_FUNCTION(3, "DSI3_TE"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "SCP_DMIC1_CLK") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(2, "LCM1_RST"), + MTK_FUNCTION(3, "AGPS_SYNC"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "SCP_DMIC1_DAT"), + MTK_FUNCTION(6, "DISP_PWM1") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "DMIC2_CLK"), + MTK_FUNCTION(6, "DISP_PWM2") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "LCM3_RST"), + MTK_FUNCTION(4, "DMIC2_DAT"), + MTK_FUNCTION(6, "DISP_PWM3") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "UTXD4"), + MTK_FUNCTION(6, "DISP_PWM4"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "URXD4"), + MTK_FUNCTION(3, "SPI2_A_MI"), + MTK_FUNCTION(4, "CLKM0_A"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "MD_NTN_UTXD1"), + MTK_FUNCTION(3, "SPI2_A_MO"), + MTK_FUNCTION(4, "CLKM1_A"), + MTK_FUNCTION(6, "UCTS4"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "MD_NTN_URXD1"), + MTK_FUNCTION(3, "SPI2_A_CLK"), + MTK_FUNCTION(4, "CLKM2_A"), + MTK_FUNCTION(5, "DSI3_HSYNC"), + MTK_FUNCTION(6, "URTS4"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(3, "SPI2_A_CSB"), + MTK_FUNCTION(4, "CLKM3_A"), + MTK_FUNCTION(6, "EDP_TX_HPD"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "LCM4_RST"), + MTK_FUNCTION(2, "DP_TX_HPD"), + MTK_FUNCTION(3, "SSPM_JTAG_TCK_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(5, "SCP_JTAG0_TCK_VLP"), + MTK_FUNCTION(6, "SPU0_TCK"), + MTK_FUNCTION(7, "IO_JTAG_TCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "DSI4_TE"), + MTK_FUNCTION(2, "DP_OC_EN"), + MTK_FUNCTION(3, "SSPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG0_TRSTN_VLP"), + MTK_FUNCTION(6, "SPU0_NTRST"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "UCTS5"), + MTK_FUNCTION(2, "DP_RAUX_SBU1"), + MTK_FUNCTION(3, "SSPM_JTAG_TDI_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(5, "SCP_JTAG0_TDI_VLP"), + MTK_FUNCTION(6, "SPU0_TDI"), + MTK_FUNCTION(7, "IO_JTAG_TDI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "URTS5"), + MTK_FUNCTION(2, "DP_RAUX_SBU2"), + MTK_FUNCTION(3, "SSPM_JTAG_TDO_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(5, "SCP_JTAG0_TDO_VLP"), + MTK_FUNCTION(6, "SPU0_TDO"), + MTK_FUNCTION(7, "IO_JTAG_TDO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "UTXD5"), + MTK_FUNCTION(3, "SSPM_JTAG_TMS_VLP"), + MTK_FUNCTION(4, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(5, "SCP_JTAG0_TMS_VLP"), + MTK_FUNCTION(6, "SPU0_TMS"), + MTK_FUNCTION(7, "IO_JTAG_TMS") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "URXD5"), + MTK_FUNCTION(3, "MD_INT3"), + MTK_FUNCTION(4, "CLKM0_B"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "SPU0_UTX"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(2, "SPMI_P_TRIG_FLAG"), + MTK_FUNCTION(3, "MD_INT4"), + MTK_FUNCTION(4, "CLKM1_B"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "SPU0_URX"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "I2S_MCK0"), + MTK_FUNCTION(3, "GPS_PPS0"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "I2SIN6_0_BCK"), + MTK_FUNCTION(3, "SPI4_B_CLK"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "CCU1_UTXD"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "I2SIN6_0_LRCK"), + MTK_FUNCTION(3, "SPI4_B_CSB"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "CCU1_URXD"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "I2SIN6_0_DI"), + MTK_FUNCTION(3, "SPI4_B_MI"), + MTK_FUNCTION(4, "URXD2"), + MTK_FUNCTION(5, "CCU1_URTS"), + MTK_FUNCTION(6, "MD32_0_RXD"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "I2SOUT6_0_DO"), + MTK_FUNCTION(3, "SPI4_B_MO"), + MTK_FUNCTION(4, "UTXD2"), + MTK_FUNCTION(5, "CCU1_UCTS"), + MTK_FUNCTION(6, "MD32_0_TXD"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SPI3_A_CLK"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "DSI2_HSYNC"), + MTK_FUNCTION(3, "SPI3_A_CSB"), + MTK_FUNCTION(4, "PWM_VLP"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SCP_SCL4"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST1_VLP"), + MTK_FUNCTION(5, "UFS_MPHY_SCL"), + MTK_FUNCTION(6, "TP_GPIO0_AO") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SCP_SDA4"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST2_VLP"), + MTK_FUNCTION(5, "UFS_MPHY_SDA"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SCP_SCL5"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "CCU0_UTXD"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST3_VLP"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SCP_SDA5"), + MTK_FUNCTION(3, "CCU0_URXD"), + MTK_FUNCTION(4, "SCP_ILDO_DTEST4_VLP"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SCP_SCL6"), + MTK_FUNCTION(2, "PWM_VLP"), + MTK_FUNCTION(3, "CCU0_URTS"), + MTK_FUNCTION(4, "DSI_HSYNC"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SCP_SDA6"), + MTK_FUNCTION(3, "CCU0_UCTS"), + MTK_FUNCTION(4, "DSI1_HSYNC"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SCP_SCL1"), + MTK_FUNCTION(3, "TDM_DATA2") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SCP_SDA1"), + MTK_FUNCTION(3, "TDM_DATA3") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "TDM_MCK") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "I2SOUT2_BCK"), + MTK_FUNCTION(3, "TDM_BCK") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "I2SOUT2_LRCK"), + MTK_FUNCTION(3, "TDM_LRCK") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "I2SOUT2_DO"), + MTK_FUNCTION(3, "TDM_DATA0") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "TDM_DATA1") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2SIN1_BCK") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MCU_M_PMIC_POC_I") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "MCU_B_PMIC_POC_I") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "MFG_PMIC_POC_I") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "PRE_UVLO") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "DPM2PMIC"), + MTK_FUNCTION(2, "SRCLKENA1") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCP_VREQ_VAO") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "CMFLASH0") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "DCXO_FPM_LPM") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SPMI_M_SCL") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SPMI_M_SDA") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SPMI_P_SCL") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SPMI_P_SDA") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "MD_INT4") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "CMMCLK1") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "SCP_SPI0_CK"), + MTK_FUNCTION(2, "SPI6_B_CLK"), + MTK_FUNCTION(3, "PWM_VLP"), + MTK_FUNCTION(4, "I2SOUT5_BCK"), + MTK_FUNCTION(6, "TP_GPIO0_AO") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "SCP_SPI0_CS"), + MTK_FUNCTION(2, "SPI6_B_CSB"), + MTK_FUNCTION(4, "I2SOUT5_LRCK"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "SCP_SPI0_MO"), + MTK_FUNCTION(2, "SPI6_B_MO"), + MTK_FUNCTION(4, "I2SOUT5_DATA0"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "SCP_SPI0_MI"), + MTK_FUNCTION(2, "SPI6_B_MI"), + MTK_FUNCTION(4, "I2SOUT5_DATA1"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "SCP_SPI1_CK"), + MTK_FUNCTION(2, "SPI7_B_CLK"), + MTK_FUNCTION(4, "I2SIN5_DATA0"), + MTK_FUNCTION(5, "PWM_VLP"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "SCP_SPI1_CS"), + MTK_FUNCTION(2, "SPI7_B_CSB"), + MTK_FUNCTION(4, "I2SIN5_DATA1"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "SCP_SPI1_MO"), + MTK_FUNCTION(2, "SPI7_B_MO"), + MTK_FUNCTION(4, "I2SIN5_BCK"), + MTK_FUNCTION(6, "TP_GPIO6_AO") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "SCP_SPI1_MI"), + MTK_FUNCTION(2, "SPI7_B_MI"), + MTK_FUNCTION(4, "I2SIN5_LRCK"), + MTK_FUNCTION(6, "TP_GPIO7_AO") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "LCM1_RST"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "SF_D0"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(5, "KPCOL2"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "SF_D1"), + MTK_FUNCTION(4, "DISP_PWM1"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "SF_D2"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(5, "KPROW2"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "I2S_MCK1"), + MTK_FUNCTION(2, "SF_D3"), + MTK_FUNCTION(4, "MD32_0_GPIO0"), + MTK_FUNCTION(5, "CLKM0_A"), + MTK_FUNCTION(6, "TP_GPIO14_AO"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "I2SIN1_BCK"), + MTK_FUNCTION(2, "I2SIN4_BCK"), + MTK_FUNCTION(3, "SPI6_A_CLK"), + MTK_FUNCTION(4, "MD32_1_GPIO0"), + MTK_FUNCTION(5, "CLKM1_A"), + MTK_FUNCTION(6, "TP_GPIO15_AO"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(2, "I2SIN4_LRCK"), + MTK_FUNCTION(3, "SPI6_A_CSB"), + MTK_FUNCTION(4, "MD32_2_GPIO0"), + MTK_FUNCTION(5, "CLKM2_A"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "I2SIN1_DI_A"), + MTK_FUNCTION(2, "I2SIN4_DATA0"), + MTK_FUNCTION(3, "SPI6_A_MO"), + MTK_FUNCTION(4, "MD32_3_GPIO0"), + MTK_FUNCTION(5, "CLKM3_A"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "I2SOUT1_DO"), + MTK_FUNCTION(2, "I2SOUT4_DATA0"), + MTK_FUNCTION(3, "SPI6_A_MI"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "SPU0_SCL"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(4, "SPU0_SDA"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "SCL10"), + MTK_FUNCTION(2, "SF_CS"), + MTK_FUNCTION(3, "SCP_DMIC1_CLK"), + MTK_FUNCTION(4, "I2SIN5_DATA2"), + MTK_FUNCTION(5, "SCP_SCL_OIS"), + MTK_FUNCTION(6, "TP_GPIO10_AO"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "SDA10"), + MTK_FUNCTION(2, "SF_CK"), + MTK_FUNCTION(3, "SCP_DMIC1_DAT"), + MTK_FUNCTION(4, "I2SIN5_DATA3"), + MTK_FUNCTION(5, "SCP_SDA_OIS"), + MTK_FUNCTION(6, "TP_GPIO11_AO"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "DSI1_TE"), + MTK_FUNCTION(5, "I2S_MCK0"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "SPU1_SCL"), + MTK_FUNCTION(3, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "USB_DRVVBUS_2P"), + MTK_FUNCTION(5, "I2S_MCK1"), + MTK_FUNCTION(6, "IDDIG_2P"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "SPU1_SDA"), + MTK_FUNCTION(3, "DISP_PWM2"), + MTK_FUNCTION(4, "VBUSVALID_2P"), + MTK_FUNCTION(5, "I2S_MCK2"), + MTK_FUNCTION(6, "VBUSVALID_3P"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SCP_SPI3_CK"), + MTK_FUNCTION(2, "SPI3_B_CLK"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "TP_UTXD1_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART0_TXD"), + MTK_FUNCTION(6, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "SCP_SPI3_CS"), + MTK_FUNCTION(2, "SPI3_B_CSB"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "TP_URXD1_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART0_RXD"), + MTK_FUNCTION(6, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "SCP_SPI3_MO"), + MTK_FUNCTION(2, "SPI3_B_MO"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "MD32PCM_UTXD_AO_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART1_TXD"), + MTK_FUNCTION(6, "TP_GPIO8_AO"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "SCP_SPI3_MI"), + MTK_FUNCTION(2, "SPI3_B_MI"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "MD32PCM_URXD_AO_VLP"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_UART1_RXD"), + MTK_FUNCTION(6, "TP_GPIO9_AO"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "SPI1_CLK"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "MD_UCTS0"), + MTK_FUNCTION(4, "TP_UCTS1_VLP"), + MTK_FUNCTION(6, "SPU0_GPIO_O"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "SPI1_CSB"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "MD_URTS0"), + MTK_FUNCTION(4, "TP_URTS1_VLP"), + MTK_FUNCTION(6, "SPU0_GPIO_I"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "SPI1_MO"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "MD_UCTS1"), + MTK_FUNCTION(6, "SPU1_GPIO_O"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "SPI1_MI"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "MD_URTS1"), + MTK_FUNCTION(6, "SPU1_GPIO_I"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SPI0_SPU_CLK"), + MTK_FUNCTION(2, "SPI4_A_CLK"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_DBG_UART_TX"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "SPI0_SPU_CSB"), + MTK_FUNCTION(2, "SPI4_A_CSB"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "SPI0_SPU_MO"), + MTK_FUNCTION(2, "SPI4_A_MO"), + MTK_FUNCTION(3, "LCM1_RST"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "SPI0_SPU_MI"), + MTK_FUNCTION(2, "SPI4_A_MI"), + MTK_FUNCTION(3, "DSI1_TE"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "DP_TX_HPD"), + MTK_FUNCTION(4, "AD_ILDO_DTEST0") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "VBUSVALID"), + MTK_FUNCTION(3, "DP_OC_EN"), + MTK_FUNCTION(4, "AD_ILDO_DTEST1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(2, "LCM2_RST"), + MTK_FUNCTION(3, "DP_RAUX_SBU1"), + MTK_FUNCTION(4, "AD_ILDO_DTEST2"), + MTK_FUNCTION(6, "IDDIG_3P") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(2, "DSI2_TE"), + MTK_FUNCTION(3, "DP_RAUX_SBU2"), + MTK_FUNCTION(4, "AD_ILDO_DTEST3"), + MTK_FUNCTION(6, "USB_DRVVBUS_3P"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(5, "I2SIN2_LRCK"), + MTK_FUNCTION(6, "TP_UTXD_MD_VCORE") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(6, "TP_URXD_MD_VCORE") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "HFRP_JTAG0_TCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JCK"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TCK_VLP"), + MTK_FUNCTION(7, "JTCK2_SEL1") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(3, "HFRP_JTAG0_TMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JMS"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TMS_VLP"), + MTK_FUNCTION(7, "JTMS2_SEL1") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "HFRP_JTAG0_TDI"), + MTK_FUNCTION(4, "UDI_TDI_0"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JDI"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDI_VLP"), + MTK_FUNCTION(7, "JTDI2_SEL1") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "HFRP_JTAG0_TDO"), + MTK_FUNCTION(4, "UDI_TDO_0"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JDO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDO_VLP"), + MTK_FUNCTION(7, "JTDO2_SEL1") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "DSI2_HSYNC"), + MTK_FUNCTION(3, "HFRP_JTAG0_TRSTN"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TRSTN_VLP"), + MTK_FUNCTION(7, "JTRSTN2_SEL1") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "DSI3_HSYNC"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L1_JINTP") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(4, "CLKM0_A"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JDI"), + MTK_FUNCTION(6, "TSFDC_SCK"), + MTK_FUNCTION(7, "SCP_JTAG0_TDI_VCORE") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(4, "CLKM1_B"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JMS"), + MTK_FUNCTION(6, "TSFDC_SDI"), + MTK_FUNCTION(7, "SCP_JTAG0_TMS_VCORE") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JDO"), + MTK_FUNCTION(6, "TSFDC_SCF"), + MTK_FUNCTION(7, "SCP_JTAG0_TDO_VCORE") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(6, "TSFDC_26M") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JCK"), + MTK_FUNCTION(6, "TSFDC_SDO"), + MTK_FUNCTION(7, "SCP_JTAG0_TCK_VCORE") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "CONN_BGF_DSP_L5_JINTP"), + MTK_FUNCTION(6, "TSFDC_FOUT"), + MTK_FUNCTION(7, "SCP_JTAG0_TRSTN_VCORE") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS16"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS17"), + MTK_FUNCTION(4, "PCM0_LRCK"), + MTK_FUNCTION(6, "SPM_JTAG_TCK_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS18"), + MTK_FUNCTION(4, "MD_GPS_BLANK"), + MTK_FUNCTION(6, "SPM_JTAG_TMS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS19"), + MTK_FUNCTION(4, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "SPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "MIPI2_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS20"), + MTK_FUNCTION(4, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "SPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "MIPI2_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS21"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "MIPI3_D_SCLK"), + MTK_FUNCTION(2, "BPI_BUS22"), + MTK_FUNCTION(4, "TP_UTXD_GNSS_VLP"), + MTK_FUNCTION(5, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK_VCORE") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "MIPI3_D_SDATA"), + MTK_FUNCTION(2, "BPI_BUS23"), + MTK_FUNCTION(4, "TP_URXD_GNSS_VLP"), + MTK_FUNCTION(5, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS_VCORE") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(4, "PCIE_WAKEN_1P"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(4, "PCIE_PERSTN_1P"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(2, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "PCIE_CLKREQN_1P"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TRSTN_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(2, "AUD_DAC_26M_CLK"), + MTK_FUNCTION(4, "TP_UTXD_MD_VLP"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TCK_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "BPI_BUS4"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "TP_URXD_MD_VLP"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TMS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(2, "GPS_PPS0"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "GPS_PPS1"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(6, "SCP_JTAG_LITTLE_TDI_VCORE") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "EDP_TX_HPD"), + MTK_FUNCTION(5, "AGPS_SYNC"), + MTK_FUNCTION(6, "SSPM_UTXD_AO_VCORE") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL"), + MTK_FUNCTION(6, "TP_URTS1_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "DIGRF_IRQ"), + MTK_FUNCTION(6, "TP_UCTS1_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "MIPI_M_SCLK"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(6, "TP_UTXD_CONSYS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "MIPI_M_SDATA"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(6, "TP_URXD_CONSYS_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(4, "UTXD2"), + MTK_FUNCTION(5, "CLKM0_A"), + MTK_FUNCTION(6, "SSPM_URXD_AO_VCORE"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(4, "URXD2"), + MTK_FUNCTION(5, "CLKM1_A"), + MTK_FUNCTION(6, "TP_UTXD1_VCORE") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "MD_INT0"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(5, "CLKM2_A"), + MTK_FUNCTION(6, "TP_URXD1_VCORE") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MD_UTXD1"), + MTK_FUNCTION(5, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(6, "CONN_BG_GPS_MCU_DBG_UART_TX") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MD_URXD1"), + MTK_FUNCTION(5, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "TP_UTXD1_VLP"), + MTK_FUNCTION(4, "ADSP_UTXD0"), + MTK_FUNCTION(5, "SSPM_UTXD_AO_VLP"), + MTK_FUNCTION(6, "HFRP_UTXD1") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "TP_URXD1_VLP"), + MTK_FUNCTION(4, "ADSP_URXD0"), + MTK_FUNCTION(5, "SSPM_URXD_AO_VLP"), + MTK_FUNCTION(6, "HFRP_URXD1") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "SCP_SCL0"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "SCP_SDA0"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "SCP_SCL2"), + MTK_FUNCTION(6, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "SCP_SDA2"), + MTK_FUNCTION(6, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "SCP_SPI2_CK"), + MTK_FUNCTION(2, "SPI2_B_CLK"), + MTK_FUNCTION(3, "PWM_VLP"), + MTK_FUNCTION(4, "SCP_SCL2"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "SCP_SPI2_CS"), + MTK_FUNCTION(2, "SPI2_B_CSB"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "SCP_SPI2_MO"), + MTK_FUNCTION(2, "SPI2_B_MO"), + MTK_FUNCTION(4, "SCP_SDA2"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "SCP_SPI2_MI"), + MTK_FUNCTION(2, "SPI2_B_MI"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(4, "CLKM1_A"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "VBUSVALID_1P"), + MTK_FUNCTION(4, "MD32_2_RXD"), + MTK_FUNCTION(5, "DISP_PWM3") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "EDP_TX_HPD"), + MTK_FUNCTION(4, "MD32_2_TXD"), + MTK_FUNCTION(5, "DISP_PWM4") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(2, "LCM3_RST"), + MTK_FUNCTION(4, "MD_URXD1_CONN"), + MTK_FUNCTION(6, "TP_UTXD_GNSS_VCORE") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(2, "DSI3_TE"), + MTK_FUNCTION(4, "MD_UTXD1_CONN"), + MTK_FUNCTION(6, "TP_URXD_GNSS_VCORE") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "DMIC_CLK"), + MTK_FUNCTION(2, "SCP_DMIC_CLK"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(4, "CLKM2_B"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "SPU1_UTX"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "DMIC_DAT"), + MTK_FUNCTION(2, "SCP_DMIC_DAT"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "CLKM3_B"), + MTK_FUNCTION(5, "TP_GPIO8_AO"), + MTK_FUNCTION(6, "SPU1_URX"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "IDDIG_1P"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "GPS_PPS1"), + MTK_FUNCTION(4, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "DISP_PWM1") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "USB_DRVVBUS_1P"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TRSTN"), + MTK_FUNCTION(4, "ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(5, "HFRP_JTAG1_TRSTN"), + MTK_FUNCTION(6, "SPU1_NTRST"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TRST_B") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "SCL11"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TCK"), + MTK_FUNCTION(4, "ADSP_JTAG1_TCK"), + MTK_FUNCTION(5, "HFRP_JTAG1_TCK"), + MTK_FUNCTION(6, "SPU1_TCK"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TCK") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "SDA11"), + MTK_FUNCTION(2, "CMVREF3"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TMS"), + MTK_FUNCTION(4, "ADSP_JTAG1_TMS"), + MTK_FUNCTION(5, "HFRP_JTAG1_TMS"), + MTK_FUNCTION(6, "SPU1_TMS"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TMS") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "SCL12"), + MTK_FUNCTION(2, "CMVREF4"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDO"), + MTK_FUNCTION(4, "ADSP_JTAG1_TDO"), + MTK_FUNCTION(5, "HFRP_JTAG1_TDO"), + MTK_FUNCTION(6, "SPU1_TDO"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TDO") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "SDA12"), + MTK_FUNCTION(2, "CMVREF5"), + MTK_FUNCTION(3, "MFG_EB_JTAG_TDI"), + MTK_FUNCTION(4, "ADSP_JTAG1_TDI"), + MTK_FUNCTION(5, "HFRP_JTAG1_TDI"), + MTK_FUNCTION(6, "SPU1_TDI"), + MTK_FUNCTION(7, "CONN_BG_GPS_MCU_TDI") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MD_GPS_L1_BLANK"), + MTK_FUNCTION(2, "PMSR_SMAP"), + MTK_FUNCTION(3, "TP_GPIO2_AO") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MD_GPS_L5_BLANK"), + MTK_FUNCTION(3, "TP_GPIO4_AO") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "SCP_SCL8") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "SCP_SDA8") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(2, "SCP_SCL9"), + MTK_FUNCTION(6, "UDI_TDI_6") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(2, "SCP_SDA9"), + MTK_FUNCTION(6, "UDI_TDI_7") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(4, "MD32_3_RXD") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(3, "CLKM0_B"), + MTK_FUNCTION(4, "MD32_3_TXD"), + MTK_FUNCTION(6, "UDI_TDO_7") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "MD32_3_GPIO0"), + MTK_FUNCTION(3, "CLKM2_B"), + MTK_FUNCTION(6, "UDI_TDI_2") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(3, "CLKM3_B"), + MTK_FUNCTION(6, "UDI_TDI_3") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "CMMCLK3") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(3, "CLKM1_B"), + MTK_FUNCTION(6, "UDI_TDI_1") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(6, "UDI_TDI_4") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(6, "UDI_TDI_5") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(7, "TSFDC_BG_COMP") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "SCP_SCL7"), + MTK_FUNCTION(6, "TP_GPIO15_AO") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "SCP_SDA7"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "SCL13"), + MTK_FUNCTION(2, "CMVREF6"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(5, "CLKM2_B"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "SDA13"), + MTK_FUNCTION(2, "CMVREF7"), + MTK_FUNCTION(3, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(5, "CLKM3_B"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(0, 206), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(2, "MD32_2_GPIO0"), + MTK_FUNCTION(5, "VBUSVALID"), + MTK_FUNCTION(6, "UDI_TDO_3") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(0, 207), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "PCIE_WAKEN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP_MAX"), + MTK_FUNCTION(4, "FMI2S_A_BCK"), + MTK_FUNCTION(6, "UDI_TDO_4") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(0, 208), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "PCIE_CLKREQN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP_MAX_W"), + MTK_FUNCTION(4, "FMI2S_A_LRCK"), + MTK_FUNCTION(5, "CLKM0_B"), + MTK_FUNCTION(6, "UDI_TDO_5") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(0, 209), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "PCIE_PERSTN_2P"), + MTK_FUNCTION(2, "PMSR_SMAP"), + MTK_FUNCTION(4, "FMI2S_A_DI"), + MTK_FUNCTION(5, "CLKM1_B"), + MTK_FUNCTION(6, "UDI_TDO_6") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(0, 210), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "CMMCLK4") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(0, 211), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "CMMCLK5"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(0, 212), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "CMMCLK6"), + MTK_FUNCTION(2, "TP_GPIO10_AO"), + MTK_FUNCTION(5, "IDDIG"), + MTK_FUNCTION(6, "UDI_TDO_1") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(0, 213), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "CMMCLK7"), + MTK_FUNCTION(2, "TP_GPIO11_AO"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "UDI_TDO_2") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "SCP_SCL3"), + MTK_FUNCTION(2, "SDA14_E1_SCL14_E2"), + MTK_FUNCTION(6, "GBE1_MDC"), + MTK_FUNCTION(7, "GBE0_MDC") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "SCP_SDA3"), + MTK_FUNCTION(2, "SCL14_E1_SDA14_E2"), + MTK_FUNCTION(6, "GBE1_MDIO"), + MTK_FUNCTION(7, "GBE0_MDIO") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(0, 216), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "GPS_PPS0") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(0, 217), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(0, 218), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "SPI0_WP"), + MTK_FUNCTION(3, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(5, "GPS_L5_ELNA_EN"), + MTK_FUNCTION(6, "TP_GPIO14_AO") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(0, 219), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "SPI0_HOLD"), + MTK_FUNCTION(3, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(4, "SPMI_M_TRIG_FLAG"), + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN_VLP"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(0, 220), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO220"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(6, "SPM_JTAG_TCK_VLP"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(0, 221), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO221"), + MTK_FUNCTION(1, "SPI0_CSB"), + MTK_FUNCTION(6, "SPM_JTAG_TMS_VLP"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(0, 222), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO222"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(2, "SCP_SCL7"), + MTK_FUNCTION(6, "SPM_JTAG_TDO_VLP"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(0, 223), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO223"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(2, "SCP_SDA7"), + MTK_FUNCTION(6, "SPM_JTAG_TDI_VLP"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(0, 224), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO224"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "DMIC2_CLK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS0"), + MTK_FUNCTION(4, "GBE0_TXER"), + MTK_FUNCTION(5, "GBE1_TXER"), + MTK_FUNCTION(6, "GBE1_AUX_PPS0"), + MTK_FUNCTION(7, "MD32_1_TXD") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(0, 225), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO225"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "DMIC2_DAT"), + MTK_FUNCTION(3, "GBE0_AUX_PPS1"), + MTK_FUNCTION(4, "GBE0_RXER"), + MTK_FUNCTION(5, "GBE1_RXER"), + MTK_FUNCTION(6, "GBE1_AUX_PPS1"), + MTK_FUNCTION(7, "MD32_1_RXD") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(0, 226), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO226"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "I2SIN3_BCK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS2"), + MTK_FUNCTION(4, "GBE0_COL"), + MTK_FUNCTION(5, "GBE1_COL"), + MTK_FUNCTION(6, "GBE1_AUX_PPS2"), + MTK_FUNCTION(7, "GBE1_MDC") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(0, 227), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO227"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "I2SIN3_LRCK"), + MTK_FUNCTION(3, "GBE0_AUX_PPS3"), + MTK_FUNCTION(4, "GBE0_INTR"), + MTK_FUNCTION(5, "GBE1_INTR"), + MTK_FUNCTION(6, "GBE1_AUX_PPS3"), + MTK_FUNCTION(7, "GBE1_MDIO") + ), + MTK_PIN( + 228, "GPIO228", + MTK_EINT_FUNCTION(0, 228), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO228"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "I2SIN3_DI"), + MTK_FUNCTION(3, "GBE0_MDC"), + MTK_FUNCTION(4, "GBE1_MDC"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_AICE_TCKC") + ), + MTK_PIN( + 229, "GPIO229", + MTK_EINT_FUNCTION(0, 229), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO229"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "I2SOUT3_DO"), + MTK_FUNCTION(3, "GBE0_MDIO"), + MTK_FUNCTION(4, "GBE1_MDIO"), + MTK_FUNCTION(5, "CONN_BG_GPS_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "AVB_CLK2") + ), + MTK_PIN( + 230, "GPIO230", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO230"), + MTK_FUNCTION(1, "CONN_TOP_CLK") + ), + MTK_PIN( + 231, "GPIO231", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO231"), + MTK_FUNCTION(1, "CONN_TOP_DATA") + ), + MTK_PIN( + 232, "GPIO232", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO232"), + MTK_FUNCTION(1, "CONN_HRST_B") + ), + MTK_PIN( + 233, "GPIO233", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO233"), + MTK_FUNCTION(1, "I2SIN0_BCK") + ), + MTK_PIN( + 234, "GPIO234", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO234"), + MTK_FUNCTION(1, "I2SIN0_LRCK") + ), + MTK_PIN( + 235, "GPIO235", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO235"), + MTK_FUNCTION(1, "I2SIN0_DI") + ), + MTK_PIN( + 236, "GPIO236", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO236"), + MTK_FUNCTION(1, "I2SOUT0_DO") + ), + MTK_PIN( + 237, "GPIO237", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO237"), + MTK_FUNCTION(1, "CONN_UARTHUB_UART_TX"), + MTK_FUNCTION(3, "UTXD3") + ), + MTK_PIN( + 238, "GPIO238", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO238"), + MTK_FUNCTION(1, "CONN_UARTHUB_UART_RX"), + MTK_FUNCTION(3, "URXD3") + ), + MTK_PIN( + 239, "GPIO239", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO239"), + MTK_FUNCTION(1, "TP_UTXD_CONSYS_VLP"), + MTK_FUNCTION(2, "TP_URXD_CONSYS_VLP") + ), + MTK_PIN( + 240, "GPIO240", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO240"), + MTK_FUNCTION(1, "TP_URXD_CONSYS_VLP"), + MTK_FUNCTION(2, "TP_UTXD_CONSYS_VLP") + ), + MTK_PIN( + 241, "GPIO241", + MTK_EINT_FUNCTION(0, 241), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO241"), + MTK_FUNCTION(1, "PCIE_PERSTN") + ), + MTK_PIN( + 242, "GPIO242", + MTK_EINT_FUNCTION(0, 242), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO242"), + MTK_FUNCTION(1, "PCIE_WAKEN") + ), + MTK_PIN( + 243, "GPIO243", + MTK_EINT_FUNCTION(0, 243), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO243"), + MTK_FUNCTION(1, "PCIE_CLKREQN") + ), + MTK_PIN( + 244, "GPIO244", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO244"), + MTK_FUNCTION(1, "CONN_RST") + ), + MTK_PIN( + 245, "GPIO245", + MTK_EINT_FUNCTION(0, 245), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO245") + ), + MTK_PIN( + 246, "GPIO246", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO246"), + MTK_FUNCTION(1, "CONN_PTA_TXD0") + ), + MTK_PIN( + 247, "GPIO247", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO247"), + MTK_FUNCTION(1, "CONN_PTA_RXD0") + ), + MTK_PIN( + 248, "GPIO248", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO248"), + MTK_FUNCTION(3, "UCTS3") + ), + MTK_PIN( + 249, "GPIO249", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO249"), + MTK_FUNCTION(3, "URTS3") + ), + MTK_PIN( + 250, "GPIO250", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO250") + ), + MTK_PIN( + 251, "GPIO251", + MTK_EINT_FUNCTION(0, 251), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO251"), + MTK_FUNCTION(1, "IDDIG_1P") + ), + MTK_PIN( + 252, "GPIO252", + MTK_EINT_FUNCTION(0, 252), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO252"), + MTK_FUNCTION(1, "USB_DRVVBUS_1P") + ), + MTK_PIN( + 253, "GPIO253", + MTK_EINT_FUNCTION(0, 253), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO253"), + MTK_FUNCTION(1, "VBUSVALID_1P") + ), + MTK_PIN( + 254, "GPIO254", + MTK_EINT_FUNCTION(0, 254), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO254"), + MTK_FUNCTION(1, "IDDIG_2P") + ), + MTK_PIN( + 255, "GPIO255", + MTK_EINT_FUNCTION(0, 255), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO255"), + MTK_FUNCTION(1, "USB_DRVVBUS_2P") + ), + MTK_PIN( + 256, "GPIO256", + MTK_EINT_FUNCTION(0, 256), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO256"), + MTK_FUNCTION(1, "VBUSVALID_2P") + ), + MTK_PIN( + 257, "GPIO257", + MTK_EINT_FUNCTION(0, 257), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO257"), + MTK_FUNCTION(1, "VBUSVALID_3P") + ), + MTK_PIN( + 258, "GPIO258", + MTK_EINT_FUNCTION(0, 258), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO258"), + MTK_FUNCTION(7, "AVB_CLK1") + ), + MTK_PIN( + 259, "GPIO259", + MTK_EINT_FUNCTION(0, 259), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO259"), + MTK_FUNCTION(1, "GBE0_TXD0"), + MTK_FUNCTION(2, "GBE1_TXD0") + ), + MTK_PIN( + 260, "GPIO260", + MTK_EINT_FUNCTION(0, 260), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO260"), + MTK_FUNCTION(1, "GBE0_TXD1"), + MTK_FUNCTION(2, "GBE1_TXD1") + ), + MTK_PIN( + 261, "GPIO261", + MTK_EINT_FUNCTION(0, 261), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO261"), + MTK_FUNCTION(1, "GBE0_TXC"), + MTK_FUNCTION(2, "GBE1_TXC") + ), + MTK_PIN( + 262, "GPIO262", + MTK_EINT_FUNCTION(0, 262), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO262"), + MTK_FUNCTION(1, "GBE0_TXEN"), + MTK_FUNCTION(2, "GBE1_TXEN") + ), + MTK_PIN( + 263, "GPIO263", + MTK_EINT_FUNCTION(0, 263), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO263"), + MTK_FUNCTION(1, "GBE0_RXD0"), + MTK_FUNCTION(2, "GBE1_RXD0"), + MTK_FUNCTION(3, "GBE0_AUX_PPS0") + ), + MTK_PIN( + 264, "GPIO264", + MTK_EINT_FUNCTION(0, 264), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO264"), + MTK_FUNCTION(1, "GBE0_RXD1"), + MTK_FUNCTION(2, "GBE1_RXD1"), + MTK_FUNCTION(3, "GBE0_AUX_PPS1") + ), + MTK_PIN( + 265, "GPIO265", + MTK_EINT_FUNCTION(0, 265), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO265"), + MTK_FUNCTION(1, "GBE0_RXC"), + MTK_FUNCTION(2, "GBE1_RXC"), + MTK_FUNCTION(3, "GBE0_AUX_PPS2") + ), + MTK_PIN( + 266, "GPIO266", + MTK_EINT_FUNCTION(0, 266), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO266"), + MTK_FUNCTION(1, "GBE0_RXDV"), + MTK_FUNCTION(2, "GBE1_RXDV"), + MTK_FUNCTION(3, "GBE0_AUX_PPS3") + ), + MTK_PIN( + 267, "GPIO267", + MTK_EINT_FUNCTION(0, 267), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO267"), + MTK_FUNCTION(1, "GBE0_TXD2"), + MTK_FUNCTION(2, "GBE1_TXD2"), + MTK_FUNCTION(3, "GBE0_RXER"), + MTK_FUNCTION(4, "GBE1_RXER") + ), + MTK_PIN( + 268, "GPIO268", + MTK_EINT_FUNCTION(0, 268), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO268"), + MTK_FUNCTION(1, "GBE0_TXD3"), + MTK_FUNCTION(2, "GBE1_TXD3") + ), + MTK_PIN( + 269, "GPIO269", + MTK_EINT_FUNCTION(0, 269), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO269"), + MTK_FUNCTION(1, "GBE0_RXD2"), + MTK_FUNCTION(2, "GBE1_RXD2"), + MTK_FUNCTION(3, "GBE0_MDC") + ), + MTK_PIN( + 270, "GPIO270", + MTK_EINT_FUNCTION(0, 270), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO270"), + MTK_FUNCTION(1, "GBE0_RXD3"), + MTK_FUNCTION(2, "GBE1_RXD3"), + MTK_FUNCTION(3, "GBE0_MDIO") + ), + MTK_PIN( + 271, "veint271", + MTK_EINT_FUNCTION(0, 271), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 272, "veint272", + MTK_EINT_FUNCTION(0, 272), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 273, "veint273", + MTK_EINT_FUNCTION(0, 273), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 274, "veint274", + MTK_EINT_FUNCTION(0, 274), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 275, "veint275", + MTK_EINT_FUNCTION(0, 275), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 276, "veint276", + MTK_EINT_FUNCTION(0, 276), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 277, "veint277", + MTK_EINT_FUNCTION(0, 277), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 278, "veint278", + MTK_EINT_FUNCTION(0, 278), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 279, "veint279", + MTK_EINT_FUNCTION(0, 279), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 280, "veint280", + MTK_EINT_FUNCTION(0, 280), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 281, "veint281", + MTK_EINT_FUNCTION(0, 281), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 282, "veint282", + MTK_EINT_FUNCTION(0, 282), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 283, "veint283", + MTK_EINT_FUNCTION(0, 283), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 284, "veint284", + MTK_EINT_FUNCTION(0, 284), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 285, "veint285", + MTK_EINT_FUNCTION(0, 285), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 286, "veint286", + MTK_EINT_FUNCTION(0, 286), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 287, "veint287", + MTK_EINT_FUNCTION(0, 287), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 288, "veint288", + MTK_EINT_FUNCTION(0, 288), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 289, "veint289", + MTK_EINT_FUNCTION(0, 289), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 290, "veint290", + MTK_EINT_FUNCTION(0, 290), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 291, "veint291", + MTK_EINT_FUNCTION(0, 291), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ), + MTK_PIN( + 292, "veint292", + MTK_EINT_FUNCTION(0, 292), + DRV_GRP4, + MTK_FUNCTION(0, NULL) + ) +}; + +#endif /* __PINCTRL_MTK_MT8196_H */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2025-02-19 9:19 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-15 6:35 [PATCH v3 0/2] MediaTek pinctrl patch on mt8196 Cathy Xu 2025-01-15 6:35 ` [PATCH v3 1/2] dt-bindings: pinctrl: mediatek: add support for mt8196 Cathy Xu 2025-01-15 9:50 ` Krzysztof Kozlowski 2025-01-16 2:20 ` Cathy Xu (许华婷) 2025-01-16 7:28 ` Krzysztof Kozlowski 2025-01-16 8:18 ` Cathy Xu (许华婷) 2025-01-16 8:33 ` Chen-Yu Tsai 2025-01-20 9:12 ` Cathy Xu (许华婷) 2025-01-16 10:20 ` Krzysztof Kozlowski 2025-01-20 9:17 ` Cathy Xu (许华婷) 2025-01-20 12:42 ` AngeloGioacchino Del Regno 2025-01-21 9:56 ` Cathy Xu (许华婷) 2025-01-21 10:03 ` Chen-Yu Tsai 2025-02-17 9:45 ` Cathy Xu (许华婷) 2025-02-17 10:24 ` Chen-Yu Tsai 2025-02-19 8:54 ` Cathy Xu (许华婷) 2025-01-15 6:35 ` [PATCH v3 2/2] pinctrl: mediatek: add mt8196 driver Cathy Xu
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