* [PATCH v1 01/14] net/zxdh: add network processor registers ops
@ 2025-02-10 1:44 Bingbin Chen
2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen
` (7 more replies)
0 siblings, 8 replies; 114+ messages in thread
From: Bingbin Chen @ 2025-02-10 1:44 UTC (permalink / raw)
To: dev; +Cc: Bingbin Chen
[-- Attachment #1.1.1: Type: text/plain, Size: 35481 bytes --]
Add (np)network processor registers read/write interfaces.
Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn>
---
drivers/net/zxdh/zxdh_np.c | 792 +++++++++++++++++++++++++++++++------
drivers/net/zxdh/zxdh_np.h | 94 ++++-
2 files changed, 761 insertions(+), 125 deletions(-)
diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c
index 1e6e8f0e75..cbab2a3aaa 100644
--- a/drivers/net/zxdh/zxdh_np.c
+++ b/drivers/net/zxdh/zxdh_np.c
@@ -14,7 +14,6 @@
#include "zxdh_np.h"
#include "zxdh_logs.h"
-static uint64_t g_np_bar_offset;
static ZXDH_DEV_MGR_T g_dev_mgr;
static ZXDH_SDT_MGR_T g_sdt_mgr;
static uint32_t g_dpp_dtb_int_enable;
@@ -22,14 +21,185 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX];
ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX];
ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX];
ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX];
-ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX];
-ZXDH_REG_T g_dpp_reg_info[4];
-ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4];
ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX];
ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg;
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = {
+ {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
+ {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
+ {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0},
+ {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = {
+ {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = {
+ {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = {
+ {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = {
+ {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = {
+ {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = {
+ {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
+};
+
+ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = {
+ {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0},
+};
+
+ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = {
+ {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
+ {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
+ {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
+ {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
+ {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0},
+ {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0},
+ {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"rw_len", 123, 2},
+ {"v46_flag", 121, 1},
+ {"lpm_wr_vld", 120, 1},
+ {"baddr", 119, 20},
+ {"ecc_en", 99, 1},
+ {"rw_addr", 29, 30},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"data_mode", 123, 2},
+ {"cpu_wr", 121, 1},
+ {"cpu_rd", 120, 1},
+ {"cpu_rd_mode", 119, 1},
+ {"addr", 113, 26},
+ {"data_h", 0, 1},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"data_mode", 123, 2},
+ {"cpu_wr", 121, 1},
+ {"cpu_rd", 120, 1},
+ {"cpu_rd_mode", 119, 1},
+ {"addr", 113, 26},
+ {"data_h", 63, 32},
+ {"data_l", 31, 32},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"data_mode", 123, 2},
+ {"cpu_wr", 121, 1},
+ {"cpu_rd", 120, 1},
+ {"cpu_rd_mode", 119, 1},
+ {"addr", 113, 26},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"ram_reg_flag", 123, 1},
+ {"zgroup_id", 122, 2},
+ {"zblock_id", 120, 3},
+ {"zcell_id", 117, 2},
+ {"mask", 115, 4},
+ {"sram_addr", 111, 9},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"block_sel", 123, 3},
+ {"init_en", 120, 1},
+ {"row_or_col_msk", 119, 1},
+ {"vben", 118, 1},
+ {"reg_tcam_flag", 117, 1},
+ {"uload", 116, 8},
+ {"rd_wr", 108, 1},
+ {"wr_mode", 107, 8},
+ {"data_or_mask", 99, 1},
+ {"addr", 98, 9},
+ {"vbit", 89, 8},
+};
+
+ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = {
+ {"valid", 127, 1},
+ {"type_mode", 126, 3},
+ {"std_h", 63, 32},
+ {"std_l", 31, 32},
+};
+
+ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = {
+ {
+ "ddr",
+ ZXDH_DTB_TABLE_DDR,
+ 8,
+ g_dtb_ddr_table_cmd_info,
+ },
+ {
+ "eram 1 bit",
+ ZXDH_DTB_TABLE_ERAM_1,
+ 8,
+ g_dtb_eram_table_cmd_1_info,
+ },
+ {
+ "eram 64 bit",
+ ZXDH_DTB_TABLE_ERAM_64,
+ 9,
+ g_dtb_eram_table_cmd_64_info,
+ },
+ {
+ "eram 128 bit",
+ ZXDH_DTB_TABLE_ERAM_128,
+ 7,
+ g_dtb_eram_table_cmd_128_info,
+ },
+ {
+ "zcam",
+ ZXDH_DTB_TABLE_ZCAM,
+ 8,
+ g_dtb_zcam_table_cmd_info,
+ },
+ {
+ "etcam",
+ ZXDH_DTB_TABLE_ETCAM,
+ 13,
+ g_dtb_etcam_table_cmd_info,
+ },
+ {
+ "mc_hash",
+ ZXDH_DTB_TABLE_MC_HASH,
+ 4,
+ g_dtb_mc_hash_table_cmd_info
+ },
+};
+
#define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr)
#define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id])
+#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id])
+
+#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \
+ (((data_len) & 0x3ff) | \
+ ((int_en) << 29) | \
+ ((cmd_type) << 30))
#define ZXDH_COMM_MASK_BIT(_bitnum_)\
(0x1U << (_bitnum_))
@@ -115,8 +285,23 @@ do {\
} \
} while (0)
+static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data)
+{
+ return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8;
+}
+
+static inline uint32_t
+zxdh_np_comm_convert32(uint32_t dw_data)
+{
+ return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 |
+ ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24;
+}
+
#define ZXDH_COMM_CONVERT16(w_data) \
- (((w_data) & 0xff) << 8)
+ zxdh_np_comm_convert16(w_data)
+
+#define ZXDH_COMM_CONVERT32(w_data) \
+ zxdh_np_comm_convert32(w_data)
#define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \
(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index)
@@ -174,7 +359,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len)
uc_byte_mode = dw_byte_len % 4 & 0xff;
for (i = 0; i < dw_byte_num; i++) {
- (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp);
+ (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp);
p_dw_tmp++;
}
@@ -198,6 +383,329 @@ zxdh_np_dev_init(void)
return 0;
}
+static uint32_t
+zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+ ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+ p_dev_info = ZXDH_DEV_INFO_GET(dev_id);
+
+ if (p_dev_info == NULL) {
+ PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist",
+ dev_id);
+ return ZXDH_ERR;
+ }
+ if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) {
+ p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data);
+ } else {
+ PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid",
+ p_dev_info->access_type);
+ return ZXDH_ERR;
+ }
+
+ return ZXDH_OK;
+}
+
+static uint32_t
+zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+ ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+ p_dev_info = ZXDH_DEV_INFO_GET(dev_id);
+
+ if (p_dev_info == NULL) {
+ PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist",
+ dev_id);
+ return ZXDH_ERR;
+ }
+ if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) {
+ p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data);
+ } else {
+ PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid",
+ p_dev_info->access_type);
+ return ZXDH_ERR;
+ }
+
+ return ZXDH_OK;
+}
+
+static void
+zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data)
+{
+ uint32_t data = 0;
+ uint64_t addr = 0;
+
+ data = *p_data;
+
+ if (zxdh_np_comm_is_big_endian())
+ data = ZXDH_COMM_CONVERT32(data);
+
+ addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET;
+ *((volatile uint32_t *)addr) = data;
+}
+
+static void
+zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data)
+{
+ uint32_t data = 0;
+ uint64_t addr = 0;
+
+ addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET;
+ data = *((volatile uint32_t *)addr);
+
+ if (zxdh_np_comm_is_big_endian())
+ data = ZXDH_COMM_CONVERT32(data);
+
+ *p_data = data;
+}
+
+static uint64_t
+zxdh_np_dev_get_pcie_addr(uint32_t dev_id)
+{
+ ZXDH_DEV_MGR_T *p_dev_mgr = NULL;
+ ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+ p_dev_mgr = &g_dev_mgr;
+ p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+ if (p_dev_info == NULL)
+ return ZXDH_DEV_TYPE_INVALID;
+
+ return p_dev_info->pcie_addr;
+}
+
+static void
+zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+ uint32_t i;
+ uint64_t abs_addr = 0;
+
+ abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr;
+
+ for (i = 0; i < size; i++)
+ zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i);
+}
+
+static void
+zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+ uint32_t i;
+ uint64_t abs_addr = 0;
+
+ abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr;
+
+ for (i = 0; i < size; i++)
+ zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i);
+}
+
+static uint32_t
+zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+ return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data);
+}
+
+static uint32_t
+zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+ return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data);
+}
+
+static uint32_t
+zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+ return zxdh_np_write(dev_id, addr, p_data);
+}
+
+static uint32_t
+zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+ return zxdh_np_read(dev_id, addr, p_data);
+}
+
+ZXDH_REG_T g_dpp_reg_info[] = {
+ {
+ "cpu_ind_cmd",
+ 669,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000014,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 4,
+ g_smmu0_smmu0_cpu_ind_cmd_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "cpu_ind_rd_done",
+ 670,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000040,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_cpu_ind_rd_done_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "cpu_ind_rdat0",
+ 671,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000044,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_cpu_ind_rdat0_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "cpu_ind_rdat1",
+ 672,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000048,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_cpu_ind_rdat1_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "cpu_ind_rdat2",
+ 673,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x0000004c,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_cpu_ind_rdat2_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "cpu_ind_rdat3",
+ 674,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000050,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_cpu_ind_rdat3_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "wr_arb_cpu_rdy",
+ 676,
+ SMMU0,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_NUL_ARRAY,
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x0000010c,
+ (32 / 8),
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ g_smmu0_smmu0_wr_arb_cpu_rdy_reg,
+ zxdh_np_se_smmu0_write,
+ zxdh_np_se_smmu0_read,
+ },
+ {
+ "info_queue_buf_space_left_0_127",
+ 820,
+ DTB4K,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_UNI_ARRAY,
+ ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x000c,
+ (32 / 8),
+ 0,
+ 127 + 1,
+ 0,
+ 32,
+ 1,
+ g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg,
+ zxdh_np_write,
+ zxdh_np_read,
+ },
+ {
+ "cfg_epid_v_func_num_0_127",
+ 821,
+ DTB4K,
+ ZXDH_REG_FLAG_DIRECT,
+ ZXDH_REG_UNI_ARRAY,
+ ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010,
+ (32 / 8),
+ 0,
+ 127 + 1,
+ 0,
+ 32,
+ 7,
+ g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg,
+ zxdh_np_write,
+ zxdh_np_read,
+ }
+};
+
+static uint32_t
+zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset)
+{
+ uint32_t addr = 0;
+ ZXDH_REG_T *p_reg_info = NULL;
+
+ p_reg_info = &g_dpp_reg_info[reg_no];
+
+ addr = p_reg_info->addr;
+
+ if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) {
+ if (n_offset > (p_reg_info->n_size - 1))
+ PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%d, n:%d,"
+ "size:%d", reg_no, n_offset, p_reg_info->n_size - 1);
+
+ addr += n_offset * p_reg_info->n_step;
+ } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) {
+ if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1)))
+ PMD_DRV_LOG(ERR, "reg n_offset or m_offset is out of range, reg_no:%d,"
+ "n:%d, n_size:%d, m:%d, m_size:%d,", reg_no, n_offset,
+ p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1);
+
+ addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step;
+ }
+
+ return addr;
+}
+
static uint32_t
zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type,
ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr,
@@ -221,7 +729,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type,
} else {
/* device is new. */
p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0);
- ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+ if (p_dev_info == NULL) {
+ PMD_DRV_LOG(ERR, "%s point null!", __func__);
+ return ZXDH_PAR_CHK_POINT_NULL;
+ }
p_dev_mgr->p_dev_array[dev_id] = p_dev_info;
p_dev_mgr->device_num++;
}
@@ -234,6 +745,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type,
p_dev_info->dma_vir_addr = dma_vir_addr;
p_dev_info->dma_phy_addr = dma_phy_addr;
+ p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write;
+ p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read;
+
return 0;
}
@@ -335,6 +849,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id)
return p_dpp_dtb_mgr[dev_id];
}
+static uint32_t
+zxdh_np_dtb_mgr_create(uint32_t dev_id)
+{
+ if (p_dpp_dtb_mgr[dev_id] != NULL) {
+ PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager"
+ " is exist!!!", ZXDH_RC_DTB_MGR_EXIST);
+ return ZXDH_RC_DTB_MGR_EXIST;
+ }
+
+ p_dpp_dtb_mgr[dev_id] = (ZXDH_DTB_MGR_T *)rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0);
+ if (p_dpp_dtb_mgr[dev_id] == NULL) {
+ PMD_DRV_LOG(ERR, "%s point null!", __func__);
+ return ZXDH_PAR_CHK_POINT_NULL;
+ }
+
+ return ZXDH_OK;
+}
+
static uint32_t
zxdh_np_dtb_soft_init(uint32_t dev_id)
{
@@ -345,10 +877,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id)
p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id);
if (p_dtb_mgr == NULL) {
- p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0);
+ zxdh_np_dtb_mgr_create(dev_id);
+
p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id);
if (p_dtb_mgr == NULL)
- return 1;
+ return ZXDH_RC_DTB_MGR_NOT_EXIST;
}
return 0;
@@ -428,36 +961,10 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset)
np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE)
? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0;
- g_np_bar_offset = bar_offset;
return np_addr;
}
-int
-zxdh_np_host_init(uint32_t dev_id,
- ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl)
-{
- ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0};
- uint32_t rc;
- uint64_t agent_addr;
-
- ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl);
-
- sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10);
- sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr,
- p_dev_init_ctrl->np_bar_offset);
- sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP;
- rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl);
- ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init");
-
- zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport);
-
- agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr;
- zxdh_np_dev_agent_addr_set(dev_id, agent_addr);
-
- return 0;
-}
-
static ZXDH_RISCV_DTB_MGR *
zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id)
{
@@ -574,20 +1081,39 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no,
ZXDH_FIELD_T *p_field_info = NULL;
uint32_t rc = 0;
uint32_t i;
+ uint32_t addr = 0;
+ uint32_t reg_module = 0;
+
+ p_reg_info = &g_dpp_reg_info[reg_no];
+ p_field_info = p_reg_info->p_fields;
+
+ reg_module = p_reg_info->module_no;
+
+ addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset);
+
+ if (reg_module == DTB4K) {
+ rc = p_reg_info->p_read_fun(dev_id, addr, p_buff);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun");
+ }
- if (reg_no < 4) {
- p_reg_info = &g_dpp_reg_info[reg_no];
- p_field_info = p_reg_info->p_fields;
- for (i = 0; i < p_reg_info->field_num; i++) {
- rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff,
- p_reg_info->width * 8,
- (uint32_t *)p_data + i,
- p_field_info[i].msb_pos,
- p_field_info[i].len);
- ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex");
- PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset);
+ if (!zxdh_np_comm_is_big_endian()) {
+ for (i = 0; i < p_reg_info->width / 4; i++) {
+ PMD_DRV_LOG(DEBUG, "%s data = 0x%08x.", __func__,
+ p_buff[i]);
+ p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]);
}
}
+
+ for (i = 0; i < p_reg_info->field_num; i++) {
+ rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff,
+ p_reg_info->width * 8,
+ (uint32_t *)p_data + i,
+ p_field_info[i].msb_pos,
+ p_field_info[i].len);
+ ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex");
+ PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset);
+ }
+
return rc;
}
@@ -596,20 +1122,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id,
uint32_t queue_id,
ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info)
{
- ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0};
- uint32_t rc;
+ uint32_t rc = 0;
+ uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR +
+ ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010;
+ uint32_t epid_v_func = 0;
- rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM,
- 0, queue_id, &vm_info);
- ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read");
+ rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel");
- p_vm_info->dbi_en = vm_info.dbi_en;
- p_vm_info->queue_en = vm_info.queue_en;
- p_vm_info->epid = vm_info.cfg_epid;
- p_vm_info->vector = vm_info.cfg_vector;
- p_vm_info->vfunc_num = vm_info.cfg_vfunc_num;
- p_vm_info->func_num = vm_info.cfg_func_num;
- p_vm_info->vfunc_active = vm_info.cfg_vfunc_active;
+ p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1);
+ p_vm_info->queue_en = (epid_v_func >> 30 & 0x1);
+ p_vm_info->epid = (epid_v_func >> 24 & 0xF);
+ p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF);
+ p_vm_info->vector = (epid_v_func >> 8 & 0x7);
+ p_vm_info->func_num = (epid_v_func >> 5 & 0x7);
+ p_vm_info->vfunc_active = (epid_v_func & 0x1);
return rc;
}
@@ -695,29 +1222,52 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no,
ZXDH_REG_T *p_reg_info = NULL;
ZXDH_FIELD_T *p_field_info = NULL;
uint32_t temp_data;
- uint32_t rc;
+ uint32_t rc = ZXDH_OK;
uint32_t i;
+ uint32_t reg_module = 0;
+ uint32_t addr = 0;
+
+ p_reg_info = &g_dpp_reg_info[reg_no];
+ p_field_info = p_reg_info->p_fields;
+
+ reg_module = p_reg_info->module_no;
+
+ for (i = 0; i < p_reg_info->field_num; i++) {
+ if (p_field_info[i].len <= 32) {
+ temp_data = *((uint32_t *)p_data + i) & ZXDH_COMM_GET_BIT_MASK(uint32_t,
+ p_field_info[i].len);
+ rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff,
+ p_reg_info->width * 8,
+ temp_data,
+ p_field_info[i].msb_pos,
+ p_field_info[i].len);
+ ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex");
+ }
+ }
+
+ PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]);
- if (reg_no < 4) {
- p_reg_info = &g_dpp_reg_info[reg_no];
- p_field_info = p_reg_info->p_fields;
-
- for (i = 0; i < p_reg_info->field_num; i++) {
- if (p_field_info[i].len <= 32) {
- temp_data = *((uint32_t *)p_data + i);
- rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff,
- p_reg_info->width * 8,
- temp_data,
- p_field_info[i].msb_pos,
- p_field_info[i].len);
- ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex");
- PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!",
- dev_id, m_offset, n_offset);
- }
+ if (!zxdh_np_comm_is_big_endian()) {
+ for (i = 0; i < p_reg_info->width / 4; i++) {
+ p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]);
+
+ PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.",
+ p_buff[i]);
}
}
- return 0;
+ addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset);
+
+ PMD_DRV_LOG(DEBUG, "reg_no = %d. m_offset = %d n_offset = %d",
+ reg_no, m_offset, n_offset);
+ PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr);
+
+ if (reg_module == DTB4K) {
+ rc = p_reg_info->p_write_fun(dev_id, addr, p_buff);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun");
+ }
+
+ return rc;
}
static uint32_t
@@ -796,11 +1346,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id,
{
uint32_t rc;
- if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) {
- *p_item_num = 32;
- return 0;
- }
-
rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE,
0, queue_id, p_item_num);
ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
@@ -850,20 +1395,11 @@ static void
zxdh_np_dtb_mgr_destroy(uint32_t dev_id)
{
if (p_dpp_dtb_mgr[dev_id] != NULL) {
- free(p_dpp_dtb_mgr[dev_id]);
+ rte_free(p_dpp_dtb_mgr[dev_id]);
p_dpp_dtb_mgr[dev_id] = NULL;
}
}
-static void
-zxdh_np_tlb_mgr_destroy(uint32_t dev_id)
-{
- if (g_p_dpp_tlb_mgr[dev_id] != NULL) {
- free(g_p_dpp_tlb_mgr[dev_id]);
- g_p_dpp_tlb_mgr[dev_id] = NULL;
- }
-}
-
static void
zxdh_np_sdt_mgr_destroy(uint32_t dev_id)
{
@@ -874,7 +1410,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id)
p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET();
if (p_sdt_tbl_temp != NULL)
- free(p_sdt_tbl_temp);
+ rte_free(p_sdt_tbl_temp);
ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL;
@@ -891,7 +1427,7 @@ zxdh_np_dev_del(uint32_t dev_id)
p_dev_info = p_dev_mgr->p_dev_array[dev_id];
if (p_dev_info != NULL) {
- free(p_dev_info);
+ rte_free(p_dev_info);
p_dev_mgr->p_dev_array[dev_id] = NULL;
p_dev_mgr->device_num--;
}
@@ -910,7 +1446,6 @@ zxdh_np_online_uninit(uint32_t dev_id,
"port name %s queue id %d", __func__, port_name, queue_id);
zxdh_np_dtb_mgr_destroy(dev_id);
- zxdh_np_tlb_mgr_destroy(dev_id);
zxdh_np_sdt_mgr_destroy(dev_id);
zxdh_np_dev_del(dev_id);
@@ -925,7 +1460,7 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no)
static ZXDH_DTB_TABLE_T *
-zxdh_np_table_info_get(uint32_t table_type)
+zxdh_np_dtb_table_info_get(uint32_t table_type)
{
return &g_dpp_dtb_table_info[table_type];
}
@@ -940,11 +1475,11 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
ZXDH_DTB_TABLE_T *p_table_info = NULL;
ZXDH_DTB_FIELD_T *p_field_info = NULL;
uint32_t temp_data;
- uint32_t rc;
+ uint32_t rc = 0;
ZXDH_COMM_CHECK_POINT(p_cmd_data);
ZXDH_COMM_CHECK_POINT(p_cmd_buff);
- p_table_info = zxdh_np_table_info_get(table_type);
+ p_table_info = zxdh_np_dtb_table_info_get(table_type);
p_field_info = p_table_info->p_fields;
ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
@@ -958,7 +1493,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
p_field_info[field_cnt].lsb_pos,
p_field_info[field_cnt].len);
- ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
+ ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex");
}
return rc;
@@ -1112,7 +1647,7 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
ZXDH_DTB_ENTRY_T *p_dtb_one_entry)
{
uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0};
- ZXDH_SDTTBL_ERAM_T sdt_eram = {0};
+ ZXDH_SDT_TBL_ERAM_T sdt_eram = {0};
ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL;
uint32_t base_addr;
uint32_t index;
@@ -1283,16 +1818,25 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id,
uint32_t queue_id,
ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info)
{
- ZXDH_DTB_QUEUE_LEN_T dtb_len = {0};
uint32_t rc;
- dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type;
- dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en;
- dtb_len.cfg_queue_dtb_len = p_item_info->data_len;
+ uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR +
+ ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000;
+ uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR +
+ ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004;
+ uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR +
+ ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008;
+ uint32_t dtb_len = 0;
- rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN,
- 0, queue_id, (void *)&dtb_len);
- ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
+ rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32,
+ 1, &p_item_info->data_hddr);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
+ rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32,
+ 1, &p_item_info->data_laddr);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
+ dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len);
+ rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
return rc;
}
@@ -1577,8 +2121,8 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_
uint32_t tbl_type = 0;
uint32_t clutch_en = 0;
- ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL;
- ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
+ ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL;
+ ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL;
ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32,
ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
@@ -1587,7 +2131,7 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_
switch (tbl_type) {
case ZXDH_SDT_TBLT_ERAM:
{
- p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info;
+ p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info;
p_sdt_eram->table_type = tbl_type;
p_sdt_eram->eram_clutch_en = clutch_en;
break;
@@ -1595,7 +2139,7 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_
case ZXDH_SDT_TBLT_PORTTBL:
{
- p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info;
+ p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info;
p_sdt_porttbl->table_type = tbl_type;
p_sdt_porttbl->porttbl_clutch_en = clutch_en;
break;
@@ -1661,7 +2205,7 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no,
{
uint32_t index = p_dump_eram_entry->index;
uint32_t *p_data = p_dump_eram_entry->p_data;
- ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0};
+ ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0};
uint32_t temp_data[4] = {0};
uint32_t row_index = 0;
uint32_t col_index = 0;
@@ -2058,3 +2602,29 @@ zxdh_np_dtb_stats_get(uint32_t dev_id,
return rc;
}
+
+int
+zxdh_np_host_init(uint32_t dev_id,
+ ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl)
+{
+ ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0};
+ uint32_t rc;
+ uint64_t agent_addr;
+
+ ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl);
+
+ sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10);
+ sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr,
+ p_dev_init_ctrl->np_bar_offset);
+ sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP;
+
+ rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl);
+ ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init");
+
+ zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport);
+
+ agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr;
+ zxdh_np_dev_agent_addr_set(dev_id, agent_addr);
+
+ return 0;
+}
diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h
index 7da29cf7bd..35130bdd1b 100644
--- a/drivers/net/zxdh/zxdh_np.h
+++ b/drivers/net/zxdh/zxdh_np.h
@@ -6,7 +6,10 @@
#define ZXDH_NP_H
#include <stdint.h>
+#include <pthread.h>
+#define ZXDH_OK (0)
+#define ZXDH_ERR (1)
#define ZXDH_DISABLE (0)
#define ZXDH_ENABLE (1)
#define ZXDH_PORT_NAME_MAX (32)
@@ -51,11 +54,23 @@
#define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9)
#define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10)
+#define ZXDH_REG_NUL_ARRAY (0 << 0)
+#define ZXDH_REG_UNI_ARRAY (1 << 0)
+#define ZXDH_REG_BIN_ARRAY (1 << 1)
+#define ZXDH_REG_FLAG_INDIRECT (1 << 0)
+#define ZXDH_REG_FLAG_DIRECT (0 << 0)
+#define ZXDH_FIELD_FLAG_RO (1 << 0)
+#define ZXDH_FIELD_FLAG_RW (1 << 1)
+
+#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000)
+#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000)
+
#define ZXDH_ACL_TBL_ID_MIN (0)
#define ZXDH_ACL_TBL_ID_MAX (7)
#define ZXDH_ACL_TBL_ID_NUM (8U)
#define ZXDH_ACL_BLOCK_NUM (8U)
+#define ZXDH_RD_CNT_MAX (100)
#define ZXDH_SMMU0_READ_REG_MAX_NUM (4)
#define ZXDH_DTB_ITEM_ACK_SIZE (16)
@@ -95,6 +110,8 @@
#define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \
(ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK)
+#define ZXDH_SE_OPR_RD (1)
+
/**errco code */
#define ZXDH_RC_BASE (0x1000U)
#define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200)
@@ -144,6 +161,17 @@
#define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17)
#define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18)
+typedef enum zxdh_module_base_addr_e {
+ ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000,
+ ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000,
+} ZXDH_MODULE_BASE_ADDR_E;
+
+typedef enum zxdh_sys_base_addr_e {
+ ZXDH_SYS_SE_SMMU0_BASE_ADDR = (ZXDH_SYS_NP_BASE_ADDR0 + 0x00300000),
+ ZXDH_SYS_DTB_BASE_ADDR = (ZXDH_SYS_NP_BASE_ADDR1 + 0x00000000),
+ ZXDH_SYS_MAX_BASE_ADDR = 0x20000000,
+} ZXDH_SYS_BASE_ADDR_E;
+
typedef enum zxdh_module_init_e {
ZXDH_MODULE_INIT_NPPU = 0,
ZXDH_MODULE_INIT_PPU,
@@ -165,14 +193,24 @@ typedef enum zxdh_dev_type_e {
} ZXDH_DEV_TYPE_E;
typedef enum zxdh_reg_info_e {
- ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0,
- ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1,
- ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2,
- ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3,
- ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4,
+ ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0,
+ ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1,
+ ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2,
+ ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3,
+ ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4,
+ ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5,
+ ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6,
+ ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7,
+ ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8,
ZXDH_REG_ENUM_MAX_VALUE
} ZXDH_REG_INFO_E;
+typedef enum zxdh_dev_mutex_type_e {
+ ZXDH_DEV_MUTEX_T_SMMU0 = 0,
+ ZXDH_DEV_MUTEX_T_DTB = 1,
+ ZXDH_DEV_MUTEX_T_MAX
+} ZXDH_DEV_MUTEX_TYPE_E;
+
typedef enum zxdh_dev_access_type_e {
ZXDH_DEV_ACCESS_TYPE_PCIE = 0,
ZXDH_DEV_ACCESS_TYPE_RISCV = 1,
@@ -192,6 +230,29 @@ typedef enum zxdh_acl_pri_mode_e {
ZXDH_ACL_PRI_INVALID,
} ZXDH_ACL_PRI_MODE_E;
+typedef enum zxdh_module_e {
+ CFG = 1,
+ NPPU,
+ PPU,
+ ETM,
+ STAT,
+ CAR,
+ SE,
+ SMMU0 = SE,
+ SMMU1 = SE,
+ DTB,
+ TRPG,
+ TSN,
+ AXI,
+ PTPTM,
+ DTB4K,
+ STAT4K,
+ PPU4K,
+ SE4K,
+ SMMU14K,
+ MODULE_MAX
+} ZXDH_MODULE_E;
+
typedef struct zxdh_d_node {
void *data;
struct zxdh_d_node *prev;
@@ -256,6 +317,15 @@ typedef struct dpp_sdt_soft_table_t {
ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX];
} ZXDH_SDT_SOFT_TABLE_T;
+typedef struct zxdh_mutex_t {
+ pthread_mutex_t mutex;
+} ZXDH_MUTEX_T;
+
+typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id,
+ uint32_t addr, uint32_t size, uint32_t *p_data);
+typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id,
+ uint32_t addr, uint32_t size, uint32_t *p_data);
+
typedef struct zxdh_sys_init_ctrl_t {
ZXDH_DEV_TYPE_E device_type;
uint32_t flags;
@@ -282,6 +352,8 @@ typedef struct dpp_dev_cfg_t {
uint64_t dma_phy_addr;
uint64_t agent_addr;
uint32_t init_flags[ZXDH_MODULE_INIT_MAX];
+ ZXDH_DEV_WRITE_FUNC p_pcie_write_fun;
+ ZXDH_DEV_READ_FUNC p_pcie_read_fun;
} ZXDH_DEV_CFG_T;
typedef struct zxdh_dev_mngr_t {
@@ -476,7 +548,7 @@ typedef struct zxdh_sdt_tbl_eram_t {
uint32_t eram_base_addr;
uint32_t eram_table_depth;
uint32_t eram_clutch_en;
-} ZXDH_SDTTBL_ERAM_T;
+} ZXDH_SDT_TBL_ERAM_T;
typedef union zxdh_endian_u {
unsigned int a;
@@ -505,12 +577,6 @@ typedef struct zxdh_dtb_queue_item_info_t {
uint32_t data_hddr;
} ZXDH_DTB_QUEUE_ITEM_INFO_T;
-typedef struct zxdh_dtb_queue_len_t {
- uint32_t cfg_dtb_cmd_type;
- uint32_t cfg_dtb_cmd_int_en;
- uint32_t cfg_queue_dtb_len;
-} ZXDH_DTB_QUEUE_LEN_T;
-
typedef struct zxdh_dtb_eram_entry_info_t {
uint32_t index;
uint32_t *p_data;
@@ -537,12 +603,12 @@ typedef struct zxdh_sdt_tbl_etcam_t {
uint32_t as_rsp_mode;
uint32_t etcam_table_depth;
uint32_t etcam_clutch_en;
-} ZXDH_SDTTBL_ETCAM_T;
+} ZXDH_SDT_TBL_ETCAM_T;
typedef struct zxdh_sdt_tbl_porttbl_t {
uint32_t table_type;
uint32_t porttbl_clutch_en;
-} ZXDH_SDTTBL_PORTTBL_T;
+} ZXDH_SDT_TBL_PORT_TBL_T;
typedef struct zxdh_dtb_hash_entry_info_t {
uint8_t *p_actu_key;
--
2.27.0
[-- Attachment #1.1.2: Type: text/html , Size: 86101 bytes --]
^ permalink raw reply related [flat|nested] 114+ messages in thread* [PATCH v1 02/14] net/zxdh: support compatibility check 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-02-10 1:46 ` Bingbin Chen 2025-02-10 17:25 ` Stephen Hemminger 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen ` (6 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:46 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5383 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 +++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index cbab2a3aaa..538e3829aa 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -23,6 +23,9 @@ ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -965,6 +968,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + rte_memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2626,5 +2714,10 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 35130bdd1b..1df85bd382 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_OPR_RD (1) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -628,6 +631,15 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 9837 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 02/14] net/zxdh: support compatibility check 2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-02-10 17:25 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:25 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:46:45 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + > +static void > +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, > + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) > +{ > + void *fw_addr = NULL; > + uint64_t module_compatible_addr = 0; Why do you initialize variables then set then in the next statement. Sure the compiler will optimize away the waste, but not good style. > + > + module_compatible_addr = compatible_base_addr + > + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); > + > + fw_addr = (void *)module_compatible_addr; You could skip the temporary variable here and just put cast in the memcpy. > + > + rte_memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); > +} We want to get rid of rte_memcpy(), only use it where it is performance sensitive and variable size. ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 03/14] net/zxdh: add agent channel 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-02-10 1:47 ` Bingbin Chen 2025-02-10 17:28 ` Stephen Hemminger ` (3 more replies) 2025-02-10 1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (5 subsequent siblings) 7 siblings, 4 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:47 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 21723 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 481 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 77 ++++++ 2 files changed, 557 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 538e3829aa..bab8b23a68 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -13,6 +13,7 @@ #include "zxdh_np.h" #include "zxdh_logs.h" +#include "zxdh_msg.h" static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; @@ -234,6 +235,21 @@ do {\ } \ } while (0) +#define ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, becall, mutex)\ +do {\ + uint32_t temp_rc = rc;\ + if ((temp_rc) != ZXDH_OK) {\ + PMD_DRV_LOG(ERR, "ZXDH %s:%d [ErrorCode:0x%x]!-- %s"\ + "Call %s Fail!", __FILE__, __LINE__, temp_rc, __func__, becall);\ + if (zxdh_np_comm_mutex_unlock(mutex) != 0) { \ + PMD_DRV_LOG(ERR, "File: [%s], Function:[%s], Line:%u mutex"\ + "unlock failed!-->Return ERROR",\ + __FILE__, __func__, __LINE__);\ + } \ + RTE_ASSERT(0);\ + } \ +} while (0) + #define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ do {\ if ((point) == NULL) {\ @@ -330,6 +346,66 @@ zxdh_np_comm_convert32(uint32_t dw_data) #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) +static uint32_t +zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) +{ + int32_t rc = 0; + + rc = pthread_mutex_init(&p_mutex->mutex, NULL); + if (rc != 0) { + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Create mutex failed", + ZXDH_MUTEX_LOCK_INIT_FAIL); + return ZXDH_MUTEX_LOCK_INIT_FAIL; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_mutex_destroy(ZXDH_MUTEX_T *p_mutex) +{ + int32_t rc = 0; + + rc = pthread_mutex_destroy(&p_mutex->mutex); + if (rc != 0) { + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Destroy mutex fail", + ZXDH_MUTEX_LOCK_DESTROY_FAIL); + return ZXDH_MUTEX_LOCK_DESTROY_FAIL; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_mutex_lock(ZXDH_MUTEX_T *p_mutex) +{ + int32_t rc = 0; + + rc = pthread_mutex_lock(&p_mutex->mutex); + if (rc != 0) { + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Get mutex lock fail.", + ZXDH_MUTEX_LOCK_LOCK_FAIL); + return rc; + } + + return rc; +} + +static uint32_t +zxdh_np_comm_mutex_unlock(ZXDH_MUTEX_T *p_mutex) +{ + int32_t rc = 0; + + rc = pthread_mutex_unlock(&p_mutex->mutex); + if (rc != 0) { + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Release mutex lock fail.", + ZXDH_MUTEX_LOCK_ULOCK_FAIL); + return ZXDH_MUTEX_LOCK_ULOCK_FAIL; + } + + return rc; +} + static uint32_t zxdh_np_comm_is_big_endian(void) { @@ -386,6 +462,83 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_mutex_get(uint32_t dev_id, uint32_t type, ZXDH_MUTEX_T **p_mutex_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %d ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_MUTEX_T_DTB: + { + *p_mutex_out = &p_dev_info->dtb_mutex; + } + break; + + default: + { + PMD_DRV_LOG(ERR, "mutex type is invalid!"); + return ZXDH_ERR; + } + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -715,6 +868,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, uint64_t riscv_addr, uint64_t dma_vir_addr, uint64_t dma_phy_addr) { + uint32_t rtn = ZXDH_OK; ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; @@ -751,7 +905,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; - return 0; + rtn = zxdh_np_comm_mutex_create(&p_dev_info->dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_create"); + + return rtn; } static uint32_t @@ -843,6 +1000,277 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + { + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + } + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + { + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + } + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + { + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + } + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + { + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + } + case ZXDH_RC_CTRLCH_MSG_DROP: + { + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + } + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + rte_memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__); + } + + rte_free(recv_buffer); + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = {0}; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_PCIE_BAR_MSG; + msgcfg.oper = ZXDH_BAR_MSG_NUM_REQ; + agent_msg.msg = (void *)&msgcfg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T); + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_REG_MSG; + msgcfg.subtype = reg_type; + msgcfg.oper = ZXDH_RD; + msgcfg.reg_no = reg_no; + msgcfg.addr = addr; + msgcfg.val_len = reg_width / 4; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent read resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + rte_memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_REG_MSG; + msgcfg.subtype = reg_type; + msgcfg.oper = ZXDH_WR; + msgcfg.reg_no = reg_no; + msgcfg.addr = addr; + msgcfg.val_len = reg_width / 4; + + rte_memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent write resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + rte_memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1053,6 +1481,30 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, + "zxdh_np_agent_channel_pcie_bar_request", p_dtb_mutex); + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1171,17 +1623,27 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = 0; + uint32_t reg_width = 0; + uint32_t reg_real_no = 0; + uint32_t reg_type = 0; p_reg_info = &g_dpp_reg_info[reg_no]; p_field_info = p_reg_info->p_fields; reg_module = p_reg_info->module_no; + reg_type = p_reg_info->flags; + reg_width = p_reg_info->width; + reg_real_no = p_reg_info->reg_no; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1314,11 +1776,17 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t reg_module = 0; uint32_t addr = 0; + uint32_t reg_width = 0; + uint32_t reg_type = 0; + uint32_t reg_real_no = 0; p_reg_info = &g_dpp_reg_info[reg_no]; p_field_info = p_reg_info->p_fields; reg_module = p_reg_info->module_no; + reg_width = p_reg_info->width; + reg_type = p_reg_info->flags; + reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1353,6 +1821,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -1515,6 +1987,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { + zxdh_np_comm_mutex_destroy(&p_dev_info->dtb_mutex); rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; @@ -2698,6 +3171,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); @@ -2719,5 +3193,10 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 1df85bd382..f454765f30 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -111,10 +111,17 @@ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) #define ZXDH_SE_OPR_RD (1) +#define ZXDH_CHANNEL_REPS_LEN (4) #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -127,6 +134,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_MUTEX_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_MUTEX_LOCK_INIT_FAIL (ZXDH_MUTEX_LOCK_BASE | 0x001) +#define ZXDH_MUTEX_LOCK_LOCK_FAIL (ZXDH_MUTEX_LOCK_BASE | 0x002) +#define ZXDH_MUTEX_LOCK_ULOCK_FAIL (ZXDH_MUTEX_LOCK_BASE | 0X003) +#define ZXDH_MUTEX_LOCK_DESTROY_FAIL (ZXDH_MUTEX_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -164,6 +177,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -349,6 +369,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -357,6 +378,7 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_MUTEX_T dtb_mutex; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -631,6 +653,38 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_np_agent_msg_type_e { + ZXDH_REG_MSG = 0, + ZXDH_DTB_MSG, + ZXDH_TM_MSG, + ZXDH_PLCR_MSG, + ZXDH_PKTRX_IND_REG_RW_MSG, + ZXDH_PCIE_BAR_MSG, + ZXDH_RESET_MSG, + ZXDH_PXE_MSG, + ZXDH_TM_FLOW_SHAPE, + ZXDH_TM_TD, + ZXDH_TM_SE_SHAPE, + ZXDH_TM_PP_SHAPE, + ZXDH_PLCR_CAR_RATE, + ZXDH_PLCR_CAR_PKT_RATE, + ZXDH_PPU_THASH_RSK, + ZXDH_ACL_MSG, + ZXDH_STAT_MSG, + ZXDH_RES_MSG, + ZXDH_MSG_MAX +} MSG_TYPE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -640,6 +694,29 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 49618 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 03/14] net/zxdh: add agent channel 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-02-10 17:28 ` Stephen Hemminger 2025-02-10 17:30 ` Stephen Hemminger ` (2 subsequent siblings) 3 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:28 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:47:02 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) > +{ > + int32_t rc = 0; > + > + rc = pthread_mutex_init(&p_mutex->mutex, NULL); > + if (rc != 0) { > + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Create mutex failed", > + ZXDH_MUTEX_LOCK_INIT_FAIL); > + return ZXDH_MUTEX_LOCK_INIT_FAIL; > + } We went through this recently with other drivers on the mailing list. You are adding dead code. On pthread man page: RETURN VALUE pthread_mutex_init always returns 0. The other mutex functions return 0 on success and a non-zero error code on error. ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 03/14] net/zxdh: add agent channel 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen 2025-02-10 17:28 ` Stephen Hemminger @ 2025-02-10 17:30 ` Stephen Hemminger 2025-02-10 17:31 ` Stephen Hemminger 2025-02-10 18:23 ` Stephen Hemminger 3 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:30 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:47:02 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > > +#define ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, becall, mutex)\ > +do {\ > + uint32_t temp_rc = rc;\ > + if ((temp_rc) != ZXDH_OK) {\ > + PMD_DRV_LOG(ERR, "ZXDH %s:%d [ErrorCode:0x%x]!-- %s"\ > + "Call %s Fail!", __FILE__, __LINE__, temp_rc, __func__, becall);\ > + if (zxdh_np_comm_mutex_unlock(mutex) != 0) { \ > + PMD_DRV_LOG(ERR, "File: [%s], Function:[%s], Line:%u mutex"\ > + "unlock failed!-->Return ERROR",\ > + __FILE__, __func__, __LINE__);\ > + } \ > + RTE_ASSERT(0);\ > + } \ > +} while (0) Way to verbose and messy. 1. Your wrapper functions already log on error. 2. The messages are broken across lines and don't give any more information, just more words 3. The file and line is already logged by the PMD_DRV_LOG 4. RTE_ASSERT() is ignored unless RTE_ASSERT_DEBUG is enabled, and in that case it panics. ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 03/14] net/zxdh: add agent channel 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen 2025-02-10 17:28 ` Stephen Hemminger 2025-02-10 17:30 ` Stephen Hemminger @ 2025-02-10 17:31 ` Stephen Hemminger 2025-02-10 18:23 ` Stephen Hemminger 3 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:31 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:47:02 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + > + switch (type) { > + case ZXDH_DEV_MUTEX_T_DTB: > + { > + *p_mutex_out = &p_dev_info->dtb_mutex; > + } > + break; > + > + default: > + { > + PMD_DRV_LOG(ERR, "mutex type is invalid!"); > + return ZXDH_ERR; > + } > + } > + Why all the extra { } here? ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 03/14] net/zxdh: add agent channel 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen ` (2 preceding siblings ...) 2025-02-10 17:31 ` Stephen Hemminger @ 2025-02-10 18:23 ` Stephen Hemminger 3 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 18:23 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:47:02 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > Add agent channel to access (np)network processor registers > that are not mapped by PCIE. > > Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> > --- > drivers/net/zxdh/zxdh_np.c | 481 ++++++++++++++++++++++++++++++++++++- > drivers/net/zxdh/zxdh_np.h | 77 ++++++ > 2 files changed, 557 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c > index 538e3829aa..bab8b23a68 100644 > --- a/drivers/net/zxdh/zxdh_np.c > +++ b/drivers/net/zxdh/zxdh_np.c > @@ -13,6 +13,7 @@ > > #include "zxdh_np.h" > #include "zxdh_logs.h" > +#include "zxdh_msg.h" > > static ZXDH_DEV_MGR_T g_dev_mgr; > static ZXDH_SDT_MGR_T g_sdt_mgr; > @@ -234,6 +235,21 @@ do {\ > } \ > } while (0) > > +#define ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, becall, mutex)\ > +do {\ > + uint32_t temp_rc = rc;\ > + if ((temp_rc) != ZXDH_OK) {\ > + PMD_DRV_LOG(ERR, "ZXDH %s:%d [ErrorCode:0x%x]!-- %s"\ > + "Call %s Fail!", __FILE__, __LINE__, temp_rc, __func__, becall);\ > + if (zxdh_np_comm_mutex_unlock(mutex) != 0) { \ > + PMD_DRV_LOG(ERR, "File: [%s], Function:[%s], Line:%u mutex"\ > + "unlock failed!-->Return ERROR",\ > + __FILE__, __func__, __LINE__);\ > + } \ > + RTE_ASSERT(0);\ > + } \ > +} while (0) > + > #define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ > do {\ > if ((point) == NULL) {\ > @@ -330,6 +346,66 @@ zxdh_np_comm_convert32(uint32_t dw_data) > #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ > (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) > > +static uint32_t > +zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) > +{ > + int32_t rc = 0; > + > + rc = pthread_mutex_init(&p_mutex->mutex, NULL); > + if (rc != 0) { > + PMD_DRV_LOG(ERR, "ErrCode[ 0x%x ]: Create mutex failed", > + ZXDH_MUTEX_LOCK_INIT_FAIL); > + return ZXDH_MUTEX_LOCK_INIT_FAIL; > + } > + > + return ZXDH_OK; > +} Why do you need a pthread mutex versus one of the other existing DPDK locking primitives. A pthread_mutex is slower, has more errors to check, and is not portable. The one reason would be if you are trying to synchronize something that is slow (might sleep) or with an external non-DPDK program ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 04/14] net/zxdh: modify dtb queue ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-02-10 1:47 ` Bingbin Chen 2025-02-10 17:31 ` Stephen Hemminger 2025-02-10 1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (4 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:47 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 25896 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 513 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 +++++++ 2 files changed, 505 insertions(+), 105 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index bab8b23a68..1f16f75a23 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,7 @@ ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -539,6 +540,33 @@ zxdh_np_dev_opr_mutex_get(uint32_t dev_id, uint32_t type, ZXDH_MUTEX_T **p_mutex return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_mutex_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_MUTEX_T **p_mutex_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_MUTEX_T_DTB: + { + *p_mutex_out = &p_dev_info->dtb_queue_mutex[index]; + } + break; + + default: + { + PMD_DRV_LOG(ERR, "mutex type is invalid!"); + return ZXDH_ERR; + } + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -871,6 +899,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, uint32_t rtn = ZXDH_OK; ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -908,6 +937,11 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, rtn = zxdh_np_comm_mutex_create(&p_dev_info->dtb_mutex); ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_create"); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) { + rtn = zxdh_np_comm_mutex_create(&p_dev_info->dtb_queue_mutex[i]); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_create"); + } + return rtn; } @@ -1271,6 +1305,88 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_DTB_MSG; + msgcfg.oper = ZXDH_QUEUE_REQUEST; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + msgcfg.vport = vport_info; + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %d, msg_result: %d", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %d, queue_id: %d", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_DTB_MSG; + msgcfg.oper = ZXDH_QUEUE_RELEASE; + msgcfg.queue_id = queue_id; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %d", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1505,48 +1621,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1853,52 +1927,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1933,20 +1961,76 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + uint32_t vport_info = (uint32_t)vport; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + zxdh_np_comm_mutex_lock(p_dtb_mutex); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + zxdh_np_comm_mutex_unlock(p_dtb_mutex); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + zxdh_np_comm_mutex_unlock(p_dtb_mutex); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "%s:dev_id %d vport 0x%x name %s queue_id %d done.", + __func__, dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(devid, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_mutex_get"); + + zxdh_np_comm_mutex_lock(p_dtb_mutex); - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %d not request.", queueid); + zxdh_np_comm_mutex_unlock(p_dtb_mutex); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } + + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %d name error.", queueid); + zxdh_np_comm_mutex_unlock(p_dtb_mutex); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + zxdh_np_comm_mutex_unlock(p_dtb_mutex); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "%s:queueid %d", __func__, queueid); return rc; } @@ -1982,12 +2066,17 @@ zxdh_np_dev_del(uint32_t dev_id) { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { zxdh_np_comm_mutex_destroy(&p_dev_info->dtb_mutex); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + zxdh_np_comm_mutex_destroy(&p_dev_info->dtb_queue_mutex[i]); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; @@ -2417,24 +2506,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_MUTEX_T *p_mutex = NULL; + + zxdh_np_dev_dtb_opr_mutex_get(dev_id, ZXDH_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + zxdh_np_comm_mutex_lock(p_mutex); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2449,8 +2548,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2470,6 +2571,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + zxdh_np_comm_mutex_unlock(p_mutex); + return rc; } @@ -2860,20 +2963,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_MUTEX_T *p_mutex = NULL; + + zxdh_np_dev_dtb_opr_mutex_get(dev_id, ZXDH_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + zxdh_np_comm_mutex_lock(p_mutex); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2885,11 +2996,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.int_en = int_flag; item_info.data_len = desc_len / 4; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + zxdh_np_comm_mutex_unlock(p_mutex); + return rc; } @@ -2932,16 +3042,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_MUTEX_T *p_mutex = NULL; + + zxdh_np_dev_dtb_opr_mutex_get(dev_id, ZXDH_DEV_MUTEX_T_DTB, queue_id, &p_mutex); + zxdh_np_comm_mutex_lock(p_mutex); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2956,14 +3073,17 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + zxdh_np_comm_mutex_unlock(p_mutex); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + zxdh_np_comm_mutex_unlock(p_mutex); return 0; } @@ -3164,6 +3284,183 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = {0}; + + down_queue_cfg.down_start_phy_addr = phy_addr; + down_queue_cfg.down_start_vir_addr = vir_addr; + down_queue_cfg.down_item_size = size; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = {0}; + + dump_queue_cfg.up_start_phy_addr = phy_addr; + dump_queue_cfg.up_start_vir_addr = vir_addr; + dump_queue_cfg.up_item_size = size; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -3198,5 +3495,11 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + + PMD_DRV_LOG(INFO, "%s done, queue_id = %u", + __func__, p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index f454765f30..887760b3d8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -379,6 +379,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_MUTEX_T dtb_mutex; + ZXDH_MUTEX_T dtb_queue_mutex[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -567,6 +568,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -593,6 +666,15 @@ typedef struct zxdh_dtb_table_t { ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -685,6 +767,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -717,6 +804,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56019 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 04/14] net/zxdh: modify dtb queue ops 2025-02-10 1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-02-10 17:31 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:31 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:47:30 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c > index bab8b23a68..1f16f75a23 100644 > --- a/drivers/net/zxdh/zxdh_np.c > +++ b/drivers/net/zxdh/zxdh_np.c > @@ -27,6 +27,7 @@ ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; > static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; > static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { > ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; > +uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; Shouldn't this be static (so not visible everywhere) and const? ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 05/14] net/zxdh: add tables dump address ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (2 preceding siblings ...) 2025-02-10 1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-02-10 1:48 ` Bingbin Chen 2025-02-10 17:33 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (3 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:48 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 40663 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1146 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1237 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1f16f75a23..845d06a056 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -28,6 +28,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -347,6 +348,58 @@ zxdh_np_comm_convert32(uint32_t dw_data) #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +#define ZXDH_INIT_D_NODE(ptr, pdata) \ + do {\ + ZXDH_D_NODE *temp_ptr = ptr;\ + (temp_ptr)->data = pdata;\ + (temp_ptr)->prev = NULL;\ + (temp_ptr)->next = NULL;\ + } while (0) + +#define ZXDH_INIT_RBT_TN(p_tn, p_newkey) \ + do {\ + ZXDH_RB_TN *p_temp_tn = p_tn;\ + (p_temp_tn)->p_key = p_newkey; \ + (p_temp_tn)->color_lsv = 0; \ + (p_temp_tn)->p_left = NULL; \ + (p_temp_tn)->p_right = NULL; \ + (p_temp_tn)->p_parent = NULL; \ + ZXDH_INIT_D_NODE(&((p_temp_tn)->tn_ln), (p_temp_tn));\ + } while (0) + +#define ZXDH_GET_TN_LSV(p_tn) \ + ((p_tn)->color_lsv >> 2) + +#define ZXDH_SET_TN_LSV(p_tn, list_val) \ + do {\ + ZXDH_RB_TN *p_temp_tn = p_tn;\ + (p_temp_tn)->color_lsv &= 0x3;\ + (p_temp_tn)->color_lsv |= ((list_val) << 2); \ + } while (0) + +#define ZXDH_SET_TN_COLOR(p_tn, color) \ + do {\ + ZXDH_RB_TN *p_temp_tn = p_tn;\ + (p_temp_tn)->color_lsv &= 0xfffffffc;\ + (p_temp_tn)->color_lsv |= ((color) & 0x3);\ + } while (0) + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + +#define ZXDH_GET_TN_COLOR(p_tn) \ + zxdh_np_get_tn_color(p_tn) + static uint32_t zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) { @@ -449,6 +502,947 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_creat(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(INFO, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = (ZXDH_LISTSTACK_MANAGER *)rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, " %s Fail", __func__); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + PMD_DRV_LOG(INFO, " %s! ERROR LINE:%d ", __func__, __LINE__); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " %s is null! LINE:%d ", __func__, __LINE__); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(INFO, " %s is null! LINE:%d ", __func__, __LINE__); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_swich_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = ZXDH_GET_TN_COLOR(p_tn1); + color2 = ZXDH_GET_TN_COLOR(p_tn2); + + ZXDH_SET_TN_COLOR(p_tn1, color2); + ZXDH_SET_TN_COLOR(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + ZXDH_SET_TN_COLOR(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (ZXDH_GET_TN_COLOR(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (ZXDH_GET_TN_COLOR(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + ZXDH_SET_TN_COLOR(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + ZXDH_SET_TN_COLOR(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + ZXDH_SET_TN_COLOR(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_swich_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " %s already init!", __func__); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_creat(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_creat"); + + p_rb_cfg->p_keybase = (uint8_t *)rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = (ZXDH_RB_TN *)rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + ZXDH_INIT_RBT_TN(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + rte_memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + ZXDH_SET_TN_LSV(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + ZXDH_INIT_D_NODE(&p_ins_tn->tn_ln, p_ins_tn); + } + + ZXDH_SET_TN_COLOR(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(INFO, "info , rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = ZXDH_GET_TN_LSV(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + ZXDH_SET_TN_COLOR(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(ZXDH_GET_TN_COLOR(p_par_tn) == ZXDH_RBT_RED); + + ZXDH_SET_TN_COLOR(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (ZXDH_GET_TN_COLOR(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_swich_color(p_unc_tn, p_par_tn); + } else { + if (ZXDH_GET_TN_COLOR(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + ZXDH_GET_TN_COLOR(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (ZXDH_GET_TN_COLOR(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + ZXDH_SET_TN_COLOR(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(ZXDH_GET_TN_COLOR(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_swich_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (ZXDH_GET_TN_COLOR(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_swich_color(p_unc_tn, p_par_tn); + + ZXDH_SET_TN_COLOR(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(ZXDH_GET_TN_COLOR(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_swich_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (ZXDH_GET_TN_COLOR(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_swich_color(p_unc_tn, p_par_tn); + + ZXDH_SET_TN_COLOR(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(ZXDH_GET_TN_COLOR(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_swich_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (ZXDH_GET_TN_COLOR(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + ZXDH_SET_TN_COLOR(p_del_tn, ZXDH_GET_TN_COLOR(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (ZXDH_GET_TN_COLOR(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (ZXDH_GET_TN_COLOR(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + ZXDH_SET_TN_COLOR(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, ZXDH_GET_TN_LSV(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = ZXDH_GET_TN_LSV(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " %s! LINE:%d ", __func__, __LINE__); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = (uint8_t *)rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + rte_memcpy(p_rb_key, p_data, len); + + p_rb_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, " ICM %s:%d[Error:POINT NULL] ! FUNCTION : %s!", + __FILE__, __LINE__, __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + ZXDH_INIT_RBT_TN(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rte_memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1954,10 +2948,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%d", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = (ZXDH_RB_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -1988,6 +3084,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "%s:dev_id %d vport 0x%x name %s queue_id %d done.", @@ -2027,6 +3126,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, zxdh_np_comm_mutex_unlock(p_dtb_mutex); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3435,12 +4537,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + dtb_dump_addr_info.phy_addr = phy_addr; + dtb_dump_addr_info.vir_addr = vir_addr; + dtb_dump_addr_info.size = size; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3458,6 +4591,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 887760b3d8..f7d09f3fae 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -122,6 +122,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -140,6 +147,26 @@ #define ZXDH_MUTEX_LOCK_ULOCK_FAIL (ZXDH_MUTEX_LOCK_BASE | 0X003) #define ZXDH_MUTEX_LOCK_DESTROY_FAIL (ZXDH_MUTEX_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -184,6 +211,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -289,6 +344,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 110600 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 05/14] net/zxdh: add tables dump address ops 2025-02-10 1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-02-10 17:33 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:33 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:48:50 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + > +#define ZXDH_INIT_D_NODE(ptr, pdata) \ > + do {\ > + ZXDH_D_NODE *temp_ptr = ptr;\ > + (temp_ptr)->data = pdata;\ > + (temp_ptr)->prev = NULL;\ > + (temp_ptr)->next = NULL;\ > + } while (0) > + > +#define ZXDH_INIT_RBT_TN(p_tn, p_newkey) \ > + do {\ > + ZXDH_RB_TN *p_temp_tn = p_tn;\ > + (p_temp_tn)->p_key = p_newkey; \ > + (p_temp_tn)->color_lsv = 0; \ > + (p_temp_tn)->p_left = NULL; \ > + (p_temp_tn)->p_right = NULL; \ > + (p_temp_tn)->p_parent = NULL; \ > + ZXDH_INIT_D_NODE(&((p_temp_tn)->tn_ln), (p_temp_tn));\ > + } while (0) > + > +#define ZXDH_GET_TN_LSV(p_tn) \ > + ((p_tn)->color_lsv >> 2) > + > +#define ZXDH_SET_TN_LSV(p_tn, list_val) \ > + do {\ > + ZXDH_RB_TN *p_temp_tn = p_tn;\ > + (p_temp_tn)->color_lsv &= 0x3;\ > + (p_temp_tn)->color_lsv |= ((list_val) << 2); \ > + } while (0) > + > +#define ZXDH_SET_TN_COLOR(p_tn, color) \ > + do {\ > + ZXDH_RB_TN *p_temp_tn = p_tn;\ > + (p_temp_tn)->color_lsv &= 0xfffffffc;\ > + (p_temp_tn)->color_lsv |= ((color) & 0x3);\ > + } while (0) > + Prefer using inline functions instead of macros. That way you get type safety and everything is more readable. ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 06/14] net/zxdh: add eram tables ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (3 preceding siblings ...) 2025-02-10 1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (7 more replies) 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (2 subsequent siblings) 7 siblings, 8 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35785 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 936 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 11 + 2 files changed, 756 insertions(+), 191 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 845d06a056..880658a63f 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -29,6 +29,13 @@ static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static uint32_t g_dtb_delay_time = 50; +static uint32_t g_dtb_down_overtime = 2 * 1000; +static uint32_t g_dtb_dump_overtime = 5 * 1000 * 1000; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -198,6 +205,81 @@ ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -297,12 +379,13 @@ do {\ } \ } while (0) -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ +#define ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, becall, ptr)\ do {\ if ((rc) != 0) {\ PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ " %s Fail!", __FILE__, __LINE__, __func__, becall);\ rte_free(ptr);\ + RTE_ASSERT(0);\ } \ } while (0) @@ -355,6 +438,28 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + #define ZXDH_INIT_D_NODE(ptr, pdata) \ do {\ ZXDH_D_NODE *temp_ptr = ptr;\ @@ -3217,6 +3322,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3251,6 +3362,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + ZXDH_DTB_TABLE_T *p_table_info; + ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + ZXDH_COMM_GET_BIT_MASK(uint32_t, p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3301,6 +3445,32 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = {0}; + + dtb_eram_dump_form_info.valid = 1; + dtb_eram_dump_form_info.up_type = ZXDH_DTB_DUMP_MODE_ERAM; + dtb_eram_dump_form_info.base_addr = base_addr; + dtb_eram_dump_form_info.tb_depth = depth; + dtb_eram_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_eram_dump_form_info.tb_dst_addr_l = addr_low32; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -3390,6 +3560,72 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + { + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + p_sdt_eram->eram_clutch_en = clutch_en; + break; + } + + case ZXDH_SDT_TBLT_PORTTBL: + { + p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + } + default: + { + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %d ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -3404,12 +3640,15 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -3565,6 +3804,99 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(INFO, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(INFO, "[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + rte_memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(INFO, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_dtb_item_buff_rd", p_item_buff); + + PMD_DRV_LOG(INFO, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3699,6 +4031,123 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_elemet_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_elemet_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(INFO, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > g_dtb_down_overtime) { + PMD_DRV_LOG(ERR, "Error!!! dpp dtb down queue [%d] item [%d]" + "ack success is overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(g_dtb_delay_time); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3710,7 +4159,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -3724,9 +4172,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -3747,7 +4192,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } } @@ -3756,7 +4200,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; @@ -3768,7 +4211,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -3778,16 +4220,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); - return rc; -} + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; + return rc; } int @@ -3802,7 +4238,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -3818,9 +4253,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -3842,7 +4274,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } } @@ -3851,7 +4282,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; @@ -3864,83 +4294,27 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - rte_free(p_data_buff_ex); - return 0; + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + + return rc; } -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) { - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); - - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - { - p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; - break; - } - - case ZXDH_SDT_TBLT_PORTTBL: - { - p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - } - default: - { - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; switch (eram_mode) { case ZXDH_ERAM128_TBL_128b: @@ -3965,82 +4339,6 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, *p_col_index = col_index; } -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - { - memcpy(p_data, temp_data, (128 / 8)); - break; - } - case ZXDH_ERAM128_TBL_64b: - { - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - } - case ZXDH_ERAM128_TBL_1b: - { - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - } - } - return rc; -} - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - { - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); - break; - } - default: - { - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - } - - return 0; -} - static void zxdh_np_stat_cfg_soft_get(uint32_t dev_id, ZXDH_PPU_STAT_CFG_T *p_stat_cfg) @@ -4105,6 +4403,182 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_elemet_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_elemet_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(INFO, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(INFO, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(INFO, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > g_dtb_dump_overtime) { + PMD_DRV_LOG(ERR, "Error!!! dpp dtb dump queue [%d] item [%d]" + "ack success is overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(g_dtb_delay_time); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -4132,6 +4606,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %d element %d dump done.", queue_id, queue_element_id); + return rc; } @@ -4190,33 +4674,6 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -4245,6 +4702,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; @@ -4255,6 +4720,95 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + { + memcpy(p_data, temp_data, (128 / 8)); + break; + } + case ZXDH_ERAM128_TBL_64b: + { + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + case ZXDH_ERAM128_TBL_1b: + { + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + { + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + } + default: + { + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index f7d09f3fae..4a972bed46 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -175,6 +175,9 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -610,6 +613,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89629 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v1 07/14] net/zxdh: get flow tables resources 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:35 ` Stephen Hemminger 2025-02-10 17:35 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (6 subsequent siblings) 7 siblings, 2 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 32952 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 18 ++ drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 522 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 338 +++++++++++++++++++-- 4 files changed, 858 insertions(+), 21 deletions(-) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index 858e3c3d47..18b661b1ab 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1400,6 +1400,11 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) struct zxdh_hw *hw = eth_dev->data->dev_private; int ret = 0; + if (zxdh_shared_data != NULL && zxdh_shared_data->np_init_done) { + g_dtb_data.dev_refcnt++; + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { @@ -1407,6 +1412,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(0, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index fd4699c34d..b2ff7d32f6 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -40,6 +40,7 @@ #define ZXDH_DTB_TABLE_CONF_SIZE (32 * (16 + 16 * 1024)) #define ZXDH_MAX_NAME_LEN 32 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 880658a63f..1e4b214a6e 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -334,6 +334,20 @@ do {\ } \ } while (0) +#define ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, point, mutex)\ +do {\ + if ((point) == NULL) {\ + PMD_DRV_LOG(ERR, "ZXDH %s:%d[Error:POINT NULL] !"\ + "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ + if (zxdh_np_comm_mutex_unlock(mutex) != 0) { \ + PMD_DRV_LOG(ERR, "File: [%s], Function:[%s], Line:%u"\ + "mutex unlock failed!-->Return ERROR", __FILE__,\ + __func__, __LINE__);\ + } \ + RTE_ASSERT(0);\ + } \ +} while (0) + #define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ do {\ if ((point) == NULL) {\ @@ -2486,6 +2500,39 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = {0}; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + + msgcfg.dev_id = 0; + msgcfg.type = ZXDH_RES_MSG; + msgcfg.sub_type = sub_type; + msgcfg.oper = opr; + agent_msg.msg = (void *)&msgcfg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T); + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "%s send msg failed", __func__); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5203,3 +5250,478 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } + +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + { + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + } + + case ZXDH_HASH_TBL_REQ: + { + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + } + + case ZXDH_ERAM_TBL_REQ: + { + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + } + + case ZXDH_ACL_TBL_REQ: + { + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + } + + case ZXDH_STAT_CFG_REQ: + { + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + } + + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + rte_memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rsp_buff, p_dtb_mutex); + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_comm_mutex_unlock", p_rsp_buff); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rsp_buff, p_dtb_mutex); + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_comm_mutex_unlock", p_rsp_buff); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rsp_buff, p_dtb_mutex); + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_comm_mutex_unlock", p_rsp_buff); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rsp_buff, p_dtb_mutex); + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_comm_mutex_unlock", p_rsp_buff); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_MUTEX_T *p_dtb_mutex = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_MUTEX_TYPE_E mutex = 0; + + mutex = ZXDH_DEV_MUTEX_T_DTB; + rc = zxdh_np_dev_opr_mutex_get(dev_id, (uint32_t)mutex, &p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rsp_buff, p_dtb_mutex); + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + rc = zxdh_np_comm_mutex_unlock(p_dtb_mutex); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_comm_mutex_unlock", p_rsp_buff); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} + +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 4a972bed46..39e31b12f7 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -129,6 +129,13 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_ETCAM_BLOCK_NUM (8) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -434,6 +441,174 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_mutex_t { pthread_mutex_t mutex; } ZXDH_MUTEX_T; @@ -474,6 +649,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_MUTEX_T dtb_mutex; ZXDH_MUTEX_T dtb_queue_mutex[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -742,14 +918,6 @@ typedef struct zxdh_etcam_dump_info_t { uint32_t tb_width; } ZXDH_ETCAM_DUMP_INFO_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDT_TBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -801,19 +969,6 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDT_TBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; @@ -874,6 +1029,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -916,6 +1094,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -929,5 +1224,6 @@ int zxdh_np_dtb_stats_get(uint32_t dev_id, ZXDH_STAT_CNT_MODE_E rd_mode, uint32_t index, uint32_t *p_data); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 68112 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 07/14] net/zxdh: get flow tables resources 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-02-10 17:35 ` Stephen Hemminger 2025-02-10 17:35 ` Stephen Hemminger 1 sibling, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:35 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:10 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, > + uint32_t sub_type, > + uint32_t opr, > + uint32_t *p_rsp_buff, > + uint32_t buff_size) > +{ > + uint32_t rc = ZXDH_OK; > + > + uint32_t msg_result = 0; > + ZXDH_AGENT_SE_RES_MSG_T msgcfg = {0}; > + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; > + > + msgcfg.dev_id = 0; > + msgcfg.type = ZXDH_RES_MSG; > + msgcfg.sub_type = sub_type; > + msgcfg.oper = opr; > + agent_msg.msg = (void *)&msgcfg; > + agent_msg.msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T); All this would be more readable as one initializer ZXDH_AGENT_SE_RES_MSG_T msgcfg = { .dev_id = 0, .type = ZXDH_RES_MSG, .sub_type = sub_type, .oper = opr, }; etc. ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 07/14] net/zxdh: get flow tables resources 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-02-10 17:35 ` Stephen Hemminger @ 2025-02-10 17:35 ` Stephen Hemminger 1 sibling, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:35 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:10 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_get_se_buff_size(uint32_t opr) > +{ > + uint32_t buff_size = 0; > + > + switch (opr) { > + case ZXDH_HASH_FUNC_BULK_REQ: > + { > + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); > + break; > + } C does not require each case to have { } ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 08/14] net/zxdh: support hash resources configuration 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:36 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (5 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35030 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 798 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 260 ++++++++++++ 2 files changed, 1058 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1e4b214a6e..bcae32e94e 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -36,6 +36,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -519,6 +536,20 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define ZXDH_GET_TN_COLOR(p_tn) \ zxdh_np_get_tn_color(p_tn) +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + static uint32_t zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) { @@ -840,6 +871,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -865,6 +923,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5715,6 +5813,703 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + ZXDH_INIT_D_NODE(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + ZXDH_INIT_D_NODE(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = (ZXDH_SE_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%d] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + { + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + } + break; + + default: + { + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %d]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + break; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x]," + "ZBlock[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZBLCK, zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x], ZBlk[%d]," + "ZCell[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t dev_id = 0; + + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + dev_id = p_se_cfg->dev_id; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = 0; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + dev_id = p_se_cfg->dev_id; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init," + "do not init again!", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %d!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = (HASH_DDR_CFG *)rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "ICM %s:%d[Error:POINT NULL] !" + "FUNCTION : %s!", __FILE__, __LINE__, __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + ZXDH_INIT_RBT_TN(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same but other ddr attribute is different"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = (ZXDH_SE_ITEM_CFG **)rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "ICM %s:%d[Error:POINT NULL] !" + "FUNCTION : %s!", __FILE__, __LINE__, __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = (ZXDH_HASH_BULK_ZCAM_STAT *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "ICM %s:%d[Error:POINT NULL] ! FUNCTION" + ": %s!", __FILE__, __LINE__, __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %d ] is not init before" + " used!", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input param 'zcell_num' is [ %d ]," + "actually bulk[ %d ]monopolize zcells is [ %d ]!", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %d ] is not init" + " before used!", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input param 'zreg_num' is [ %d ]," + "actually bulk[ %d ]monopolize zregs is [ %d ]!", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "%s dev_id[0x%x],se_type[0x%x] invlaid!", + __func__, dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5723,5 +6518,8 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) rc = zxdh_np_agent_se_res_get(dev_id, type); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 39e31b12f7..31d4af2c05 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -136,6 +136,43 @@ #define ZXDH_ETCAM_MAX_NUM (8) #define ZXDH_ETCAM_BLOCK_NUM (8) +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -249,6 +286,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -377,6 +419,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -390,6 +439,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90949 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 08/14] net/zxdh: support hash resources configuration 2025-02-10 1:50 ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-02-10 17:36 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:36 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:11 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { > + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, > + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, > + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, > + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b > +}; > +uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] > + [ZXDH_HASH_FUNC_ID_NUM] > + [ZXDH_HASH_TBL_ID_NUM] = {0}; > +static uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { > + 0x04C11DB7, > + 0xF4ACFB13, > + 0x20044009, > + 0x00210801 > +}; CRC tables should be const? ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 09/14] net/zxdh: implement tables initialization 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:40 ` Stephen Hemminger 2025-02-10 17:43 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (4 subsequent siblings) 7 siblings, 2 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 36273 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 713 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 187 ++++++++++ 2 files changed, 895 insertions(+), 5 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index bcae32e94e..3de6330271 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -23,7 +23,10 @@ ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -54,6 +57,10 @@ static uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -550,6 +557,49 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *_dst_, uint32_t _src_, + uint32_t _start_pos_, uint32_t _len_) +{ + (*_dst_) = + ((*_dst_) & ~(ZXDH_COMM_GET_BIT_MASK(uint32_t, (_len_)) << (_start_pos_))) | + (((_src_) & ZXDH_COMM_GET_BIT_MASK(uint32_t, (_len_))) << (_start_pos_)); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(_dst_, _src_, _start_pos_, _len_)\ + zxdh_np_comm_uint32_write_bits(&(_dst_), _src_, _start_pos_, _len_) + static uint32_t zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) { @@ -2225,6 +2275,244 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "Error: %s soft sdt table not Init!", __func__); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, + "Error: %s soft sdt table Item Invalid!", __func__); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "%s 0x%08x 0x%08x", __func__, + p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, + "Error: %s Soft Table Item Invalid !", __func__); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "%s sdt_no: 0x%08x", __func__, sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + { + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case ZXDH_SDT_TBLT_HASH: + { + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case ZXDH_SDT_TBLT_ETCAM: + { + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + case ZXDH_SDT_TBLT_PORTTBL: + { + p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + } + + default: + { + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", + table_type); + return ZXDH_ERR; + } + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -4490,10 +4778,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -6473,12 +6761,401 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + { + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + } + + case ZXDH_SDT_TBLT_HASH: + { + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + } + + case ZXDH_SDT_TBLT_ETCAM: + { + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + } + + default: + { + PMD_DRV_LOG(ERR, "zxdh_np_apt_se_set_callback table_type[ %d ]" + "is invalid!", table_type); + return ZXDH_ERR; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = 0; + uint32_t entry_size = 0; + + uint32_t dev_id = 0; + + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + dev_id = p_se_cfg->dev_id; + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%d], table_id[%d] is already init," + "do not init again!", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + PMD_DRV_LOG(INFO, "%s dev_id %d done.", __func__, p_acl_cfg->dev_id); + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %d ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to reduce block_num in order to match with entry_num.", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + ZXDH_INIT_D_NODE(&p_acl_cfg->acl_tbls[table_id].entry_dn, &p_acl_cfg->acl_tbls[table_id]); + rc = (uint32_t)zxdh_comm_double_link_insert_last(&(p_acl_cfg->acl_tbls + [table_id].entry_dn), &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %d ] is already used by table[ %d ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6489,8 +7166,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6507,6 +7190,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 31d4af2c05..b1b9dc9a1b 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -101,6 +101,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -173,6 +177,57 @@ #define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) #define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -291,6 +346,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -446,6 +523,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -869,6 +961,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_mutex_t { pthread_mutex_t mutex; } ZXDH_MUTEX_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 88681 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 09/14] net/zxdh: implement tables initialization 2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-02-10 17:40 ` Stephen Hemminger 2025-02-10 17:43 ` Stephen Hemminger 1 sibling, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:40 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:12 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static inline void > +zxdh_np_comm_uint32_write_bits(uint32_t *_dst_, uint32_t _src_, > + uint32_t _start_pos_, uint32_t _len_) > +{ > + (*_dst_) = > + ((*_dst_) & ~(ZXDH_COMM_GET_BIT_MASK(uint32_t, (_len_)) << (_start_pos_))) | > + (((_src_) & ZXDH_COMM_GET_BIT_MASK(uint32_t, (_len_))) << (_start_pos_)); > +} > + Would be more readable if mask computed once. Don't need _ on function args static inline void zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, uint32_t start_pos, uint32_t len) { uint32_t mask = ZXDH_COMM_GET_BIT_MASK(uint32_t, len) << start_pos; *dst = (*dst & mask) | (src & mask); } ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 09/14] net/zxdh: implement tables initialization 2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-02-10 17:40 ` Stephen Hemminger @ 2025-02-10 17:43 ` Stephen Hemminger 1 sibling, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:43 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:12 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, > + uint32_t sdt_hig32, uint32_t sdt_low32) > +{ > + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; > + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; > + > + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); > + > + if (p_sdt_soft_tbl == NULL) { > + PMD_DRV_LOG(ERR, "Error: %s soft sdt table not Init!", __func__); > + RTE_ASSERT(0); > + return ZXDH_RC_TABLE_SDT_MGR_INVALID; > + } > + > + if (dev_id != p_sdt_soft_tbl->device_id) { > + PMD_DRV_LOG(ERR, > + "Error: %s soft sdt table Item Invalid!", __func__); > + RTE_ASSERT(0); > + return ZXDH_RC_TABLE_PARA_INVALID; > + } > + > + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; > + p_sdt_item->valid = ZXDH_SDT_VALID; > + p_sdt_item->table_cfg[0] = sdt_hig32; > + p_sdt_item->table_cfg[1] = sdt_low32; > + > + PMD_DRV_LOG(DEBUG, "%s 0x%08x 0x%08x", __func__, > + p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); Duplication here. define PMD_DRV_LOG(level, ...) \ RTE_LOG_LINE_PREFIX(level, ZXDH_DRIVER, "%s(): ", __func__, __VA_ARGS__) ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (2 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:45 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (3 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35571 bytes --] Implement hash tables write write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 956 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 + 2 files changed, 968 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 3de6330271..ba84d2064e 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -600,6 +600,71 @@ zxdh_np_comm_uint32_write_bits(uint32_t *_dst_, uint32_t _src_, #define ZXDH_COMM_UINT32_WRITE_BITS(_dst_, _src_, _start_pos_, _len_)\ zxdh_np_comm_uint32_write_bits(&(_dst_), _src_, _start_pos_, _len_) +static inline uint32_t +ZXDH_ZBLK_ADDR_CONV(uint32_t zblk_idx) +{ + return ((zblk_idx) / ZXDH_ZBLK_NUM_PER_ZGRP) * (1 << ZXDH_ZBLK_IDX_BT_WIDTH) + (zblk_idx) + % ZXDH_ZBLK_NUM_PER_ZGRP; +} + +static inline uint32_t +ZXDH_ZCELL_ADDR_CONV(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (ZXDH_ZBLK_ADDR_CONV(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) \ + | ((ZXDH_ZBLK_ADDR_CONV(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((ZXDH_ZCELL_ADDR_CONV(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static uint32_t zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) { @@ -1828,6 +1893,17 @@ zxdh_np_dev_dtb_opr_mutex_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_mutex_get(uint32_t dev_id, uint32_t fun_id, ZXDH_MUTEX_T **p_mutex_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + *p_mutex_out = &p_dev_info->hash_mutex[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2203,6 +2279,11 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_create"); } + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) { + rtn = zxdh_np_comm_mutex_create(&p_dev_info->hash_mutex[i]); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_create"); + } + return rtn; } @@ -3717,6 +3798,9 @@ zxdh_np_dev_del(uint32_t dev_id) for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) zxdh_np_comm_mutex_destroy(&p_dev_info->dtb_queue_mutex[i]); + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + zxdh_np_comm_mutex_destroy(&p_dev_info->hash_mutex[i]); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; @@ -3878,6 +3962,72 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = {0}; + + dtb_zcam_form_info.valid = 1; + dtb_zcam_form_info.type_mode = ZXDH_DTB_TABLE_MODE_ZCAM; + dtb_zcam_form_info.ram_reg_flag = reg_sram_flag; + dtb_zcam_form_info.zgroup_id = zgroup_id; + dtb_zcam_form_info.zblock_id = zblock_id; + dtb_zcam_form_info.zcell_id = zcell_id; + dtb_zcam_form_info.mask = mask; + dtb_zcam_form_info.sram_addr = sram_addr & 0x1FF; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + rte_memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = 0; + uint32_t zgroup_id = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t mask = 0; + uint32_t sram_addr = 0; + + mask = (addr >> 17) & 0xF; + reg_sram_flag = (addr >> 16) & 0x1; + zgroup_id = (addr >> 14) & 0x3; + zblock_id = (addr >> 11) & 0x7; + zcell_id = (addr >> 9) & 0x3; + sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4580,6 +4730,797 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + rte_memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = (ZXDH_HASH_RBKEY_INFO *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "ICM %s:%d[Error:POINT NULL] !" + "FUNCTION : %s!", __FILE__, __LINE__, __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ZXDH_INIT_RBT_TN(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + uint32_t rst_actual_size = 0; + + p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + rte_memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + rte_memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + ZXDH_INIT_D_NODE(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = 0; + uint32_t item_entry_max = 4; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "Entry in item pos is: [%d]," + "entry size is: [%d].", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = NULL; + uint8_t bulk_id = 0; + uint8_t key_type = 0; + uint8_t table_id = 0; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + HASH_DDR_CFG *p_ddr_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + bulk_id = p_hash_entry_cfg->bulk_id; + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + table_id = p_hash_entry_cfg->table_id; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Hash DDR width mode" + " is not match to the key type.", ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s," + "item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = (ZXDH_SE_ITEM_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = 0; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = 0; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + bulk_id = p_hash_entry_cfg->bulk_id; + table_id = p_hash_entry_cfg->table_id; + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx is [0x%x]," + "p_zblk->hash_arg is [0x%x], crc_value is [0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id is [0x%x]," + "item_idx is [0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = 0; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + + PMD_DRV_LOG(DEBUG, "insert zreg start"); + bulk_id = p_hash_entry_cfg->bulk_id; + table_id = p_hash_entry_cfg->table_id; + p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey_new); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = 0; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_SE_ITEM_CFG *p_item_info = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_item_info = p_rbkey_new->p_item_info; + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_MUTEX_T *p_hash_mutex = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_mutex_get(dev_id, p_hash_cfg->fun_id, &p_hash_mutex); + + rc = zxdh_np_comm_mutex_lock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rb_tn_rtn, p_hash_mutex); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_item, p_hash_mutex); + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_comm_double_link_del", p_hash_mutex); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_dtb_hash_form_write", p_hash_mutex); + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + + p_hash_cfg->hash_stat.delete_ok++; + + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t rtn = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_MUTEX_T *p_hash_mutex = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_mutex_get(dev_id, p_hash_cfg->fun_id, &p_hash_mutex); + + rc = zxdh_np_comm_mutex_lock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, + "zxdh_np_hash_red_black_node_alloc", p_hash_mutex); + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, + "zxdh_np_dtb_hash_form_write", p_hash_mutex); + } + + rtn = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_comm_mutex_unlock"); + + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "hash_insert_ddr", p_hash_mutex); + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "hash_insert_zcell", p_hash_mutex); + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "hash_insert_zreg", p_hash_mutex); + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_comm_rb_delete", p_hash_mutex); + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, + "zxdh_np_dtb_hash_form_write", p_hash_mutex); + + p_hash_cfg->hash_stat.insert_ok++; + + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t aucKey[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t aucRst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = aucKey; + entry.p_rst = aucRst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} int zxdh_np_dtb_table_entry_write(uint32_t dev_id, @@ -4621,6 +5562,12 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; } + case ZXDH_SDT_TBLT_HASH: + { + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; + } default: { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); @@ -4703,6 +5650,15 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; } + case ZXDH_SDT_TBLT_HASH: + { + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; + } default: { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b1b9dc9a1b..2c94125817 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -92,6 +94,7 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -538,6 +541,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1096,6 +1107,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_MUTEX_T dtb_mutex; ZXDH_MUTEX_T dtb_queue_mutex[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_MUTEX_T hash_mutex[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90526 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops 2025-02-10 1:50 ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-02-10 17:45 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:45 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:13 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static inline uint32_t > +ZXDH_ZBLK_ADDR_CONV(uint32_t zblk_idx) Do not name functions with all upper case, that is reserved for macros. > +{ > + return ((zblk_idx) / ZXDH_ZBLK_NUM_PER_ZGRP) * (1 << ZXDH_ZBLK_IDX_BT_WIDTH) + (zblk_idx) > + % ZXDH_ZBLK_NUM_PER_ZGRP; Indent the previous line since it is contunation of expression > +} > + > +static inline uint32_t > +ZXDH_ZCELL_ADDR_CONV(uint32_t zcell_idx) > +{ > + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & > + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); > + > + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); > + > + return (ZXDH_ZBLK_ADDR_CONV(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; > +} ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 11/14] net/zxdh: get hash table entry result 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (3 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:46 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (2 subsequent siblings) 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 17134 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 491 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 498 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index ba84d2064e..09ff42b3be 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1388,6 +1388,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = ZXDH_GET_TN_LSV(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -4054,6 +4088,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = {0}; + + dtb_zcam_dump_form_info.valid = 1; + dtb_zcam_dump_form_info.up_type = ZXDH_DTB_DUMP_MODE_ZCAM; + dtb_zcam_dump_form_info.tb_width = tb_width; + dtb_zcam_dump_form_info.sram_addr = addr & 0x1FF; + dtb_zcam_dump_form_info.ram_reg_flag = (addr >> 16) & 0x1; + dtb_zcam_dump_form_info.z_reg_cell_id = (addr >> 9) & 0x3; + dtb_zcam_dump_form_info.zblock_id = (addr >> 11) & 0x7; + dtb_zcam_dump_form_info.zgroup_id = (addr >> 14) & 0x3; + dtb_zcam_dump_form_info.tb_depth = depth; + dtb_zcam_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_zcam_dump_form_info.tb_dst_addr_l = addr_low32; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -6162,6 +6228,407 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %d.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + rte_memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "%s fail!", __func__); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rte_memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_MUTEX_T *p_hash_mutex = NULL; + + rte_memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_mutex_get(dev_id, p_hash_cfg->fun_id, &p_hash_mutex); + + rc = zxdh_np_comm_mutex_lock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return ZXDH_OK; + } + + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rb_tn_rtn, p_hash_mutex); + p_rbkey = p_rb_tn_rtn->p_key; + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_rbkey, p_hash_mutex); + p_item = p_rbkey->p_item_info; + ZXDH_COMM_CHECK_DEV_POINT_UNLOCK(dev_id, p_item, p_hash_mutex); + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + rc = zxdh_np_comm_mutex_unlock(p_hash_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t aucKey[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t aucRst[ZXDH_HASH_RST_MAX] = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = aucKey; + hash_entry.p_rst = aucRst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + rte_memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + rte_memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6172,6 +6639,9 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); @@ -6188,6 +6658,27 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; } + case ZXDH_SDT_TBLT_HASH: + { + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, " %s hash fail", __func__); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; + } default: { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 2c94125817..0762db5fad 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1279,6 +1279,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 48142 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 11/14] net/zxdh: get hash table entry result 2025-02-10 1:50 ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-02-10 17:46 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:46 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:14 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, > + uint32_t addr, > + uint32_t tb_width, > + uint32_t depth, > + uint32_t addr_high32, > + uint32_t addr_low32, > + uint32_t *p_dump_info) > +{ > + uint32_t rc = ZXDH_OK; > + > + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = {0}; > + > + dtb_zcam_dump_form_info.valid = 1; > + dtb_zcam_dump_form_info.up_type = ZXDH_DTB_DUMP_MODE_ZCAM; > + dtb_zcam_dump_form_info.tb_width = tb_width; > + dtb_zcam_dump_form_info.sram_addr = addr & 0x1FF; > + dtb_zcam_dump_form_info.ram_reg_flag = (addr >> 16) & 0x1; > + dtb_zcam_dump_form_info.z_reg_cell_id = (addr >> 9) & 0x3; > + dtb_zcam_dump_form_info.zblock_id = (addr >> 11) & 0x7; > + dtb_zcam_dump_form_info.zgroup_id = (addr >> 14) & 0x3; > + dtb_zcam_dump_form_info.tb_depth = depth; > + dtb_zcam_dump_form_info.tb_dst_addr_h = addr_high32; > + dtb_zcam_dump_form_info.tb_dst_addr_l = addr_low32; > + Looks like structure initializer here. ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 12/14] net/zxdh: delete all hash entries 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (4 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:47 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen 7 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 39462 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 45 ++ drivers/net/zxdh/zxdh_np.c | 1092 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 19 + 3 files changed, 1156 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index 18b661b1ab..b99e79ca4a 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -966,6 +966,29 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + uint32_t sdt_no; + int ret = 0; + if (!g_dtb_data.init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(0, g_dtb_data.queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(0, g_dtb_data.queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -974,6 +997,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!g_dtb_data.init_done && !g_dtb_data.dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--g_dtb_data.dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1394,6 +1419,25 @@ zxdh_init_once(void) return ret; } +static int zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + int ret = 0; + if (!g_dtb_data.init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(0, g_dtb_data.queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(0, g_dtb_data.queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { @@ -1423,6 +1467,7 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); return -1; } + zxdh_tbl_entry_offline_destroy(hw); } if (zxdh_shared_data != NULL) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 09ff42b3be..230a1d44be 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -417,6 +417,17 @@ do {\ } \ } while (0) +#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE2PTR(point, ptr0, ptr1)\ +do {\ + if ((point) == NULL) {\ + PMD_DRV_LOG(ERR, " ZXDH %s:%d[Error:POINT NULL] ! FUNCTION"\ + ": %s!", __FILE__, __LINE__, __func__);\ + rte_free(ptr0);\ + rte_free(ptr1);\ + RTE_ASSERT(0);\ + } \ +} while (0) + #define ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, becall, ptr)\ do {\ if ((rc) != 0) {\ @@ -578,6 +589,8 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) + static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) { @@ -1809,6 +1822,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + rte_memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3841,6 +3868,240 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = 0; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + + dev_id = p_se_cfg->dev_id; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%d] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + { + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + } + break; + + default: + { + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %d] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + break; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + p_se_cfg = dpp_se_cfg[dev_id]; + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(INFO, "Error[0x%x], fun_id [%d] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3853,6 +4114,10 @@ zxdh_np_online_uninit(uint32_t dev_id, PMD_DRV_LOG(ERR, "%s:dtb release error," "port name %s queue id %d", __func__, port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4120,6 +4385,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5915,6 +6199,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_elemet_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -6129,6 +6436,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %d success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %d fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8673,3 +9075,693 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } + +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + rte_memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, + "zxdh_np_dtb_hash_zcam_del_one_hw", p_data_buff); + + if (srh_succ) { + rc = zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, + "zxdh_np_dtb_data_write", p_data_buff); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, + "zxdh_np_dtb_write_down_table_data", p_data_buff); + + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, + "zxdh_np_dtb_tab_down_success_status_check", p_data_buff); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d" + " Mono Zreg_id :%d", zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_dtb_write_dump_desc_info", + p_dump_desc_buf); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_dtb_write_dump_desc_info", + p_dump_desc_buf); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + rte_memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + rte_memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, + "zxdh_np_dtb_sdt_hash_zcam_mono_space_dump", p_data); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + ZXDH_COMM_CHECK_RC_MEMORY_FREE(rc, "zxdh_np_dtb_hash_table_zcam_dump", + p_data); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + rc = zxdh_np_soft_sdt_tbl_get(0, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = (uint8_t *)rte_zmalloc(NULL, max_item_num * + sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_key, p_dump_data); + p_rst = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + ZXDH_COMM_CHECK_POINT_MEMORY_FREE2PTR(p_rst, p_dump_data, p_key); + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(0, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(0, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 0762db5fad..2ba9554684 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -95,6 +95,11 @@ #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) #define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -231,6 +236,10 @@ #define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) #define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) +/* hash */ +#define ZXDH_SDT_L2_ENTRY_TABLE0 (64) +#define ZXDH_SDT_MC_TABLE0 (76) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -1677,6 +1686,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1691,5 +1705,10 @@ int zxdh_np_dtb_stats_get(uint32_t dev_id, uint32_t index, uint32_t *p_data); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 112084 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 12/14] net/zxdh: delete all hash entries 2025-02-10 1:50 ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-02-10 17:47 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:47 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:15 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE2PTR(point, ptr0, ptr1)\ > +do {\ > + if ((point) == NULL) {\ > + PMD_DRV_LOG(ERR, " ZXDH %s:%d[Error:POINT NULL] ! FUNCTION"\ > + ": %s!", __FILE__, __LINE__, __func__);\ > + rte_free(ptr0);\ > + rte_free(ptr1);\ > + RTE_ASSERT(0);\ Again, PMD_DRV_LOG already puts function name in, and making louder by SCREAMING UPPER CASE won't fix the problem ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v1 13/14] net/zxdh: add acl tables ops 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (5 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen 7 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31917 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 915 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 31 ++ 2 files changed, 945 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 230a1d44be..9de3e2f406 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -678,6 +678,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static uint32_t zxdh_np_comm_mutex_create(ZXDH_MUTEX_T *p_mutex) { @@ -4102,6 +4107,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "%s fail, etcam_is not init!", __func__); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %d ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -4118,6 +4182,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4327,6 +4392,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = {0}; + + dtb_etcam_form_info.valid = 1; + dtb_etcam_form_info.type_mode = ZXDH_DTB_TABLE_MODE_ETCAM; + dtb_etcam_form_info.block_sel = block_idx; + dtb_etcam_form_info.init_en = 0; + dtb_etcam_form_info.row_or_col_msk = row_or_col_msk; + dtb_etcam_form_info.vben = vben; + dtb_etcam_form_info.reg_tcam_flag = reg_tcam_flag; + dtb_etcam_form_info.uload = flush; + dtb_etcam_form_info.rd_wr = rd_wr; + dtb_etcam_form_info.wr_mode = wr_mode; + dtb_etcam_form_info.data_or_mask = data_or_mask; + dtb_etcam_form_info.addr = ram_addr; + dtb_etcam_form_info.vbit = vbit; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + rte_memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + rte_memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4385,6 +4514,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = {0}; + + dtb_etcam_dump_form_info.valid = 1; + dtb_etcam_dump_form_info.up_type = ZXDH_DTB_DUMP_MODE_ETCAM; + dtb_etcam_dump_form_info.block_sel = p_etcam_dump_info->block_sel; + dtb_etcam_dump_form_info.addr = p_etcam_dump_info->addr; + dtb_etcam_dump_form_info.rd_mode = p_etcam_dump_info->rd_mode; + dtb_etcam_dump_form_info.data_or_mask = p_etcam_dump_info->data_or_mask; + dtb_etcam_dump_form_info.tb_depth = p_etcam_dump_info->tb_depth; + dtb_etcam_dump_form_info.tb_width = p_etcam_dump_info->tb_width; + dtb_etcam_dump_form_info.tb_dst_addr_h = addr_high32; + dtb_etcam_dump_form_info.tb_dst_addr_l = addr_low32; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4404,6 +4562,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -4412,7 +4602,7 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc; @@ -5872,6 +6062,327 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = 0; + uint32_t entry_pos = 0; + + block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + { + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + } + case ZXDH_ERAM128_TBL_64b: + { + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + } + case ZXDH_ERAM128_TBL_1b: + { + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + } + default: + { + break; + } + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + rte_memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + rte_memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -5918,6 +6429,12 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; } + case ZXDH_SDT_TBLT_ETCAM: + { + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; + } default: { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); @@ -7031,6 +7548,393 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + rte_memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + rte_memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = (uint8_t *)rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "%s point null!", __func__); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + rte_memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + rte_memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + rte_memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware success: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware fail: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + { + rte_memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + } + + case ZXDH_ERAM128_TBL_64b: + { + rte_memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ZXDH_ERAM128_TBL_1b: + { + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -7081,6 +7985,15 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; } + case ZXDH_SDT_TBLT_ETCAM: + { + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; + } default: { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 2ba9554684..08a9b3c3a6 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1295,6 +1295,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1309,6 +1327,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 91335 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v1 14/14] net/zxdh: clean stat values 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (6 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-02-10 1:50 ` Bingbin Chen 2025-02-10 17:50 ` Stephen Hemminger ` (2 more replies) 7 siblings, 3 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-10 1:50 UTC (permalink / raw) To: dev; +Cc: Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 12934 bytes --] Implement stat values clean operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev_ops.c | 4 + drivers/net/zxdh/zxdh_np.c | 344 +++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 23 +- 3 files changed, 370 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c index 1a21ded58e..284bf27d10 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.c +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c @@ -1500,11 +1500,15 @@ static int zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type int zxdh_dev_stats_reset(struct rte_eth_dev *dev) { struct zxdh_hw *hw = dev->data->dev_private; + uint64_t stats_data; zxdh_hw_stats_reset(dev, ZXDH_VQM_DEV_STATS_RESET); if (hw->is_pf) zxdh_hw_stats_reset(dev, ZXDH_MAC_STATS_RESET); + zxdh_np_stat_ppu_cnt_get_ex(0, ZXDH_STAT_64_MODE, 0, + ZXDH_STAT_RD_CLR_MODE_CLR, (uint32_t *)&stats_data); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 9de3e2f406..e4d360c8f5 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -3420,6 +3420,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + uint32_t reg_type = 0; + uint32_t reg_module = 0; + ZXDH_REG_T *p_reg_info = NULL; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = 0; + + p_reg_info = &g_dpp_reg_info[reg_no]; + reg_module = p_reg_info->module_no; + reg_type = p_reg_info->flags; + reg_real_no = p_reg_info->reg_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -10678,3 +10709,316 @@ zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, return rc; } + +static uint32_t +zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) +{ + uint32_t rc = ZXDH_OK; + + uint32_t data = 0; + uint32_t rd_cnt = 0; + uint32_t done_flag = 0; + + while (!done_flag) { + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read32 Fail!", rc); + return rc; + } + + done_flag = (data >> pos) & 0x1; + + if (done_flag) + break; + + if (rd_cnt > ZXDH_RD_CNT_MAX * ZXDH_RD_CNT_MAX) + return ZXDH_ERR; + + rd_cnt++; + } + + return rc; +} + +static uint32_t +zxdh_np_se_smmu0_ind_read(uint32_t dev_id, + uint32_t base_addr, + uint32_t index, + uint32_t rd_mode, + uint32_t rd_clr_mode, + uint32_t *p_data) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t temp_data[4] = {0}; + uint32_t *p_temp_data = NULL; + ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_MUTEX_T *p_ind_mutex = NULL; + + rc = zxdh_np_dev_opr_mutex_get(dev_id, ZXDH_DEV_MUTEX_T_SMMU0, &p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); + + rc = zxdh_np_comm_mutex_lock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); + + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_se_done_status_check", p_ind_mutex); + + if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { + cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = ZXDH_RD_MODE_HOLD; + cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; + + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + { + if ((0xFFFFFFFF - (base_addr)) < (index)) { + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; + break; + } + + case ZXDH_ERAM128_OPR_64b: + { + if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x1; + break; + } + + case ZXDH_ERAM128_OPR_32b: + { + if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x3; + break; + } + + case ZXDH_ERAM128_OPR_1b: + { + if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = index & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x7F; + break; + } + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; + } else { + cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = ZXDH_RD_MODE_CLEAR; + + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + { + if ((0xFFFFFFFF - (base_addr)) < (index)) { + PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + + if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 7); + cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; + break; + } + + case ZXDH_ERAM128_OPR_64b: + { + if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 6); + cpu_ind_cmd.cpu_req_mode = 2; + break; + } + + case ZXDH_ERAM128_OPR_32b: + { + if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + return ZXDH_ERR; + } + + row_index = (index << 5); + cpu_ind_cmd.cpu_req_mode = 1; + break; + } + + case ZXDH_ERAM128_OPR_1b: + { + PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ", + rd_clr_mode, rd_mode); + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + RTE_ASSERT(0); + return ZXDH_ERR; + } + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; + } + + rc = zxdh_np_reg_write(dev_id, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_reg_write", p_ind_mutex); + + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, + "zxdh_np_se_done_status_check", p_ind_mutex); + + p_temp_data = temp_data; + for (i = 0; i < 4; i++) { + rc = zxdh_np_reg_read(dev_id, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_reg_read", p_ind_mutex); + } + + if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + { + rte_memcpy(p_data, p_temp_data, (128 / 8)); + break; + } + + case ZXDH_ERAM128_OPR_64b: + { + rte_memcpy(p_data, p_temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + } + + case ZXDH_ERAM128_OPR_32b: + { + rte_memcpy(p_data, p_temp_data + ((3 - col_index)), (32 / 8)); + break; + } + + case ZXDH_ERAM128_OPR_1b: + { + ZXDH_COMM_UINT32_GET_BITS(p_data[0], + *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + } + } + } else { + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + { + rte_memcpy(p_data, p_temp_data, (128 / 8)); + break; + } + + case ZXDH_ERAM128_OPR_64b: + { + rte_memcpy(p_data, p_temp_data, (64 / 8)); + break; + } + + case ZXDH_ERAM128_OPR_32b: + { + rte_memcpy(p_data, p_temp_data, (64 / 8)); + break; + } + } + } + + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); + + return rc; +} + +uint32_t +zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, + ZXDH_STAT_CNT_MODE_E rd_mode, + uint32_t index, + uint32_t clr_mode, + uint32_t *p_data) +{ + uint32_t rc = ZXDH_OK; + uint32_t ppu_eram_baddr = 0; + uint32_t ppu_eram_depth = 0; + uint32_t eram_rd_mode = 0; + uint32_t eram_clr_mode = 0; + ZXDH_PPU_STAT_CFG_T stat_cfg = {0}; + + zxdh_np_stat_cfg_soft_get(dev_id, &stat_cfg); + + ppu_eram_depth = stat_cfg.eram_depth; + ppu_eram_baddr = stat_cfg.eram_baddr; + + if ((index >> (ZXDH_STAT_128_MODE - rd_mode)) < ppu_eram_depth) { + if (rd_mode == ZXDH_STAT_128_MODE) + eram_rd_mode = ZXDH_ERAM128_OPR_128b; + else + eram_rd_mode = ZXDH_ERAM128_OPR_64b; + + if (clr_mode == ZXDH_STAT_RD_CLR_MODE_UNCLR) + eram_clr_mode = ZXDH_RD_MODE_HOLD; + else + eram_clr_mode = ZXDH_RD_MODE_CLEAR; + + rc = zxdh_np_se_smmu0_ind_read(dev_id, + ppu_eram_baddr, + index, + eram_rd_mode, + eram_clr_mode, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_smmu0_ind_read"); + } else { + PMD_DRV_LOG(ERR, "DPDK DONT HAVE DDR STAT."); + } + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 08a9b3c3a6..bcb4699c6f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1188,6 +1188,12 @@ typedef struct zxdh_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_t { uint32_t cfg_vfunc_active; } ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T; +typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { + uint32_t cpu_ind_rw; + uint32_t cpu_ind_rd_mode; + uint32_t cpu_req_mode; + uint32_t cpu_ind_addr; +} ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; typedef uint32_t (*ZXDH_REG_WRITE)(uint32_t dev_id, uint32_t addr, uint32_t *p_data); typedef uint32_t (*ZXDH_REG_READ)(uint32_t dev_id, uint32_t addr, uint32_t *p_data); @@ -1498,6 +1504,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_stat_rd_clr_mode_e { + ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, + ZXDH_STAT_RD_CLR_MODE_CLR = 1, + ZXDH_STAT_RD_CLR_MODE_MAX, +} STAT_RD_CLR_MODE_E; + +typedef enum zxdh_eram128_rd_clr_mode_e { + ZXDH_RD_MODE_HOLD = 0, + ZXDH_RD_MODE_CLEAR = 1, +} ZXDH_ERAM128_RD_CLR_MODE_E; + typedef enum zxdh_np_agent_msg_type_e { ZXDH_REG_MSG = 0, ZXDH_DTB_MSG, @@ -1741,5 +1758,9 @@ uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, __rte_unused uint32_t flush_mode); - +uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, + ZXDH_STAT_CNT_MODE_E rd_mode, + uint32_t index, + uint32_t clr_mode, + uint32_t *p_data); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 37723 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 14/14] net/zxdh: clean stat values 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen @ 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 18:19 ` Stephen Hemminger 2 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:50 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:17 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + > + case ZXDH_ERAM128_OPR_64b: > + { > + if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); > + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); > + return ZXDH_ERR; > + } > + > + row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; > + col_index = index & 0x1; > + break; > + } More repeats of __func__ with PMD_DRV_LOG and extra { } ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 14/14] net/zxdh: clean stat values 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen 2025-02-10 17:50 ` Stephen Hemminger @ 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 18:19 ` Stephen Hemminger 2 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 17:50 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:17 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + p_temp_data = temp_data; > + for (i = 0; i < 4; i++) { > + rc = zxdh_np_reg_read(dev_id, > + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, > + 0, > + 0, > + p_temp_data + 3 - i); > + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_reg_read", p_ind_mutex); > + } Looks like lots of extra indentation here (could be mailer just getting confused). ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v1 14/14] net/zxdh: clean stat values 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 17:50 ` Stephen Hemminger @ 2025-02-10 18:19 ` Stephen Hemminger 2 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-10 18:19 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:50:17 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > +static uint32_t > +zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > + uint32_t base_addr, > + uint32_t index, > + uint32_t rd_mode, > + uint32_t rd_clr_mode, > + uint32_t *p_data) > +{ > + uint32_t rc = ZXDH_OK; > + uint32_t i = 0; > + uint32_t row_index = 0; > + uint32_t col_index = 0; > + uint32_t temp_data[4] = {0}; > + uint32_t *p_temp_data = NULL; > + ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; > + ZXDH_MUTEX_T *p_ind_mutex = NULL; > + > + rc = zxdh_np_dev_opr_mutex_get(dev_id, ZXDH_DEV_MUTEX_T_SMMU0, &p_ind_mutex); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_mutex_get"); > + > + rc = zxdh_np_comm_mutex_lock(p_ind_mutex); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_lock"); > + > + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); > + ZXDH_COMM_CHECK_DEV_RC_UNLOCK(dev_id, rc, "zxdh_np_se_done_status_check", p_ind_mutex); > + > + if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { > + cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; > + cpu_ind_cmd.cpu_ind_rd_mode = ZXDH_RD_MODE_HOLD; > + cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; > + > + switch (rd_mode) { > + case ZXDH_ERAM128_OPR_128b: > + { > + if ((0xFFFFFFFF - (base_addr)) < (index)) { > + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); > + PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); > + return ZXDH_PAR_CHK_INVALID_INDEX; > + } > + if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > + PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); > + rc = zxdh_np_comm_mutex_unlock(p_ind_mutex); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_mutex_unlock"); > + return ZXDH_ERR; > + } The error paths here are a bit of a mess. Do you really have to check return value of mutex_unlock if already have an error? ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v2 00/14] add network processor ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (4 preceding siblings ...) 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (13 more replies) 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-10 23:19 ` [PATCH v1 01/14] net/zxdh: add network processor registers ops Stephen Hemminger 7 siblings, 14 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 1208 bytes --] V2: - resolve code style and github-robot build issue. - eliminate commit warning. - remove unnecessary initialization, which first usage will set. - replace mutex lock with spinlock. V1: - updated network processor driver. - improve insert/delete/get table code funcs. Bingbin Chen (14): net/zxdh: add network processor registers ops net/zxdh: support compatibility check net/zxdh: add agent channel net/zxdh: modify dtb queue ops net/zxdh: add tables dump address ops net/zxdh: add eram tables ops net/zxdh: get flow tables resources net/zxdh: support hash resources configuration net/zxdh: implement tables initialization net/zxdh: support hash tables write and delete ops net/zxdh: get hash table entry result net/zxdh: delete all hash entries net/zxdh: add acl tables ops net/zxdh: clean stat values drivers/net/zxdh/zxdh_ethdev.c | 63 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_ethdev_ops.c | 4 + drivers/net/zxdh/zxdh_np.c | 11306 +++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 1258 ++- 5 files changed, 11205 insertions(+), 1427 deletions(-) -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 2335 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v2 01/14] net/zxdh: add network processor registers ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 02/14] net/zxdh: support compatibility check Bingbin Chen ` (12 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 50252 bytes --] Add (np)network processor registers read/write interfaces. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 968 +++++++++++++++++++++++++++---------- drivers/net/zxdh/zxdh_np.h | 94 +++- 2 files changed, 790 insertions(+), 272 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1e6e8f0e75..edc06beaf9 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -14,22 +14,192 @@ #include "zxdh_np.h" #include "zxdh_logs.h" -static uint64_t g_np_bar_offset; static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; -ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; -ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; -ZXDH_REG_T g_dpp_reg_info[4]; -ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; -ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, +}; + +static ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, +}; + +static ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 0, 1}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 63, 32}, + {"data_l", 31, 32}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag", 123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel", 123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr", 108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + +static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { + { + "ddr", + ZXDH_DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + ZXDH_DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + ZXDH_DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + ZXDH_DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + ZXDH_DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + ZXDH_DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + ZXDH_DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ + (((data_len) & 0x3ff) | \ + ((int_en) << 29) | \ + ((cmd_type) << 30)) #define ZXDH_COMM_MASK_BIT(_bitnum_)\ (0x1U << (_bitnum_)) @@ -46,8 +216,7 @@ ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\ do {\ if (NULL == (point)) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "dev: %d [POINT NULL]", (dev_id));\ RTE_ASSERT(0);\ } \ } while (0) @@ -55,33 +224,22 @@ do {\ #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d !"\ - "-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "dev: %d, %s failed!", (dev_id), becall);\ RTE_ASSERT(0);\ } \ } while (0) -#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ - } \ -} while (0) - #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d !-- %s Call %s"\ - " Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ } \ } while (0) #define ZXDH_COMM_CHECK_RC(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d!-- %s Call %s "\ - "Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ RTE_ASSERT(0);\ } \ } while (0) @@ -89,34 +247,28 @@ do {\ #define ZXDH_COMM_CHECK_POINT(point)\ do {\ if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "[POINT NULL]");\ RTE_ASSERT(0);\ } \ } while (0) +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) +{ + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; +} -#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ - rte_free(ptr);\ - RTE_ASSERT(0);\ - } \ -} while (0) - -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ -do {\ - if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ - " %s Fail!", __FILE__, __LINE__, __func__, becall);\ - rte_free(ptr);\ - } \ -} while (0) +static inline uint32_t +zxdh_np_comm_convert32(uint32_t dw_data) +{ + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; +} #define ZXDH_COMM_CONVERT16(w_data) \ - (((w_data) & 0xff) << 8) + zxdh_np_comm_convert16(w_data) + +#define ZXDH_COMM_CONVERT32(w_data) \ + zxdh_np_comm_convert32(w_data) #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) @@ -174,7 +326,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) uc_byte_mode = dw_byte_len % 4 & 0xff; for (i = 0; i < dw_byte_num; i++) { - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); p_dw_tmp++; } @@ -198,6 +350,329 @@ zxdh_np_dev_init(void) return 0; } +static uint32_t +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static void +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + data = *p_data; + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + *((volatile uint32_t *)addr) = data; +} + +static void +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + data = *((volatile uint32_t *)addr); + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *p_data = data; +} + +static uint64_t +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) + return ZXDH_DEV_TYPE_INVALID; + + return p_dev_info->pcie_addr; +} + +static void +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); +} + +static void +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); +} + +static uint32_t +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_write(dev_id, addr, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_read(dev_id, addr, p_data); +} + +static ZXDH_REG_T g_dpp_reg_info[] = { + { + .reg_name = "cpu_ind_cmd", + .reg_no = 669, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 4, + .p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rd_done", + .reg_no = 670, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat0", + .reg_no = 671, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat1", + .reg_no = 672, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat2", + .reg_no = 673, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat3", + .reg_no = 674, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "wr_arb_cpu_rdy", + .reg_no = 676, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "info_queue_buf_space_left_0_127", + .reg_no = 820, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 1, + .p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cfg_epid_v_func_num_0_127", + .reg_no = 821, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 7, + .p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + } +}; + +static uint32_t +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) +{ + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = NULL; + + p_reg_info = &g_dpp_reg_info[reg_no]; + + addr = p_reg_info->addr; + + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { + if (n_offset > (p_reg_info->n_size - 1)) + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%d, n:%d," + "size:%d", reg_no, n_offset, p_reg_info->n_size - 1); + + addr += n_offset * p_reg_info->n_step; + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + PMD_DRV_LOG(ERR, "reg n_offset or m_offset is out of range, reg_no:%d," + "n:%d, n_size:%d, m:%d, m_size:%d,", reg_no, n_offset, + p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1); + + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; + } + + return addr; +} + static uint32_t zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, @@ -221,7 +696,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, } else { /* device is new. */ p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } p_dev_mgr->p_dev_array[dev_id] = p_dev_info; p_dev_mgr->device_num++; } @@ -234,6 +712,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->dma_vir_addr = dma_vir_addr; p_dev_info->dma_phy_addr = dma_phy_addr; + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + return 0; } @@ -282,8 +763,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id) p_sdt_mgr->channel_num++; } else { - PMD_DRV_LOG(ERR, "Error: %s for dev[%d]" - "is called repeatedly!", __func__, dev_id); + PMD_DRV_LOG(ERR, "called repeatedly!"); return 1; } @@ -335,6 +815,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) return p_dpp_dtb_mgr[dev_id]; } +static uint32_t +zxdh_np_dtb_mgr_create(uint32_t dev_id) +{ + if (p_dpp_dtb_mgr[dev_id] != NULL) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); + return ZXDH_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[dev_id] = (ZXDH_DTB_MGR_T *)rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + if (p_dpp_dtb_mgr[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dtb_soft_init(uint32_t dev_id) { @@ -345,10 +843,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id) p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) { - p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + zxdh_np_dtb_mgr_create(dev_id); + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) - return 1; + return ZXDH_RC_DTB_MGR_NOT_EXIST; } return 0; @@ -428,36 +927,10 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE) ? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0; - g_np_bar_offset = bar_offset; return np_addr; } -int -zxdh_np_host_init(uint32_t dev_id, - ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) -{ - ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; - uint32_t rc; - uint64_t agent_addr; - - ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); - - sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); - sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, - p_dev_init_ctrl->np_bar_offset); - sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; - rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); - - zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); - - agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; - zxdh_np_dev_agent_addr_set(dev_id, agent_addr); - - return 0; -} - static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -570,24 +1043,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t rc = 0; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - for (i = 0; i < p_reg_info->field_num; i++) { - rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - (uint32_t *)p_data + i, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]); + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); } } + + for (i = 0; i < p_reg_info->field_num; i++) { + rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + (uint32_t *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex"); + PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + } + return rc; } @@ -596,20 +1082,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info) { - ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; - uint32_t rc; + uint32_t rc = 0; + uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010; + uint32_t epid_v_func = 0; - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM, - 0, queue_id, &vm_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read"); + rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel"); - p_vm_info->dbi_en = vm_info.dbi_en; - p_vm_info->queue_en = vm_info.queue_en; - p_vm_info->epid = vm_info.cfg_epid; - p_vm_info->vector = vm_info.cfg_vector; - p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; - p_vm_info->func_num = vm_info.cfg_func_num; - p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1); + p_vm_info->queue_en = (epid_v_func >> 30 & 0x1); + p_vm_info->epid = (epid_v_func >> 24 & 0xF); + p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF); + p_vm_info->vector = (epid_v_func >> 8 & 0x7); + p_vm_info->func_num = (epid_v_func >> 5 & 0x7); + p_vm_info->vfunc_active = (epid_v_func & 0x1); return rc; } @@ -692,32 +1179,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t temp_data; - uint32_t rc; + uint32_t rc = ZXDH_OK; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + for (i = 0; i < p_reg_info->field_num; i++) { + if (p_field_info[i].len <= 32) { + temp_data = *((uint32_t *)p_data + i) & ZXDH_COMM_GET_BIT_MASK(uint32_t, + p_field_info[i].len); + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); + } + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - - for (i = 0; i < p_reg_info->field_num; i++) { - if (p_field_info[i].len <= 32) { - temp_data = *((uint32_t *)p_data + i); - rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - temp_data, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", - dev_id, m_offset, n_offset); - } + PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]); + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); + + PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.", + p_buff[i]); } } - return 0; + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + PMD_DRV_LOG(DEBUG, "reg_no = %d. m_offset = %d n_offset = %d", + reg_no, m_offset, n_offset); + PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } + + return rc; } static uint32_t @@ -796,11 +1301,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, { uint32_t rc; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) { - *p_item_num = 32; - return 0; - } - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE, 0, queue_id, p_item_num); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); @@ -850,20 +1350,11 @@ static void zxdh_np_dtb_mgr_destroy(uint32_t dev_id) { if (p_dpp_dtb_mgr[dev_id] != NULL) { - free(p_dpp_dtb_mgr[dev_id]); + rte_free(p_dpp_dtb_mgr[dev_id]); p_dpp_dtb_mgr[dev_id] = NULL; } } -static void -zxdh_np_tlb_mgr_destroy(uint32_t dev_id) -{ - if (g_p_dpp_tlb_mgr[dev_id] != NULL) { - free(g_p_dpp_tlb_mgr[dev_id]); - g_p_dpp_tlb_mgr[dev_id] = NULL; - } -} - static void zxdh_np_sdt_mgr_destroy(uint32_t dev_id) { @@ -874,7 +1365,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id) p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET(); if (p_sdt_tbl_temp != NULL) - free(p_sdt_tbl_temp); + rte_free(p_sdt_tbl_temp); ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL; @@ -891,7 +1382,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { - free(p_dev_info); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; } @@ -906,11 +1397,9 @@ zxdh_np_online_uninit(uint32_t dev_id, rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id); if (rc != 0) - PMD_DRV_LOG(ERR, "%s:dtb release error," - "port name %s queue id %d", __func__, port_name, queue_id); + PMD_DRV_LOG(ERR, "dtb release port name %s queue id %d", port_name, queue_id); zxdh_np_dtb_mgr_destroy(dev_id); - zxdh_np_tlb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -925,7 +1414,7 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no) static ZXDH_DTB_TABLE_T * -zxdh_np_table_info_get(uint32_t table_type) +zxdh_np_dtb_table_info_get(uint32_t table_type) { return &g_dpp_dtb_table_info[table_type]; } @@ -940,11 +1429,11 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_T *p_table_info = NULL; ZXDH_DTB_FIELD_T *p_field_info = NULL; uint32_t temp_data; - uint32_t rc; + uint32_t rc = 0; ZXDH_COMM_CHECK_POINT(p_cmd_data); ZXDH_COMM_CHECK_POINT(p_cmd_buff); - p_table_info = zxdh_np_table_info_get(table_type); + p_table_info = zxdh_np_dtb_table_info_get(table_type); p_field_info = p_table_info->p_fields; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); @@ -958,7 +1447,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, p_field_info[field_cnt].lsb_pos, p_field_info[field_cnt].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex"); } return rc; @@ -1022,17 +1511,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc; switch (wrt_mode) { case ZXDH_ERAM128_OPR_128b: - { if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]" - "INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__, - base_addr, index, __func__); + PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index); return ZXDH_PAR_CHK_INVALID_INDEX; } @@ -1042,27 +1528,22 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, } temp_idx = index << 7; break; - } - case ZXDH_ERAM128_OPR_64b: - { if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "dpp_se_smmu0_ind_write : index out of range"); return 1; } temp_idx = index << 6; break; - } - case ZXDH_ERAM128_OPR_1b: - { if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "dpp_se_smmu0_ind_write : index out of range"); return 1; } - temp_idx = index; - } + break; + default: + break; } dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx; @@ -1086,16 +1567,12 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) switch (mode) { case ZXDH_ERAM128_OPR_128b: - { dtb_len += 2; break; - } case ZXDH_ERAM128_OPR_64b: case ZXDH_ERAM128_OPR_1b: - { dtb_len += 1; break; - } default: break; } @@ -1112,7 +1589,7 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_DTB_ENTRY_T *p_dtb_one_entry) { uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0}; - ZXDH_SDTTBL_ERAM_T sdt_eram = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram = {0}; ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL; uint32_t base_addr; uint32_t index; @@ -1130,21 +1607,16 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, switch (opr_mode) { case ZXDH_ERAM128_TBL_128b: - { opr_mode = ZXDH_ERAM128_OPR_128b; break; - } case ZXDH_ERAM128_TBL_64b: - { opr_mode = ZXDH_ERAM128_OPR_64b; break; - } - case ZXDH_ERAM128_TBL_1b: - { opr_mode = ZXDH_ERAM128_OPR_1b; break; - } + default: + break; } if (del_en) { @@ -1187,11 +1659,11 @@ zxdh_np_dtb_data_write(uint8_t *p_data_buff, uint8_t *cmd = (uint8_t *)entry->cmd; uint8_t *data = (uint8_t *)entry->data; - rte_memcpy(p_cmd, cmd, cmd_size); + memcpy(p_cmd, cmd, cmd_size); if (!entry->data_in_cmd_flag) { zxdh_np_comm_swap(data, data_size); - rte_memcpy(p_data, data, data_size); + memcpy(p_data, data, data_size); } return 0; @@ -1283,16 +1755,25 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info) { - ZXDH_DTB_QUEUE_LEN_T dtb_len = {0}; uint32_t rc; - dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; - dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; - dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000; + uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004; + uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008; + uint32_t dtb_len = 0; - rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN, - 0, queue_id, (void *)&dtb_len); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32, + 1, &p_item_info->data_hddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32, + 1, &p_item_info->data_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len); + rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); return rc; } @@ -1400,7 +1881,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -1414,9 +1894,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1428,27 +1905,20 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: - { rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; - } default: - { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } - } addr_offset = dtb_len * ZXDH_DTB_LEN_POS_SETP; dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); @@ -1458,7 +1928,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1468,7 +1937,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); + return rc; } @@ -1492,7 +1961,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -1508,9 +1976,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1523,27 +1988,20 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: - { rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; - } default: - { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } - } addr_offset = dtb_len * ZXDH_DTB_LEN_POS_SETP; dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1554,21 +2012,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - rte_free(p_data_buff_ex); - return 0; + return rc; } static uint32_t @@ -1577,8 +2031,8 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_ uint32_t tbl_type = 0; uint32_t clutch_en = 0; - ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); @@ -1586,26 +2040,20 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_ switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: - { - p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info; + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; p_sdt_eram->table_type = tbl_type; p_sdt_eram->eram_clutch_en = clutch_en; break; - } case ZXDH_SDT_TBLT_PORTTBL: - { - p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; p_sdt_porttbl->table_type = tbl_type; p_sdt_porttbl->porttbl_clutch_en = clutch_en; break; - } default: - { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; } - } return 0; } @@ -1634,22 +2082,18 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, switch (eram_mode) { case ZXDH_ERAM128_TBL_128b: - { row_index = index; break; - } case ZXDH_ERAM128_TBL_64b: - { row_index = (index >> 1); col_index = index & 0x1; break; - } case ZXDH_ERAM128_TBL_1b: - { row_index = (index >> 7); col_index = index & 0x7F; break; - } + default: + break; } *p_row_index = row_index; *p_col_index = col_index; @@ -1661,7 +2105,7 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, { uint32_t index = p_dump_eram_entry->index; uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; uint32_t temp_data[4] = {0}; uint32_t row_index = 0; uint32_t col_index = 0; @@ -1676,21 +2120,17 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, switch (rd_mode) { case ZXDH_ERAM128_TBL_128b: - { memcpy(p_data, temp_data, (128 / 8)); break; - } case ZXDH_ERAM128_TBL_64b: - { memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); break; - } case ZXDH_ERAM128_TBL_1b: - { ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; - } + default: + break; } return rc; } @@ -1713,20 +2153,16 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: - { rc = zxdh_np_dtb_eram_data_get(dev_id, queue_id, sdt_no, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; - } default: - { PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; } - } return 0; } @@ -1737,10 +2173,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -1945,22 +2381,18 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - { row_index = index; break; - } case ZXDH_ERAM128_OPR_64b: - { row_index = (index >> 1); col_index = index & 0x1; break; - } case ZXDH_ERAM128_OPR_1b: - { row_index = (index >> 7); col_index = index & 0x7F; break; - } + default: + break; } eram_dump_base_addr = base_addr + row_index; @@ -1974,23 +2406,17 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - { memcpy(p_data, temp_data, (128 / 8)); break; - } - case ZXDH_ERAM128_OPR_64b: - { memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); break; - } - case ZXDH_ERAM128_OPR_1b: - { ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; - } + default: + break; } return rc; @@ -2058,3 +2484,29 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } + +int +zxdh_np_host_init(uint32_t dev_id, + ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; + uint32_t rc; + uint64_t agent_addr; + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); + + sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); + sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, + p_dev_init_ctrl->np_bar_offset); + sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; + + rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); + + zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); + + agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; + zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + + return 0; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 7da29cf7bd..cc298d0eff 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -6,7 +6,10 @@ #define ZXDH_NP_H #include <stdint.h> +#include <rte_spinlock.h> +#define ZXDH_OK (0) +#define ZXDH_ERR (1) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -51,11 +54,23 @@ #define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9) #define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10) +#define ZXDH_REG_NUL_ARRAY (0 << 0) +#define ZXDH_REG_UNI_ARRAY (1 << 0) +#define ZXDH_REG_BIN_ARRAY (1 << 1) +#define ZXDH_REG_FLAG_INDIRECT (1 << 0) +#define ZXDH_REG_FLAG_DIRECT (0 << 0) +#define ZXDH_FIELD_FLAG_RO (1 << 0) +#define ZXDH_FIELD_FLAG_RW (1 << 1) + +#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000) +#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000) + #define ZXDH_ACL_TBL_ID_MIN (0) #define ZXDH_ACL_TBL_ID_MAX (7) #define ZXDH_ACL_TBL_ID_NUM (8U) #define ZXDH_ACL_BLOCK_NUM (8U) +#define ZXDH_RD_CNT_MAX (100) #define ZXDH_SMMU0_READ_REG_MAX_NUM (4) #define ZXDH_DTB_ITEM_ACK_SIZE (16) @@ -95,6 +110,8 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_SE_OPR_RD (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -144,6 +161,17 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +typedef enum zxdh_module_base_addr_e { + ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, + ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, +} ZXDH_MODULE_BASE_ADDR_E; + +typedef enum zxdh_sys_base_addr_e { + ZXDH_SYS_SE_SMMU0_BASE_ADDR = (ZXDH_SYS_NP_BASE_ADDR0 + 0x00300000), + ZXDH_SYS_DTB_BASE_ADDR = (ZXDH_SYS_NP_BASE_ADDR1 + 0x00000000), + ZXDH_SYS_MAX_BASE_ADDR = 0x20000000, +} ZXDH_SYS_BASE_ADDR_E; + typedef enum zxdh_module_init_e { ZXDH_MODULE_INIT_NPPU = 0, ZXDH_MODULE_INIT_PPU, @@ -165,14 +193,24 @@ typedef enum zxdh_dev_type_e { } ZXDH_DEV_TYPE_E; typedef enum zxdh_reg_info_e { - ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0, - ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1, - ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2, - ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3, - ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0, + ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5, + ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6, + ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7, + ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8, ZXDH_REG_ENUM_MAX_VALUE } ZXDH_REG_INFO_E; +typedef enum zxdh_dev_spinlock_type_e { + ZXDH_DEV_SPINLOCK_T_SMMU0 = 0, + ZXDH_DEV_SPINLOCK_T_DTB = 1, + ZXDH_DEV_SPINLOCK_T_MAX +} ZXDH_DEV_SPINLOCK_TYPE_E; + typedef enum zxdh_dev_access_type_e { ZXDH_DEV_ACCESS_TYPE_PCIE = 0, ZXDH_DEV_ACCESS_TYPE_RISCV = 1, @@ -192,6 +230,29 @@ typedef enum zxdh_acl_pri_mode_e { ZXDH_ACL_PRI_INVALID, } ZXDH_ACL_PRI_MODE_E; +typedef enum zxdh_module_e { + CFG = 1, + NPPU, + PPU, + ETM, + STAT, + CAR, + SE, + SMMU0 = SE, + SMMU1 = SE, + DTB, + TRPG, + TSN, + AXI, + PTPTM, + DTB4K, + STAT4K, + PPU4K, + SE4K, + SMMU14K, + MODULE_MAX +} ZXDH_MODULE_E; + typedef struct zxdh_d_node { void *data; struct zxdh_d_node *prev; @@ -256,6 +317,15 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef struct zxdh_spin_lock_t { + rte_spinlock_t spinlock; +} ZXDH_SPINLOCK_T; + +typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); +typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); + typedef struct zxdh_sys_init_ctrl_t { ZXDH_DEV_TYPE_E device_type; uint32_t flags; @@ -282,6 +352,8 @@ typedef struct dpp_dev_cfg_t { uint64_t dma_phy_addr; uint64_t agent_addr; uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; + ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; + ZXDH_DEV_READ_FUNC p_pcie_read_fun; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -476,7 +548,7 @@ typedef struct zxdh_sdt_tbl_eram_t { uint32_t eram_base_addr; uint32_t eram_table_depth; uint32_t eram_clutch_en; -} ZXDH_SDTTBL_ERAM_T; +} ZXDH_SDT_TBL_ERAM_T; typedef union zxdh_endian_u { unsigned int a; @@ -505,12 +577,6 @@ typedef struct zxdh_dtb_queue_item_info_t { uint32_t data_hddr; } ZXDH_DTB_QUEUE_ITEM_INFO_T; -typedef struct zxdh_dtb_queue_len_t { - uint32_t cfg_dtb_cmd_type; - uint32_t cfg_dtb_cmd_int_en; - uint32_t cfg_queue_dtb_len; -} ZXDH_DTB_QUEUE_LEN_T; - typedef struct zxdh_dtb_eram_entry_info_t { uint32_t index; uint32_t *p_data; @@ -537,12 +603,12 @@ typedef struct zxdh_sdt_tbl_etcam_t { uint32_t as_rsp_mode; uint32_t etcam_table_depth; uint32_t etcam_clutch_en; -} ZXDH_SDTTBL_ETCAM_T; +} ZXDH_SDT_TBL_ETCAM_T; typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; -} ZXDH_SDTTBL_PORTTBL_T; +} ZXDH_SDT_TBL_PORT_TBL_T; typedef struct zxdh_dtb_hash_entry_info_t { uint8_t *p_actu_key; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 124724 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 02/14] net/zxdh: support compatibility check 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 03/14] net/zxdh: add agent channel Bingbin Chen ` (11 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5609 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 94 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 +++++ 2 files changed, 106 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index edc06beaf9..f6d1a215e3 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -13,6 +13,7 @@ #include "zxdh_np.h" #include "zxdh_logs.h" +#include "zxdh_msg.h" static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; @@ -23,6 +24,9 @@ static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -931,6 +935,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2508,5 +2597,10 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index cc298d0eff..a592436b4f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_OPR_RD (1) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -628,6 +631,15 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 10240 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 03/14] net/zxdh: add agent channel 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (10 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 18898 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 386 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 78 ++++++++ 2 files changed, 463 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index f6d1a215e3..cf5a192a02 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -298,6 +298,24 @@ zxdh_np_comm_convert32(uint32_t dw_data) #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) +static inline void +zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) +{ + rte_spinlock_init(&p_spinlock->spinlock); +} + +static inline void +zxdh_np_comm_spinlock_lock(ZXDH_SPINLOCK_T *p_spinlock) +{ + rte_spinlock_lock(&p_spinlock->spinlock); +} + +static inline void +zxdh_np_comm_spinlock_unlock(ZXDH_SPINLOCK_T *p_spinlock) +{ + rte_spinlock_unlock(&p_spinlock->spinlock); +} + static uint32_t zxdh_np_comm_is_big_endian(void) { @@ -354,6 +372,70 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %d ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_spinlock; + break; + case ZXDH_DEV_SPINLOCK_T_SMMU0: + *p_spinlock_out = &p_dev_info->smmu0_spinlock; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -719,6 +801,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + zxdh_np_comm_spinlock_create(&p_dev_info->dtb_spinlock); return 0; } @@ -810,6 +893,269 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_DROP: + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret); + } + + rte_free(recv_buffer); + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T), + }; + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PCIE_BAR_MSG, + .oper = ZXDH_BAR_MSG_NUM_REQ, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_RD, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent read resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_WR, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent write resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1020,6 +1366,24 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_pcie_bar_request"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1138,12 +1502,19 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1275,6 +1646,9 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1309,6 +1683,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -1683,7 +2061,7 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); @@ -2581,6 +2959,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); @@ -2602,5 +2981,10 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a592436b4f..a5fde341e9 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -111,10 +111,17 @@ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) #define ZXDH_SE_OPR_RD (1) +#define ZXDH_CHANNEL_REPS_LEN (4) #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -127,6 +134,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_SPIN_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_SPIN_LOCK_INIT_FAIL (ZXDH_SPIN_LOCK_BASE | 0x001) +#define ZXDH_SPIN_LOCK_LOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0x002) +#define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) +#define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -164,6 +177,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -349,6 +369,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -357,6 +378,8 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_SPINLOCK_T dtb_spinlock; + ZXDH_SPINLOCK_T smmu0_spinlock; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -631,6 +654,38 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_np_agent_msg_type_e { + ZXDH_REG_MSG = 0, + ZXDH_DTB_MSG, + ZXDH_TM_MSG, + ZXDH_PLCR_MSG, + ZXDH_PKTRX_IND_REG_RW_MSG, + ZXDH_PCIE_BAR_MSG, + ZXDH_RESET_MSG, + ZXDH_PXE_MSG, + ZXDH_TM_FLOW_SHAPE, + ZXDH_TM_TD, + ZXDH_TM_SE_SHAPE, + ZXDH_TM_PP_SHAPE, + ZXDH_PLCR_CAR_RATE, + ZXDH_PLCR_CAR_PKT_RATE, + ZXDH_PPU_THASH_RSK, + ZXDH_ACL_MSG, + ZXDH_STAT_MSG, + ZXDH_RES_MSG, + ZXDH_MSG_MAX +} MSG_TYPE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -640,6 +695,29 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 42934 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 04/14] net/zxdh: modify dtb queue ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (2 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (9 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 25966 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 495 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 ++++++++ 2 files changed, 485 insertions(+), 107 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index cf5a192a02..eb57d61898 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -17,16 +17,15 @@ static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; -static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -436,6 +435,25 @@ zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_queue_spinlock[index]; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -767,6 +785,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -802,6 +821,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; zxdh_np_comm_spinlock_create(&p_dev_info->dtb_spinlock); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + zxdh_np_comm_spinlock_create(&p_dev_info->dtb_queue_spinlock[i]); + return 0; } @@ -1156,6 +1179,89 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_REQUEST, + .vport = vport_info, + }; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %d, msg_result: %d", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %d, queue_id: %d", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_RELEASE, + .queue_id = queue_id, + }; + + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %d", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1384,48 +1490,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1715,52 +1779,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1795,20 +1813,74 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + uint32_t vport_info = (uint32_t)vport; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "dev_id %d vport 0x%x name %s queue_id %d done.", + dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(devid, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %d not request.", queueid); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %d name error.", queueid); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "queueid %d", queueid); return rc; } @@ -2260,24 +2332,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + zxdh_np_comm_spinlock_lock(p_spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2292,8 +2374,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2313,6 +2397,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + zxdh_np_comm_spinlock_unlock(p_spinlock); + return rc; } @@ -2326,8 +2412,6 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, uint32_t rc = 0; uint32_t dtb_interrupt_status = 0; - dtb_interrupt_status = g_dpp_dtb_int_enable; - rc = zxdh_np_dtb_tab_down_info_set(dev_id, queue_id, dtb_interrupt_status, @@ -2658,20 +2742,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + zxdh_np_comm_spinlock_lock(p_spinlock); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2683,11 +2775,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.int_en = int_flag; item_info.data_len = desc_len / 4; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + zxdh_np_comm_spinlock_unlock(p_spinlock); + return rc; } @@ -2730,16 +2821,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + zxdh_np_comm_spinlock_lock(p_spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2754,14 +2852,17 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + zxdh_np_comm_spinlock_unlock(p_spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + zxdh_np_comm_spinlock_unlock(p_spinlock); return 0; } @@ -2952,6 +3053,181 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = { + .down_start_phy_addr = phy_addr, + .down_start_vir_addr = vir_addr, + .down_item_size = size, + }; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = { + .up_start_phy_addr = phy_addr, + .up_start_vir_addr = vir_addr, + .up_item_size = size, + }; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -2986,5 +3262,10 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + + PMD_DRV_LOG(INFO, "host init done, queue_id = %u", p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a5fde341e9..0ad068053a 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -380,6 +380,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; + ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -568,6 +569,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -594,6 +667,15 @@ typedef struct zxdh_dtb_table_t { ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -686,6 +768,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -718,6 +805,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 55801 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 05/14] net/zxdh: add tables dump address ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (3 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (8 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 40315 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1144 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1235 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index eb57d61898..87975c13c3 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -26,6 +26,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -297,6 +298,58 @@ zxdh_np_comm_convert32(uint32_t dw_data) #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +static inline void +zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) +{ + ptr->data = pdata; + ptr->prev = NULL; + ptr->next = NULL; +} + +static inline void +zxdh_np_init_rbt_tn(ZXDH_RB_TN *p_tn, void *p_newkey) +{ + p_tn->p_key = p_newkey; + p_tn->color_lsv = 0; + p_tn->p_left = NULL; + p_tn->p_right = NULL; + p_tn->p_parent = NULL; + zxdh_np_init_d_node(&p_tn->tn_ln, p_tn); +} + +static inline uint32_t +zxdh_np_get_tn_lsv(ZXDH_RB_TN *p_tn) +{ + return p_tn->color_lsv >> 2; +} + +static inline void +zxdh_np_set_tn_lsv(ZXDH_RB_TN *p_tn, uint32_t list_val) +{ + p_tn->color_lsv &= 0x3; + p_tn->color_lsv |= (list_val << 2); +} + +static inline void +zxdh_np_set_tn_color(ZXDH_RB_TN *p_tn, uint32_t color) +{ + p_tn->color_lsv &= 0xfffffffc; + p_tn->color_lsv |= (color & 0x3); +} + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + static inline void zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) { @@ -357,6 +410,945 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_create(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(INFO, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = (ZXDH_LISTSTACK_MANAGER *)rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " p_list is null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(INFO, "dw_index is invalid"); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_switch_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = zxdh_np_get_tn_color(p_tn1); + color2 = zxdh_np_get_tn_color(p_tn2); + + zxdh_np_set_tn_color(p_tn1, color2); + zxdh_np_set_tn_color(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (zxdh_np_get_tn_color(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + zxdh_np_set_tn_color(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + zxdh_np_set_tn_color(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " p_rb_cfg already init!"); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_create(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_create"); + + p_rb_cfg->p_keybase = (uint8_t *)rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = (ZXDH_RB_TN *)rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + zxdh_np_init_rbt_tn(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + zxdh_np_set_tn_lsv(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + zxdh_np_init_d_node(&p_ins_tn->tn_ln, p_ins_tn); + } + + zxdh_np_set_tn_color(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(INFO, "info , rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = zxdh_np_get_tn_lsv(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(zxdh_np_get_tn_color(p_par_tn) == ZXDH_RBT_RED); + + zxdh_np_set_tn_color(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + } else { + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (zxdh_np_get_tn_color(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_switch_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (zxdh_np_get_tn_color(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + zxdh_np_set_tn_color(p_del_tn, zxdh_np_get_tn_color(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (zxdh_np_get_tn_color(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (zxdh_np_get_tn_color(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + zxdh_np_set_tn_color(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, zxdh_np_get_tn_lsv(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(INFO, "p_list point null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = (uint8_t *)rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + memcpy(p_rb_key, p_data, len); + + p_rb_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1806,10 +2798,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%d", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = (ZXDH_RB_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -1839,6 +2933,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "dev_id %d vport 0x%x name %s queue_id %d done.", @@ -1877,6 +2974,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3202,12 +4302,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = { + .sdt_no = sdt_no, + .phy_addr = phy_addr, + .vir_addr = vir_addr, + .size = size, + }; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3225,6 +4356,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 0ad068053a..d0388f3447 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -122,6 +122,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -140,6 +147,26 @@ #define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) #define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -184,6 +211,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -289,6 +344,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 109251 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 06/14] net/zxdh: add eram tables ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (4 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (7 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 32161 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 884 ++++++++++++++++++++++++++++++------- drivers/net/zxdh/zxdh_np.h | 15 + 2 files changed, 738 insertions(+), 161 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 87975c13c3..64ce699e52 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -196,6 +200,81 @@ static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +static ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -305,6 +384,28 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + static inline void zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) { @@ -3058,6 +3159,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3092,6 +3199,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + ZXDH_DTB_TABLE_T *p_table_info; + ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + ZXDH_COMM_GET_BIT_MASK(uint32_t, p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3141,6 +3281,31 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ERAM, + .base_addr = base_addr, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, @@ -3219,6 +3384,65 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + p_sdt_eram->eram_clutch_en = clutch_en; + break; + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %d ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -3239,6 +3463,9 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -3389,6 +3616,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(INFO, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(INFO, "[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(INFO, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + + PMD_DRV_LOG(INFO, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3521,6 +3840,122 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(INFO, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) { + PMD_DRV_LOG(ERR, "down queue %d item %d overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3589,17 +4024,11 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); return rc; } -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; -} - int zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint32_t queue_id, @@ -3673,71 +4102,25 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) { - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + uint32_t row_index = 0; + uint32_t col_index = 0; - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; + switch (eram_mode) { + case ZXDH_ERAM128_TBL_128b: + row_index = index; break; - - case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; - - switch (eram_mode) { - case ZXDH_ERAM128_TBL_128b: - row_index = index; - break; - case ZXDH_ERAM128_TBL_64b: - row_index = (index >> 1); - col_index = index & 0x1; + case ZXDH_ERAM128_TBL_64b: + row_index = (index >> 1); + col_index = index & 0x1; break; case ZXDH_ERAM128_TBL_1b: row_index = (index >> 7); @@ -3750,74 +4133,6 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, *p_col_index = col_index; } -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - memcpy(p_data, temp_data, (128 / 8)); - break; - case ZXDH_ERAM128_TBL_64b: - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - case ZXDH_ERAM128_TBL_1b: - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - default: - break; - } - return rc; -} - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - static void zxdh_np_stat_cfg_soft_get(uint32_t dev_id, ZXDH_PPU_STAT_CFG_T *p_stat_cfg) @@ -3882,6 +4197,181 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(INFO, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(INFO, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(INFO, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) { + PMD_DRV_LOG(ERR, "dump queue %d item %d overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -3909,6 +4399,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %d element %d dump done.", queue_id, queue_element_id); + return rc; } @@ -3967,33 +4467,6 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -4022,6 +4495,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; @@ -4032,6 +4513,87 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_data, temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_TBL_64b: + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d0388f3447..8ece4c160f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -175,6 +175,13 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) + +#define ZXDH_DTB_DELAY_TIME (50) +#define ZXDH_DTB_DOWN_OVER_TIME (2000) +#define ZXDH_DTB_DUMP_OVER_TIME (0x4c4b40) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -611,6 +618,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 80323 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 07/14] net/zxdh: get flow tables resources 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (5 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (6 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31703 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 18 ++ drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 490 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 336 ++++++++++++++++++++-- 4 files changed, 824 insertions(+), 21 deletions(-) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index 858e3c3d47..18b661b1ab 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1400,6 +1400,11 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) struct zxdh_hw *hw = eth_dev->data->dev_private; int ret = 0; + if (zxdh_shared_data != NULL && zxdh_shared_data->np_init_done) { + g_dtb_data.dev_refcnt++; + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { @@ -1407,6 +1412,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(0, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index fd4699c34d..b2ff7d32f6 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -40,6 +40,7 @@ #define ZXDH_DTB_TABLE_CONF_SIZE (32 * (16 + 16 * 1024)) #define ZXDH_MAX_NAME_LEN 32 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 64ce699e52..23542a0c07 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2355,6 +2355,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -4975,3 +5009,459 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } + +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_ERR; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_ERR; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_ERR; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_ERR; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_dtb_spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + return ZXDH_ERR; + } + + zxdh_np_comm_spinlock_unlock(p_dtb_spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 8ece4c160f..79434192ea 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -129,6 +129,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_ETCAM_BLOCK_NUM (8) /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -438,6 +444,173 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -479,6 +652,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -747,14 +921,6 @@ typedef struct zxdh_etcam_dump_info_t { uint32_t tb_width; } ZXDH_ETCAM_DUMP_INFO_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDT_TBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -806,19 +972,6 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDT_TBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; @@ -879,6 +1032,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t version_compatible_item; uint8_t major; @@ -921,6 +1097,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -934,5 +1227,6 @@ int zxdh_np_dtb_stats_get(uint32_t dev_id, ZXDH_STAT_CNT_MODE_E rd_mode, uint32_t index, uint32_t *p_data); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 65666 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 08/14] net/zxdh: support hash resources configuration 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (6 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (5 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35142 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 782 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 262 +++++++++++++ 2 files changed, 1044 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 23542a0c07..ed07b7c059 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -31,6 +31,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +static ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static const uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +static uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -451,6 +468,19 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); } +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) static inline void zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) { @@ -729,6 +759,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -754,6 +811,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5455,6 +5552,688 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) p_se_res->valid = 1; return rc; } + +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + zxdh_np_init_d_node(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + zxdh_np_init_d_node(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = (ZXDH_SE_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%d] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + break; + default: + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %d]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x]," + "ZBlock[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZBLCK, zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x], ZBlk[%d]," + "ZCell[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init," + "do not init again!", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %d!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = (HASH_DDR_CFG *)rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same but other ddr attribute is different"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = (ZXDH_SE_ITEM_CFG **)rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = (ZXDH_HASH_BULK_ZCAM_STAT *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %d ] is not init before" + " used!", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input param 'zcell_num' is [ %d ]," + "actually bulk[ %d ]monopolize zcells is [ %d ]!", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %d ] is not init" + " before used!", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input param 'zreg_num' is [ %d ]," + "actually bulk[ %d ]monopolize zregs is [ %d ]!", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "dev_id[0x%x],se_type[0x%x] invlaid!", dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5463,5 +6242,8 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) rc = zxdh_np_agent_se_res_get(dev_id, type); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 79434192ea..4eb1c716ac 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -135,6 +135,44 @@ #define ZXDH_ERAM_MAX_NUM (60) #define ZXDH_ETCAM_MAX_NUM (8) #define ZXDH_ETCAM_BLOCK_NUM (8) + +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -252,6 +290,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -380,6 +423,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -393,6 +443,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; @@ -611,6 +872,7 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T std_nic_res; ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90812 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 09/14] net/zxdh: implement tables initialization 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (7 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (4 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35399 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 674 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 187 ++++++++++ 2 files changed, 861 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index ed07b7c059..6721a3524b 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -22,6 +22,9 @@ static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +static ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -49,6 +52,10 @@ static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +static ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -481,6 +488,50 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, + uint32_t start_pos, uint32_t len) +{ + uint32_t mask = ZXDH_COMM_GET_BIT_MASK(uint32_t, len) << start_pos; + *dst = (*dst & mask) | (src & mask); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ + zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) + static inline void zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) { @@ -2086,6 +2137,231 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "soft sdt table not init!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft sdt table item invalid!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "0x%08x 0x%08x", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft table item invalid !"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "sdt_no: 0x%08x", sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL; + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", + table_type); + return ZXDH_ERR; + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -3412,6 +3688,7 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -6198,12 +6475,383 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + case ZXDH_SDT_TBLT_HASH: + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + case ZXDH_SDT_TBLT_ETCAM: + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + default: + PMD_DRV_LOG(ERR, "zxdh_np_apt_se_set_callback table_type[ %d ]" + "is invalid!", table_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + uint32_t entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%d], table_id[%d] is already init," + "do not init again!", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %d ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to reduce block_num in order to match with entry_num.", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + zxdh_np_init_d_node(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_tbls[table_id]); + rc = zxdh_comm_double_link_insert_last(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %d ] is already used by table[ %d ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6213,8 +6861,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6231,6 +6885,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 4eb1c716ac..974799a7d9 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -101,6 +101,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -173,6 +177,57 @@ #define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) #define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -295,6 +350,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + typedef enum zxdh_module_base_addr_e { ZXDH_MODULE_SE_SMMU0_BASE_ADDR = 0x00000000, ZXDH_MODULE_DTB_ENQ_BASE_ADDR = 0x00000000, @@ -450,6 +527,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -873,6 +965,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 86571 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (8 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (3 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 34971 bytes --] Implement hash tables write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 931 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 17 + 2 files changed, 947 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 6721a3524b..ea25d431b9 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -532,6 +532,76 @@ zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, #define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) +static inline uint32_t +zxdh_np_zblk_addr_conv(uint32_t zblk_idx) +{ + uint32_t group_size = 1 << ZXDH_ZBLK_IDX_BT_WIDTH; + uint32_t group_number = zblk_idx / ZXDH_ZBLK_NUM_PER_ZGRP; + uint32_t offset_in_group = zblk_idx % ZXDH_ZBLK_NUM_PER_ZGRP; + + return group_number * group_size + offset_in_group; +} + +static inline uint32_t +zxdh_np_zcell_addr_conv(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (zxdh_np_zblk_addr_conv(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | \ + (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) | \ + ((zxdh_np_zblk_addr_conv(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | \ + ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((zxdh_np_zcell_addr_conv(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static inline void zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) { @@ -1695,6 +1765,16 @@ zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_spinlock_get(uint32_t dev_id, + uint32_t fun_id, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *p_spinlock_out = &p_dev_info->hash_spinlock[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2066,7 +2146,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) zxdh_np_comm_spinlock_create(&p_dev_info->dtb_queue_spinlock[i]); - return 0; + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + zxdh_np_comm_spinlock_create(&p_dev_info->hash_spinlock[i]); + + return ZXDH_OK; } static uint32_t @@ -3689,6 +3772,65 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ZCAM, + .ram_reg_flag = reg_sram_flag, + .zgroup_id = zgroup_id, + .zblock_id = zblock_id, + .zcell_id = zcell_id, + .mask = mask, + .sram_addr = sram_addr & 0x1FF, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = (addr >> 16) & 0x1; + uint32_t zgroup_id = (addr >> 14) & 0x3; + uint32_t zblock_id = (addr >> 11) & 0x7; + uint32_t zcell_id = (addr >> 9) & 0x3; + uint32_t mask = (addr >> 17) & 0xF; + uint32_t sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4363,6 +4505,782 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = (ZXDH_HASH_RBKEY_INFO *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_init_rbt_tn(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint32_t rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + zxdh_np_init_d_node(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t item_entry_max = 4; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "Entry in item pos is: [%d]," + "entry size is: [%d].", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + HASH_DDR_CFG *p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + uint8_t key_type = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Hash DDR width mode" + " is not match to the key type.", ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s," + "item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = (ZXDH_SE_ITEM_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx is [0x%x]," + "p_zblk->hash_arg is [0x%x], crc_value is [0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id is [0x%x]," + "item_idx is [0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_D_NODE *p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = p_hash_entry_cfg->table_id; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + ZXDH_SE_ITEM_CFG *p_item_info = p_rbkey_new->p_item_info; + + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + zxdh_np_comm_spinlock_lock(p_hash_spinlock); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(ERR, "Error!there is not item in hash!"); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_comm_double_link_del failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_hash_form_write failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + zxdh_np_comm_spinlock_lock(p_hash_spinlock); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_hash_red_black_node_alloc failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dtb_hash_form_write failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + } + + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_ddr failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zcell failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash form write failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_ERR; + } + + p_hash_cfg->hash_stat.insert_ok++; + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = temp_key; + entry.p_rst = temp_rst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} int zxdh_np_dtb_table_entry_write(uint32_t dev_id, @@ -4402,6 +5320,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -4479,6 +5401,13 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 974799a7d9..a006efe516 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -92,6 +94,12 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -542,6 +550,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1101,6 +1117,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_SPINLOCK_T hash_spinlock[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90277 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 11/14] net/zxdh: get hash table entry result 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (9 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (2 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16528 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 479 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 486 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index ea25d431b9..8ac33e88ed 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1282,6 +1282,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -3857,6 +3891,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ZCAM, + .tb_width = tb_width, + .sram_addr = addr & 0x1FF, + .ram_reg_flag = (addr >> 16) & 0x1, + .z_reg_cell_id = (addr >> 9) & 0x3, + .zblock_id = (addr >> 11) & 0x7, + .zgroup_id = (addr >> 14) & 0x3, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5899,6 +5965,397 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %d.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "hash search failed!"); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + zxdh_np_comm_spinlock_lock(p_hash_spinlock); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return ZXDH_OK; + } + + p_rbkey = p_rb_tn_rtn->p_key; + p_item = p_rbkey->p_item_info; + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + zxdh_np_comm_spinlock_unlock(p_hash_spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = temp_key; + hash_entry.p_rst = temp_rst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -5909,6 +6366,9 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); @@ -5923,6 +6383,25 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; + case ZXDH_SDT_TBLT_HASH: + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, "hash search failed"); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a006efe516..8f0218cc97 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1289,6 +1289,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 47532 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 12/14] net/zxdh: delete all hash entries 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (10 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 37531 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 45 ++ drivers/net/zxdh/zxdh_np.c | 1050 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 14 + 3 files changed, 1109 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index 18b661b1ab..b99e79ca4a 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -966,6 +966,29 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + uint32_t sdt_no; + int ret = 0; + if (!g_dtb_data.init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(0, g_dtb_data.queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(0, g_dtb_data.queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -974,6 +997,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!g_dtb_data.init_done && !g_dtb_data.dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--g_dtb_data.dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1394,6 +1419,25 @@ zxdh_init_once(void) return ret; } +static int zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + int ret = 0; + if (!g_dtb_data.init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(0, g_dtb_data.queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(0, g_dtb_data.queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { @@ -1423,6 +1467,7 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); return -1; } + zxdh_tbl_entry_offline_destroy(hw); } if (zxdh_shared_data != NULL) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 8ac33e88ed..3ca053b6a5 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -510,6 +510,7 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) @@ -1702,6 +1703,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3652,6 +3667,219 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_HASH_CFG *p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_D_HEAD *p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%d] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + break; + default: + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %d] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = dpp_se_cfg[dev_id]; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(INFO, "Error[0x%x], fun_id [%d] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3663,6 +3891,10 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != 0) PMD_DRV_LOG(ERR, "dtb release port name %s queue id %d", port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -3923,6 +4155,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5657,6 +5908,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -5870,6 +6144,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %d success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %d fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8329,3 +8698,684 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } + +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + + if (srh_succ) { + zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d" + " Mono Zreg_id :%d", zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + rc = zxdh_np_soft_sdt_tbl_get(0, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = (uint8_t *)rte_zmalloc(NULL, max_item_num * + sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_rst = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + rte_free(p_key); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(0, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(0, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 8f0218cc97..6d1e6df06c 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -236,6 +236,10 @@ #define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) #define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) +/* hash */ +#define ZXDH_SDT_L2_ENTRY_TABLE0 (64) +#define ZXDH_SDT_MC_TABLE0 (76) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -1687,6 +1691,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1701,5 +1710,10 @@ int zxdh_np_dtb_stats_get(uint32_t dev_id, uint32_t index, uint32_t *p_data); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 106934 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 13/14] net/zxdh: add acl tables ops 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (11 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31148 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 895 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 31 ++ 2 files changed, 926 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 3ca053b6a5..760560d8b7 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -603,6 +603,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static inline void zxdh_np_comm_spinlock_create(ZXDH_SPINLOCK_T *p_spinlock) { @@ -3880,6 +3885,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "etcam_is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %d ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3895,6 +3959,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4097,6 +4162,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ETCAM, + .block_sel = block_idx, + .init_en = 0, + .row_or_col_msk = row_or_col_msk, + .vben = vben, + .reg_tcam_flag = reg_tcam_flag, + .uload = flush, + .rd_wr = rd_wr, + .wr_mode = wr_mode, + .data_or_mask = data_or_mask, + .addr = ram_addr, + .vbit = vbit, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4155,6 +4284,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ETCAM, + .block_sel = p_etcam_dump_info->block_sel, + .addr = p_etcam_dump_info->addr, + .rd_mode = p_etcam_dump_info->rd_mode, + .data_or_mask = p_etcam_dump_info->data_or_mask, + .tb_depth = p_etcam_dump_info->tb_depth, + .tb_width = p_etcam_dump_info->tb_width, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4174,6 +4332,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5599,6 +5789,317 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + uint32_t entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_TBL_64b: + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + case ZXDH_ERAM128_TBL_1b: + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + default: + break; + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -5641,6 +6142,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -6725,6 +7230,389 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = (uint8_t *)rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware success: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware fail: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + + case ZXDH_ERAM128_TBL_64b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6771,6 +7659,13 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6d1e6df06c..5bff4530da 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1300,6 +1300,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1314,6 +1332,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90246 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v2 14/14] net/zxdh: clean stat values 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen ` (12 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-02-22 7:22 ` Bingbin Chen 2025-02-22 17:34 ` Stephen Hemminger 13 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-02-22 7:22 UTC (permalink / raw) To: stephen, wang.junlong1; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 12339 bytes --] Implement stat values clean operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev_ops.c | 4 + drivers/net/zxdh/zxdh_np.c | 302 +++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 23 ++- 3 files changed, 328 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c index 1a21ded58e..284bf27d10 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.c +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c @@ -1500,11 +1500,15 @@ static int zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type int zxdh_dev_stats_reset(struct rte_eth_dev *dev) { struct zxdh_hw *hw = dev->data->dev_private; + uint64_t stats_data; zxdh_hw_stats_reset(dev, ZXDH_VQM_DEV_STATS_RESET); if (hw->is_pf) zxdh_hw_stats_reset(dev, ZXDH_MAC_STATS_RESET); + zxdh_np_stat_ppu_cnt_get_ex(0, ZXDH_STAT_64_MODE, 0, + ZXDH_STAT_RD_CLR_MODE_CLR, (uint32_t *)&stats_data); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 760560d8b7..362814f410 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2197,6 +2197,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, zxdh_np_comm_spinlock_create(&p_dev_info->dtb_spinlock); + zxdh_np_comm_spinlock_create(&p_dev_info->smmu0_spinlock); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) zxdh_np_comm_spinlock_create(&p_dev_info->dtb_queue_spinlock[i]); @@ -3238,6 +3240,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -10274,3 +10302,277 @@ zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, return rc; } + +static uint32_t +zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) +{ + uint32_t rc = ZXDH_OK; + + uint32_t data = 0; + uint32_t rd_cnt = 0; + uint32_t done_flag = 0; + + while (!done_flag) { + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read32 Fail!", rc); + return rc; + } + + done_flag = (data >> pos) & 0x1; + + if (done_flag) + break; + + if (rd_cnt > ZXDH_RD_CNT_MAX * ZXDH_RD_CNT_MAX) + return ZXDH_ERR; + + rd_cnt++; + } + + return rc; +} + +static uint32_t +zxdh_np_se_smmu0_ind_read(uint32_t dev_id, + uint32_t base_addr, + uint32_t index, + uint32_t rd_mode, + uint32_t rd_clr_mode, + uint32_t *p_data) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t temp_data[4] = {0}; + uint32_t *p_temp_data = NULL; + ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + zxdh_np_comm_spinlock_lock(p_ind_spinlock); + + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + + if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { + cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = ZXDH_RD_MODE_HOLD; + cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; + + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + if ((0xFFFFFFFF - (base_addr)) < (index)) { + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; + break; + case ZXDH_ERAM128_OPR_64b: + if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x1; + break; + case ZXDH_ERAM128_OPR_32b: + if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x3; + break; + case ZXDH_ERAM128_OPR_1b: + if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = index & ZXDH_ERAM128_BADDR_MASK; + col_index = index & 0x7F; + break; + default: + break; + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; + } else { + cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; + cpu_ind_cmd.cpu_ind_rd_mode = ZXDH_RD_MODE_CLEAR; + + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + if ((0xFFFFFFFF - (base_addr)) < (index)) { + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 7); + cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_OPR_64b: + if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 6); + cpu_ind_cmd.cpu_req_mode = 2; + break; + case ZXDH_ERAM128_OPR_32b: + if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { + PMD_DRV_LOG(ERR, "index out of range!"); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + row_index = (index << 5); + cpu_ind_cmd.cpu_req_mode = 1; + break; + case ZXDH_ERAM128_OPR_1b: + PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error!", + rd_clr_mode, rd_mode); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + default: + break; + } + + cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; + } + + rc = zxdh_np_reg_write(dev_id, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + + p_temp_data = temp_data; + for (i = 0; i < 4; i++) { + rc = zxdh_np_reg_read(dev_id, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + return ZXDH_ERR; + } + } + + if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + memcpy(p_data, p_temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_OPR_64b: + memcpy(p_data, p_temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_OPR_32b: + memcpy(p_data, p_temp_data + ((3 - col_index)), (32 / 8)); + break; + case ZXDH_ERAM128_OPR_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], + *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } else { + switch (rd_mode) { + case ZXDH_ERAM128_OPR_128b: + memcpy(p_data, p_temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_OPR_64b: + memcpy(p_data, p_temp_data, (64 / 8)); + break; + case ZXDH_ERAM128_OPR_32b: + memcpy(p_data, p_temp_data, (64 / 8)); + break; + default: + break; + } + } + + zxdh_np_comm_spinlock_unlock(p_ind_spinlock); + + return rc; +} + +uint32_t +zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, + ZXDH_STAT_CNT_MODE_E rd_mode, + uint32_t index, + uint32_t clr_mode, + uint32_t *p_data) +{ + uint32_t rc = ZXDH_OK; + uint32_t ppu_eram_baddr = 0; + uint32_t ppu_eram_depth = 0; + uint32_t eram_rd_mode = 0; + uint32_t eram_clr_mode = 0; + ZXDH_PPU_STAT_CFG_T stat_cfg = {0}; + + zxdh_np_stat_cfg_soft_get(dev_id, &stat_cfg); + + ppu_eram_depth = stat_cfg.eram_depth; + ppu_eram_baddr = stat_cfg.eram_baddr; + + if ((index >> (ZXDH_STAT_128_MODE - rd_mode)) < ppu_eram_depth) { + if (rd_mode == ZXDH_STAT_128_MODE) + eram_rd_mode = ZXDH_ERAM128_OPR_128b; + else + eram_rd_mode = ZXDH_ERAM128_OPR_64b; + + if (clr_mode == ZXDH_STAT_RD_CLR_MODE_UNCLR) + eram_clr_mode = ZXDH_RD_MODE_HOLD; + else + eram_clr_mode = ZXDH_RD_MODE_CLEAR; + + rc = zxdh_np_se_smmu0_ind_read(dev_id, + ppu_eram_baddr, + index, + eram_rd_mode, + eram_clr_mode, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_smmu0_ind_read"); + } else { + PMD_DRV_LOG(ERR, "not have ddr stat."); + } + + return rc; +} diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 5bff4530da..efec836bce 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1193,6 +1193,12 @@ typedef struct zxdh_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_t { uint32_t cfg_vfunc_active; } ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T; +typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { + uint32_t cpu_ind_rw; + uint32_t cpu_ind_rd_mode; + uint32_t cpu_req_mode; + uint32_t cpu_ind_addr; +} ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; typedef uint32_t (*ZXDH_REG_WRITE)(uint32_t dev_id, uint32_t addr, uint32_t *p_data); typedef uint32_t (*ZXDH_REG_READ)(uint32_t dev_id, uint32_t addr, uint32_t *p_data); @@ -1503,6 +1509,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_stat_rd_clr_mode_e { + ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, + ZXDH_STAT_RD_CLR_MODE_CLR = 1, + ZXDH_STAT_RD_CLR_MODE_MAX, +} STAT_RD_CLR_MODE_E; + +typedef enum zxdh_eram128_rd_clr_mode_e { + ZXDH_RD_MODE_HOLD = 0, + ZXDH_RD_MODE_CLEAR = 1, +} ZXDH_ERAM128_RD_CLR_MODE_E; + typedef enum zxdh_np_agent_msg_type_e { ZXDH_REG_MSG = 0, ZXDH_DTB_MSG, @@ -1746,5 +1763,9 @@ uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, __rte_unused uint32_t flush_mode); - +uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, + ZXDH_STAT_CNT_MODE_E rd_mode, + uint32_t index, + uint32_t clr_mode, + uint32_t *p_data); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 34832 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v2 14/14] net/zxdh: clean stat values 2025-02-22 7:22 ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen @ 2025-02-22 17:34 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-02-22 17:34 UTC (permalink / raw) To: Bingbin Chen; +Cc: wang.junlong1, dev On Sat, 22 Feb 2025 15:22:32 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > Implement stat values clean operation by agent channel. > > Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> > --- The conversion to spinlock is good idea, but now the lock annotation is catching a different issue. It helps to have a cover letter on each patch series -------------------------------BEGIN LOGS---------------------------- #################################################################################### #### [Begin job log] "ubuntu-22.04-clang-stdatomic" at step Build and test #################################################################################### [2300/3227] Compiling C object drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_common.c.o [2301/3227] Compiling C object drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_msg.c.o [2302/3227] Compiling C object drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_queue.c.o [2303/3227] Compiling C object drivers/libtmp_rte_net_xsc.a.p/net_xsc_xsc_tx.c.o [2304/3227] Linking static target drivers/libtmp_rte_net_xsc.a [2305/3227] Compiling C object drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_np.c.o FAILED: drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_np.c.o ccache clang -Idrivers/libtmp_rte_net_zxdh.a.p -Idrivers -I../drivers -Idrivers/net/zxdh -I../drivers/net/zxdh -Ilib/ethdev -I../lib/ethdev -I. -I.. -Iconfig -I../config -Ilib/eal/include -I../lib/eal/include -Ilib/eal/linux/include -I../lib/eal/linux/include -Ilib/eal/x86/include -I../lib/eal/x86/include -I../kernel/linux -Ilib/eal/common -I../lib/eal/common -Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs -Ilib/log -I../lib/log -Ilib/metrics -I../lib/metrics -Ilib/telemetry -I../lib/telemetry -Ilib/net -I../lib/net -Ilib/mbuf -I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring -Ilib/meter -I../lib/meter -Idrivers/bus/pci -I../drivers/bus/pci -I../drivers/bus/pci/linux -Ilib/pci -I../lib/pci -Idrivers/bus/vdev -I../drivers/bus/vdev -Xclang -fcolor-diagnostics -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Wextra -Werror -std=c11 -O2 -g -include rte_config.h -Wvla -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral -Wformat-security -Wmissing-declarations -W missing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef -Wwrite-strings -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC -march=corei7 -mrtm -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -Wno-address-of-packed-member -Wno-vla -DRTE_LOG_DEFAULT_LOGTYPE=pmd.net.zxdh -DRTE_ANNOTATE_LOCKS -Wthread-safety -MD -MQ drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_np.c.o -MF drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_np.c.o.d -o drivers/libtmp_rte_net_zxdh.a.p/net_zxdh_zxdh_np.c.o -c ../drivers/net/zxdh/zxdh_np.c ../drivers/net/zxdh/zxdh_np.c:621:1: error: mutex 'p_spinlock->spinlock' is still held at the end of function [-Werror,-Wthread-safety-analysis] } ^ ../drivers/net/zxdh/zxdh_np.c:620:2: note: mutex acquired here rte_spinlock_lock(&p_spinlock->spinlock); ^ ../drivers/net/zxdh/zxdh_np.c:626:2: error: releasing spinlock 'p_spinlock->spinlock' that was not held [-Werror,-Wthread-safety-analysis] rte_spinlock_unlock(&p_spinlock->spinlock); ^ 2 errors generated. ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v3 00/14] net/zxdh: add network processor ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (5 preceding siblings ...) 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (13 more replies) 2025-03-10 23:19 ` [PATCH v1 01/14] net/zxdh: add network processor registers ops Stephen Hemminger 7 siblings, 14 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 1399 bytes --] V3: - resolve code style. - resolve spin lock build issue. - rebase code baseline. - modify parameters of the plcr function. V2: - resolve code style and github-robot build issue. - eliminate commit warning. - remove unnecessary initialization, which first usage will set. - replace mutex lock with spinlock. V1: - updated network processor driver. - improve insert/delete/get table code funcs. Bingbin Chen (14): net/zxdh: add network processor registers ops net/zxdh: support compatibility check net/zxdh: add agent channel net/zxdh: modify dtb queue ops net/zxdh: add tables dump address ops net/zxdh: add eram tables ops net/zxdh: get flow tables resources net/zxdh: support hash resources configuration net/zxdh: implement tables initialization net/zxdh: support hash tables write and delete ops net/zxdh: get hash table entry result net/zxdh: delete all hash entries net/zxdh: add acl tables ops net/zxdh: modify parameters of the plcr function drivers/net/zxdh/zxdh_ethdev.c | 70 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_msg.c | 3 +- drivers/net/zxdh/zxdh_mtr.c | 8 +- drivers/net/zxdh/zxdh_np.c | 11387 +++++++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 1223 +++- 6 files changed, 11118 insertions(+), 1574 deletions(-) -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 2685 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v3 01/14] net/zxdh: add network processor registers ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 02/14] net/zxdh: support compatibility check Bingbin Chen ` (12 subsequent siblings) 13 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 50368 bytes --] Add (np)network processor registers read/write interfaces. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 969 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 95 +++- 2 files changed, 845 insertions(+), 219 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 28c9e4c1c1..946e987a34 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -15,7 +15,6 @@ #include "zxdh_logs.h" #include "zxdh_msg.h" -static uint64_t g_np_bar_offset; static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; static uint32_t g_dpp_dtb_int_enable; @@ -23,14 +22,185 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_REG_T g_dpp_reg_info[4]; -static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, +}; + +static ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, +}; + +static ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 0, 1}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 63, 32}, + {"data_l", 31, 32}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag", 123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel", 123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr", 108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + +static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { + { + "ddr", + ZXDH_DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + ZXDH_DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + ZXDH_DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + ZXDH_DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + ZXDH_DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + ZXDH_DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + ZXDH_DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ + (((data_len) & 0x3ff) | \ + ((int_en) << 29) | \ + ((cmd_type) << 30)) #define ZXDH_COMM_MASK_BIT(_bitnum_)\ (0x1U << (_bitnum_)) @@ -47,8 +217,7 @@ static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\ do {\ if (NULL == (point)) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "dev: %d [POINT NULL]", (dev_id));\ RTE_ASSERT(0);\ } \ } while (0) @@ -56,33 +225,22 @@ do {\ #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d !"\ - "-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "dev: %d, %s failed!", (dev_id), becall);\ RTE_ASSERT(0);\ } \ } while (0) -#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ - } \ -} while (0) - #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d !-- %s Call %s"\ - " Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ } \ } while (0) #define ZXDH_COMM_CHECK_RC(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d!-- %s Call %s "\ - "Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ RTE_ASSERT(0);\ } \ } while (0) @@ -90,34 +248,28 @@ do {\ #define ZXDH_COMM_CHECK_POINT(point)\ do {\ if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "[POINT NULL]");\ RTE_ASSERT(0);\ } \ } while (0) +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) +{ + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; +} -#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ - rte_free(ptr);\ - RTE_ASSERT(0);\ - } \ -} while (0) - -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ -do {\ - if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ - " %s Fail!", __FILE__, __LINE__, __func__, becall);\ - rte_free(ptr);\ - } \ -} while (0) +static inline uint32_t +zxdh_np_comm_convert32(uint32_t dw_data) +{ + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; +} #define ZXDH_COMM_CONVERT16(w_data) \ - (((w_data) & 0xff) << 8) + zxdh_np_comm_convert16(w_data) + +#define ZXDH_COMM_CONVERT32(w_data) \ + zxdh_np_comm_convert32(w_data) #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) @@ -143,7 +295,7 @@ do {\ #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) -ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"cara_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -155,7 +307,7 @@ ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carb_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carb_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -167,7 +319,7 @@ ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carc_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carc_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -179,7 +331,7 @@ ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { +static ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { {"pktrx_glbal_cfg_0", ZXDH_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, }; @@ -215,7 +367,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) uc_byte_mode = dw_byte_len % 4 & 0xff; for (i = 0; i < dw_byte_num; i++) { - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); p_dw_tmp++; } @@ -239,6 +391,397 @@ zxdh_np_dev_init(void) return 0; } +static uint32_t +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static void +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + data = *p_data; + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + *((volatile uint32_t *)addr) = data; +} + +static void +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + data = *((volatile uint32_t *)addr); + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *p_data = data; +} + +static uint64_t +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) + return ZXDH_DEV_TYPE_INVALID; + + return p_dev_info->pcie_addr; +} + +static void +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); +} + +static void +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); +} + +static uint32_t +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_write(dev_id, addr, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_read(dev_id, addr, p_data); +} + +static ZXDH_REG_T g_dpp_reg_info[] = { + { + .reg_name = "cpu_ind_cmd", + .reg_no = 669, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 4, + .p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rd_done", + .reg_no = 670, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat0", + .reg_no = 671, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat1", + .reg_no = 672, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat2", + .reg_no = 673, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat3", + .reg_no = 674, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "wr_arb_cpu_rdy", + .reg_no = 676, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "info_queue_buf_space_left_0_127", + .reg_no = 820, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 1, + .p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cfg_epid_v_func_num_0_127", + .reg_no = 821, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 7, + .p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cara_queue_ram0_159_0", + .reg_no = 721, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x000000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x7FFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_cara_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carb_queue_ram0_159_0", + .reg_no = 738, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x100000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0xFFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carb_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carc_queue_ram0_159_0", + .reg_no = 755, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x200000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x3FF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carc_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "pktrx_glbal_cfg_0", + .reg_no = 448, + .module_no = NPPU, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_NPPU_BASE_ADDR + ZXDH_MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, +}; + +static uint32_t +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) +{ + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = NULL; + + p_reg_info = &g_dpp_reg_info[reg_no]; + + addr = p_reg_info->addr; + + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { + if (n_offset > (p_reg_info->n_size - 1)) + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%d, n:%d," + "size:%d", reg_no, n_offset, p_reg_info->n_size - 1); + + addr += n_offset * p_reg_info->n_step; + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + PMD_DRV_LOG(ERR, "reg n_offset or m_offset is out of range, reg_no:%d," + "n:%d, n_size:%d, m:%d, m_size:%d,", reg_no, n_offset, + p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1); + + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; + } + + return addr; +} + static uint32_t zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, @@ -262,7 +805,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, } else { /* device is new. */ p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } p_dev_mgr->p_dev_array[dev_id] = p_dev_info; p_dev_mgr->device_num++; } @@ -275,6 +821,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->dma_vir_addr = dma_vir_addr; p_dev_info->dma_phy_addr = dma_phy_addr; + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + return 0; } @@ -323,8 +872,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id) p_sdt_mgr->channel_num++; } else { - PMD_DRV_LOG(ERR, "Error: %s for dev[%d]" - "is called repeatedly!", __func__, dev_id); + PMD_DRV_LOG(ERR, "called repeatedly!"); return 1; } @@ -376,6 +924,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) return p_dpp_dtb_mgr[dev_id]; } +static uint32_t +zxdh_np_dtb_mgr_create(uint32_t dev_id) +{ + if (p_dpp_dtb_mgr[dev_id] != NULL) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); + return ZXDH_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[dev_id] = (ZXDH_DTB_MGR_T *)rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + if (p_dpp_dtb_mgr[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dtb_soft_init(uint32_t dev_id) { @@ -386,10 +952,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id) p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) { - p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + zxdh_np_dtb_mgr_create(dev_id); + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) - return 1; + return ZXDH_RC_DTB_MGR_NOT_EXIST; } return 0; @@ -469,36 +1036,10 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE) ? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0; - g_np_bar_offset = bar_offset; return np_addr; } -int -zxdh_np_host_init(uint32_t dev_id, - ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) -{ - ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; - uint32_t rc; - uint64_t agent_addr; - - ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); - - sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); - sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, - p_dev_init_ctrl->np_bar_offset); - sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; - rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); - - zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); - - agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; - zxdh_np_dev_agent_addr_set(dev_id, agent_addr); - - return 0; -} - static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -611,24 +1152,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t rc = 0; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - for (i = 0; i < p_reg_info->field_num; i++) { - rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - (uint32_t *)p_data + i, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]); + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); } } + + for (i = 0; i < p_reg_info->field_num; i++) { + rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + (uint32_t *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex"); + PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + } + return rc; } @@ -637,20 +1191,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info) { - ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; - uint32_t rc; + uint32_t rc = 0; + uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010; + uint32_t epid_v_func = 0; - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM, - 0, queue_id, &vm_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read"); + rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel"); - p_vm_info->dbi_en = vm_info.dbi_en; - p_vm_info->queue_en = vm_info.queue_en; - p_vm_info->epid = vm_info.cfg_epid; - p_vm_info->vector = vm_info.cfg_vector; - p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; - p_vm_info->func_num = vm_info.cfg_func_num; - p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1); + p_vm_info->queue_en = (epid_v_func >> 30 & 0x1); + p_vm_info->epid = (epid_v_func >> 24 & 0xF); + p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF); + p_vm_info->vector = (epid_v_func >> 8 & 0x7); + p_vm_info->func_num = (epid_v_func >> 5 & 0x7); + p_vm_info->vfunc_active = (epid_v_func & 0x1); return rc; } @@ -733,32 +1288,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t temp_data; - uint32_t rc; + uint32_t rc = ZXDH_OK; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + for (i = 0; i < p_reg_info->field_num; i++) { + if (p_field_info[i].len <= 32) { + temp_data = *((uint32_t *)p_data + i) & ZXDH_COMM_GET_BIT_MASK(uint32_t, + p_field_info[i].len); + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); + } + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - - for (i = 0; i < p_reg_info->field_num; i++) { - if (p_field_info[i].len <= 32) { - temp_data = *((uint32_t *)p_data + i); - rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - temp_data, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", - dev_id, m_offset, n_offset); - } + PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]); + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); + + PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.", + p_buff[i]); } } - return 0; + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + PMD_DRV_LOG(DEBUG, "reg_no = %d. m_offset = %d n_offset = %d", + reg_no, m_offset, n_offset); + PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } + + return rc; } static uint32_t @@ -837,11 +1410,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, { uint32_t rc; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) { - *p_item_num = 32; - return 0; - } - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE, 0, queue_id, p_item_num); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); @@ -891,20 +1459,11 @@ static void zxdh_np_dtb_mgr_destroy(uint32_t dev_id) { if (p_dpp_dtb_mgr[dev_id] != NULL) { - free(p_dpp_dtb_mgr[dev_id]); + rte_free(p_dpp_dtb_mgr[dev_id]); p_dpp_dtb_mgr[dev_id] = NULL; } } -static void -zxdh_np_tlb_mgr_destroy(uint32_t dev_id) -{ - if (g_p_dpp_tlb_mgr[dev_id] != NULL) { - free(g_p_dpp_tlb_mgr[dev_id]); - g_p_dpp_tlb_mgr[dev_id] = NULL; - } -} - static void zxdh_np_sdt_mgr_destroy(uint32_t dev_id) { @@ -914,7 +1473,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id) p_sdt_tbl_temp = ZXDH_SDT_SOFT_TBL_GET(dev_id); p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET(); - free(p_sdt_tbl_temp); + rte_free(p_sdt_tbl_temp); ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL; @@ -931,7 +1490,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { - free(p_dev_info); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; } @@ -946,11 +1505,9 @@ zxdh_np_online_uninit(uint32_t dev_id, rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id); if (rc != 0) - PMD_DRV_LOG(ERR, "%s:dtb release error," - "port name %s queue id %d", __func__, port_name, queue_id); + PMD_DRV_LOG(ERR, "dtb release port name %s queue id %d", port_name, queue_id); zxdh_np_dtb_mgr_destroy(dev_id); - zxdh_np_tlb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -965,7 +1522,7 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no) static ZXDH_DTB_TABLE_T * -zxdh_np_table_info_get(uint32_t table_type) +zxdh_np_dtb_table_info_get(uint32_t table_type) { return &g_dpp_dtb_table_info[table_type]; } @@ -984,7 +1541,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_COMM_CHECK_POINT(p_cmd_data); ZXDH_COMM_CHECK_POINT(p_cmd_buff); - p_table_info = zxdh_np_table_info_get(table_type); + p_table_info = zxdh_np_dtb_table_info_get(table_type); p_field_info = p_table_info->p_fields; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); @@ -998,7 +1555,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, p_field_info[field_cnt].lsb_pos, p_field_info[field_cnt].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex"); } return rc; @@ -1062,17 +1619,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc = 0; switch (wrt_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]" - "INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__, - base_addr, index, __func__); - + PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { @@ -1095,6 +1649,9 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, } temp_idx = index; + break; + default: + break; } dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx; @@ -1140,7 +1697,7 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_DTB_ENTRY_T *p_dtb_one_entry) { uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0}; - ZXDH_SDTTBL_ERAM_T sdt_eram = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram = {0}; ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL; uint32_t base_addr; uint32_t index; @@ -1166,6 +1723,8 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, case ZXDH_ERAM128_TBL_1b: opr_mode = ZXDH_ERAM128_OPR_1b; break; + default: + break; } if (del_en) { @@ -1304,16 +1863,26 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info) { - ZXDH_DTB_QUEUE_LEN_T dtb_len = {0}; uint32_t rc; - dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; - dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; - dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000; + uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004; + uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008; + uint32_t dtb_len = 0; + + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32, + 1, &p_item_info->data_hddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32, + 1, &p_item_info->data_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len); + rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); - rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN, - 0, queue_id, (void *)&dtb_len); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); return rc; } @@ -1421,7 +1990,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff; - uint8_t *p_data_buff_ex; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -1435,9 +2003,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1455,7 +2020,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1463,9 +2027,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); @@ -1475,7 +2037,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1485,7 +2046,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return rc; } @@ -1509,7 +2069,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -1525,9 +2084,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1546,7 +2102,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1554,9 +2109,7 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1567,21 +2120,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - rte_free(p_data_buff_ex); - return 0; + return rc; } static uint32_t @@ -1590,8 +2139,8 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_ uint32_t tbl_type = 0; uint32_t clutch_en = 0; - ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); @@ -1599,12 +2148,12 @@ zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_ switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info; + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; p_sdt_eram->table_type = tbl_type; p_sdt_eram->eram_clutch_en = clutch_en; break; case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; p_sdt_porttbl->table_type = tbl_type; p_sdt_porttbl->porttbl_clutch_en = clutch_en; break; @@ -1650,6 +2199,8 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, row_index = (index >> 7); col_index = index & 0x7F; break; + default: + break; } *p_row_index = row_index; *p_col_index = col_index; @@ -1661,7 +2212,7 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, { uint32_t index = p_dump_eram_entry->index; uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; uint32_t temp_data[4] = {0}; uint32_t row_index = 0; uint32_t col_index = 0; @@ -1685,6 +2236,8 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } return rc; } @@ -1727,10 +2280,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -1945,6 +2498,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, row_index = (index >> 7); col_index = index & 0x7F; break; + default: + break; } eram_dump_base_addr = base_addr + row_index; @@ -1967,6 +2522,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } return rc; @@ -2035,6 +2592,32 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +int +zxdh_np_host_init(uint32_t dev_id, + ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; + uint32_t rc; + uint64_t agent_addr; + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); + + sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); + sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, + p_dev_init_ctrl->np_bar_offset); + sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; + + rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); + + zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); + + agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; + zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + + return 0; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { @@ -2177,7 +2760,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, 0, &cpu_ind_cmd); - rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER, 0); + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); p_temp_data = temp_data; for (i = 0; i < 4; i++) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 7ff5c34c73..90847284fe 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -6,14 +6,16 @@ #define ZXDH_NP_H #include <stdint.h> +#include <rte_spinlock.h> +#define ZXDH_OK (0) +#define ZXDH_ERR (1) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) #define ZXDH_DEV_CHANNEL_MAX (2) #define ZXDH_DEV_SDT_ID_MAX (256U) -#define ZXDH_RD_CNT_MAX (128) /*DTB*/ #define ZXDH_DTB_QUEUE_ITEM_NUM_MAX (32) @@ -54,11 +56,23 @@ #define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9) #define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10) +#define ZXDH_REG_NUL_ARRAY (0 << 0) +#define ZXDH_REG_UNI_ARRAY (1 << 0) +#define ZXDH_REG_BIN_ARRAY (1 << 1) +#define ZXDH_REG_FLAG_INDIRECT (1 << 0) +#define ZXDH_REG_FLAG_DIRECT (0 << 0) +#define ZXDH_FIELD_FLAG_RO (1 << 0) +#define ZXDH_FIELD_FLAG_RW (1 << 1) + +#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000) +#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000) + #define ZXDH_ACL_TBL_ID_MIN (0) #define ZXDH_ACL_TBL_ID_MAX (7) #define ZXDH_ACL_TBL_ID_NUM (8U) #define ZXDH_ACL_BLOCK_NUM (8U) +#define ZXDH_RD_CNT_MAX (100) #define ZXDH_SMMU0_READ_REG_MAX_NUM (4) #define ZXDH_DTB_ITEM_ACK_SIZE (16) @@ -206,11 +220,15 @@ typedef enum zxdh_dev_type_e { } ZXDH_DEV_TYPE_E; typedef enum zxdh_reg_info_e { - ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0, - ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1, - ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2, - ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3, - ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0, + ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5, + ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6, + ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7, + ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0 = 9, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0 = 10, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0 = 11, @@ -218,6 +236,12 @@ typedef enum zxdh_reg_info_e { ZXDH_REG_ENUM_MAX_VALUE } ZXDH_REG_INFO_E; +typedef enum zxdh_dev_spinlock_type_e { + ZXDH_DEV_SPINLOCK_T_SMMU0 = 0, + ZXDH_DEV_SPINLOCK_T_DTB = 1, + ZXDH_DEV_SPINLOCK_T_MAX +} ZXDH_DEV_SPINLOCK_TYPE_E; + typedef enum zxdh_dev_access_type_e { ZXDH_DEV_ACCESS_TYPE_PCIE = 0, ZXDH_DEV_ACCESS_TYPE_RISCV = 1, @@ -237,6 +261,29 @@ typedef enum zxdh_acl_pri_mode_e { ZXDH_ACL_PRI_INVALID, } ZXDH_ACL_PRI_MODE_E; +typedef enum zxdh_module_e { + CFG = 1, + NPPU, + PPU, + ETM, + STAT, + CAR, + SE, + SMMU0 = SE, + SMMU1 = SE, + DTB, + TRPG, + TSN, + AXI, + PTPTM, + DTB4K, + STAT4K, + PPU4K, + SE4K, + SMMU14K, + MODULE_MAX +} ZXDH_MODULE_E; + typedef struct zxdh_d_node { void *data; struct zxdh_d_node *prev; @@ -301,6 +348,15 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef struct zxdh_spin_lock_t { + rte_spinlock_t spinlock; +} ZXDH_SPINLOCK_T; + +typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); +typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); + typedef struct zxdh_sys_init_ctrl_t { ZXDH_DEV_TYPE_E device_type; uint32_t flags; @@ -327,6 +383,8 @@ typedef struct dpp_dev_cfg_t { uint64_t dma_phy_addr; uint64_t agent_addr; uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; + ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; + ZXDH_DEV_READ_FUNC p_pcie_read_fun; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -521,7 +579,7 @@ typedef struct zxdh_sdt_tbl_eram_t { uint32_t eram_base_addr; uint32_t eram_table_depth; uint32_t eram_clutch_en; -} ZXDH_SDTTBL_ERAM_T; +} ZXDH_SDT_TBL_ERAM_T; typedef union zxdh_endian_u { unsigned int a; @@ -550,12 +608,6 @@ typedef struct zxdh_dtb_queue_item_info_t { uint32_t data_hddr; } ZXDH_DTB_QUEUE_ITEM_INFO_T; -typedef struct zxdh_dtb_queue_len_t { - uint32_t cfg_dtb_cmd_type; - uint32_t cfg_dtb_cmd_int_en; - uint32_t cfg_queue_dtb_len; -} ZXDH_DTB_QUEUE_LEN_T; - typedef struct zxdh_dtb_eram_entry_info_t { uint32_t index; uint32_t *p_data; @@ -582,12 +634,12 @@ typedef struct zxdh_sdt_tbl_etcam_t { uint32_t as_rsp_mode; uint32_t etcam_table_depth; uint32_t etcam_clutch_en; -} ZXDH_SDTTBL_ETCAM_T; +} ZXDH_SDT_TBL_ETCAM_T; typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; -} ZXDH_SDTTBL_PORTTBL_T; +} ZXDH_SDT_TBL_PORTTBL_T; typedef struct zxdh_dtb_hash_entry_info_t { uint8_t *p_actu_key; @@ -614,15 +666,6 @@ typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_addr; } ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; -typedef enum zxdh_smmu0_smmu0_type_e { - ZXDH_DEV_MUTEX_T_SMMU0 = 0, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 1, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, - ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER = 3, - ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 4, - ZXDH_SMMU0_SMMU0_ED_ARB_CPU_RDYR = 5, -} ZXDH_SEMMU0_SEMMU0_TYPE_E; - typedef enum zxdh_stat_rd_clr_mode_e { ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, ZXDH_STAT_RD_CLR_MODE_CLR = 1, @@ -635,8 +678,8 @@ typedef enum zxdh_eram128_rd_clr_mode_e { } ZXDH_ERAM128_RD_CLR_MODE_E; typedef enum zxdh_se_opr_mode_e { - ZXDH_SE_OPR_RD = 0, - ZXDH_SE_OPR_WR = 1, + ZXDH_SE_OPR_WR = 0, + ZXDH_SE_OPR_RD = 1, } ZXDH_SE_OPR_MODE_E; typedef enum zxdh_stat_car_type_e { -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 122439 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 00/14] net/zxdh: add network processor ops 2025-03-05 8:13 ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (13 more replies) 0 siblings, 14 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 1888 bytes --] v4: - change some tables to const. - use %u instead of %d. - delete cast of ret_zmalloc() return. - resolve code functionality issues. V3: - resolve code style. - resolve spin lock build issue. - rebase code baseline. - modify parameters of the plcr function. V2: - resolve code style and github-robot build issue. - eliminate commit warning. - remove unnecessary initialization, which first usage will set. - replace mutex lock with spinlock. V1: - updated network processor driver. - improve insert/delete/get table code funcs. Bingbin Chen (14): net/zxdh: add network processor registers ops net/zxdh: support compatibility check net/zxdh: add agent channel net/zxdh: modify dtb queue ops net/zxdh: add tables dump address ops net/zxdh: add eram tables ops net/zxdh: get flow tables resources net/zxdh: support hash resources configuration net/zxdh: implement tables initialization net/zxdh: support hash tables write and delete ops net/zxdh: get hash table entry result net/zxdh: delete all hash entries net/zxdh: add acl tables ops net/zxdh: fix debugging errors drivers/net/zxdh/zxdh_ethdev.c | 89 +- drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_ethdev_ops.c | 15 +- drivers/net/zxdh/zxdh_msg.c | 20 +- drivers/net/zxdh/zxdh_msg.h | 12 +- drivers/net/zxdh/zxdh_mtr.c | 8 +- drivers/net/zxdh/zxdh_np.c | 11631 +++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 1243 ++- drivers/net/zxdh/zxdh_pci.c | 24 +- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 11 +- drivers/net/zxdh/zxdh_tables.c | 42 +- drivers/net/zxdh/zxdh_tables.h | 68 +- 13 files changed, 11464 insertions(+), 1702 deletions(-) -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 3887 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v4 01/14] net/zxdh: add network processor registers ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 02/14] net/zxdh: support compatibility check Bingbin Chen ` (12 subsequent siblings) 13 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 100114 bytes --] Add (np)network processor registers read/write interfaces. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1877 ++++++++++++++++++++++++++---------- drivers/net/zxdh/zxdh_np.h | 226 +++-- 2 files changed, 1511 insertions(+), 592 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 28c9e4c1c1..1534cb2709 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -15,7 +15,6 @@ #include "zxdh_logs.h" #include "zxdh_msg.h" -static uint64_t g_np_bar_offset; static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; static uint32_t g_dpp_dtb_int_enable; @@ -23,32 +22,209 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_REG_T g_dpp_reg_info[4]; -static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 0, 1}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 63, 32}, + {"data_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag", 123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel", 123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr", 108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { + { + "ddr", + ZXDH_DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + ZXDH_DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + ZXDH_DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + ZXDH_DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + ZXDH_DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + ZXDH_DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + ZXDH_DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ + (((data_len) & 0x3ff) | \ + ((int_en) << 29) | \ + ((cmd_type) << 30)) -#define ZXDH_COMM_MASK_BIT(_bitnum_)\ - (0x1U << (_bitnum_)) +static inline uint32_t +zxdh_np_comm_mask_bit(uint32_t bitnum) { + return (uint32_t)(0x1U << bitnum); +} -#define ZXDH_COMM_GET_BIT_MASK(_inttype_, _bitqnt_)\ - ((_inttype_)(((_bitqnt_) < 32))) +static inline uint32_t +zxdh_np_comm_get_bit_mask(uint32_t bit_quantity) { + if (bit_quantity < 32) + return zxdh_np_comm_mask_bit(bit_quantity & 0x1F) - 1; + else + return 0xFFFFFFFF; +} #define ZXDH_COMM_UINT32_GET_BITS(_uidst_, _uisrc_, _uistartpos_, _uilen_)\ ((_uidst_) = (((_uisrc_) >> (_uistartpos_)) & \ - (ZXDH_COMM_GET_BIT_MASK(uint32_t, (_uilen_))))) + (zxdh_np_comm_get_bit_mask((_uilen_))))) #define ZXDH_REG_DATA_MAX (128) #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\ do {\ if (NULL == (point)) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "dev: %u [POINT NULL]", (dev_id));\ RTE_ASSERT(0);\ } \ } while (0) @@ -56,33 +232,22 @@ do {\ #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d !"\ - "-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "dev: %u, %s failed!", (dev_id), becall);\ RTE_ASSERT(0);\ } \ } while (0) -#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ - } \ -} while (0) - #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d !-- %s Call %s"\ - " Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ } \ } while (0) #define ZXDH_COMM_CHECK_RC(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d!-- %s Call %s "\ - "Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ RTE_ASSERT(0);\ } \ } while (0) @@ -90,34 +255,28 @@ do {\ #define ZXDH_COMM_CHECK_POINT(point)\ do {\ if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "[POINT NULL]");\ RTE_ASSERT(0);\ } \ } while (0) +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) +{ + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; +} -#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ - rte_free(ptr);\ - RTE_ASSERT(0);\ - } \ -} while (0) - -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ -do {\ - if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ - " %s Fail!", __FILE__, __LINE__, __func__, becall);\ - rte_free(ptr);\ - } \ -} while (0) +static inline uint32_t +zxdh_np_comm_convert32(uint32_t dw_data) +{ + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; +} #define ZXDH_COMM_CONVERT16(w_data) \ - (((w_data) & 0xff) << 8) + zxdh_np_comm_convert16(w_data) + +#define ZXDH_COMM_CONVERT32(w_data) \ + zxdh_np_comm_convert32(w_data) #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) @@ -132,10 +291,12 @@ do {\ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.data_len[(INDEX)]) #define ZXDH_DTB_TAB_UP_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) + (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.start_vir_addr + \ + (INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) #define ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.item_size) + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + \ + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size) #define ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.wr_index) @@ -143,7 +304,25 @@ do {\ #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) -ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"cara_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -155,7 +334,7 @@ ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carb_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carb_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -167,7 +346,7 @@ ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carc_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carc_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -179,10 +358,69 @@ ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { +static ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { {"pktrx_glbal_cfg_0", ZXDH_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, }; +static uint32_t zxdh_dtb_info_print(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + ZXDH_DTB_QUEUE_ITEM_INFO_T *item_info) +{ + uint64_t element_start_addr = 0; + uint64_t ack_start_addr = 0; + uint64_t data_addr = 0; + uint32_t data = 0; + uint32_t i = 0; + uint32_t j = 0; + + PMD_DRV_LOG(DEBUG, "queue: %u, element:%u, %s table info is:", + queue_id, item_index, (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "cmd_vld : %u", item_info->cmd_vld); + PMD_DRV_LOG(DEBUG, "cmd_type : %s", (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "int_en : %u", item_info->int_en); + PMD_DRV_LOG(DEBUG, "data_len : %u", item_info->data_len); + PMD_DRV_LOG(DEBUG, "data_hddr : 0x%x", item_info->data_hddr); + PMD_DRV_LOG(DEBUG, "data_laddr : 0x%x", item_info->data_laddr); + + if (item_info->cmd_type == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + ack_start_addr = + ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, item_index); + } + ack_start_addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index) + ZXDH_DTB_ITEM_ACK_SIZE; + } else { + ack_start_addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + } + PMD_DRV_LOG(DEBUG, "dtb data:"); + + PMD_DRV_LOG(DEBUG, "ack info:"); + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(ack_start_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + + for (i = 0; i < item_info->data_len; i++) { + data_addr = element_start_addr + 16 * i; + + PMD_DRV_LOG(DEBUG, "row_%u:", i); + + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(data_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + } + + PMD_DRV_LOG(DEBUG, "zxdh dtb info print end."); + return ZXDH_OK; +} + static uint32_t zxdh_np_comm_is_big_endian(void) { @@ -215,7 +453,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) uc_byte_mode = dw_byte_len % 4 & 0xff; for (i = 0; i < dw_byte_num; i++) { - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); p_dw_tmp++; } @@ -239,6 +477,392 @@ zxdh_np_dev_init(void) return 0; } +static uint32_t +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static void +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + data = *p_data; + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + *((volatile uint32_t *)addr) = data; +} + +static void +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + data = *((volatile uint32_t *)addr); + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *p_data = data; +} + +static uint64_t +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) + return ZXDH_DEV_TYPE_INVALID; + + return p_dev_info->pcie_addr; +} + +static void +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); +} + +static void +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); +} + +static uint32_t +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_write(dev_id, addr, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_read(dev_id, addr, p_data); +} + +static ZXDH_REG_T g_dpp_reg_info[] = { + { + .reg_name = "cpu_ind_cmd", + .reg_no = 669, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 4, + .p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rd_done", + .reg_no = 670, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat0", + .reg_no = 671, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat1", + .reg_no = 672, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat2", + .reg_no = 673, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat3", + .reg_no = 674, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "wr_arb_cpu_rdy", + .reg_no = 676, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "info_queue_buf_space_left_0_127", + .reg_no = 820, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 1, + .p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cfg_epid_v_func_num_0_127", + .reg_no = 821, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 7, + .p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cara_queue_ram0_159_0", + .reg_no = 721, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x000000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x7FFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_cara_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carb_queue_ram0_159_0", + .reg_no = 738, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x100000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0xFFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carb_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carc_queue_ram0_159_0", + .reg_no = 755, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x200000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x3FF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carc_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "pktrx_glbal_cfg_0", + .reg_no = 448, + .module_no = NPPU, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_NPPU_BASE_ADDR + ZXDH_MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, +}; + +static uint32_t +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) +{ + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = NULL; + + p_reg_info = &g_dpp_reg_info[reg_no]; + + addr = p_reg_info->addr; + + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { + if (n_offset > (p_reg_info->n_size - 1)) + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%u", reg_no); + + addr += n_offset * p_reg_info->n_step; + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + PMD_DRV_LOG(ERR, "reg n_offset/m_offset out of range, reg_no:%u", reg_no); + + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; + } + + return addr; +} + static uint32_t zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, @@ -262,7 +886,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, } else { /* device is new. */ p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } p_dev_mgr->p_dev_array[dev_id] = p_dev_info; p_dev_mgr->device_num++; } @@ -275,7 +902,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->dma_vir_addr = dma_vir_addr; p_dev_info->dma_phy_addr = dma_phy_addr; - return 0; + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + + return ZXDH_OK; } static uint32_t @@ -323,8 +953,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id) p_sdt_mgr->channel_num++; } else { - PMD_DRV_LOG(ERR, "Error: %s for dev[%d]" - "is called repeatedly!", __func__, dev_id); + PMD_DRV_LOG(ERR, "called repeatedly!"); return 1; } @@ -367,6 +996,61 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret); + } + + rte_free(recv_buffer); + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -376,6 +1060,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) return p_dpp_dtb_mgr[dev_id]; } +static uint32_t +zxdh_np_dtb_mgr_create(uint32_t dev_id) +{ + if (p_dpp_dtb_mgr[dev_id] != NULL) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); + return ZXDH_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + if (p_dpp_dtb_mgr[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dtb_soft_init(uint32_t dev_id) { @@ -386,10 +1088,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id) p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) { - p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + zxdh_np_dtb_mgr_create(dev_id); + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) - return 1; + return ZXDH_RC_DTB_MGR_NOT_EXIST; } return 0; @@ -469,36 +1172,9 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE) ? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0; - g_np_bar_offset = bar_offset; - return np_addr; } -int -zxdh_np_host_init(uint32_t dev_id, - ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) -{ - ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; - uint32_t rc; - uint64_t agent_addr; - - ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); - - sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); - sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, - p_dev_init_ctrl->np_bar_offset); - sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; - rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); - - zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); - - agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; - zxdh_np_dev_agent_addr_set(dev_id, agent_addr); - - return 0; -} - static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -611,24 +1287,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t rc = 0; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - for (i = 0; i < p_reg_info->field_num; i++) { - rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - (uint32_t *)p_data + i, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]); + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); } } + + for (i = 0; i < p_reg_info->field_num; i++) { + rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + (uint32_t *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex"); + PMD_DRV_LOG(DEBUG, "dev_id %u(%u)(%u)is ok!", dev_id, m_offset, n_offset); + } + return rc; } @@ -637,20 +1326,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info) { - ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; - uint32_t rc; + uint32_t rc = 0; + uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010; + uint32_t epid_v_func = 0; - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM, - 0, queue_id, &vm_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read"); + rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel"); - p_vm_info->dbi_en = vm_info.dbi_en; - p_vm_info->queue_en = vm_info.queue_en; - p_vm_info->epid = vm_info.cfg_epid; - p_vm_info->vector = vm_info.cfg_vector; - p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; - p_vm_info->func_num = vm_info.cfg_func_num; - p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1); + p_vm_info->queue_en = (epid_v_func >> 30 & 0x1); + p_vm_info->epid = (epid_v_func >> 24 & 0xF); + p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF); + p_vm_info->vector = (epid_v_func >> 8 & 0x7); + p_vm_info->func_num = (epid_v_func >> 5 & 0x7); + p_vm_info->vfunc_active = (epid_v_func & 0x1); return rc; } @@ -733,32 +1423,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t temp_data; - uint32_t rc; + uint32_t rc = ZXDH_OK; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + for (i = 0; i < p_reg_info->field_num; i++) { + if (p_field_info[i].len <= 32) { + temp_data = *((uint32_t *)p_data + i) & + zxdh_np_comm_get_bit_mask(p_field_info[i].len); + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); + } + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - - for (i = 0; i < p_reg_info->field_num; i++) { - if (p_field_info[i].len <= 32) { - temp_data = *((uint32_t *)p_data + i); - rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - temp_data, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", - dev_id, m_offset, n_offset); - } + PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]); + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); + + PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.", + p_buff[i]); } } - return 0; + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + PMD_DRV_LOG(DEBUG, "reg_no = %u. m_offset = %u n_offset = %u", + reg_no, m_offset, n_offset); + PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } + + return rc; } static uint32_t @@ -837,11 +1545,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, { uint32_t rc; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) { - *p_item_num = 32; - return 0; - } - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE, 0, queue_id, p_item_num); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); @@ -874,7 +1577,7 @@ zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_DEV_POINT(devid, pname); @@ -891,20 +1594,11 @@ static void zxdh_np_dtb_mgr_destroy(uint32_t dev_id) { if (p_dpp_dtb_mgr[dev_id] != NULL) { - free(p_dpp_dtb_mgr[dev_id]); + rte_free(p_dpp_dtb_mgr[dev_id]); p_dpp_dtb_mgr[dev_id] = NULL; } } -static void -zxdh_np_tlb_mgr_destroy(uint32_t dev_id) -{ - if (g_p_dpp_tlb_mgr[dev_id] != NULL) { - free(g_p_dpp_tlb_mgr[dev_id]); - g_p_dpp_tlb_mgr[dev_id] = NULL; - } -} - static void zxdh_np_sdt_mgr_destroy(uint32_t dev_id) { @@ -914,7 +1608,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id) p_sdt_tbl_temp = ZXDH_SDT_SOFT_TBL_GET(dev_id); p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET(); - free(p_sdt_tbl_temp); + rte_free(p_sdt_tbl_temp); ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL; @@ -931,7 +1625,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { - free(p_dev_info); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; } @@ -946,11 +1640,9 @@ zxdh_np_online_uninit(uint32_t dev_id, rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id); if (rc != 0) - PMD_DRV_LOG(ERR, "%s:dtb release error," - "port name %s queue id %d", __func__, port_name, queue_id); + PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); zxdh_np_dtb_mgr_destroy(dev_id); - zxdh_np_tlb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -964,8 +1656,8 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no) } -static ZXDH_DTB_TABLE_T * -zxdh_np_table_info_get(uint32_t table_type) +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_table_info_get(uint32_t table_type) { return &g_dpp_dtb_table_info[table_type]; } @@ -977,20 +1669,20 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, void *p_cmd_buff) { uint32_t field_cnt; - ZXDH_DTB_TABLE_T *p_table_info = NULL; - ZXDH_DTB_FIELD_T *p_field_info = NULL; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; uint32_t temp_data; uint32_t rc = 0; ZXDH_COMM_CHECK_POINT(p_cmd_data); ZXDH_COMM_CHECK_POINT(p_cmd_buff); - p_table_info = zxdh_np_table_info_get(table_type); + p_table_info = zxdh_np_dtb_table_info_get(table_type); p_field_info = p_table_info->p_fields; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { - temp_data = *((uint32_t *)p_cmd_data + field_cnt) & ZXDH_COMM_GET_BIT_MASK(uint32_t, - p_field_info[field_cnt].len); + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, ZXDH_DTB_TABLE_CMD_SIZE_BIT, @@ -998,7 +1690,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, p_field_info[field_cnt].lsb_pos, p_field_info[field_cnt].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex"); } return rc; @@ -1062,17 +1754,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc = 0; switch (wrt_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]" - "INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__, - base_addr, index, __func__); - + PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { @@ -1095,11 +1784,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, } temp_idx = index; + break; + default: + break; } dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx; - PMD_DRV_LOG(INFO, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); + PMD_DRV_LOG(DEBUG, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); rc = zxdh_np_dtb_smmu0_write_entry_data(dev_id, wrt_mode, @@ -1131,6 +1823,126 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + uint32_t tmp = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32, + ZXDH_SDT_H_ERAM_MODE_BT_POS, ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + p_sdt_eram->eram_clutch_en = clutch_en; + break; + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + p_sdt_hash->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32, + ZXDH_SDT_H_HASH_ID_BT_POS, ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32, + ZXDH_SDT_H_LEARN_EN_BT_POS, ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + p_sdt_hash->keep_alive_baddr += (tmp << ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32, + ZXDH_SDT_L_RSP_MODE_BT_POS, ZXDH_SDT_L_RSP_MODE_BT_LEN); + p_sdt_hash->hash_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + p_sdt_etcam->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_ID_BT_POS, ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + p_sdt_etcam->as_eram_baddr += (tmp << ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + p_sdt_etcam->etcam_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %u ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%u] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -1140,17 +1952,21 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_DTB_ENTRY_T *p_dtb_one_entry) { uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0}; - ZXDH_SDTTBL_ERAM_T sdt_eram = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram = {0}; ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL; uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -1166,8 +1982,19 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, case ZXDH_ERAM128_TBL_1b: opr_mode = ZXDH_ERAM128_OPR_1b; break; + default: + break; } + PMD_DRV_LOG(DEBUG, "std no:0x%x, index:0x%x, base addr:0x%x", sdt_no, index, base_addr); + if (opr_mode == ZXDH_ERAM128_OPR_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1], + peramdata->p_data[2], peramdata->p_data[3]); + else if (opr_mode == ZXDH_ERAM128_OPR_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1]); + if (del_en) { memset((uint8_t *)buff, 0, sizeof(buff)); rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, @@ -1274,6 +2101,9 @@ zxdh_np_dtb_item_ack_rd(uint32_t dev_id, val = *((volatile uint32_t *)(addr)); + if (!zxdh_np_comm_is_big_endian()) + val = ZXDH_COMM_CONVERT32(val); + *p_data = val; return 0; @@ -1294,7 +2124,10 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, else addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; - *((volatile uint32_t *)(addr)) = data; + if (!zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *((volatile uint32_t *)addr) = data; return 0; } @@ -1304,16 +2137,26 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info) { - ZXDH_DTB_QUEUE_LEN_T dtb_len = {0}; uint32_t rc; - dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; - dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; - dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000; + uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004; + uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008; + uint32_t dtb_len = 0; + + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32, + 1, &p_item_info->data_hddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32, + 1, &p_item_info->data_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len); + rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); - rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN, - 0, queue_id, (void *)&dtb_len); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); return rc; } @@ -1335,7 +2178,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t rc; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1344,7 +2187,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } @@ -1383,6 +2226,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, item_info.data_hddr = ((phy_addr >> 4) >> 32) & 0xffffffff; item_info.data_laddr = (phy_addr >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); + rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; @@ -1421,7 +2266,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff; - uint8_t *p_data_buff_ex; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -1435,9 +2279,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1446,6 +2287,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, for (entry_index = 0; entry_index < entrynum; entry_index++) { pentry = down_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: @@ -1453,9 +2295,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1463,9 +2304,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); @@ -1475,7 +2314,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1485,18 +2323,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return rc; } -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; -} - int zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint32_t queue_id, @@ -1509,7 +2339,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -1525,9 +2354,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1537,16 +2363,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, pentry = delete_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1554,9 +2381,7 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1567,158 +2392,43 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - - rte_free(p_data_buff_ex); - return 0; -} - -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) -{ - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); - - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; - break; - case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; - - switch (eram_mode) { - case ZXDH_ERAM128_TBL_128b: - row_index = index; - break; - case ZXDH_ERAM128_TBL_64b: - row_index = (index >> 1); - col_index = index & 0x1; - break; - case ZXDH_ERAM128_TBL_1b: - row_index = (index >> 7); - col_index = index & 0x7F; - break; - } - *p_row_index = row_index; - *p_col_index = col_index; -} -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - memcpy(p_data, temp_data, (128 / 8)); - break; - case ZXDH_ERAM128_TBL_64b: - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - case ZXDH_ERAM128_TBL_1b: - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - } return rc; } - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc = 0; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) +{ + uint32_t row_index = 0; + uint32_t col_index = 0; + + switch (eram_mode) { + case ZXDH_ERAM128_TBL_128b: + row_index = index; + break; + case ZXDH_ERAM128_TBL_64b: + row_index = (index >> 1); + col_index = index & 0x1; + break; + case ZXDH_ERAM128_TBL_1b: + row_index = (index >> 7); + col_index = index & 0x7F; break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; + break; } - - return 0; + *p_row_index = row_index; + *p_col_index = col_index; } static void @@ -1727,10 +2437,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -1748,12 +2458,12 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1769,6 +2479,11 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.cmd_type = ZXDH_DTB_DIR_UP_TYPE; item_info.int_en = int_flag; item_info.data_len = desc_len / 4; + item_info.data_hddr = + ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) >> 32) & 0xffffffff; + item_info.data_laddr = + (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) return 0; @@ -1778,6 +2493,33 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -1799,8 +2541,8 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, desc_len, p_dump_info); if (rc != 0) { - PMD_DRV_LOG(ERR, "the queue %d element id %d dump" - " info set failed!", queue_id, queue_element_id); + PMD_DRV_LOG(ERR, "queue %u element %u dump info set failed!", + queue_id, queue_element_id); zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } @@ -1819,7 +2561,7 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t i; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1849,37 +2591,9 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, *p_item_index = item_index; - return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -1898,7 +2612,7 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); if (rc != 0) { - PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %d!", base_addr); + PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %u!", base_addr); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; } @@ -1918,6 +2632,103 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + eram_base_addr = sdt_eram_info.eram_base_addr; + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_data, temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_TBL_64b: + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + + PMD_DRV_LOG(DEBUG, "[eram_dump]std no:0x%x, index:0x%x, base addr:0x%x", + sdt_no, p_dump_eram_entry->index, eram_dump_base_addr); + if (rd_mode == ZXDH_ERAM128_TBL_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1], + p_dump_eram_entry->p_data[2], p_dump_eram_entry->p_data[3]); + else if (rd_mode == ZXDH_ERAM128_TBL_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1]); + + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, @@ -1945,6 +2756,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, row_index = (index >> 7); col_index = index & 0x7F; break; + default: + break; } eram_dump_base_addr = base_addr + row_index; @@ -1967,6 +2780,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } return rc; @@ -2035,6 +2850,32 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +int +zxdh_np_host_init(uint32_t dev_id, + ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; + uint32_t rc; + uint64_t agent_addr; + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); + + sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); + sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, + p_dev_init_ctrl->np_bar_offset); + sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; + + rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); + + zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); + + agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; + zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + + return 0; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { @@ -2047,7 +2888,7 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) while (!done_flag) { rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read Fail!", rc); + PMD_DRV_LOG(ERR, "reg_read fail!"); return rc; } @@ -2073,7 +2914,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t rd_clr_mode, uint32_t *p_data) { - uint32_t rc = 0; + uint32_t rc = ZXDH_OK; uint32_t i = 0; uint32_t row_index = 0; uint32_t col_index = 0; @@ -2082,6 +2923,10 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; @@ -2090,42 +2935,42 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - if ((0xFFFFFFFF - (base_addr)) < (index)) + if ((0xFFFFFFFF - (base_addr)) < (index)) { + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; - + } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x1; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x3; break; case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x7F; break; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; @@ -2136,56 +2981,69 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 7); cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6); cpu_ind_cmd.cpu_req_mode = 2; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 5); cpu_ind_cmd.cpu_req_mode = 1; break; case ZXDH_ERAM128_OPR_1b: - PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ", - rd_clr_mode, rd_mode); - return -1; + PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", + rd_clr_mode, rd_mode); + return ZXDH_ERR; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; } rc = zxdh_np_reg_write(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, - 0, - 0, - &cpu_ind_cmd); + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } - rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER, 0); + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } p_temp_data = temp_data; for (i = 0; i < 4; i++) { rc = zxdh_np_reg_read(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, - 0, - 0, - p_temp_data + 3 - i); + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { @@ -2203,6 +3061,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } } else { switch (rd_mode) { @@ -2215,6 +3075,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: memcpy(p_data, p_temp_data, (64 / 8)); break; + default: + break; } } @@ -2266,70 +3128,18 @@ zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, } static uint32_t -zxdh_np_agent_channel_sync_send(ZXDH_AGENT_CHANNEL_MSG_T *p_msg, - uint32_t *p_data, - uint32_t rep_len) -{ - uint32_t ret = 0; - uint32_t vport = 0; - struct zxdh_pci_bar_msg in = {0}; - struct zxdh_msg_recviver_mem result = {0}; - uint32_t *recv_buffer; - uint8_t *reply_ptr = NULL; - uint16_t reply_msg_len = 0; - uint64_t agent_addr = 0; - - if (ZXDH_IS_PF(vport)) - in.src = ZXDH_MSG_CHAN_END_PF; - else - in.src = ZXDH_MSG_CHAN_END_VF; - - in.virt_addr = agent_addr; - in.payload_addr = p_msg->msg; - in.payload_len = p_msg->msg_len; - in.dst = ZXDH_MSG_CHAN_END_RISC; - in.module_id = ZXDH_BAR_MDOULE_NPSDK; - - recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); - if (recv_buffer == NULL) { - PMD_DRV_LOG(ERR, "%s point null!", __func__); - return ZXDH_PAR_CHK_POINT_NULL; - } - - result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; - result.recv_buffer = recv_buffer; - - ret = zxdh_bar_chan_sync_msg_send(&in, &result); - if (ret == ZXDH_BAR_MSG_OK) { - reply_ptr = (uint8_t *)(result.recv_buffer); - if (*reply_ptr == 0XFF) { - reply_msg_len = *(uint16_t *)(reply_ptr + 1); - memcpy(p_data, reply_ptr + 4, - ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); - } else { - PMD_DRV_LOG(ERR, "Message not replied"); - } - } else { - PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__); - } - - rte_free(recv_buffer); - return ret; -} - -static uint32_t -zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, +zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) { uint32_t ret = 0; - ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), + }; - agent_msg.msg = (void *)p_msg; - agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T); - - ret = zxdh_np_agent_channel_sync_send(&agent_msg, p_data, rep_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_sync_send failed."); return 1; } @@ -2337,25 +3147,25 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport, uint32_t car_type, uint32_t *p_profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_REQUEST; - msgcfg.vport = vport; - msgcfg.car_type = car_type; - msgcfg.profile_id = 0xFFFF; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_REQUEST, + .vport = vport, + .car_type = car_type, + .profile_id = 0xFFFF, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2365,7 +3175,8 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, } static uint32_t -zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, +zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, + uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id __rte_unused, void *p_car_profile_cfg) @@ -2395,9 +3206,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgpktcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_a_type failed."); return 1; } @@ -2429,9 +3240,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_b_type failed."); return 1; } @@ -2442,25 +3253,25 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport, uint32_t car_type __rte_unused, uint32_t profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_RELEASE; - msgcfg.vport = vport; - msgcfg.profile_id = profileid; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_RELEASE, + .vport = vport, + .profile_id = profileid, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2478,11 +3289,12 @@ zxdh_np_stat_cara_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { + .cara_drop = drop_flag, + .cara_plcr_en = plcr_en, + .cara_profile_id = profile_id, + }; - queue_cfg.cara_drop = drop_flag; - queue_cfg.cara_plcr_en = plcr_en; - queue_cfg.cara_profile_id = profile_id; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0, 0, @@ -2502,11 +3314,11 @@ zxdh_np_stat_carb_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; - - queue_cfg.carb_drop = drop_flag; - queue_cfg.carb_plcr_en = plcr_en; - queue_cfg.carb_profile_id = profile_id; + ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { + .carb_drop = drop_flag, + .carb_plcr_en = plcr_en, + .carb_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0, @@ -2527,10 +3339,11 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; - queue_cfg.carc_drop = drop_flag; - queue_cfg.carc_plcr_en = plcr_en; - queue_cfg.carc_profile_id = profile_id; + ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { + .carc_drop = drop_flag, + .carc_plcr_en = plcr_en, + .carc_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0, @@ -2553,12 +3366,12 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, uint32_t profile_id_l = 0; uint64_t temp_profile_id = 0; - profile_id = (uint32_t *)rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); + profile_id = rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); if (profile_id == NULL) { - PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__); + PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -2566,7 +3379,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, temp_profile_id = (((uint64_t)profile_id_l) << 32) | ((uint64_t)profile_id_h); if (0 != (uint32_t)(temp_profile_id >> 56)) { - PMD_DRV_LOG(ERR, "%s: profile_id is overflow!", __func__); + PMD_DRV_LOG(ERR, "profile_id is overflow!"); return 1; } @@ -2583,11 +3396,12 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, void *p_car_profile_cfg) { uint32_t ret = 0; + uint32_t dev_id = 0; - ret = zxdh_np_agent_channel_plcr_car_rate(car_type, + ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__); + PMD_DRV_LOG(ERR, "plcr_car_rate set failed!"); return 1; } @@ -2599,13 +3413,12 @@ zxdh_np_car_profile_id_delete(uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t profileid = 0; - - profileid = profile_id & 0xFFFF; + uint32_t dev_id = 0; + uint32_t profileid = profile_id & 0xFFFF; - ret = zxdh_np_agent_channel_plcr_profileid_release(vport_id, flags, profileid); + ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__); + PMD_DRV_LOG(ERR, "plcr profiled id release failed!"); return 1; } @@ -2624,32 +3437,32 @@ zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, if (car_type == ZXDH_STAT_CAR_A_TYPE) { if (flow_id > ZXDH_CAR_A_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_A_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else if (car_type == ZXDH_STAT_CAR_B_TYPE) { if (flow_id > ZXDH_CAR_B_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_B_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else { if (flow_id > ZXDH_CAR_C_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_C_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 7ff5c34c73..6d2c7aa976 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -6,14 +6,16 @@ #define ZXDH_NP_H #include <stdint.h> +#include <rte_spinlock.h> +#define ZXDH_OK (0) +#define ZXDH_ERR (1) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) #define ZXDH_DEV_CHANNEL_MAX (2) #define ZXDH_DEV_SDT_ID_MAX (256U) -#define ZXDH_RD_CNT_MAX (128) /*DTB*/ #define ZXDH_DTB_QUEUE_ITEM_NUM_MAX (32) @@ -54,11 +56,23 @@ #define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9) #define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10) +#define ZXDH_REG_NUL_ARRAY (0 << 0) +#define ZXDH_REG_UNI_ARRAY (1 << 0) +#define ZXDH_REG_BIN_ARRAY (1 << 1) +#define ZXDH_REG_FLAG_INDIRECT (1 << 0) +#define ZXDH_REG_FLAG_DIRECT (0 << 0) +#define ZXDH_FIELD_FLAG_RO (1 << 0) +#define ZXDH_FIELD_FLAG_RW (1 << 1) + +#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000) +#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000) + #define ZXDH_ACL_TBL_ID_MIN (0) #define ZXDH_ACL_TBL_ID_MAX (7) #define ZXDH_ACL_TBL_ID_NUM (8U) #define ZXDH_ACL_BLOCK_NUM (8U) +#define ZXDH_RD_CNT_MAX (100) #define ZXDH_SMMU0_READ_REG_MAX_NUM (4) #define ZXDH_DTB_ITEM_ACK_SIZE (16) @@ -98,6 +112,57 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -206,11 +271,15 @@ typedef enum zxdh_dev_type_e { } ZXDH_DEV_TYPE_E; typedef enum zxdh_reg_info_e { - ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0, - ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1, - ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2, - ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3, - ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0, + ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5, + ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6, + ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7, + ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0 = 9, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0 = 10, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0 = 11, @@ -218,6 +287,12 @@ typedef enum zxdh_reg_info_e { ZXDH_REG_ENUM_MAX_VALUE } ZXDH_REG_INFO_E; +typedef enum zxdh_dev_spinlock_type_e { + ZXDH_DEV_SPINLOCK_T_SMMU0 = 0, + ZXDH_DEV_SPINLOCK_T_DTB = 1, + ZXDH_DEV_SPINLOCK_T_MAX +} ZXDH_DEV_SPINLOCK_TYPE_E; + typedef enum zxdh_dev_access_type_e { ZXDH_DEV_ACCESS_TYPE_PCIE = 0, ZXDH_DEV_ACCESS_TYPE_RISCV = 1, @@ -237,6 +312,29 @@ typedef enum zxdh_acl_pri_mode_e { ZXDH_ACL_PRI_INVALID, } ZXDH_ACL_PRI_MODE_E; +typedef enum zxdh_module_e { + CFG = 1, + NPPU, + PPU, + ETM, + STAT, + CAR, + SE, + SMMU0 = SE, + SMMU1 = SE, + DTB, + TRPG, + TSN, + AXI, + PTPTM, + DTB4K, + STAT4K, + PPU4K, + SE4K, + SMMU14K, + MODULE_MAX +} ZXDH_MODULE_E; + typedef struct zxdh_d_node { void *data; struct zxdh_d_node *prev; @@ -301,6 +399,49 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef struct zxdh_spin_lock_t { + rte_spinlock_t spinlock; +} ZXDH_SPINLOCK_T; + +typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); +typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); + typedef struct zxdh_sys_init_ctrl_t { ZXDH_DEV_TYPE_E device_type; uint32_t flags; @@ -327,6 +468,8 @@ typedef struct dpp_dev_cfg_t { uint64_t dma_phy_addr; uint64_t agent_addr; uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; + ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; + ZXDH_DEV_READ_FUNC p_pcie_read_fun; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -338,8 +481,8 @@ typedef struct zxdh_dev_mngr_t { typedef struct zxdh_dtb_addr_info_t { uint32_t sdt_no; uint32_t size; - uint32_t phy_addr; - uint32_t vir_addr; + uint64_t phy_addr; + uint64_t vir_addr; } ZXDH_DTB_ADDR_INFO_T; typedef struct zxdh_dev_init_ctrl_t { @@ -349,12 +492,12 @@ typedef struct zxdh_dev_init_ctrl_t { uint32_t queue_id; uint32_t np_bar_offset; uint32_t np_bar_len; - uint32_t pcie_vir_addr; - uint32_t down_phy_addr; - uint32_t down_vir_addr; - uint32_t dump_phy_addr; - uint32_t dump_vir_addr; - uint32_t dump_sdt_num; + uint64_t pcie_vir_addr; + uint64_t down_phy_addr; + uint64_t down_vir_addr; + uint64_t dump_phy_addr; + uint64_t dump_vir_addr; + uint64_t dump_sdt_num; ZXDH_DTB_ADDR_INFO_T dump_addr_info[]; } ZXDH_DEV_INIT_CTRL_T; @@ -424,7 +567,7 @@ typedef struct zxdh_reg_t { uint32_t m_step; uint32_t n_step; uint32_t field_num; - ZXDH_FIELD_T *p_fields; + const ZXDH_FIELD_T *p_fields; ZXDH_REG_WRITE p_write_fun; ZXDH_REG_READ p_read_fun; @@ -515,14 +658,6 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDTTBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -538,7 +673,7 @@ typedef struct zxdh_dtb_table_t { const char *table_type; uint32_t table_no; uint32_t field_num; - ZXDH_DTB_FIELD_T *p_fields; + const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; typedef struct zxdh_dtb_queue_item_info_t { @@ -550,12 +685,6 @@ typedef struct zxdh_dtb_queue_item_info_t { uint32_t data_hddr; } ZXDH_DTB_QUEUE_ITEM_INFO_T; -typedef struct zxdh_dtb_queue_len_t { - uint32_t cfg_dtb_cmd_type; - uint32_t cfg_dtb_cmd_int_en; - uint32_t cfg_queue_dtb_len; -} ZXDH_DTB_QUEUE_LEN_T; - typedef struct zxdh_dtb_eram_entry_info_t { uint32_t index; uint32_t *p_data; @@ -571,23 +700,10 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDTTBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; -} ZXDH_SDTTBL_PORTTBL_T; +} ZXDH_SDT_TBL_PORTTBL_T; typedef struct zxdh_dtb_hash_entry_info_t { uint8_t *p_actu_key; @@ -614,15 +730,6 @@ typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_addr; } ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; -typedef enum zxdh_smmu0_smmu0_type_e { - ZXDH_DEV_MUTEX_T_SMMU0 = 0, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 1, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, - ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER = 3, - ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 4, - ZXDH_SMMU0_SMMU0_ED_ARB_CPU_RDYR = 5, -} ZXDH_SEMMU0_SEMMU0_TYPE_E; - typedef enum zxdh_stat_rd_clr_mode_e { ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, ZXDH_STAT_RD_CLR_MODE_CLR = 1, @@ -635,8 +742,8 @@ typedef enum zxdh_eram128_rd_clr_mode_e { } ZXDH_ERAM128_RD_CLR_MODE_E; typedef enum zxdh_se_opr_mode_e { - ZXDH_SE_OPR_RD = 0, - ZXDH_SE_OPR_WR = 1, + ZXDH_SE_OPR_WR = 0, + ZXDH_SE_OPR_RD = 1, } ZXDH_SE_OPR_MODE_E; typedef enum zxdh_stat_car_type_e { @@ -730,11 +837,6 @@ typedef struct dpp_agent_car_pkt_profile_msg { uint32_t pri[ZXDH_CAR_PRI_MAX]; } ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T; -typedef struct zxdh_agent_channel_msg_t { - uint32_t msg_len; - void *msg; -} ZXDH_AGENT_CHANNEL_MSG_T; - typedef struct zxdh_agent_channel_plcr_msg { uint8_t dev_id; uint8_t type; @@ -803,6 +905,10 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 244256 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 00/14] net/zxdh: add network processor ops 2025-03-17 14:57 ` [PATCH v4 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (15 more replies) 0 siblings, 16 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 2084 bytes --] v5: - the VF read/write table function is fixed. v4: - change some tables to const. - use %u instead of %d. - delete cast of ret_zmalloc() return. - resolve code functionality issues. V3: - resolve code style. - resolve spin lock build issue. - rebase code baseline. - modify parameters of the plcr function. V2: - resolve code style and github-robot build issue. - eliminate commit warning. - remove unnecessary initialization, which first usage will set. - replace mutex lock with spinlock. V1: - updated network processor driver. - improve insert/delete/get table code funcs. Bingbin Chen (14): net/zxdh: add network processor registers ops net/zxdh: support compatibility check net/zxdh: add agent channel net/zxdh: modify dtb queue ops net/zxdh: add tables dump address ops net/zxdh: add eram tables ops net/zxdh: get flow tables resources net/zxdh: support hash resources configuration net/zxdh: implement tables initialization net/zxdh: support hash tables write and delete ops net/zxdh: get hash table entry result net/zxdh: delete all hash entries net/zxdh: add acl tables ops net/zxdh: fix debugging errors drivers/net/zxdh/zxdh_common.h | 99 + drivers/net/zxdh/zxdh_ethdev.c | 89 +- drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +- drivers/net/zxdh/zxdh_ethdev_ops.h | 35 + drivers/net/zxdh/zxdh_msg.c | 381 +- drivers/net/zxdh/zxdh_msg.h | 99 +- drivers/net/zxdh/zxdh_mtr.c | 50 +- drivers/net/zxdh/zxdh_mtr.h | 5 + drivers/net/zxdh/zxdh_np.c | 11631 +++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 1243 ++- drivers/net/zxdh/zxdh_pci.c | 24 +- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 12 +- drivers/net/zxdh/zxdh_tables.c | 42 +- drivers/net/zxdh/zxdh_tables.h | 68 +- 16 files changed, 11970 insertions(+), 1920 deletions(-) -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 4303 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v5 01/14] net/zxdh: add network processor registers ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 02/14] net/zxdh: support compatibility check Bingbin Chen ` (14 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 100114 bytes --] Add (np)network processor registers read/write interfaces. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1877 ++++++++++++++++++++++++++---------- drivers/net/zxdh/zxdh_np.h | 226 +++-- 2 files changed, 1511 insertions(+), 592 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 28c9e4c1c1..1534cb2709 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -15,7 +15,6 @@ #include "zxdh_logs.h" #include "zxdh_msg.h" -static uint64_t g_np_bar_offset; static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; static uint32_t g_dpp_dtb_int_enable; @@ -23,32 +22,209 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_REG_T g_dpp_reg_info[4]; -static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 0, 1}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 63, 32}, + {"data_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag", 123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel", 123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr", 108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { + { + "ddr", + ZXDH_DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + ZXDH_DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + ZXDH_DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + ZXDH_DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + ZXDH_DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + ZXDH_DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + ZXDH_DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ + (((data_len) & 0x3ff) | \ + ((int_en) << 29) | \ + ((cmd_type) << 30)) -#define ZXDH_COMM_MASK_BIT(_bitnum_)\ - (0x1U << (_bitnum_)) +static inline uint32_t +zxdh_np_comm_mask_bit(uint32_t bitnum) { + return (uint32_t)(0x1U << bitnum); +} -#define ZXDH_COMM_GET_BIT_MASK(_inttype_, _bitqnt_)\ - ((_inttype_)(((_bitqnt_) < 32))) +static inline uint32_t +zxdh_np_comm_get_bit_mask(uint32_t bit_quantity) { + if (bit_quantity < 32) + return zxdh_np_comm_mask_bit(bit_quantity & 0x1F) - 1; + else + return 0xFFFFFFFF; +} #define ZXDH_COMM_UINT32_GET_BITS(_uidst_, _uisrc_, _uistartpos_, _uilen_)\ ((_uidst_) = (((_uisrc_) >> (_uistartpos_)) & \ - (ZXDH_COMM_GET_BIT_MASK(uint32_t, (_uilen_))))) + (zxdh_np_comm_get_bit_mask((_uilen_))))) #define ZXDH_REG_DATA_MAX (128) #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\ do {\ if (NULL == (point)) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "dev: %u [POINT NULL]", (dev_id));\ RTE_ASSERT(0);\ } \ } while (0) @@ -56,33 +232,22 @@ do {\ #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d !"\ - "-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "dev: %u, %s failed!", (dev_id), becall);\ RTE_ASSERT(0);\ } \ } while (0) -#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ - } \ -} while (0) - #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d !-- %s Call %s"\ - " Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ } \ } while (0) #define ZXDH_COMM_CHECK_RC(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d!-- %s Call %s "\ - "Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ RTE_ASSERT(0);\ } \ } while (0) @@ -90,34 +255,28 @@ do {\ #define ZXDH_COMM_CHECK_POINT(point)\ do {\ if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "[POINT NULL]");\ RTE_ASSERT(0);\ } \ } while (0) +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) +{ + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; +} -#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ - rte_free(ptr);\ - RTE_ASSERT(0);\ - } \ -} while (0) - -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ -do {\ - if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ - " %s Fail!", __FILE__, __LINE__, __func__, becall);\ - rte_free(ptr);\ - } \ -} while (0) +static inline uint32_t +zxdh_np_comm_convert32(uint32_t dw_data) +{ + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; +} #define ZXDH_COMM_CONVERT16(w_data) \ - (((w_data) & 0xff) << 8) + zxdh_np_comm_convert16(w_data) + +#define ZXDH_COMM_CONVERT32(w_data) \ + zxdh_np_comm_convert32(w_data) #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) @@ -132,10 +291,12 @@ do {\ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.data_len[(INDEX)]) #define ZXDH_DTB_TAB_UP_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) + (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.start_vir_addr + \ + (INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) #define ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.item_size) + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + \ + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size) #define ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.wr_index) @@ -143,7 +304,25 @@ do {\ #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) -ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"cara_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -155,7 +334,7 @@ ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carb_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carb_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -167,7 +346,7 @@ ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carc_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carc_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -179,10 +358,69 @@ ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { +static ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { {"pktrx_glbal_cfg_0", ZXDH_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, }; +static uint32_t zxdh_dtb_info_print(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + ZXDH_DTB_QUEUE_ITEM_INFO_T *item_info) +{ + uint64_t element_start_addr = 0; + uint64_t ack_start_addr = 0; + uint64_t data_addr = 0; + uint32_t data = 0; + uint32_t i = 0; + uint32_t j = 0; + + PMD_DRV_LOG(DEBUG, "queue: %u, element:%u, %s table info is:", + queue_id, item_index, (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "cmd_vld : %u", item_info->cmd_vld); + PMD_DRV_LOG(DEBUG, "cmd_type : %s", (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "int_en : %u", item_info->int_en); + PMD_DRV_LOG(DEBUG, "data_len : %u", item_info->data_len); + PMD_DRV_LOG(DEBUG, "data_hddr : 0x%x", item_info->data_hddr); + PMD_DRV_LOG(DEBUG, "data_laddr : 0x%x", item_info->data_laddr); + + if (item_info->cmd_type == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + ack_start_addr = + ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, item_index); + } + ack_start_addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index) + ZXDH_DTB_ITEM_ACK_SIZE; + } else { + ack_start_addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + } + PMD_DRV_LOG(DEBUG, "dtb data:"); + + PMD_DRV_LOG(DEBUG, "ack info:"); + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(ack_start_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + + for (i = 0; i < item_info->data_len; i++) { + data_addr = element_start_addr + 16 * i; + + PMD_DRV_LOG(DEBUG, "row_%u:", i); + + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(data_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + } + + PMD_DRV_LOG(DEBUG, "zxdh dtb info print end."); + return ZXDH_OK; +} + static uint32_t zxdh_np_comm_is_big_endian(void) { @@ -215,7 +453,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) uc_byte_mode = dw_byte_len % 4 & 0xff; for (i = 0; i < dw_byte_num; i++) { - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); p_dw_tmp++; } @@ -239,6 +477,392 @@ zxdh_np_dev_init(void) return 0; } +static uint32_t +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static void +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + data = *p_data; + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + *((volatile uint32_t *)addr) = data; +} + +static void +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + data = *((volatile uint32_t *)addr); + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *p_data = data; +} + +static uint64_t +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) + return ZXDH_DEV_TYPE_INVALID; + + return p_dev_info->pcie_addr; +} + +static void +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); +} + +static void +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); +} + +static uint32_t +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_write(dev_id, addr, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_read(dev_id, addr, p_data); +} + +static ZXDH_REG_T g_dpp_reg_info[] = { + { + .reg_name = "cpu_ind_cmd", + .reg_no = 669, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 4, + .p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rd_done", + .reg_no = 670, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat0", + .reg_no = 671, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat1", + .reg_no = 672, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat2", + .reg_no = 673, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat3", + .reg_no = 674, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "wr_arb_cpu_rdy", + .reg_no = 676, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "info_queue_buf_space_left_0_127", + .reg_no = 820, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 1, + .p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cfg_epid_v_func_num_0_127", + .reg_no = 821, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 7, + .p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cara_queue_ram0_159_0", + .reg_no = 721, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x000000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x7FFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_cara_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carb_queue_ram0_159_0", + .reg_no = 738, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x100000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0xFFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carb_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carc_queue_ram0_159_0", + .reg_no = 755, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x200000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x3FF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carc_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "pktrx_glbal_cfg_0", + .reg_no = 448, + .module_no = NPPU, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_NPPU_BASE_ADDR + ZXDH_MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, +}; + +static uint32_t +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) +{ + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = NULL; + + p_reg_info = &g_dpp_reg_info[reg_no]; + + addr = p_reg_info->addr; + + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { + if (n_offset > (p_reg_info->n_size - 1)) + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%u", reg_no); + + addr += n_offset * p_reg_info->n_step; + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + PMD_DRV_LOG(ERR, "reg n_offset/m_offset out of range, reg_no:%u", reg_no); + + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; + } + + return addr; +} + static uint32_t zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, @@ -262,7 +886,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, } else { /* device is new. */ p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } p_dev_mgr->p_dev_array[dev_id] = p_dev_info; p_dev_mgr->device_num++; } @@ -275,7 +902,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->dma_vir_addr = dma_vir_addr; p_dev_info->dma_phy_addr = dma_phy_addr; - return 0; + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + + return ZXDH_OK; } static uint32_t @@ -323,8 +953,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id) p_sdt_mgr->channel_num++; } else { - PMD_DRV_LOG(ERR, "Error: %s for dev[%d]" - "is called repeatedly!", __func__, dev_id); + PMD_DRV_LOG(ERR, "called repeatedly!"); return 1; } @@ -367,6 +996,61 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret); + } + + rte_free(recv_buffer); + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -376,6 +1060,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) return p_dpp_dtb_mgr[dev_id]; } +static uint32_t +zxdh_np_dtb_mgr_create(uint32_t dev_id) +{ + if (p_dpp_dtb_mgr[dev_id] != NULL) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); + return ZXDH_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + if (p_dpp_dtb_mgr[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dtb_soft_init(uint32_t dev_id) { @@ -386,10 +1088,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id) p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) { - p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + zxdh_np_dtb_mgr_create(dev_id); + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) - return 1; + return ZXDH_RC_DTB_MGR_NOT_EXIST; } return 0; @@ -469,36 +1172,9 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE) ? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0; - g_np_bar_offset = bar_offset; - return np_addr; } -int -zxdh_np_host_init(uint32_t dev_id, - ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) -{ - ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; - uint32_t rc; - uint64_t agent_addr; - - ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); - - sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); - sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, - p_dev_init_ctrl->np_bar_offset); - sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; - rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); - - zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); - - agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; - zxdh_np_dev_agent_addr_set(dev_id, agent_addr); - - return 0; -} - static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -611,24 +1287,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t rc = 0; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - for (i = 0; i < p_reg_info->field_num; i++) { - rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - (uint32_t *)p_data + i, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]); + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); } } + + for (i = 0; i < p_reg_info->field_num; i++) { + rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + (uint32_t *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex"); + PMD_DRV_LOG(DEBUG, "dev_id %u(%u)(%u)is ok!", dev_id, m_offset, n_offset); + } + return rc; } @@ -637,20 +1326,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info) { - ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; - uint32_t rc; + uint32_t rc = 0; + uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010; + uint32_t epid_v_func = 0; - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM, - 0, queue_id, &vm_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read"); + rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel"); - p_vm_info->dbi_en = vm_info.dbi_en; - p_vm_info->queue_en = vm_info.queue_en; - p_vm_info->epid = vm_info.cfg_epid; - p_vm_info->vector = vm_info.cfg_vector; - p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; - p_vm_info->func_num = vm_info.cfg_func_num; - p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1); + p_vm_info->queue_en = (epid_v_func >> 30 & 0x1); + p_vm_info->epid = (epid_v_func >> 24 & 0xF); + p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF); + p_vm_info->vector = (epid_v_func >> 8 & 0x7); + p_vm_info->func_num = (epid_v_func >> 5 & 0x7); + p_vm_info->vfunc_active = (epid_v_func & 0x1); return rc; } @@ -733,32 +1423,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t temp_data; - uint32_t rc; + uint32_t rc = ZXDH_OK; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + for (i = 0; i < p_reg_info->field_num; i++) { + if (p_field_info[i].len <= 32) { + temp_data = *((uint32_t *)p_data + i) & + zxdh_np_comm_get_bit_mask(p_field_info[i].len); + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); + } + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - - for (i = 0; i < p_reg_info->field_num; i++) { - if (p_field_info[i].len <= 32) { - temp_data = *((uint32_t *)p_data + i); - rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - temp_data, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", - dev_id, m_offset, n_offset); - } + PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]); + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); + + PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.", + p_buff[i]); } } - return 0; + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + PMD_DRV_LOG(DEBUG, "reg_no = %u. m_offset = %u n_offset = %u", + reg_no, m_offset, n_offset); + PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } + + return rc; } static uint32_t @@ -837,11 +1545,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, { uint32_t rc; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) { - *p_item_num = 32; - return 0; - } - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE, 0, queue_id, p_item_num); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); @@ -874,7 +1577,7 @@ zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_DEV_POINT(devid, pname); @@ -891,20 +1594,11 @@ static void zxdh_np_dtb_mgr_destroy(uint32_t dev_id) { if (p_dpp_dtb_mgr[dev_id] != NULL) { - free(p_dpp_dtb_mgr[dev_id]); + rte_free(p_dpp_dtb_mgr[dev_id]); p_dpp_dtb_mgr[dev_id] = NULL; } } -static void -zxdh_np_tlb_mgr_destroy(uint32_t dev_id) -{ - if (g_p_dpp_tlb_mgr[dev_id] != NULL) { - free(g_p_dpp_tlb_mgr[dev_id]); - g_p_dpp_tlb_mgr[dev_id] = NULL; - } -} - static void zxdh_np_sdt_mgr_destroy(uint32_t dev_id) { @@ -914,7 +1608,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id) p_sdt_tbl_temp = ZXDH_SDT_SOFT_TBL_GET(dev_id); p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET(); - free(p_sdt_tbl_temp); + rte_free(p_sdt_tbl_temp); ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL; @@ -931,7 +1625,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { - free(p_dev_info); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; } @@ -946,11 +1640,9 @@ zxdh_np_online_uninit(uint32_t dev_id, rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id); if (rc != 0) - PMD_DRV_LOG(ERR, "%s:dtb release error," - "port name %s queue id %d", __func__, port_name, queue_id); + PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); zxdh_np_dtb_mgr_destroy(dev_id); - zxdh_np_tlb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -964,8 +1656,8 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no) } -static ZXDH_DTB_TABLE_T * -zxdh_np_table_info_get(uint32_t table_type) +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_table_info_get(uint32_t table_type) { return &g_dpp_dtb_table_info[table_type]; } @@ -977,20 +1669,20 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, void *p_cmd_buff) { uint32_t field_cnt; - ZXDH_DTB_TABLE_T *p_table_info = NULL; - ZXDH_DTB_FIELD_T *p_field_info = NULL; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; uint32_t temp_data; uint32_t rc = 0; ZXDH_COMM_CHECK_POINT(p_cmd_data); ZXDH_COMM_CHECK_POINT(p_cmd_buff); - p_table_info = zxdh_np_table_info_get(table_type); + p_table_info = zxdh_np_dtb_table_info_get(table_type); p_field_info = p_table_info->p_fields; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { - temp_data = *((uint32_t *)p_cmd_data + field_cnt) & ZXDH_COMM_GET_BIT_MASK(uint32_t, - p_field_info[field_cnt].len); + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, ZXDH_DTB_TABLE_CMD_SIZE_BIT, @@ -998,7 +1690,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, p_field_info[field_cnt].lsb_pos, p_field_info[field_cnt].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex"); } return rc; @@ -1062,17 +1754,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc = 0; switch (wrt_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]" - "INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__, - base_addr, index, __func__); - + PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { @@ -1095,11 +1784,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, } temp_idx = index; + break; + default: + break; } dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx; - PMD_DRV_LOG(INFO, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); + PMD_DRV_LOG(DEBUG, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); rc = zxdh_np_dtb_smmu0_write_entry_data(dev_id, wrt_mode, @@ -1131,6 +1823,126 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + uint32_t tmp = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32, + ZXDH_SDT_H_ERAM_MODE_BT_POS, ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + p_sdt_eram->eram_clutch_en = clutch_en; + break; + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + p_sdt_hash->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32, + ZXDH_SDT_H_HASH_ID_BT_POS, ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32, + ZXDH_SDT_H_LEARN_EN_BT_POS, ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + p_sdt_hash->keep_alive_baddr += (tmp << ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32, + ZXDH_SDT_L_RSP_MODE_BT_POS, ZXDH_SDT_L_RSP_MODE_BT_LEN); + p_sdt_hash->hash_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + p_sdt_etcam->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_ID_BT_POS, ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + p_sdt_etcam->as_eram_baddr += (tmp << ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + p_sdt_etcam->etcam_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %u ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%u] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -1140,17 +1952,21 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_DTB_ENTRY_T *p_dtb_one_entry) { uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0}; - ZXDH_SDTTBL_ERAM_T sdt_eram = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram = {0}; ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL; uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -1166,8 +1982,19 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, case ZXDH_ERAM128_TBL_1b: opr_mode = ZXDH_ERAM128_OPR_1b; break; + default: + break; } + PMD_DRV_LOG(DEBUG, "std no:0x%x, index:0x%x, base addr:0x%x", sdt_no, index, base_addr); + if (opr_mode == ZXDH_ERAM128_OPR_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1], + peramdata->p_data[2], peramdata->p_data[3]); + else if (opr_mode == ZXDH_ERAM128_OPR_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1]); + if (del_en) { memset((uint8_t *)buff, 0, sizeof(buff)); rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, @@ -1274,6 +2101,9 @@ zxdh_np_dtb_item_ack_rd(uint32_t dev_id, val = *((volatile uint32_t *)(addr)); + if (!zxdh_np_comm_is_big_endian()) + val = ZXDH_COMM_CONVERT32(val); + *p_data = val; return 0; @@ -1294,7 +2124,10 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, else addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; - *((volatile uint32_t *)(addr)) = data; + if (!zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *((volatile uint32_t *)addr) = data; return 0; } @@ -1304,16 +2137,26 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info) { - ZXDH_DTB_QUEUE_LEN_T dtb_len = {0}; uint32_t rc; - dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; - dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; - dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000; + uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004; + uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008; + uint32_t dtb_len = 0; + + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32, + 1, &p_item_info->data_hddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32, + 1, &p_item_info->data_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len); + rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); - rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN, - 0, queue_id, (void *)&dtb_len); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); return rc; } @@ -1335,7 +2178,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t rc; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1344,7 +2187,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } @@ -1383,6 +2226,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, item_info.data_hddr = ((phy_addr >> 4) >> 32) & 0xffffffff; item_info.data_laddr = (phy_addr >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); + rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; @@ -1421,7 +2266,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff; - uint8_t *p_data_buff_ex; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -1435,9 +2279,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1446,6 +2287,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, for (entry_index = 0; entry_index < entrynum; entry_index++) { pentry = down_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: @@ -1453,9 +2295,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1463,9 +2304,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); @@ -1475,7 +2314,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1485,18 +2323,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return rc; } -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; -} - int zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint32_t queue_id, @@ -1509,7 +2339,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -1525,9 +2354,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1537,16 +2363,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, pentry = delete_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1554,9 +2381,7 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1567,158 +2392,43 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - - rte_free(p_data_buff_ex); - return 0; -} - -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) -{ - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); - - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; - break; - case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; - - switch (eram_mode) { - case ZXDH_ERAM128_TBL_128b: - row_index = index; - break; - case ZXDH_ERAM128_TBL_64b: - row_index = (index >> 1); - col_index = index & 0x1; - break; - case ZXDH_ERAM128_TBL_1b: - row_index = (index >> 7); - col_index = index & 0x7F; - break; - } - *p_row_index = row_index; - *p_col_index = col_index; -} -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - memcpy(p_data, temp_data, (128 / 8)); - break; - case ZXDH_ERAM128_TBL_64b: - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - case ZXDH_ERAM128_TBL_1b: - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - } return rc; } - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc = 0; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) +{ + uint32_t row_index = 0; + uint32_t col_index = 0; + + switch (eram_mode) { + case ZXDH_ERAM128_TBL_128b: + row_index = index; + break; + case ZXDH_ERAM128_TBL_64b: + row_index = (index >> 1); + col_index = index & 0x1; + break; + case ZXDH_ERAM128_TBL_1b: + row_index = (index >> 7); + col_index = index & 0x7F; break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; + break; } - - return 0; + *p_row_index = row_index; + *p_col_index = col_index; } static void @@ -1727,10 +2437,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -1748,12 +2458,12 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1769,6 +2479,11 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.cmd_type = ZXDH_DTB_DIR_UP_TYPE; item_info.int_en = int_flag; item_info.data_len = desc_len / 4; + item_info.data_hddr = + ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) >> 32) & 0xffffffff; + item_info.data_laddr = + (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) return 0; @@ -1778,6 +2493,33 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -1799,8 +2541,8 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, desc_len, p_dump_info); if (rc != 0) { - PMD_DRV_LOG(ERR, "the queue %d element id %d dump" - " info set failed!", queue_id, queue_element_id); + PMD_DRV_LOG(ERR, "queue %u element %u dump info set failed!", + queue_id, queue_element_id); zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } @@ -1819,7 +2561,7 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t i; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1849,37 +2591,9 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, *p_item_index = item_index; - return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -1898,7 +2612,7 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); if (rc != 0) { - PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %d!", base_addr); + PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %u!", base_addr); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; } @@ -1918,6 +2632,103 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + eram_base_addr = sdt_eram_info.eram_base_addr; + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_data, temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_TBL_64b: + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + + PMD_DRV_LOG(DEBUG, "[eram_dump]std no:0x%x, index:0x%x, base addr:0x%x", + sdt_no, p_dump_eram_entry->index, eram_dump_base_addr); + if (rd_mode == ZXDH_ERAM128_TBL_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1], + p_dump_eram_entry->p_data[2], p_dump_eram_entry->p_data[3]); + else if (rd_mode == ZXDH_ERAM128_TBL_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1]); + + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, @@ -1945,6 +2756,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, row_index = (index >> 7); col_index = index & 0x7F; break; + default: + break; } eram_dump_base_addr = base_addr + row_index; @@ -1967,6 +2780,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } return rc; @@ -2035,6 +2850,32 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +int +zxdh_np_host_init(uint32_t dev_id, + ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; + uint32_t rc; + uint64_t agent_addr; + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); + + sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); + sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, + p_dev_init_ctrl->np_bar_offset); + sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; + + rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); + + zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); + + agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; + zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + + return 0; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { @@ -2047,7 +2888,7 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) while (!done_flag) { rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read Fail!", rc); + PMD_DRV_LOG(ERR, "reg_read fail!"); return rc; } @@ -2073,7 +2914,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t rd_clr_mode, uint32_t *p_data) { - uint32_t rc = 0; + uint32_t rc = ZXDH_OK; uint32_t i = 0; uint32_t row_index = 0; uint32_t col_index = 0; @@ -2082,6 +2923,10 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; @@ -2090,42 +2935,42 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - if ((0xFFFFFFFF - (base_addr)) < (index)) + if ((0xFFFFFFFF - (base_addr)) < (index)) { + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; - + } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x1; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x3; break; case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x7F; break; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; @@ -2136,56 +2981,69 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 7); cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6); cpu_ind_cmd.cpu_req_mode = 2; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 5); cpu_ind_cmd.cpu_req_mode = 1; break; case ZXDH_ERAM128_OPR_1b: - PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ", - rd_clr_mode, rd_mode); - return -1; + PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", + rd_clr_mode, rd_mode); + return ZXDH_ERR; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; } rc = zxdh_np_reg_write(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, - 0, - 0, - &cpu_ind_cmd); + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } - rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER, 0); + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } p_temp_data = temp_data; for (i = 0; i < 4; i++) { rc = zxdh_np_reg_read(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, - 0, - 0, - p_temp_data + 3 - i); + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { @@ -2203,6 +3061,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } } else { switch (rd_mode) { @@ -2215,6 +3075,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: memcpy(p_data, p_temp_data, (64 / 8)); break; + default: + break; } } @@ -2266,70 +3128,18 @@ zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, } static uint32_t -zxdh_np_agent_channel_sync_send(ZXDH_AGENT_CHANNEL_MSG_T *p_msg, - uint32_t *p_data, - uint32_t rep_len) -{ - uint32_t ret = 0; - uint32_t vport = 0; - struct zxdh_pci_bar_msg in = {0}; - struct zxdh_msg_recviver_mem result = {0}; - uint32_t *recv_buffer; - uint8_t *reply_ptr = NULL; - uint16_t reply_msg_len = 0; - uint64_t agent_addr = 0; - - if (ZXDH_IS_PF(vport)) - in.src = ZXDH_MSG_CHAN_END_PF; - else - in.src = ZXDH_MSG_CHAN_END_VF; - - in.virt_addr = agent_addr; - in.payload_addr = p_msg->msg; - in.payload_len = p_msg->msg_len; - in.dst = ZXDH_MSG_CHAN_END_RISC; - in.module_id = ZXDH_BAR_MDOULE_NPSDK; - - recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); - if (recv_buffer == NULL) { - PMD_DRV_LOG(ERR, "%s point null!", __func__); - return ZXDH_PAR_CHK_POINT_NULL; - } - - result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; - result.recv_buffer = recv_buffer; - - ret = zxdh_bar_chan_sync_msg_send(&in, &result); - if (ret == ZXDH_BAR_MSG_OK) { - reply_ptr = (uint8_t *)(result.recv_buffer); - if (*reply_ptr == 0XFF) { - reply_msg_len = *(uint16_t *)(reply_ptr + 1); - memcpy(p_data, reply_ptr + 4, - ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); - } else { - PMD_DRV_LOG(ERR, "Message not replied"); - } - } else { - PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__); - } - - rte_free(recv_buffer); - return ret; -} - -static uint32_t -zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, +zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) { uint32_t ret = 0; - ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), + }; - agent_msg.msg = (void *)p_msg; - agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T); - - ret = zxdh_np_agent_channel_sync_send(&agent_msg, p_data, rep_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_sync_send failed."); return 1; } @@ -2337,25 +3147,25 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport, uint32_t car_type, uint32_t *p_profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_REQUEST; - msgcfg.vport = vport; - msgcfg.car_type = car_type; - msgcfg.profile_id = 0xFFFF; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_REQUEST, + .vport = vport, + .car_type = car_type, + .profile_id = 0xFFFF, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2365,7 +3175,8 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, } static uint32_t -zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, +zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, + uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id __rte_unused, void *p_car_profile_cfg) @@ -2395,9 +3206,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgpktcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_a_type failed."); return 1; } @@ -2429,9 +3240,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_b_type failed."); return 1; } @@ -2442,25 +3253,25 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport, uint32_t car_type __rte_unused, uint32_t profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_RELEASE; - msgcfg.vport = vport; - msgcfg.profile_id = profileid; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_RELEASE, + .vport = vport, + .profile_id = profileid, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2478,11 +3289,12 @@ zxdh_np_stat_cara_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { + .cara_drop = drop_flag, + .cara_plcr_en = plcr_en, + .cara_profile_id = profile_id, + }; - queue_cfg.cara_drop = drop_flag; - queue_cfg.cara_plcr_en = plcr_en; - queue_cfg.cara_profile_id = profile_id; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0, 0, @@ -2502,11 +3314,11 @@ zxdh_np_stat_carb_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; - - queue_cfg.carb_drop = drop_flag; - queue_cfg.carb_plcr_en = plcr_en; - queue_cfg.carb_profile_id = profile_id; + ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { + .carb_drop = drop_flag, + .carb_plcr_en = plcr_en, + .carb_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0, @@ -2527,10 +3339,11 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; - queue_cfg.carc_drop = drop_flag; - queue_cfg.carc_plcr_en = plcr_en; - queue_cfg.carc_profile_id = profile_id; + ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { + .carc_drop = drop_flag, + .carc_plcr_en = plcr_en, + .carc_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0, @@ -2553,12 +3366,12 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, uint32_t profile_id_l = 0; uint64_t temp_profile_id = 0; - profile_id = (uint32_t *)rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); + profile_id = rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); if (profile_id == NULL) { - PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__); + PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -2566,7 +3379,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, temp_profile_id = (((uint64_t)profile_id_l) << 32) | ((uint64_t)profile_id_h); if (0 != (uint32_t)(temp_profile_id >> 56)) { - PMD_DRV_LOG(ERR, "%s: profile_id is overflow!", __func__); + PMD_DRV_LOG(ERR, "profile_id is overflow!"); return 1; } @@ -2583,11 +3396,12 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, void *p_car_profile_cfg) { uint32_t ret = 0; + uint32_t dev_id = 0; - ret = zxdh_np_agent_channel_plcr_car_rate(car_type, + ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__); + PMD_DRV_LOG(ERR, "plcr_car_rate set failed!"); return 1; } @@ -2599,13 +3413,12 @@ zxdh_np_car_profile_id_delete(uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t profileid = 0; - - profileid = profile_id & 0xFFFF; + uint32_t dev_id = 0; + uint32_t profileid = profile_id & 0xFFFF; - ret = zxdh_np_agent_channel_plcr_profileid_release(vport_id, flags, profileid); + ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__); + PMD_DRV_LOG(ERR, "plcr profiled id release failed!"); return 1; } @@ -2624,32 +3437,32 @@ zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, if (car_type == ZXDH_STAT_CAR_A_TYPE) { if (flow_id > ZXDH_CAR_A_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_A_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else if (car_type == ZXDH_STAT_CAR_B_TYPE) { if (flow_id > ZXDH_CAR_B_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_B_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else { if (flow_id > ZXDH_CAR_C_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_C_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 7ff5c34c73..6d2c7aa976 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -6,14 +6,16 @@ #define ZXDH_NP_H #include <stdint.h> +#include <rte_spinlock.h> +#define ZXDH_OK (0) +#define ZXDH_ERR (1) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) #define ZXDH_DEV_CHANNEL_MAX (2) #define ZXDH_DEV_SDT_ID_MAX (256U) -#define ZXDH_RD_CNT_MAX (128) /*DTB*/ #define ZXDH_DTB_QUEUE_ITEM_NUM_MAX (32) @@ -54,11 +56,23 @@ #define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9) #define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10) +#define ZXDH_REG_NUL_ARRAY (0 << 0) +#define ZXDH_REG_UNI_ARRAY (1 << 0) +#define ZXDH_REG_BIN_ARRAY (1 << 1) +#define ZXDH_REG_FLAG_INDIRECT (1 << 0) +#define ZXDH_REG_FLAG_DIRECT (0 << 0) +#define ZXDH_FIELD_FLAG_RO (1 << 0) +#define ZXDH_FIELD_FLAG_RW (1 << 1) + +#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000) +#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000) + #define ZXDH_ACL_TBL_ID_MIN (0) #define ZXDH_ACL_TBL_ID_MAX (7) #define ZXDH_ACL_TBL_ID_NUM (8U) #define ZXDH_ACL_BLOCK_NUM (8U) +#define ZXDH_RD_CNT_MAX (100) #define ZXDH_SMMU0_READ_REG_MAX_NUM (4) #define ZXDH_DTB_ITEM_ACK_SIZE (16) @@ -98,6 +112,57 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -206,11 +271,15 @@ typedef enum zxdh_dev_type_e { } ZXDH_DEV_TYPE_E; typedef enum zxdh_reg_info_e { - ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0, - ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1, - ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2, - ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3, - ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0, + ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5, + ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6, + ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7, + ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0 = 9, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0 = 10, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0 = 11, @@ -218,6 +287,12 @@ typedef enum zxdh_reg_info_e { ZXDH_REG_ENUM_MAX_VALUE } ZXDH_REG_INFO_E; +typedef enum zxdh_dev_spinlock_type_e { + ZXDH_DEV_SPINLOCK_T_SMMU0 = 0, + ZXDH_DEV_SPINLOCK_T_DTB = 1, + ZXDH_DEV_SPINLOCK_T_MAX +} ZXDH_DEV_SPINLOCK_TYPE_E; + typedef enum zxdh_dev_access_type_e { ZXDH_DEV_ACCESS_TYPE_PCIE = 0, ZXDH_DEV_ACCESS_TYPE_RISCV = 1, @@ -237,6 +312,29 @@ typedef enum zxdh_acl_pri_mode_e { ZXDH_ACL_PRI_INVALID, } ZXDH_ACL_PRI_MODE_E; +typedef enum zxdh_module_e { + CFG = 1, + NPPU, + PPU, + ETM, + STAT, + CAR, + SE, + SMMU0 = SE, + SMMU1 = SE, + DTB, + TRPG, + TSN, + AXI, + PTPTM, + DTB4K, + STAT4K, + PPU4K, + SE4K, + SMMU14K, + MODULE_MAX +} ZXDH_MODULE_E; + typedef struct zxdh_d_node { void *data; struct zxdh_d_node *prev; @@ -301,6 +399,49 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef struct zxdh_spin_lock_t { + rte_spinlock_t spinlock; +} ZXDH_SPINLOCK_T; + +typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); +typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); + typedef struct zxdh_sys_init_ctrl_t { ZXDH_DEV_TYPE_E device_type; uint32_t flags; @@ -327,6 +468,8 @@ typedef struct dpp_dev_cfg_t { uint64_t dma_phy_addr; uint64_t agent_addr; uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; + ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; + ZXDH_DEV_READ_FUNC p_pcie_read_fun; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -338,8 +481,8 @@ typedef struct zxdh_dev_mngr_t { typedef struct zxdh_dtb_addr_info_t { uint32_t sdt_no; uint32_t size; - uint32_t phy_addr; - uint32_t vir_addr; + uint64_t phy_addr; + uint64_t vir_addr; } ZXDH_DTB_ADDR_INFO_T; typedef struct zxdh_dev_init_ctrl_t { @@ -349,12 +492,12 @@ typedef struct zxdh_dev_init_ctrl_t { uint32_t queue_id; uint32_t np_bar_offset; uint32_t np_bar_len; - uint32_t pcie_vir_addr; - uint32_t down_phy_addr; - uint32_t down_vir_addr; - uint32_t dump_phy_addr; - uint32_t dump_vir_addr; - uint32_t dump_sdt_num; + uint64_t pcie_vir_addr; + uint64_t down_phy_addr; + uint64_t down_vir_addr; + uint64_t dump_phy_addr; + uint64_t dump_vir_addr; + uint64_t dump_sdt_num; ZXDH_DTB_ADDR_INFO_T dump_addr_info[]; } ZXDH_DEV_INIT_CTRL_T; @@ -424,7 +567,7 @@ typedef struct zxdh_reg_t { uint32_t m_step; uint32_t n_step; uint32_t field_num; - ZXDH_FIELD_T *p_fields; + const ZXDH_FIELD_T *p_fields; ZXDH_REG_WRITE p_write_fun; ZXDH_REG_READ p_read_fun; @@ -515,14 +658,6 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDTTBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -538,7 +673,7 @@ typedef struct zxdh_dtb_table_t { const char *table_type; uint32_t table_no; uint32_t field_num; - ZXDH_DTB_FIELD_T *p_fields; + const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; typedef struct zxdh_dtb_queue_item_info_t { @@ -550,12 +685,6 @@ typedef struct zxdh_dtb_queue_item_info_t { uint32_t data_hddr; } ZXDH_DTB_QUEUE_ITEM_INFO_T; -typedef struct zxdh_dtb_queue_len_t { - uint32_t cfg_dtb_cmd_type; - uint32_t cfg_dtb_cmd_int_en; - uint32_t cfg_queue_dtb_len; -} ZXDH_DTB_QUEUE_LEN_T; - typedef struct zxdh_dtb_eram_entry_info_t { uint32_t index; uint32_t *p_data; @@ -571,23 +700,10 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDTTBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; -} ZXDH_SDTTBL_PORTTBL_T; +} ZXDH_SDT_TBL_PORTTBL_T; typedef struct zxdh_dtb_hash_entry_info_t { uint8_t *p_actu_key; @@ -614,15 +730,6 @@ typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_addr; } ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; -typedef enum zxdh_smmu0_smmu0_type_e { - ZXDH_DEV_MUTEX_T_SMMU0 = 0, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 1, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, - ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER = 3, - ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 4, - ZXDH_SMMU0_SMMU0_ED_ARB_CPU_RDYR = 5, -} ZXDH_SEMMU0_SEMMU0_TYPE_E; - typedef enum zxdh_stat_rd_clr_mode_e { ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, ZXDH_STAT_RD_CLR_MODE_CLR = 1, @@ -635,8 +742,8 @@ typedef enum zxdh_eram128_rd_clr_mode_e { } ZXDH_ERAM128_RD_CLR_MODE_E; typedef enum zxdh_se_opr_mode_e { - ZXDH_SE_OPR_RD = 0, - ZXDH_SE_OPR_WR = 1, + ZXDH_SE_OPR_WR = 0, + ZXDH_SE_OPR_RD = 1, } ZXDH_SE_OPR_MODE_E; typedef enum zxdh_stat_car_type_e { @@ -730,11 +837,6 @@ typedef struct dpp_agent_car_pkt_profile_msg { uint32_t pri[ZXDH_CAR_PRI_MAX]; } ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T; -typedef struct zxdh_agent_channel_msg_t { - uint32_t msg_len; - void *msg; -} ZXDH_AGENT_CHANNEL_MSG_T; - typedef struct zxdh_agent_channel_plcr_msg { uint8_t dev_id; uint8_t type; @@ -803,6 +905,10 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 244256 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 02/14] net/zxdh: support compatibility check 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 03/14] net/zxdh: add agent channel Bingbin Chen ` (13 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5360 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 +++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1534cb2709..f0848658ac 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -24,6 +24,9 @@ static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -1175,6 +1178,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2873,6 +2961,11 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6d2c7aa976..11eb7e15d5 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -905,6 +908,15 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 9875 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 03/14] net/zxdh: add agent channel 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (12 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16208 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 315 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 53 +++++++ 2 files changed, 367 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index f0848658ac..00e02cb36f 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -480,6 +480,70 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %u ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_spinlock; + break; + case ZXDH_DEV_SPINLOCK_T_SMMU0: + *p_spinlock_out = &p_dev_info->smmu0_spinlock; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -908,6 +972,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + return ZXDH_OK; } @@ -999,6 +1066,48 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_DROP: + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_agent_channel_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg, @@ -1014,7 +1123,14 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, uint16_t reply_msg_len = 0; uint64_t agent_addr = 0; - PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); if (ZXDH_IS_PF(vport)) in.src = ZXDH_MSG_CHAN_END_PF; @@ -1054,6 +1170,165 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T), + }; + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PCIE_BAR_MSG, + .oper = ZXDH_BAR_MSG_NUM_REQ, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_RD, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent read resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_WR, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent write resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1263,6 +1538,24 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_pcie_bar_request"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1381,12 +1674,19 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1518,6 +1818,9 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1552,6 +1855,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -2945,6 +3252,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); @@ -2966,6 +3274,11 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 11eb7e15d5..a692eca9aa 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,9 +112,17 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_CHANNEL_REPS_LEN (4) + #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -178,6 +186,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_SPIN_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_SPIN_LOCK_INIT_FAIL (ZXDH_SPIN_LOCK_BASE | 0x001) +#define ZXDH_SPIN_LOCK_LOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0x002) +#define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) +#define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -215,6 +229,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -465,6 +486,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -473,6 +495,8 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_SPINLOCK_T dtb_spinlock; + ZXDH_SPINLOCK_T smmu0_spinlock; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -726,6 +750,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -917,6 +952,24 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 37167 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 04/14] net/zxdh: modify dtb queue ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (2 preceding siblings ...) 2025-03-19 8:57 ` [PATCH v5 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (11 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 26076 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 491 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 ++++++++ 2 files changed, 482 insertions(+), 106 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 00e02cb36f..3f5d286ffe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -17,16 +17,15 @@ static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; -static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -544,6 +543,25 @@ zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_queue_spinlock[index]; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -938,6 +956,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -973,7 +992,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); - rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); return ZXDH_OK; } @@ -1329,6 +1350,89 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_REQUEST, + .vport = vport_info, + }; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %u, msg_result: %u", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %u, queue_id: %u", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_RELEASE, + .queue_id = queue_id, + }; + + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %u", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1556,48 +1660,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1887,52 +1949,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1967,20 +1983,74 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + uint32_t vport_info = (uint32_t)vport; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", + dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(devid, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %u not request.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } + + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %u name error.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "release queueid %u", queueid); return rc; } @@ -2571,24 +2641,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2603,8 +2683,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2626,6 +2708,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2639,8 +2723,6 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, uint32_t rc = 0; uint32_t dtb_interrupt_status = 0; - dtb_interrupt_status = g_dpp_dtb_int_enable; - rc = zxdh_np_dtb_tab_down_info_set(dev_id, queue_id, dtb_interrupt_status, @@ -2850,20 +2932,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2880,11 +2970,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2954,16 +3043,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2978,14 +3074,18 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return 0; } @@ -3245,6 +3345,181 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = { + .down_start_phy_addr = phy_addr, + .down_start_vir_addr = vir_addr, + .down_item_size = size, + }; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = { + .up_start_phy_addr = phy_addr, + .up_start_vir_addr = vir_addr, + .up_item_size = size, + }; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -3279,6 +3554,10 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + PMD_DRV_LOG(INFO, "host init done, queue_id = %u", p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a692eca9aa..6cf8653670 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -497,6 +497,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; + ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -685,6 +686,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -703,6 +776,15 @@ typedef struct zxdh_dtb_table_t { const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -761,6 +843,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -975,6 +1062,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56114 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 05/14] net/zxdh: add tables dump address ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (3 preceding siblings ...) 2025-03-19 8:57 ` [PATCH v5 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-03-19 8:57 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (10 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 39968 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1137 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1228 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 3f5d286ffe..98135b37a7 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -26,6 +26,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -324,6 +325,51 @@ zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, #define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) +static inline void +zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) +{ + ptr->data = pdata; + ptr->prev = NULL; + ptr->next = NULL; +} + +static inline void +zxdh_np_init_rbt_tn(ZXDH_RB_TN *p_tn, void *p_newkey) +{ + p_tn->p_key = p_newkey; + p_tn->color_lsv = 0; + p_tn->p_left = NULL; + p_tn->p_right = NULL; + p_tn->p_parent = NULL; + zxdh_np_init_d_node(&p_tn->tn_ln, p_tn); +} + +static inline uint32_t +zxdh_np_get_tn_lsv(ZXDH_RB_TN *p_tn) +{ + return p_tn->color_lsv >> 2; +} + +static inline void +zxdh_np_set_tn_lsv(ZXDH_RB_TN *p_tn, uint32_t list_val) +{ + p_tn->color_lsv &= 0x3; + p_tn->color_lsv |= (list_val << 2); +} + +static inline void +zxdh_np_set_tn_color(ZXDH_RB_TN *p_tn, uint32_t color) +{ + p_tn->color_lsv &= 0xfffffffc; + p_tn->color_lsv |= (color & 0x3); +} + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -465,6 +511,945 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_create(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(ERR, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(ERR, "dw_index is invalid"); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_switch_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = zxdh_np_get_tn_color(p_tn1); + color2 = zxdh_np_get_tn_color(p_tn2); + + zxdh_np_set_tn_color(p_tn1, color2); + zxdh_np_set_tn_color(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (zxdh_np_get_tn_color(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + zxdh_np_set_tn_color(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + zxdh_np_set_tn_color(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " p_rb_cfg already init!"); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_create(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_create"); + + p_rb_cfg->p_keybase = rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + zxdh_np_init_rbt_tn(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + zxdh_np_set_tn_lsv(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + zxdh_np_init_d_node(&p_ins_tn->tn_ln, p_ins_tn); + } + + zxdh_np_set_tn_color(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(ERR, "rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = zxdh_np_get_tn_lsv(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(zxdh_np_get_tn_color(p_par_tn) == ZXDH_RBT_RED); + + zxdh_np_set_tn_color(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + } else { + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (zxdh_np_get_tn_color(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_switch_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (zxdh_np_get_tn_color(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + zxdh_np_set_tn_color(p_del_tn, zxdh_np_get_tn_color(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (zxdh_np_get_tn_color(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (zxdh_np_get_tn_color(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + zxdh_np_set_tn_color(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, zxdh_np_get_tn_lsv(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(ERR, "p_list point null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + memcpy(p_rb_key, p_data, len); + + p_rb_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1976,10 +2961,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%u", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -2009,6 +3096,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", @@ -2047,6 +3137,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3494,12 +4587,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = { + .sdt_no = sdt_no, + .phy_addr = phy_addr, + .vir_addr = vir_addr, + .size = size, + }; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3517,6 +4641,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6cf8653670..36b7628bb7 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -123,6 +123,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -192,6 +199,26 @@ #define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) #define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -236,6 +263,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -372,6 +427,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 108876 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 06/14] net/zxdh: add eram tables ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (4 preceding siblings ...) 2025-03-19 8:57 ` [PATCH v5 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (9 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 22262 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 545 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 15 + 2 files changed, 558 insertions(+), 2 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 98135b37a7..fd9c7b47c9 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -196,6 +200,81 @@ static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +static const ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -314,6 +393,17 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + static inline uint64_t zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, uint32_t INDEX) @@ -3220,6 +3310,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3254,6 +3350,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3304,6 +3433,39 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ERAM, + .base_addr = base_addr, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + PMD_DRV_LOG(DEBUG, "valid: %u", dtb_eram_dump_form_info.valid); + PMD_DRV_LOG(DEBUG, "up_type: %u", dtb_eram_dump_form_info.up_type); + PMD_DRV_LOG(DEBUG, "base_addr: 0x%x", dtb_eram_dump_form_info.base_addr); + PMD_DRV_LOG(DEBUG, "tb_depth: %u", dtb_eram_dump_form_info.tb_depth); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_h: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_h); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_l: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_l); + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -3690,6 +3852,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(DEBUG, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(DEBUG, "[index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(ERR, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + + PMD_DRV_LOG(DEBUG, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3825,6 +4079,121 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) { + PMD_DRV_LOG(ERR, "down queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3894,6 +4263,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -3972,6 +4343,8 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -4070,6 +4443,36 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + static uint32_t zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -4081,7 +4484,7 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint64_t addr; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -4089,7 +4492,8 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); else - addr = ZXDH_DTB_ITEM_ACK_SIZE; + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; *p_phy_haddr = (addr >> 32) & 0xffffffff; *p_phy_laddr = addr & 0xffffffff; @@ -4097,6 +4501,125 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(DEBUG, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) { + PMD_DRV_LOG(ERR, "dump queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -4124,6 +4647,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %u element %u dump done.", queue_id, queue_element_id); + return rc; } @@ -4210,6 +4743,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 36b7628bb7..d4a940b038 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -227,6 +227,13 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) + +#define ZXDH_DTB_DELAY_TIME (50) +#define ZXDH_DTB_DOWN_OVER_TIME (2000) +#define ZXDH_DTB_DUMP_OVER_TIME (200000) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -728,6 +735,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56696 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 07/14] net/zxdh: get flow tables resources 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (5 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (8 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 29861 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 13 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 492 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 282 +++++++++++++++++++ 4 files changed, 788 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index e683cbd616..ea34b9229b 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1809,6 +1809,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(hw->dev_id, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index 04b0b58c74..261acd17c3 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -44,6 +44,7 @@ #define ZXDH_MAX_NAME_LEN 32 #define ZXDH_SLOT_MAX 256 #define ZXDH_MAX_VF 256 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fd9c7b47c9..c93f8eb0fb 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2508,6 +2508,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5239,6 +5273,464 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} + +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + PMD_DRV_LOG(DEBUG, "se res get success."); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d4a940b038..b204889c9a 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -130,6 +130,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -521,6 +527,33 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -555,6 +588,113 @@ typedef struct zxdh_sdt_tbl_hash_t { uint32_t hash_clutch_en; } ZXDH_SDT_TBL_HASH_T; +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -596,6 +736,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -954,6 +1095,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -1178,6 +1342,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1213,5 +1494,6 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t drop_flag, uint32_t plcr_en, uint32_t profile_id); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 61852 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 08/14] net/zxdh: support hash resources configuration 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (6 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (7 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 34513 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 774 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 260 +++++++++++++ 2 files changed, 1034 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index c93f8eb0fb..22c30313fe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -31,6 +31,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +static ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static const uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +static uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -460,6 +477,20 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); } +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -819,6 +850,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -844,6 +902,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5719,6 +5817,678 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + zxdh_np_init_d_node(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + zxdh_np_init_d_node(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + break; + default: + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %u]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlock[%u] is already used", zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlk[%u], ZCell[%u] is already used", + zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %u!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = rte_zmalloc(NULL, sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %u ] is not init", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input zcell_num is %u, bulk %u monopolize zcells is %u", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %u ] is not init", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input zreg_num' is %u, actually bulk %u monopolize zregs is %u", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "dev_id[0x%x],se_type[0x%x] invalid!", dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5728,6 +6498,10 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); PMD_DRV_LOG(DEBUG, "se res get success."); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + PMD_DRV_LOG(DEBUG, "se res init success."); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b204889c9a..8937e24def 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -136,6 +136,43 @@ #define ZXDH_ERAM_MAX_NUM (60) #define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -304,6 +341,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -463,6 +505,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -476,6 +525,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89111 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 09/14] net/zxdh: implement tables initialization 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (7 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (6 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 32052 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 670 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 136 ++++++++ 2 files changed, 806 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 22c30313fe..689ec08344 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -22,6 +22,9 @@ static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +static ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -49,6 +52,10 @@ static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +static ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -491,6 +498,48 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, + uint32_t start_pos, uint32_t len) +{ + uint32_t mask = zxdh_np_comm_get_bit_mask(len); + *dst = (*dst & ~(mask << start_pos)) | ((src & mask) << start_pos); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ + zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -2240,6 +2289,232 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "soft sdt table not init!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft sdt table item invalid!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "0x%08x 0x%08x", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft table item invalid !"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "sdt_no: 0x%08x", sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + PMD_DRV_LOG(DEBUG, "sdt: %u", sdt_no); + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", + table_type); + return ZXDH_ERR; + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -6453,12 +6728,381 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + case ZXDH_SDT_TBLT_HASH: + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + case ZXDH_SDT_TBLT_ETCAM: + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + default: + PMD_DRV_LOG(ERR, "table_type[ %u ] is invalid!", table_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + uint32_t entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%u] not match to key_type[%u].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%u], table_id[%u] is already init", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %u ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode %u, etcam block_num %u is not enough for entry_num 0x%x", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is more than entry_num 0x%x", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is match with entry_num 0x%x", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + zxdh_np_init_d_node(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_tbls[table_id]); + rc = zxdh_comm_double_link_insert_last(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %u ] is already used by table[ %u ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6468,8 +7112,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6486,6 +7136,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 8937e24def..320af0573c 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -103,6 +103,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -346,6 +350,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -532,6 +558,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -955,6 +996,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 79363 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 10/14] net/zxdh: support hash tables write and delete ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (8 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (5 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35069 bytes --] Implement hash tables write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 930 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 17 + 2 files changed, 947 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 689ec08344..67edf581e2 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -540,6 +540,76 @@ zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, #define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) +static inline uint32_t +zxdh_np_zblk_addr_conv(uint32_t zblk_idx) +{ + uint32_t group_size = 1 << ZXDH_ZBLK_IDX_BT_WIDTH; + uint32_t group_number = zblk_idx / ZXDH_ZBLK_NUM_PER_ZGRP; + uint32_t offset_in_group = zblk_idx % ZXDH_ZBLK_NUM_PER_ZGRP; + + return group_number * group_size + offset_in_group; +} + +static inline uint32_t +zxdh_np_zcell_addr_conv(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (zxdh_np_zblk_addr_conv(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | \ + (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) | \ + ((zxdh_np_zblk_addr_conv(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | \ + ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((zxdh_np_zcell_addr_conv(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -1784,6 +1854,16 @@ zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_spinlock_get(uint32_t dev_id, + uint32_t fun_id, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *p_spinlock_out = &p_dev_info->hash_spinlock[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2218,6 +2298,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + rte_spinlock_init(&p_dev_info->hash_spinlock[i].spinlock); + return ZXDH_OK; } @@ -3840,6 +3923,65 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ZCAM, + .ram_reg_flag = reg_sram_flag, + .zgroup_id = zgroup_id, + .zblock_id = zblock_id, + .zcell_id = zcell_id, + .mask = mask, + .sram_addr = sram_addr & 0x1FF, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = (addr >> 16) & 0x1; + uint32_t zgroup_id = (addr >> 14) & 0x3; + uint32_t zblock_id = (addr >> 11) & 0x7; + uint32_t zcell_id = (addr >> 9) & 0x3; + uint32_t mask = (addr >> 17) & 0xF; + uint32_t sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4601,6 +4743,783 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "sdt_partner:%u", sdt_partner); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_init_rbt_tn(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint32_t rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + zxdh_np_init_d_node(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t item_entry_max = 4; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "pos is[%u], size is[%u]", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + HASH_DDR_CFG *p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + uint8_t key_type = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "hash ddr width mode is not match to the key type."); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx:[0x%x] hash_arg:[0x%x] crc_value:[0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id:[0x%x] item_idx:[0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_D_NODE *p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = p_hash_entry_cfg->table_id; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + ZXDH_SE_ITEM_CFG *p_item_info = p_rbkey_new->p_item_info; + + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(ERR, "Error!there is not item in hash!"); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_comm_double_link_del failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_hash_red_black_node_alloc failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_ddr failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zcell failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash form write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + p_hash_cfg->hash_stat.insert_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = temp_key; + entry.p_rst = temp_rst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} + + + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -4640,6 +5559,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -4719,6 +5642,13 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 320af0573c..5ca8053d5e 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -94,6 +96,12 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -573,6 +581,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1132,6 +1148,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_SPINLOCK_T hash_spinlock[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90330 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 11/14] net/zxdh: get hash table entry result 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (9 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (4 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16703 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 482 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 488 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 67edf581e2..fb61e0f99c 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1371,6 +1371,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -4015,6 +4049,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ZCAM, + .tb_width = tb_width, + .sram_addr = addr & 0x1FF, + .ram_reg_flag = (addr >> 16) & 0x1, + .z_reg_cell_id = (addr >> 9) & 0x3, + .zblock_id = (addr >> 11) & 0x7, + .zgroup_id = (addr >> 14) & 0x3, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -6160,6 +6226,399 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %u.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "hash search failed!"); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_OK; + } + + p_rbkey = p_rb_tn_rtn->p_key; + p_item = p_rbkey->p_item_info; + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + + PMD_DRV_LOG(DEBUG, "hash get sdt_no:%u", sdt_no); + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = temp_key; + hash_entry.p_rst = temp_rst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6170,10 +6629,12 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); - PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); @@ -6187,6 +6648,25 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; + case ZXDH_SDT_TBLT_HASH: + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, "hash search failed"); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 5ca8053d5e..3b66cf0b9f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1320,6 +1320,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 47918 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 12/14] net/zxdh: delete all hash entries 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (10 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 13/14] net/zxdh: add acl tables ops Bingbin Chen ` (3 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 37909 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 57 ++ drivers/net/zxdh/zxdh_np.c | 1055 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 10 + 3 files changed, 1122 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea34b9229b..ea8b18e5e1 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1119,6 +1119,30 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + uint32_t sdt_no; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -1130,6 +1154,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!dtb_data->init_done && !dtb_data->dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--dtb_data->dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1796,12 +1822,42 @@ zxdh_init_once(struct rte_eth_dev *eth_dev) return ret; } +static int +zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; + if (hw->is_pf && dtb_data->init_done) { + dtb_data->dev_refcnt++; + zxdh_tbl_entry_offline_destroy(hw); + PMD_DRV_LOG(INFO, "no need to init dtb dtb chanenl %d devref %d", + dtb_data->queueid, dtb_data->dev_refcnt); + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { @@ -1820,6 +1876,7 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); return -1; } + zxdh_tbl_entry_offline_destroy(hw); } if (zxdh_shared_data != NULL) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fb61e0f99c..1cfaee240a 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -519,6 +519,8 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) + static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) { @@ -1791,6 +1793,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3803,6 +3819,219 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_HASH_CFG *p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_D_HEAD *p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%u] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + break; + default: + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %u] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = dpp_se_cfg[dev_id]; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3814,6 +4043,10 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != 0) PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4081,6 +4314,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5904,6 +6156,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -6118,6 +6393,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %u success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %u fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8585,6 +8955,691 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + + if (srh_succ) { + zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zcell_id :%u", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zreg_id :%u", + zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = rte_zmalloc(NULL, max_item_num * sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_rst = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + rte_free(p_key); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(dev_id, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(dev_id, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 3b66cf0b9f..aedc34b193 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1879,6 +1879,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1915,5 +1920,10 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t plcr_en, uint32_t profile_id); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 107615 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 13/14] net/zxdh: add acl tables ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (11 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 14/14] net/zxdh: fix debugging errors Bingbin Chen ` (2 subsequent siblings) 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31167 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 892 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 31 ++ 2 files changed, 923 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1cfaee240a..ab8b3ae688 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -612,6 +612,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -4032,6 +4037,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "etcam_is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %u ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -4047,6 +4111,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4249,6 +4314,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ETCAM, + .block_sel = block_idx, + .init_en = 0, + .row_or_col_msk = row_or_col_msk, + .vben = vben, + .reg_tcam_flag = reg_tcam_flag, + .uload = flush, + .rd_wr = rd_wr, + .wr_mode = wr_mode, + .data_or_mask = data_or_mask, + .addr = ram_addr, + .vbit = vbit, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4314,6 +4443,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ETCAM, + .block_sel = p_etcam_dump_info->block_sel, + .addr = p_etcam_dump_info->addr, + .rd_mode = p_etcam_dump_info->rd_mode, + .data_or_mask = p_etcam_dump_info->data_or_mask, + .tb_depth = p_etcam_dump_info->tb_depth, + .tb_width = p_etcam_dump_info->tb_width, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4333,6 +4491,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5836,7 +6026,318 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + uint32_t entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_TBL_64b: + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + case ZXDH_ERAM128_TBL_1b: + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + default: + break; + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} int zxdh_np_dtb_table_entry_write(uint32_t dev_id, @@ -5881,6 +6382,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -6989,6 +7494,386 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "get done, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "get fail, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + + case ZXDH_ERAM128_TBL_64b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -7037,6 +7922,13 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index aedc34b193..b1d8b1aef8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1327,6 +1327,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1341,6 +1359,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89996 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v5 14/14] net/zxdh: fix debugging errors 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (12 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-03-19 8:58 ` Bingbin Chen 2025-03-20 19:50 ` Stephen Hemminger 2025-03-21 3:07 ` Bingbin Chen 2025-03-19 9:31 ` [v5,00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen 15 siblings, 2 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 8:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 97798 bytes --] Fix zxdh driver packet sending and receiving errors. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_common.h | 99 ++++++++ drivers/net/zxdh/zxdh_ethdev.c | 19 +- drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +++++---- drivers/net/zxdh/zxdh_ethdev_ops.h | 35 +++ drivers/net/zxdh/zxdh_msg.c | 381 +++++++++++++++++------------ drivers/net/zxdh/zxdh_msg.h | 99 +++++--- drivers/net/zxdh/zxdh_mtr.c | 50 ++-- drivers/net/zxdh/zxdh_mtr.h | 5 + drivers/net/zxdh/zxdh_np.c | 70 +++++- drivers/net/zxdh/zxdh_np.h | 8 +- drivers/net/zxdh/zxdh_pci.c | 24 +- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 12 +- drivers/net/zxdh/zxdh_tables.c | 42 ++-- drivers/net/zxdh/zxdh_tables.h | 68 +++-- 15 files changed, 708 insertions(+), 315 deletions(-) diff --git a/drivers/net/zxdh/zxdh_common.h b/drivers/net/zxdh/zxdh_common.h index d78a822ebf..b34dcddd4d 100644 --- a/drivers/net/zxdh/zxdh_common.h +++ b/drivers/net/zxdh/zxdh_common.h @@ -20,6 +20,105 @@ struct zxdh_res_para { uint16_t src_type; /* refer to BAR_DRIVER_TYPE */ }; +static inline size_t +zxdh_get_value(uint32_t fld_sz, uint8_t *addr) { + size_t result = 0; + switch (fld_sz) { + case 1: + result = *((uint8_t *)addr); + break; + case 2: + result = *((uint16_t *)addr); + break; + case 4: + result = *((uint32_t *)addr); + break; + case 8: + result = *((uint64_t *)addr); + break; + default: + printf("Error: unreachable field size %u\n", fld_sz); + break; + } + return result; +} + +static inline void +zxdh_set_value(uint32_t fld_sz, uint8_t *addr, size_t value) { + switch (fld_sz) { + case 1: + *(uint8_t *)addr = (uint8_t)value; + break; + case 2: + *(uint16_t *)addr = (uint16_t)value; + break; + case 4: + *(uint32_t *)addr = (uint32_t)value; + break; + case 8: + *(uint64_t *)addr = (uint64_t)value; + break; + default: + printf("Error: unreachable field size %u\n", fld_sz); + break; + } +} + +#define __zxdh_nullp(typ) ((struct zxdh_ifc_##typ##_bits *)0) +#define __zxdh_bit_sz(typ, fld) sizeof(__zxdh_nullp(typ)->fld) +#define __zxdh_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ + (&(__zxdh_nullp(typ)->fld))) +#define __zxdh_dw_bit_off(typ, fld) (32 - __zxdh_bit_sz(typ, fld) - \ + (__zxdh_bit_off(typ, fld) & 0x1f)) +#define __zxdh_dw_off(typ, fld) (__zxdh_bit_off(typ, fld) / 32) +#define __zxdh_64_off(typ, fld) (__zxdh_bit_off(typ, fld) / 64) +#define __zxdh_dw_mask(typ, fld) (__zxdh_mask(typ, fld) << \ + __zxdh_dw_bit_off(typ, fld)) +#define __zxdh_mask(typ, fld) ((uint32_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) +#define __zxdh_16_off(typ, fld) (__zxdh_bit_off(typ, fld) / 16) +#define __zxdh_16_bit_off(typ, fld) (16 - __zxdh_bit_sz(typ, fld) - \ + (__zxdh_bit_off(typ, fld) & 0xf)) +#define __zxdh_mask16(typ, fld) ((uint16_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) +#define __zxdh_16_mask(typ, fld) (__zxdh_mask16(typ, fld) << \ + __zxdh_16_bit_off(typ, fld)) +#define ZXDH_ST_SZ_BYTES(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 8) +#define ZXDH_ST_SZ_DW(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 32) +#define ZXDH_BYTE_OFF(typ, fld) (__zxdh_bit_off(typ, fld) / 8) +#define ZXDH_ADDR_OF(typ, p, fld) ((uint8_t *)(p) + ZXDH_BYTE_OFF(typ, fld)) + +#define BUILD_BUG_ON(condition) do { \ + if (condition) \ + __builtin_unreachable(); \ + } while (0) + +#define ZXDH_SET(typ, p, fld, v) do { \ + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ + zxdh_set_value(fld_sz, addr, v); \ +} while (0) + +#define ZXDH_GET(typ, p, fld) ({ \ + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ + zxdh_get_value(fld_sz, addr); \ +}) + +#define ZXDH_SET_ARRAY(typ, p, fld, index, value, type) \ + do { \ + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ + (index) * sizeof(type)); \ + *addr = (type)(value); \ + } while (0) + +#define ZXDH_GET_ARRAY(typ, p, fld, index, type) \ + ({ \ + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ + (index) * sizeof(type)); \ + *addr; \ + }) + int32_t zxdh_phyport_get(struct rte_eth_dev *dev, uint8_t *phyport); int32_t zxdh_panelid_get(struct rte_eth_dev *dev, uint8_t *pannelid); int32_t zxdh_hashidx_get(struct rte_eth_dev *dev, uint8_t *hash_idx); diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea8b18e5e1..ba7ea52d20 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1250,10 +1250,6 @@ zxdh_set_rxtx_funcs(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; - if (!zxdh_pci_packed_queue(hw)) { - PMD_DRV_LOG(ERR, "port %u not support packed queue", eth_dev->data->port_id); - return -1; - } if (!zxdh_pci_with_feature(hw, ZXDH_NET_F_MRG_RXBUF)) { PMD_DRV_LOG(ERR, "port %u not support rx mergeable", eth_dev->data->port_id); return -1; @@ -1498,6 +1494,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) struct zxdh_dtb_bulk_dump_info dtb_dump_baseres[] = { {"sdt_vport_att_table", 4 * 1024 * 1024, ZXDH_SDT_VPORT_ATT_TABLE, NULL}, + {"sdt_vlan_att_table", 4 * 1024 * 1024, ZXDH_SDT_VLAN_ATT_TABLE, NULL}, + {"sdt_rss_table", 4 * 1024 * 1024, ZXDH_SDT_RSS_ATT_TABLE, NULL}, {"sdt_l2_entry_table0", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE0, NULL}, {"sdt_l2_entry_table1", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE1, NULL}, {"sdt_l2_entry_table2", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE2, NULL}, @@ -1514,7 +1512,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) for (i = 0; i < (int)RTE_DIM(dtb_dump_baseres); i++) { struct zxdh_dtb_bulk_dump_info *p = dtb_dump_baseres + i; char buf[ZXDH_MAX_NAME_LEN] = {0}; - + memset(buf, '\0', sizeof(buf)); + sprintf(buf, "%s_%x", p->mz_name, hw->dev_id); p->mz_name = buf; const struct rte_memzone *generic_dump_mz = @@ -1544,6 +1543,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_bar_offset_params param = {0}; struct zxdh_bar_offset_res res = {0}; + char buf[ZXDH_MAX_NAME_LEN] = {0}; struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; @@ -1569,7 +1569,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->vport = hw->vport.vport; dpp_ctrl->vector = ZXDH_MSIX_INTR_DTB_VEC; strlcpy(dpp_ctrl->port_name, dev->device->name, sizeof(dpp_ctrl->port_name)); - dpp_ctrl->pcie_vir_addr = (uint32_t)hw->bar_addr[0]; + dpp_ctrl->pcie_vir_addr = (uint64_t)hw->bar_addr[0]; param.pcie_id = hw->pcie_id; param.virt_addr = hw->bar_addr[0] + ZXDH_CTRLCH_OFFSET; @@ -1584,7 +1584,8 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->np_bar_offset = res.bar_offset; if (!dtb_data->dtb_table_conf_mz) { - const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_conf_mz", + sprintf(buf, "%s_%x", "zxdh_dtb_table_conf_mz", hw->dev_id); + const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_CONF_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (conf_mz == NULL) { @@ -1600,7 +1601,9 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) } if (!dtb_data->dtb_table_dump_mz) { - const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_dump_mz", + memset(buf, '\0', sizeof(buf)); + sprintf(buf, "%s_%x", "zxdh_dtb_table_dump_mz", hw->dev_id); + const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_DUMP_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (dump_mz == NULL) { diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c index 2b02734c62..f8e8d26c50 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.c +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c @@ -15,6 +15,7 @@ #include "zxdh_np.h" #include "zxdh_queue.h" #include "zxdh_mtr.h" +#include "zxdh_common.h" #define ZXDH_VLAN_FILTER_GROUPS 64 #define ZXDH_INVALID_LOGIC_QID 0xFFFFU @@ -278,9 +279,11 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; uint16_t status = 0; int32_t ret = 0; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *link_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, link_msg); if (zxdh_pci_with_feature(hw, ZXDH_NET_F_STATUS)) zxdh_pci_read_dev_config(hw, offsetof(struct zxdh_net_config, status), @@ -295,17 +298,18 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) zxdh_agent_msg_build(hw, ZXDH_MAC_LINK_GET, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_BAR_MODULE_MAC); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_MAC_LINK_GET); return -1; } - link->link_speed = reply_info.reply_body.link_msg.speed; - link->link_autoneg = reply_info.reply_body.link_msg.autoneg; - hw->speed_mode = reply_info.reply_body.link_msg.speed_modes; - if ((reply_info.reply_body.link_msg.duplex & RTE_ETH_LINK_FULL_DUPLEX) == + + link->link_speed = ZXDH_GET(link_info_msg, link_msg_addr, speed); + link->link_autoneg = ZXDH_GET(link_info_msg, link_msg_addr, autoneg); + hw->speed_mode = ZXDH_GET(link_info_msg, link_msg_addr, speed_modes); + if ((ZXDH_GET(link_info_msg, link_msg_addr, duplex) & RTE_ETH_LINK_FULL_DUPLEX) == RTE_ETH_LINK_FULL_DUPLEX) link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; else @@ -433,7 +437,7 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) ret = zxdh_del_mac_table(hw, hw->vport.vport, old_addr, hw->hash_search_index, 0, 0); if (ret) { - PMD_DRV_LOG(ERR, "mac_addr_add failed, code:%d", ret); + PMD_DRV_LOG(ERR, "mac_addr_del failed, code:%d", ret); return ret; } hw->uc_num--; @@ -467,6 +471,8 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) hw->uc_num--; } rte_ether_addr_copy(addr, (struct rte_ether_addr *)hw->mac_addr); + zxdh_pci_write_dev_config(hw, offsetof(struct zxdh_net_config, mac), + &hw->mac_addr, RTE_ETHER_ADDR_LEN); return ret; } @@ -566,7 +572,7 @@ zxdh_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, void zxdh_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) { - struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[index]; uint16_t ret = 0; @@ -1072,7 +1078,9 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, { struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; struct zxdh_msg_info msg = {0}; - struct zxdh_msg_reply_info reply_msg = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_reta_msg); uint16_t idx; uint16_t i; int ret = 0; @@ -1094,21 +1102,21 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, zxdh_msg_head_build(hw, ZXDH_RSS_RETA_GET, &msg); if (hw->is_pf) { - ret = zxdh_rss_table_get(hw, hw->vport.vport, &reply_msg.reply_body.rss_reta); + ret = zxdh_rss_table_get(hw, hw->vport.vport, rss_reta_msg_addr); if (ret) { PMD_DRV_LOG(ERR, "rss reta table set failed"); return -EINVAL; } } else { ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), - &reply_msg, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "vf rss reta table get failed"); return -EINVAL; } } - struct zxdh_rss_reta *reta_table = &reply_msg.reply_body.rss_reta; + struct zxdh_rss_reta *reta_table = rss_reta_msg_addr; for (idx = 0, i = 0; i < reta_size; ++i) { idx = i / RTE_ETH_RETA_GROUP_SIZE; @@ -1232,10 +1240,13 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; struct rte_eth_rss_conf *old_rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; struct zxdh_msg_info msg = {0}; - struct zxdh_msg_reply_info reply_msg = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_hf_msg); struct zxdh_port_attr_table port_attr = {0}; - int ret; + uint32_t rss_hf; uint32_t hw_hf; + int ret; if (rss_conf == NULL) { PMD_DRV_LOG(ERR, "rss conf is NULL"); @@ -1252,16 +1263,17 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con PMD_DRV_LOG(ERR, "rss hash factor set failed"); return -EINVAL; } - reply_msg.reply_body.rss_hf.rss_hf = port_attr.rss_hash_factor; + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, port_attr.rss_hash_factor); } else { ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), - &reply_msg, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "rss hash factor set failed"); return -EINVAL; } } - rss_conf->rss_hf = zxdh_rss_hf_to_eth(reply_msg.reply_body.rss_hf.rss_hf); + rss_hf = ZXDH_GET(rss_hf, rss_hf_msg_addr, rss_hf); + rss_conf->rss_hf = zxdh_rss_hf_to_eth(rss_hf); return 0; } @@ -1382,7 +1394,8 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); enum ZXDH_BAR_MODULE_ID module_id; int ret = 0; @@ -1404,14 +1417,15 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, zxdh_agent_msg_build(hw, opcode, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); if (ret) { PMD_DRV_LOG(ERR, "Failed to get hw stats"); return -1; } - struct zxdh_msg_reply_body *reply_body = &reply_info.reply_body; - memcpy(hw_stats, &reply_body->vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); + void *hw_vqm_stats = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, vqm_stats); + memcpy(hw_stats, hw_vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); + return 0; } @@ -1578,7 +1592,9 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *hw_stas_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_stats); int ret = 0; if (hw->is_pf) { @@ -1590,13 +1606,13 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) } else { zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type", hw->vport.vport); return -1; } - memcpy(np_stats, &reply_info.reply_body.np_stats, sizeof(struct zxdh_hw_np_stats)); + memcpy(np_stats, hw_stas_addr, sizeof(struct zxdh_hw_np_stats)); } return ret; } @@ -1666,7 +1682,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; enum ZXDH_BAR_MODULE_ID module_id; int ret = 0; @@ -1685,7 +1701,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) zxdh_agent_msg_build(hw, opcode, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); if (ret) { PMD_DRV_LOG(ERR, "Failed to reset hw stats"); return -1; @@ -1767,13 +1783,13 @@ zxdh_hw_np_stats_vf_reset(struct rte_eth_dev *dev) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; int ret = 0; msg_info.data.np_stats_query.clear_mode = 1; zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) PMD_DRV_LOG(ERR, "Failed to send ZXDH_PORT_METER_STAT_GET msg. code:%d", ret); @@ -2034,29 +2050,24 @@ zxdh_dev_fw_version_get(struct rte_eth_dev *dev, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *flash_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, flash_msg); char fw_ver[ZXDH_FWVERS_LEN] = {0}; uint32_t ret = 0; zxdh_agent_msg_build(hw, ZXDH_FLASH_FIR_VERSION_GET, &msg_info); - struct zxdh_msg_recviver_mem rsp_data = { - .recv_buffer = (void *)&reply_info, - .buffer_len = sizeof(struct zxdh_msg_reply_info), - }; - ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_MODULE_FLASH); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_FLASH_FIR_VERSION_GET); return -1; } - struct zxdh_msg_reply_body *ack_msg = - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); - memcpy(fw_ver, ack_msg->flash_msg.firmware_version, ZXDH_FWVERS_LEN); + memcpy(fw_ver, flash_msg_addr, ZXDH_FWVERS_LEN); snprintf(fw_version, ZXDH_FWVERS_LEN - 1, "%s", fw_ver); return 0; @@ -2068,7 +2079,7 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; uint8_t ret = 0; zxdh_agent_msg_build(hw, ZXDH_MAC_MODULE_EEPROM_READ, &msg_info); @@ -2079,26 +2090,24 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, msg_info.data.module_eeprom_msg.offset = query->offset; msg_info.data.module_eeprom_msg.length = query->length; - struct zxdh_msg_recviver_mem rsp_data = { - .recv_buffer = (void *)&reply_info, - .buffer_len = sizeof(struct zxdh_msg_reply_info), - }; - ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_BAR_MODULE_MAC); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_MAC_MODULE_EEPROM_READ); return -1; } - struct zxdh_msg_reply_body *ack_msg = - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); - + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *module_eeprom_msg_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, module_eeprom_msg); + void *agent_mac_module_eeprom_msg_data_addr = + ZXDH_ADDR_OF(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, data); + uint8_t length = ZXDH_GET(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, length); if (data) - memcpy(data, ack_msg->module_eeprom_msg.data, ack_msg->module_eeprom_msg.length); + memcpy(data, agent_mac_module_eeprom_msg_data_addr, length); - return ack_msg->module_eeprom_msg.length; + return length; } int diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.h b/drivers/net/zxdh/zxdh_ethdev_ops.h index a5162a6d6b..97a1eb4532 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.h +++ b/drivers/net/zxdh/zxdh_ethdev_ops.h @@ -62,6 +62,30 @@ struct zxdh_hw_np_stats { uint64_t tx_ssvpc_pkts; }; +struct zxdh_ifc_hw_np_stats_bits { + uint8_t rx_unicast_pkts[0x40]; + uint8_t tx_unicast_pkts[0x40]; + uint8_t rx_unicast_bytes[0x40]; + uint8_t tx_unicast_bytes[0x40]; + uint8_t rx_multicast_pkts[0x40]; + uint8_t tx_multicast_pkts[0x40]; + uint8_t rx_multicast_bytes[0x40]; + uint8_t tx_multicast_bytes[0x40]; + uint8_t rx_broadcast_pkts[0x40]; + uint8_t tx_broadcast_pkts[0x40]; + uint8_t rx_broadcast_bytes[0x40]; + uint8_t tx_broadcast_bytes[0x40]; + uint8_t rx_mtu_drop_pkts[0x40]; + uint8_t tx_mtu_drop_pkts[0x40]; + uint8_t rx_mtu_drop_bytes[0x40]; + uint8_t tx_mtu_drop_bytes[0x40]; + uint8_t rx_mtr_drop_pkts[0x40]; + uint8_t tx_mtr_drop_pkts[0x40]; + uint8_t rx_mtr_drop_bytes[0x40]; + uint8_t tx_mtr_drop_bytes[0x40]; + uint8_t tx_ssvpc_pkts[0x40]; +}; + struct zxdh_hw_vqm_stats { uint64_t rx_total; uint64_t tx_total; @@ -72,6 +96,17 @@ struct zxdh_hw_vqm_stats { uint64_t rx_drop; }; +struct zxdh_ifc_hw_vqm_stats_bits { + uint8_t rx_total[0x40]; + uint8_t tx_total[0x40]; + uint8_t rx_bytes[0x40]; + uint8_t tx_bytes[0x40]; + uint8_t rx_error[0x40]; + uint8_t tx_error[0x40]; + uint8_t rx_drop[0x40]; +}; + + int zxdh_dev_set_link_up(struct rte_eth_dev *dev); int zxdh_dev_set_link_down(struct rte_eth_dev *dev); int32_t zxdh_dev_link_update(struct rte_eth_dev *dev, int32_t wait_to_complete); diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c index 96ad638e83..02ecd93b12 100644 --- a/drivers/net/zxdh/zxdh_msg.c +++ b/drivers/net/zxdh/zxdh_msg.c @@ -18,6 +18,7 @@ #include "zxdh_pci.h" #include "zxdh_tables.h" #include "zxdh_np.h" +#include "zxdh_common.h" #define ZXDH_REPS_INFO_FLAG_USABLE 0x00 #define ZXDH_BAR_SEQID_NUM_MAX 256 @@ -695,7 +696,7 @@ static uint16_t zxdh_bar_chan_sync_msg_reps_get(uint64_t subchan_addr, uint64_t recv_buffer, uint16_t buffer_len) { - struct zxdh_bar_msg_header msg_header = {0}; + struct zxdh_bar_msg_header msg_header; uint16_t msg_id = 0; uint16_t msg_len = 0; @@ -987,7 +988,7 @@ zxdh_bar_chan_msg_header_check(struct zxdh_bar_msg_header *msg_header) int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev) { - struct zxdh_bar_msg_header msg_header = {0}; + struct zxdh_bar_msg_header msg_header; uint64_t recv_addr = 0; uint64_t reps_addr = 0; uint16_t ret = 0; @@ -1083,22 +1084,20 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_recviver_mem result = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; int ret = 0; if (reply) { - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); result.recv_buffer = reply; result.buffer_len = reply_len; } else { - result.recv_buffer = &reply_info; - result.buffer_len = sizeof(reply_info); + result.recv_buffer = zxdh_msg_reply_info; + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); } - struct zxdh_msg_reply_head *reply_head = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); - struct zxdh_msg_reply_body *reply_body = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); + void *reply_head_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_head); + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_body); struct zxdh_pci_bar_msg in = { .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + @@ -1118,12 +1117,16 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, "vf[%d] send bar msg to pf failed.ret %d", hw->vport.vfid, ret); return -1; } - if (reply_head->flag != ZXDH_MSG_REPS_OK) { + + uint8_t flag = ZXDH_GET(msg_reply_head, reply_head_addr, flag); + uint16_t reps_len = ZXDH_GET(msg_reply_head, reply_head_addr, reps_len); + if (flag != ZXDH_MSG_REPS_OK) { PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", - hw->vport.vfid, reply_head->flag, reply_head->reps_len); + hw->vport.vfid, flag, reps_len); return -1; } - if (reply_body->flag != ZXDH_REPS_SUCC) { + uint8_t reply_body_flag = ZXDH_GET(msg_reply_body, reply_body_addr, flag); + if (reply_body_flag != ZXDH_REPS_SUCC) { PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); return -1; } @@ -1137,23 +1140,19 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_recviver_mem result = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; if (reply) { - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); result.recv_buffer = reply; result.buffer_len = reply_len; } else { - result.recv_buffer = &reply_info; - result.buffer_len = sizeof(reply_info); + result.recv_buffer = zxdh_msg_reply_info; + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); } - struct zxdh_msg_reply_head *reply_head = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); - struct zxdh_msg_reply_body *reply_body = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); struct zxdh_pci_bar_msg in = { - .payload_addr = &msg_req, + .payload_addr = msg_req, .payload_len = msg_req_len, .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + ZXDH_CTRLCH_OFFSET), .src = hw->is_pf ? ZXDH_MSG_CHAN_END_PF : ZXDH_MSG_CHAN_END_VF, @@ -1166,15 +1165,6 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, PMD_MSG_LOG(ERR, "Failed to send sync messages or receive response"); return -1; } - if (reply_head->flag != ZXDH_MSG_REPS_OK) { - PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", - hw->vport.vfid, reply_head->flag, reply_head->reps_len); - return -1; - } - if (reply_body->flag != ZXDH_REPS_SUCC) { - PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); - return -1; - } return 0; } @@ -1245,7 +1235,7 @@ zxdh_vf_promisc_uninit(struct zxdh_hw *hw, union zxdh_virport_num vport) static int zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { struct zxdh_port_attr_table port_attr = {0}; union zxdh_virport_num port = {.vport = vport}; @@ -1275,14 +1265,13 @@ zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, PMD_DRV_LOG(ERR, "vf_promisc_table_init failed, code:%d", ret); goto proc_end; } - - res_info->flag = ZXDH_REPS_SUCC; - *res_len = sizeof(res_info->flag); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); + *res_len = sizeof(uint8_t); return ret; proc_end: - *res_len = sizeof(res_info->flag); - res_info->flag = ZXDH_REPS_FAIL; + *res_len = sizeof(uint8_t); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } @@ -1311,11 +1300,12 @@ zxdh_mac_clear(struct zxdh_hw *hw, union zxdh_virport_num vport) static int zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "uninit"; struct zxdh_port_attr_table port_attr = {0}; union zxdh_virport_num vport_num = {.vport = vport}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); int ret = 0; *res_len = ZXDH_MSG_REPLYBODY_HEAD; @@ -1340,20 +1330,20 @@ zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, } *res_len += strlen(str); - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return ret; proc_end: *res_len += strlen(str); - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_FAIL; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply_body, uint16_t *reply_len) + void *reply_body, uint16_t *reply_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "add mac"; union zxdh_virport_num port = {0}; @@ -1362,6 +1352,8 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, int i = 0, ret = 0; uint16_t vf_id = port.vfid; port.vport = vport; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, reply_data); + void *mac_reply_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, mac_reply_msg); for (i = 0; i < ZXDH_MAX_MAC_ADDRS; i++) if (rte_is_same_ether_addr(&hw->vfinfo[vf_id].vf_mac[i], addr)) @@ -1369,7 +1361,7 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, ret = zxdh_add_mac_table(hw, vport, addr, hw->hash_search_index, 0, 0); if (ret == -EADDRINUSE) { - reply_body->mac_reply_msg.mac_flag = ZXDH_EEXIST_MAC_FLAG; + ZXDH_SET(mac_reply_msg, mac_reply_msg_addr, mac_flag, ZXDH_EEXIST_MAC_FLAG); PMD_DRV_LOG(ERR, "vf vport 0x%x set mac ret 0x%x failed. mac is in used.", port.vport, ret); goto failure; @@ -1389,26 +1381,27 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, success: sprintf(str, " vport 0x%x set mac ret 0x%x\n", port.vport, ret); *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - rte_memcpy(&reply_body->reply_data, str, strlen(str) + 1); - reply_body->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_SUCC); PMD_DRV_LOG(DEBUG, " reply len %d", *reply_len); return ret; failure: *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - reply_body->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { int ret, i = 0; struct zxdh_mac_filter *mac_filter = (struct zxdh_mac_filter *)cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "del mac"; uint16_t vf_id = port.vfid; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); PMD_DRV_LOG(DEBUG, "[PF GET MSG FROM VF]--vf mac to del."); ret = zxdh_del_mac_table(hw, vport, &mac_filter->mac, hw->hash_search_index, 0, 0); @@ -1428,19 +1421,19 @@ zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, sprintf(str, "vport 0x%x del mac ret 0x%x\n", port.vport, ret); *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return ret; proc_end: *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_port_promisc_msg *promisc_msg = (struct zxdh_port_promisc_msg *)cfg_data; int ret = 0; @@ -1458,24 +1451,25 @@ zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, goto proc_end; } - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); - reply->flag = ZXDH_REPS_SUCC; + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); return ret; proc_end: - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); - reply->flag = ZXDH_REPS_FAIL; + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len, uint8_t enable) + void *res_info, uint16_t *res_len, uint8_t enable) { struct zxdh_vlan_filter *vlan_filter = cfg_data; uint16_t vlan_id = vlan_filter->vlan_id; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter table"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); int ret = 0; ret = zxdh_vlan_filter_table_set(hw, vport, vlan_id, enable); @@ -1483,33 +1477,38 @@ zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_ sprintf(str, "vlan filter op-code[%d] vlan id:%d failed, code:%d\n", enable, vlan_id, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; + *res_len = strlen(str) + sizeof(uint8_t); + + memcpy(reply_data_addr, str, strlen(str) + 1); + if (ret == 0) + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_vlan_filter_table_add(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 1); } static int zxdh_vf_vlan_filter_table_del(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 0); } static int zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_vlan_filter_set *vlan_filter = cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; uint16_t vfid = port.vfid; @@ -1517,19 +1516,23 @@ zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, if (ret) sprintf(str, "[vfid:%d] vlan filter. set failed, ret:%d\n", vfid, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_vlan_offload *vlan_offload = cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan offload"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; uint16_t vfid = port.vfid; @@ -1540,18 +1543,23 @@ zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, if (ret) sprintf(str, "[vfid:%d] vlan offload set failed, ret:%d\n", vfid, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_hf_msg); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1561,22 +1569,26 @@ zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unus goto proc_end; } - reply->rss_hf.rss_hf = vport_att.rss_hash_factor; + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, vport_att.rss_hash_factor); proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; struct zxdh_rss_hf *rss_hf = cfg_data; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1596,19 +1608,23 @@ zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, } proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_enable"; struct zxdh_rss_enable *rss_enable = cfg_data; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1628,51 +1644,63 @@ zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, } proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_table_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; struct zxdh_rss_reta *rss_reta = cfg_data; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int32_t ret = 0; ret = zxdh_rss_table_set(hw, vport, rss_reta); if (ret) sprintf(str, "set rss reta tbl failed, code:%d", ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_table_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; - struct zxdh_rss_reta *rss_reta = &reply->rss_reta; + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_reta_msg); + struct zxdh_rss_reta *rss_reta = (struct zxdh_rss_reta *)rss_reta_msg_addr; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_rss_table_get(hw, vport, rss_reta); if (ret) sprintf(str, "set rss reta tbl failed, code:%d", ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { RTE_ASSERT(!cfg_data || !pf_hw); if (res_info) @@ -1734,7 +1762,7 @@ zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, static int zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, - void *cfg_data, struct zxdh_msg_reply_body *res_info, + void *cfg_data, void *res_info, uint16_t *res_len) { struct zxdh_np_stats_updata_msg *np_stats_query = @@ -1745,6 +1773,47 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, uint32_t idx = 0; int ret = 0; + void *hw_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_stats); + void *tx_unicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_pkts); + void *rx_unicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_pkts); + void *tx_unicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_bytes); + void *rx_unicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_bytes); + void *tx_multicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_pkts); + void *rx_multicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_pkts); + void *tx_multicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_bytes); + void *rx_multicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_bytes); + void *tx_broadcast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_pkts); + void *tx_broadcast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_bytes); + void *rx_broadcast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_pkts); + void *rx_broadcast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_bytes); + void *tx_mtu_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts); + void *tx_mtu_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes); + void *rx_mtu_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts); + void *rx_mtu_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes); + void *tx_mtr_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts); + void *tx_mtr_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes); + void *rx_mtr_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts); + void *rx_mtr_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes); if (!res_len || !res_info) { PMD_DRV_LOG(ERR, "get stat invalid inparams"); return -1; @@ -1760,8 +1829,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_bytes); + zxdh_data_hi_to_lo(tx_unicast_pkts_addr); + zxdh_data_hi_to_lo(tx_unicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_UNICAST_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1771,8 +1840,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_bytes); + zxdh_data_hi_to_lo(rx_unicast_pkts_addr); + zxdh_data_hi_to_lo(rx_unicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_EGRESS_BASE; ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, @@ -1781,8 +1850,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_bytes); + zxdh_data_hi_to_lo(tx_multicast_pkts_addr); + zxdh_data_hi_to_lo(tx_multicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1792,8 +1861,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_bytes); + zxdh_data_hi_to_lo(rx_multicast_pkts_addr); + zxdh_data_hi_to_lo(rx_multicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_EGRESS_BASE; ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, @@ -1802,8 +1871,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_bytes); + zxdh_data_hi_to_lo(tx_broadcast_pkts_addr); + zxdh_data_hi_to_lo(tx_broadcast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1813,8 +1882,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_bytes); + zxdh_data_hi_to_lo(rx_broadcast_pkts_addr); + zxdh_data_hi_to_lo(rx_broadcast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_EGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1824,10 +1893,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.tx_mtu_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.tx_mtu_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes, stats_data.n_bytes_dropped); + zxdh_data_hi_to_lo(tx_mtu_drop_pkts_addr); + zxdh_data_hi_to_lo(tx_mtu_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1837,10 +1906,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.rx_mtu_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.rx_mtu_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes, stats_data.n_bytes_dropped); + zxdh_data_hi_to_lo(rx_mtu_drop_pkts_addr); + zxdh_data_hi_to_lo(rx_mtu_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_EGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1850,10 +1919,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.tx_mtr_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.tx_mtr_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes, stats_data.n_bytes_dropped); + + zxdh_data_hi_to_lo(tx_mtr_drop_pkts_addr); + zxdh_data_hi_to_lo(tx_mtr_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1863,10 +1933,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.rx_mtr_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.rx_mtr_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes, stats_data.n_bytes_dropped); + + zxdh_data_hi_to_lo(rx_mtr_drop_pkts_addr); + zxdh_data_hi_to_lo(rx_mtr_drop_bytes_addr); *res_len = sizeof(struct zxdh_hw_np_stats); return 0; @@ -1875,12 +1946,13 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, static int zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = (struct zxdh_mtr_stats_query *)cfg_data; union zxdh_virport_num v_port = {.vport = vport}; + uint8_t *hw_mtr_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_mtr_stats); int ret = 0; uint32_t stat_baseaddr = zxdh_mtr_stats_query->direction == @@ -1892,14 +1964,14 @@ zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, PMD_DRV_LOG(ERR, "get stat invalid in params"); return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, - 1, idx, (uint32_t *)&res_info->hw_mtr_stats); + 1, idx, (uint32_t *)hw_mtr_stats_addr); if (ret) { PMD_DRV_LOG(ERR, "get dir %d stats failed", zxdh_mtr_stats_query->direction); return ret; } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); *res_len = sizeof(struct zxdh_hw_mtr_stats); return 0; } @@ -1908,7 +1980,7 @@ static int zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { if (!cfg_data || !res_len || !res_info) { @@ -1917,16 +1989,18 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, } struct rte_mtr_error error = {0}; int ret = 0; - uint64_t profile_id = HW_PROFILE_MAX; + uint64_t hw_profile_id = HW_PROFILE_MAX; + void *mtr_profile_info_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, mtr_profile_info); struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = (struct zxdh_plcr_profile_add *)cfg_data; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); + *res_len = sizeof(struct zxdh_mtr_profile_info); ret = zxdh_hw_profile_alloc_direct(pf_hw->eth_dev, zxdh_plcr_profile_add->car_type, - &profile_id, &error); + &hw_profile_id, &error); if (ret) { PMD_DRV_LOG(ERR, "pf 0x%x for vf 0x%x alloc hw profile failed", @@ -1935,9 +2009,9 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, ); return -1; } - zxdh_hw_profile_ref(profile_id); - res_info->mtr_profile_info.profile_id = profile_id; - res_info->flag = ZXDH_REPS_SUCC; + zxdh_hw_profile_ref(hw_profile_id); + ZXDH_SET(mtr_profile_info, mtr_profile_info_addr, profile_id, hw_profile_id); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -1946,7 +2020,7 @@ static int zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { if (!cfg_data || !res_len || !res_info) { @@ -1954,7 +2028,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; struct zxdh_plcr_profile_free *mtr_profile_free = (struct zxdh_plcr_profile_free *)cfg_data; uint64_t profile_id = mtr_profile_free->profile_id; @@ -1980,7 +2054,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, "Meter offload del profile failed "); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -1988,7 +2062,7 @@ static int zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { int ret = 0; @@ -2000,7 +2074,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, struct rte_mtr_error error = {0}; struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = (struct zxdh_plcr_flow_cfg *)cfg_data; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; ret = zxdh_np_stat_car_queue_cfg_set(pf_hw->dev_id, zxdh_plcr_flow_cfg->car_type, @@ -2019,7 +2093,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, "Failed to bind plcr flow."); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -2027,7 +2101,7 @@ static int zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { int ret = 0; @@ -2036,14 +2110,15 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, PMD_DRV_LOG(ERR, " cfg profile invalid inparams"); return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; struct rte_mtr_error error = {0}; struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = (struct zxdh_plcr_profile_cfg *)cfg_data; union zxdh_offload_profile_cfg *plcr_param = &zxdh_plcr_profile_cfg->plcr_param; - ret = zxdh_np_car_profile_cfg_set(vport, + ret = zxdh_np_car_profile_cfg_set(pf_hw->dev_id, + vport, zxdh_plcr_profile_cfg->car_type, zxdh_plcr_profile_cfg->packet_mode, zxdh_plcr_profile_cfg->hw_profile_id, @@ -2052,7 +2127,7 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, PMD_DRV_LOG(ERR, "(vport %d)config hw profilefailed", vport); return -rte_mtr_error_set(&error, ENOTSUP, RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, "Meter offload cfg profile failed"); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -2083,7 +2158,7 @@ static const zxdh_msg_process_callback zxdh_proc_cb[] = { static inline int zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, - struct zxdh_msg_reply_body *res, uint16_t *res_len) + void *res, uint16_t *res_len) { struct zxdh_msg_head *msghead = &msg_info->msg_head; int ret = -1; @@ -2096,13 +2171,13 @@ zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, ret = zxdh_proc_cb[msghead->msg_type](hw, msghead->vport, (void *)&msg_info->data, res, res_len); if (!ret) - res->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_SUCC); else - res->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_FAIL); } else { - res->flag = ZXDH_REPS_INVALID; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_INVALID); } - *res_len += sizeof(res->flag); + *res_len += sizeof(uint8_t); return ret; } @@ -2111,7 +2186,7 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *eth_dev) { struct zxdh_msg_info *msg_info = (struct zxdh_msg_info *)pay_load; - struct zxdh_msg_reply_body *reply_body = reps_buffer; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reps_buffer, reply_data); struct rte_eth_dev *dev = (struct rte_eth_dev *)eth_dev; int32_t ret = 0; struct zxdh_hw *hw; @@ -2131,14 +2206,14 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, goto msg_proc_end; } - ret = zxdh_config_process_callback(hw, msg_info, reply_body, &reply_len); - *reps_len = reply_len + sizeof(struct zxdh_msg_reply_head); + ret = zxdh_config_process_callback(hw, msg_info, reps_buffer, &reply_len); + *reps_len = reply_len + ZXDH_ST_SZ_BYTES(msg_reply_head); return ret; msg_proc_end: - memcpy(reply_body->reply_data, &ret, sizeof(ret)); + memcpy(reply_data_addr, &ret, sizeof(ret)); reply_len = sizeof(ret); - *reps_len = sizeof(struct zxdh_msg_reply_head) + reply_len; + *reps_len = ZXDH_ST_SZ_BYTES(msg_reply_head) + reply_len; return ret; } diff --git a/drivers/net/zxdh/zxdh_msg.h b/drivers/net/zxdh/zxdh_msg.h index 58836bb4b7..7dad6f7335 100644 --- a/drivers/net/zxdh/zxdh_msg.h +++ b/drivers/net/zxdh/zxdh_msg.h @@ -11,6 +11,7 @@ #include "zxdh_ethdev_ops.h" #include "zxdh_mtr.h" +#include "zxdh_common.h" #define ZXDH_BAR0_INDEX 0 #define ZXDH_CTRLCH_OFFSET (0x2000) @@ -46,8 +47,10 @@ #define ZXDH_MSG_REPLYBODY_HEAD sizeof(enum zxdh_reps_flag) #define ZXDH_MSG_HEADER_SIZE 4 -#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ - (ZXDH_MSG_PAYLOAD_MAX_LEN - sizeof(struct zxdh_msg_reply_head)) +#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ + (ZXDH_MSG_PAYLOAD_MAX_LEN - ZXDH_MSG_HEADER_SIZE) +#define ZXDH_MSG_REPLY_DATA \ + (ZXDH_MSG_REPLY_BODY_MAX_LEN - ZXDH_MSG_REPLYBODY_HEAD) #define ZXDH_MSG_HEAD_LEN 8 #define ZXDH_MSG_REQ_BODY_MAX_LEN \ @@ -329,12 +332,6 @@ struct zxdh_offset_get_msg { uint16_t type; }; -struct zxdh_msg_reply_head { - uint8_t flag; - uint16_t reps_len; - uint8_t resvd; -}; - enum zxdh_reps_flag { ZXDH_REPS_FAIL, ZXDH_REPS_SUCC = 0xaa, @@ -354,18 +351,39 @@ struct zxdh_link_info_msg { uint32_t speed; }; +struct zxdh_ifc_link_info_msg_bits { + uint8_t autoneg[0x8]; + uint8_t link_state[0x8]; + uint8_t blink_enable[0x8]; + uint8_t duplex[0x8]; + uint8_t speed_modes[0x20]; + uint8_t speed[0x20]; +}; + struct zxdh_rss_reta { uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256]; }; +struct zxdh_ifc_rss_reta_bits { + uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256 * 8]; +}; + struct zxdh_rss_hf { uint32_t rss_hf; }; +struct zxdh_ifc_rss_hf_bits { + uint8_t rss_hf[0x20]; +}; + struct zxdh_mac_reply_msg { uint8_t mac_flag; }; +struct zxdh_ifc_mac_reply_msg_bits { + uint8_t mac_flag[0x8]; +}; + struct zxdh_mac_module_eeprom_msg { uint8_t i2c_addr; uint8_t bank; @@ -375,34 +393,57 @@ struct zxdh_mac_module_eeprom_msg { uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN]; }; +struct zxdh_ifc_agent_mac_module_eeprom_msg_bits { + uint8_t i2c_addr[0x8]; + uint8_t bank[0x8]; + uint8_t page[0x8]; + uint8_t offset[0x8]; + uint8_t length[0x8]; + uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN * 8]; +}; + struct zxdh_flash_msg { uint8_t firmware_version[ZXDH_FWVERS_LEN]; }; +struct zxdh_ifc_agent_flash_msg_bits { + uint8_t firmware_version[0x100]; +}; + struct zxdh_mtr_profile_info { uint64_t profile_id; }; -struct zxdh_msg_reply_body { - enum zxdh_reps_flag flag; +struct zxdh_ifc_mtr_profile_info_bits { + uint8_t profile_id[0x40]; +}; + +struct zxdh_ifc_msg_reply_body_bits { + uint8_t flag[0x8]; union { - uint8_t reply_data[ZXDH_MSG_REPLY_BODY_MAX_LEN - sizeof(enum zxdh_reps_flag)]; - struct zxdh_hw_np_stats np_stats; - struct zxdh_link_info_msg link_msg; - struct zxdh_rss_reta rss_reta; - struct zxdh_rss_hf rss_hf; - struct zxdh_hw_vqm_stats vqm_stats; - struct zxdh_mac_reply_msg mac_reply_msg; - struct zxdh_flash_msg flash_msg; - struct zxdh_mac_module_eeprom_msg module_eeprom_msg; - struct zxdh_mtr_profile_info mtr_profile_info; - struct zxdh_mtr_stats hw_mtr_stats; + uint8_t reply_data[ZXDH_MSG_REPLY_DATA * 8]; + struct zxdh_ifc_hw_np_stats_bits hw_stats; + struct zxdh_ifc_link_info_msg_bits link_msg; + struct zxdh_ifc_rss_reta_bits rss_reta_msg; + struct zxdh_ifc_rss_hf_bits rss_hf_msg; + struct zxdh_ifc_hw_vqm_stats_bits vqm_stats; + struct zxdh_ifc_mac_reply_msg_bits mac_reply_msg; + struct zxdh_ifc_agent_flash_msg_bits flash_msg; + struct zxdh_ifc_agent_mac_module_eeprom_msg_bits module_eeprom_msg; + struct zxdh_ifc_mtr_profile_info_bits mtr_profile_info; + struct zxdh_ifc_mtr_stats_bits hw_mtr_stats; }; }; -struct zxdh_msg_reply_info { - struct zxdh_msg_reply_head reply_head; - struct zxdh_msg_reply_body reply_body; +struct zxdh_ifc_msg_reply_head_bits { + uint8_t flag[0x8]; + uint8_t reps_len[0x10]; + uint8_t resvd[0x8]; +}; + +struct zxdh_ifc_msg_reply_info_bits { + struct zxdh_ifc_msg_reply_head_bits reply_head; + struct zxdh_ifc_msg_reply_body_bits reply_body; }; struct zxdh_vf_init_msg { @@ -412,12 +453,12 @@ struct zxdh_vf_init_msg { uint8_t rss_enable; }; -struct zxdh_msg_head { - enum zxdh_msg_type msg_type; +struct __rte_packed_begin zxdh_msg_head { + uint8_t msg_type; uint16_t vport; uint16_t vf_id; uint16_t pcieid; -}; +} __rte_packed_end; struct zxdh_port_attr_set_msg { uint32_t mode; @@ -455,7 +496,7 @@ struct zxdh_rss_enable { }; struct zxdh_agent_msg_head { - enum zxdh_agent_msg_type msg_type; + uint8_t msg_type; uint8_t panel_id; uint8_t phyport; uint8_t rsv; @@ -526,7 +567,7 @@ struct zxdh_msg_info { typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); typedef int (*zxdh_msg_process_callback)(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len); + void *res_info, uint16_t *res_len); typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c index 3797a5b29b..b23f6535a8 100644 --- a/drivers/net/zxdh/zxdh_mtr.c +++ b/drivers/net/zxdh/zxdh_mtr.c @@ -281,7 +281,7 @@ zxdh_hw_profile_free_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type, { struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_delete(vport, car_type, + int ret = zxdh_np_car_profile_id_delete(hw->dev_id, vport, car_type, (uint64_t)hw_profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u free hw profile %u failed", vport, hw_profile_id); @@ -299,7 +299,7 @@ zxdh_hw_profile_alloc_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type uint64_t profile_id = HW_PROFILE_MAX; struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_add(vport, car_type, &profile_id); + int ret = zxdh_np_car_profile_id_add(hw->dev_id, vport, car_type, &profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u alloc hw profile failed", vport); @@ -326,7 +326,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, ret = zxdh_hw_profile_free_direct(dev, car_type, (uint64_t)hw_profile_id, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_free *zxdh_plcr_profile_free = &msg_info.data.zxdh_plcr_profile_free; @@ -335,7 +335,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_DELETE, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_free), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) return -rte_mtr_error_set(error, ENOTSUP, @@ -357,15 +357,19 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, ret = zxdh_hw_profile_alloc_direct(dev, CAR_A, hw_profile_id, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = &msg_info.data.zxdh_plcr_profile_add; + void *reply_body_addr = + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *mtr_profile_info_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, mtr_profile_info); zxdh_plcr_profile_add->car_type = CAR_A; zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_ADD, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_add), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, @@ -376,7 +380,7 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, "Meter offload alloc profile id msg failed "); } - *hw_profile_id = reply_info.reply_body.mtr_profile_info.profile_id; + *hw_profile_id = ZXDH_GET(mtr_profile_info, mtr_profile_info_addr, profile_id); if (*hw_profile_id == ZXDH_HW_PROFILE_MAX) { return -rte_mtr_error_set(error, ENOTSUP, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, @@ -432,7 +436,7 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, } } else { /* send msg to pf */ struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = &msg_info.data.zxdh_mtr_stats_query; @@ -442,8 +446,8 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(msg_info), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, @@ -451,7 +455,11 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, hw->vport.vport); return -rte_mtr_error_set(error, ENOTSUP, RTE_MTR_ERROR_TYPE_STATS, NULL, "Meter offload alloc profile failed"); } - struct zxdh_mtr_stats *hw_mtr_stats = &reply_info.reply_body.hw_mtr_stats; + void *reply_body_addr = + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *hw_mtr_stats_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_mtr_stats); + struct zxdh_mtr_stats *hw_mtr_stats = (struct zxdh_mtr_stats *)hw_mtr_stats_addr; mtr_stats->n_bytes_dropped = hw_mtr_stats->n_bytes_dropped; mtr_stats->n_pkts_dropped = hw_mtr_stats->n_pkts_dropped; @@ -551,7 +559,9 @@ zxdh_hw_profile_config_direct(struct rte_eth_dev *dev __rte_unused, struct zxdh_meter_profile *mp, struct rte_mtr_error *error) { - int ret = zxdh_np_car_profile_cfg_set(mp->hw_profile_owner_vport, + struct zxdh_hw *hw = dev->data->dev_private; + int ret = zxdh_np_car_profile_cfg_set(hw->dev_id, + mp->hw_profile_owner_vport, car_type, mp->profile.packet_mode, (uint32_t)hw_profile_id, &mp->plcr_param); if (ret) { @@ -573,7 +583,7 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i ret = zxdh_hw_profile_config_direct(dev, CAR_A, hw_profile_id, mp, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = &msg_info.data.zxdh_plcr_profile_cfg; @@ -588,9 +598,9 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_cfg), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); - + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info) + ); if (ret) { PMD_DRV_LOG(ERR, "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_PROFILE_CFG_SET ", @@ -874,7 +884,7 @@ zxdh_set_mtr_enable(struct rte_eth_dev *dev, uint8_t dir, bool enable, struct rt if (priv->is_pf) { ret = zxdh_get_port_attr(priv, priv->vport.vport, &port_attr); - port_attr.ingress_meter_enable = enable; + port_attr.egress_meter_enable = enable; ret = zxdh_set_port_attr(priv, priv->vport.vport, &port_attr); if (ret) { PMD_DRV_LOG(ERR, "%s set port attr failed", __func__); @@ -936,7 +946,7 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, } } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = &msg_info.data.zxdh_plcr_flow_cfg; zxdh_plcr_flow_cfg->car_type = CAR_A; @@ -947,8 +957,8 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_QUEUE_CFG_SET, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_flow_cfg), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_QUEUE_CFG_SET ", diff --git a/drivers/net/zxdh/zxdh_mtr.h b/drivers/net/zxdh/zxdh_mtr.h index 749ceb7479..3efcb6b591 100644 --- a/drivers/net/zxdh/zxdh_mtr.h +++ b/drivers/net/zxdh/zxdh_mtr.h @@ -93,6 +93,11 @@ struct zxdh_mtr_stats { uint64_t n_bytes_dropped; }; +struct zxdh_ifc_mtr_stats_bits { + uint8_t n_pkts_dropped[0x40]; + uint8_t n_bytes_dropped[0x40]; +}; + struct zxdh_hw_mtr_stats { uint32_t n_pkts_dropped_hi; uint32_t n_pkts_dropped_lo; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index ab8b3ae688..66902e7e92 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2350,6 +2350,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); @@ -3391,6 +3393,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -10542,9 +10570,9 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) uint32_t done_flag = 0; while (!done_flag) { - rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, "reg_read fail!"); + PMD_DRV_LOG(ERR, "reg_read32 fail!"); return rc; } @@ -10577,10 +10605,17 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t temp_data[4] = {0}; uint32_t *p_temp_data = NULL; ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_ind_spinlock->spinlock); rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -10592,11 +10627,13 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { + rte_spinlock_unlock(&p_ind_spinlock->spinlock); PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; @@ -10604,6 +10641,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; @@ -10612,6 +10650,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; @@ -10620,6 +10659,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; @@ -10638,10 +10678,12 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7); @@ -10650,6 +10692,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6); @@ -10658,6 +10701,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5); @@ -10665,7 +10709,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, break; case ZXDH_ERAM128_OPR_1b: PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", - rd_clr_mode, rd_mode); + rd_clr_mode, rd_mode); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; default: break; @@ -10680,12 +10725,14 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, &cpu_ind_cmd); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -10698,6 +10745,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, p_temp_data + 3 - i); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } } @@ -10736,6 +10784,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, } } + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return rc; } @@ -10789,7 +10839,7 @@ zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MS { uint32_t ret = 0; ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { - .msg = (void *)&p_msg, + .msg = (void *)p_msg, .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), }; @@ -11012,7 +11062,8 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, } uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id) { @@ -11027,7 +11078,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(dev_id, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -11045,14 +11096,14 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, } uint32_t -zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, +zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id __rte_unused, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg) { uint32_t ret = 0; - uint32_t dev_id = 0; ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); @@ -11065,11 +11116,10 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, } uint32_t -zxdh_np_car_profile_id_delete(uint32_t vport_id, +zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t dev_id = 0; uint32_t profileid = profile_id & 0xFFFF; ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b1d8b1aef8..1b8f17474d 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1934,15 +1934,17 @@ uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, uint32_t clr_mode, uint32_t *p_data); uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id); -uint32_t zxdh_np_car_profile_cfg_set(uint32_t vport_id, +uint32_t zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg); -uint32_t zxdh_np_car_profile_id_delete(uint32_t vport_id, +uint32_t zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id); uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t car_type, diff --git a/drivers/net/zxdh/zxdh_pci.c b/drivers/net/zxdh/zxdh_pci.c index 3d1a3ff0dd..4ff0f065df 100644 --- a/drivers/net/zxdh/zxdh_pci.c +++ b/drivers/net/zxdh/zxdh_pci.c @@ -27,6 +27,23 @@ 1ULL << ZXDH_F_NOTIFICATION_DATA | \ 1ULL << ZXDH_NET_F_MAC) +#define ZXDH_PMD_DEFAULT_HOST_FEATURES \ + (1ULL << ZXDH_NET_F_MRG_RXBUF | \ + 1ULL << ZXDH_NET_F_STATUS | \ + 1ULL << ZXDH_NET_F_MQ | \ + 1ULL << ZXDH_F_ANY_LAYOUT | \ + 1ULL << ZXDH_F_VERSION_1 | \ + 1ULL << ZXDH_F_RING_PACKED | \ + 1ULL << ZXDH_F_IN_ORDER | \ + 1ULL << ZXDH_F_NOTIFICATION_DATA |\ + 1ULL << ZXDH_NET_F_MAC | \ + 1ULL << ZXDH_NET_F_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_TSO4 |\ + 1ULL << ZXDH_NET_F_GUEST_TSO6 |\ + 1ULL << ZXDH_NET_F_HOST_TSO4 |\ + 1ULL << ZXDH_NET_F_HOST_TSO6) + static void zxdh_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t length) @@ -391,13 +408,18 @@ zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t l ZXDH_VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length); } +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length) +{ + ZXDH_VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length); +} + void zxdh_get_pci_dev_config(struct zxdh_hw *hw) { uint64_t guest_features = 0; uint64_t nego_features = 0; - hw->host_features = zxdh_pci_get_features(hw); + hw->host_features = ZXDH_PMD_DEFAULT_HOST_FEATURES; guest_features = (uint64_t)ZXDH_PMD_DEFAULT_GUEST_FEATURES; nego_features = guest_features & hw->host_features; diff --git a/drivers/net/zxdh/zxdh_pci.h b/drivers/net/zxdh/zxdh_pci.h index 9b8bef6c09..a1834f6615 100644 --- a/drivers/net/zxdh/zxdh_pci.h +++ b/drivers/net/zxdh/zxdh_pci.h @@ -162,7 +162,7 @@ void zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, int32_t zxdh_read_pci_caps(struct rte_pci_device *dev, struct zxdh_hw *hw); void zxdh_get_pci_dev_config(struct zxdh_hw *hw); - +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length); uint16_t zxdh_pci_get_features(struct zxdh_hw *hw); enum zxdh_msix_status zxdh_pci_msix_detect(struct rte_pci_device *dev); uint8_t zxdh_pci_isr(struct zxdh_hw *hw); diff --git a/drivers/net/zxdh/zxdh_rxtx.c b/drivers/net/zxdh/zxdh_rxtx.c index 1921a23f25..9bb57d4f84 100644 --- a/drivers/net/zxdh/zxdh_rxtx.c +++ b/drivers/net/zxdh/zxdh_rxtx.c @@ -760,7 +760,6 @@ zxdh_rx_update_mbuf(struct rte_mbuf *m, struct zxdh_net_hdr_ul *hdr) idx = (pkt_type_inner >> 4) & 0xF; m->packet_type |= zxdh_inner_l4_type[idx]; } - } static void zxdh_discard_rxbuf(struct zxdh_virtqueue *vq, struct rte_mbuf *m) @@ -818,9 +817,14 @@ zxdh_recv_pkts_packed(void *rx_queue, struct rte_mbuf **rx_pkts, seg_num = header->type_hdr.num_buffers; /* Private queue only handle type hdr */ - hdr_size = ZXDH_TYPE_HDR_SIZE; - rxm->pkt_len = ((header->type_hdr.port & 0x7f) << 8) + - header->type_hdr.pd_len; + hdr_size = header->type_hdr.pd_len << 1; + if (unlikely(hdr_size > lens[i] || hdr_size < ZXDH_TYPE_HDR_SIZE)) { + PMD_RX_LOG(ERR, "hdr_size:%u is invalid", hdr_size); + rte_pktmbuf_free(rxm); + rxvq->stats.errors++; + rxvq->stats.invalid_hdr_len_err++; + continue; + } rxm->data_off += hdr_size; rxm->nb_segs = seg_num; rxm->ol_flags = 0; diff --git a/drivers/net/zxdh/zxdh_tables.c b/drivers/net/zxdh/zxdh_tables.c index 253d9ce438..ab91d51948 100644 --- a/drivers/net/zxdh/zxdh_tables.c +++ b/drivers/net/zxdh/zxdh_tables.c @@ -8,14 +8,7 @@ #include "zxdh_tables.h" #include "zxdh_logs.h" -#define ZXDH_SDT_VPORT_ATT_TABLE 1 -#define ZXDH_SDT_PANEL_ATT_TABLE 2 -#define ZXDH_SDT_RSS_ATT_TABLE 3 -#define ZXDH_SDT_VLAN_ATT_TABLE 4 -#define ZXDH_SDT_BROCAST_ATT_TABLE 6 -#define ZXDH_SDT_UNICAST_ATT_TABLE 10 -#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 -#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 + #define ZXDH_MAC_HASH_INDEX_BASE 64 #define ZXDH_MAC_HASH_INDEX(index) (ZXDH_MAC_HASH_INDEX_BASE + (index)) @@ -40,15 +33,16 @@ zxdh_set_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_write = {ZXDH_SDT_VPORT_ATT_TABLE, (void *)&entry}; ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) - PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vport_num.vfid); + PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vfid); return ret; } @@ -72,6 +66,7 @@ zxdh_port_attr_init(struct rte_eth_dev *dev) port_attr.mtu = dev->data->mtu; port_attr.mtu_enable = 1; port_attr.is_up = 0; + port_attr.hash_search_index = hw->hash_search_index; if (!port_attr.rss_enable) port_attr.port_base_qid = 0; @@ -144,6 +139,7 @@ int zxdh_panel_table_init(struct rte_eth_dev *dev) panel.pf_vfid = zxdh_vport_to_vfid(hw->vport); panel.mtu_enable = 1; panel.mtu = dev->data->mtu; + panel.port_vfid_1588 = panel.pf_vfid; ZXDH_DTB_ERAM_ENTRY_INFO_T panel_entry = { .index = hw->phyport, @@ -212,13 +208,14 @@ zxdh_get_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_get = {ZXDH_SDT_VPORT_ATT_TABLE, &entry}; int ret; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry_get, 1); if (ret != 0) - PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vport_num.vfid, ret); + PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vfid, ret); return ret; } @@ -229,7 +226,8 @@ zxdh_delete_port_attr(struct zxdh_hw *hw, uint16_t vport, { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry = { .sdt_no = ZXDH_SDT_VPORT_ATT_TABLE, .p_entry_data = (void *)&entry @@ -247,9 +245,9 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); uint32_t ret; uint16_t group_id = 0; - uint16_t vfid = vport_num.vfid; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); @@ -351,15 +349,17 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - uint32_t ret, del_flag = 0; - uint16_t group_id = 0; union zxdh_virport_num port = (union zxdh_virport_num)vport; uint16_t vfid = zxdh_vport_to_vfid(port); + uint32_t ret, del_flag = 0; + uint16_t group_id = 0; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); unicast_table.key.sriov_vlan_id = srv_vlanid; unicast_table.key.sriov_vlan_tpid = srv_tpid; + unicast_table.entry.hit_flag = 0; + unicast_table.entry.vfid = rte_cpu_to_be_16(vfid & 0x7ff); ZXDH_DTB_HASH_ENTRY_INFO_T dtb_hash_entry = { .p_actu_key = (uint8_t *)&unicast_table.key, @@ -800,6 +800,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { @@ -820,7 +821,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss rss_vqid.vqm_qid[0] |= 0x8000; #endif ZXDH_DTB_ERAM_ENTRY_INFO_T entry = { - .index = vport_num.vfid * 32 + i, + .index = vfid * 32 + i, .p_data = (uint32_t *)&rss_vqid }; ZXDH_DTB_USER_ENTRY_T user_entry_write = { @@ -830,7 +831,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) { - PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vfid); return ret; } } @@ -843,16 +844,17 @@ zxdh_rss_table_get(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid * 32 + i, (uint32_t *)&rss_vqid}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid * 32 + i, (uint32_t *)&rss_vqid}; ZXDH_DTB_USER_ENTRY_T user_entry = {ZXDH_SDT_RSS_ATT_TABLE, &entry}; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry, 1); if (ret != 0) { - PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vfid); return -1; } diff --git a/drivers/net/zxdh/zxdh_tables.h b/drivers/net/zxdh/zxdh_tables.h index 2f2ada3a9f..cb34e38be8 100644 --- a/drivers/net/zxdh/zxdh_tables.h +++ b/drivers/net/zxdh/zxdh_tables.h @@ -9,7 +9,13 @@ /* eram */ #define ZXDH_SDT_VPORT_ATT_TABLE 1 - +#define ZXDH_SDT_PANEL_ATT_TABLE 2 +#define ZXDH_SDT_RSS_ATT_TABLE 3 +#define ZXDH_SDT_VLAN_ATT_TABLE 4 +#define ZXDH_SDT_BROCAST_ATT_TABLE 6 +#define ZXDH_SDT_UNICAST_ATT_TABLE 10 +#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 +#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 /* hash */ #define ZXDH_SDT_L2_ENTRY_TABLE0 64 #define ZXDH_SDT_L2_ENTRY_TABLE1 65 @@ -80,8 +86,6 @@ #define ZXDH_MTR_STATS_EGRESS_BASE 0x7481 #define ZXDH_MTR_STATS_INGRESS_BASE 0x7C81 -extern struct zxdh_dtb_shared_data g_dtb_data; - struct zxdh_port_vlan_table { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint16_t business_vlan_tpid:16; @@ -233,19 +237,51 @@ struct zxdh_port_attr_table { }; struct zxdh_panel_table { - uint16_t port_vfid_1588 : 11, - rsv2 : 5; - uint16_t pf_vfid : 11, - rsv1 : 1, - enable_1588_tc : 2, - trust_mode : 1, - hit_flag : 1; - uint32_t mtu : 16, - mtu_enable : 1, - rsv : 3, - tm_base_queue : 12; - uint32_t rsv_1; - uint32_t rsv_2; +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t mtu : 16; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t rsv3 : 16; + uint16_t pf_vfid : 11, + rsv4 : 5; +#else + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t mtu : 16; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t pf_vfid : 11, + rsv4 : 5; + uint16_t rsv3 : 16; +#endif }; /* 16B */ struct zxdh_mac_unicast_key { -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 217264 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v5 14/14] net/zxdh: fix debugging errors 2025-03-19 8:58 ` [PATCH v5 14/14] net/zxdh: fix debugging errors Bingbin Chen @ 2025-03-20 19:50 ` Stephen Hemminger 2025-03-21 3:07 ` Bingbin Chen 1 sibling, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-03-20 19:50 UTC (permalink / raw) To: Bingbin Chen; +Cc: wang.junlong1, yang.yonggang, dev On Wed, 19 Mar 2025 16:58:08 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > Fix zxdh driver packet sending and receiving errors. > > Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> The term fix in commit message implies that there will be a Fixes: tag that refers to a previous commit that was buggy. > --- > drivers/net/zxdh/zxdh_common.h | 99 ++++++++ > drivers/net/zxdh/zxdh_ethdev.c | 19 +- > drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +++++---- > drivers/net/zxdh/zxdh_ethdev_ops.h | 35 +++ > drivers/net/zxdh/zxdh_msg.c | 381 +++++++++++++++++------------ > drivers/net/zxdh/zxdh_msg.h | 99 +++++--- > drivers/net/zxdh/zxdh_mtr.c | 50 ++-- > drivers/net/zxdh/zxdh_mtr.h | 5 + > drivers/net/zxdh/zxdh_np.c | 70 +++++- > drivers/net/zxdh/zxdh_np.h | 8 +- > drivers/net/zxdh/zxdh_pci.c | 24 +- > drivers/net/zxdh/zxdh_pci.h | 2 +- > drivers/net/zxdh/zxdh_rxtx.c | 12 +- > drivers/net/zxdh/zxdh_tables.c | 42 ++-- > drivers/net/zxdh/zxdh_tables.h | 68 +++-- > 15 files changed, 708 insertions(+), 315 deletions(-) > > diff --git a/drivers/net/zxdh/zxdh_common.h b/drivers/net/zxdh/zxdh_common.h > index d78a822ebf..b34dcddd4d 100644 > --- a/drivers/net/zxdh/zxdh_common.h > +++ b/drivers/net/zxdh/zxdh_common.h > @@ -20,6 +20,105 @@ struct zxdh_res_para { > uint16_t src_type; /* refer to BAR_DRIVER_TYPE */ > }; > > +static inline size_t > +zxdh_get_value(uint32_t fld_sz, uint8_t *addr) { > + size_t result = 0; > + switch (fld_sz) { > + case 1: > + result = *((uint8_t *)addr); > + break; > + case 2: > + result = *((uint16_t *)addr); > + break; > + case 4: > + result = *((uint32_t *)addr); > + break; > + case 8: > + result = *((uint64_t *)addr); > + break; > + default: > + printf("Error: unreachable field size %u\n", fld_sz); No printf's > + break; > + } > + return result; > +} > + > +static inline void > +zxdh_set_value(uint32_t fld_sz, uint8_t *addr, size_t value) { > + switch (fld_sz) { > + case 1: > + *(uint8_t *)addr = (uint8_t)value; > + break; > + case 2: > + *(uint16_t *)addr = (uint16_t)value; > + break; > + case 4: > + *(uint32_t *)addr = (uint32_t)value; > + break; > + case 8: > + *(uint64_t *)addr = (uint64_t)value; > + break; > + default: > + printf("Error: unreachable field size %u\n", fld_sz); Drivers should never use printf, only logging > + break; > + } > +} > + > +#define __zxdh_nullp(typ) ((struct zxdh_ifc_##typ##_bits *)0) > +#define __zxdh_bit_sz(typ, fld) sizeof(__zxdh_nullp(typ)->fld) > +#define __zxdh_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ > + (&(__zxdh_nullp(typ)->fld))) > +#define __zxdh_dw_bit_off(typ, fld) (32 - __zxdh_bit_sz(typ, fld) - \ > + (__zxdh_bit_off(typ, fld) & 0x1f)) > +#define __zxdh_dw_off(typ, fld) (__zxdh_bit_off(typ, fld) / 32) > +#define __zxdh_64_off(typ, fld) (__zxdh_bit_off(typ, fld) / 64) > +#define __zxdh_dw_mask(typ, fld) (__zxdh_mask(typ, fld) << \ > + __zxdh_dw_bit_off(typ, fld)) > +#define __zxdh_mask(typ, fld) ((uint32_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) > +#define __zxdh_16_off(typ, fld) (__zxdh_bit_off(typ, fld) / 16) > +#define __zxdh_16_bit_off(typ, fld) (16 - __zxdh_bit_sz(typ, fld) - \ > + (__zxdh_bit_off(typ, fld) & 0xf)) > +#define __zxdh_mask16(typ, fld) ((uint16_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) > +#define __zxdh_16_mask(typ, fld) (__zxdh_mask16(typ, fld) << \ > + __zxdh_16_bit_off(typ, fld)) > +#define ZXDH_ST_SZ_BYTES(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 8) > +#define ZXDH_ST_SZ_DW(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 32) > +#define ZXDH_BYTE_OFF(typ, fld) (__zxdh_bit_off(typ, fld) / 8) > +#define ZXDH_ADDR_OF(typ, p, fld) ((uint8_t *)(p) + ZXDH_BYTE_OFF(typ, fld)) > + > +#define BUILD_BUG_ON(condition) do { \ > + if (condition) \ > + __builtin_unreachable(); \ > + } while (0) > + > +#define ZXDH_SET(typ, p, fld, v) do { \ > + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ > + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ > + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ > + zxdh_set_value(fld_sz, addr, v); \ > +} while (0) > + > +#define ZXDH_GET(typ, p, fld) ({ \ > + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ > + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ > + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ > + zxdh_get_value(fld_sz, addr); \ > +}) > + > +#define ZXDH_SET_ARRAY(typ, p, fld, index, value, type) \ > + do { \ > + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ > + (index) * sizeof(type)); \ > + *addr = (type)(value); \ > + } while (0) > + > +#define ZXDH_GET_ARRAY(typ, p, fld, index, type) \ > + ({ \ > + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ > + (index) * sizeof(type)); \ > + *addr; \ > + }) > + > int32_t zxdh_phyport_get(struct rte_eth_dev *dev, uint8_t *phyport); > int32_t zxdh_panelid_get(struct rte_eth_dev *dev, uint8_t *pannelid); > int32_t zxdh_hashidx_get(struct rte_eth_dev *dev, uint8_t *hash_idx); > diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c > index ea8b18e5e1..ba7ea52d20 100644 > --- a/drivers/net/zxdh/zxdh_ethdev.c > +++ b/drivers/net/zxdh/zxdh_ethdev.c > @@ -1250,10 +1250,6 @@ zxdh_set_rxtx_funcs(struct rte_eth_dev *eth_dev) > { > struct zxdh_hw *hw = eth_dev->data->dev_private; > > - if (!zxdh_pci_packed_queue(hw)) { > - PMD_DRV_LOG(ERR, "port %u not support packed queue", eth_dev->data->port_id); > - return -1; > - } > if (!zxdh_pci_with_feature(hw, ZXDH_NET_F_MRG_RXBUF)) { > PMD_DRV_LOG(ERR, "port %u not support rx mergeable", eth_dev->data->port_id); > return -1; > @@ -1498,6 +1494,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) > > struct zxdh_dtb_bulk_dump_info dtb_dump_baseres[] = { > {"sdt_vport_att_table", 4 * 1024 * 1024, ZXDH_SDT_VPORT_ATT_TABLE, NULL}, > + {"sdt_vlan_att_table", 4 * 1024 * 1024, ZXDH_SDT_VLAN_ATT_TABLE, NULL}, > + {"sdt_rss_table", 4 * 1024 * 1024, ZXDH_SDT_RSS_ATT_TABLE, NULL}, > {"sdt_l2_entry_table0", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE0, NULL}, > {"sdt_l2_entry_table1", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE1, NULL}, > {"sdt_l2_entry_table2", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE2, NULL}, > @@ -1514,7 +1512,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) > for (i = 0; i < (int)RTE_DIM(dtb_dump_baseres); i++) { > struct zxdh_dtb_bulk_dump_info *p = dtb_dump_baseres + i; > char buf[ZXDH_MAX_NAME_LEN] = {0}; > - > + memset(buf, '\0', sizeof(buf)); > + sprintf(buf, "%s_%x", p->mz_name, hw->dev_id); Why the memset? It is already zero, and sprintf() adds null char Use snprintf which can detect overflows in the buffer. If mz_name was maximum length (32) and dev_id was long enough can this overflow? > p->mz_name = buf; > > const struct rte_memzone *generic_dump_mz = > @@ -1544,6 +1543,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_bar_offset_params param = {0}; > struct zxdh_bar_offset_res res = {0}; > + char buf[ZXDH_MAX_NAME_LEN] = {0}; > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > int ret = 0; > > @@ -1569,7 +1569,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) > dpp_ctrl->vport = hw->vport.vport; > dpp_ctrl->vector = ZXDH_MSIX_INTR_DTB_VEC; > strlcpy(dpp_ctrl->port_name, dev->device->name, sizeof(dpp_ctrl->port_name)); > - dpp_ctrl->pcie_vir_addr = (uint32_t)hw->bar_addr[0]; > + dpp_ctrl->pcie_vir_addr = (uint64_t)hw->bar_addr[0]; No cast is needed here hw->bar_addr[0] is already uint64_t. > > param.pcie_id = hw->pcie_id; > param.virt_addr = hw->bar_addr[0] + ZXDH_CTRLCH_OFFSET; > @@ -1584,7 +1584,8 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) > dpp_ctrl->np_bar_offset = res.bar_offset; > > if (!dtb_data->dtb_table_conf_mz) { > - const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_conf_mz", > + sprintf(buf, "%s_%x", "zxdh_dtb_table_conf_mz", hw->dev_id); > + const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned(buf, > ZXDH_DTB_TABLE_CONF_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); Always use snprintf > > if (conf_mz == NULL) { > @@ -1600,7 +1601,9 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) > } > > if (!dtb_data->dtb_table_dump_mz) { > - const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_dump_mz", > + memset(buf, '\0', sizeof(buf)); > + sprintf(buf, "%s_%x", "zxdh_dtb_table_dump_mz", hw->dev_id); > + const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned(buf, > ZXDH_DTB_TABLE_DUMP_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); > > if (dump_mz == NULL) { > diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c > index 2b02734c62..f8e8d26c50 100644 > --- a/drivers/net/zxdh/zxdh_ethdev_ops.c > +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c > @@ -15,6 +15,7 @@ > #include "zxdh_np.h" > #include "zxdh_queue.h" > #include "zxdh_mtr.h" > +#include "zxdh_common.h" > > #define ZXDH_VLAN_FILTER_GROUPS 64 > #define ZXDH_INVALID_LOGIC_QID 0xFFFFU > @@ -278,9 +279,11 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > uint16_t status = 0; > int32_t ret = 0; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *link_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, link_msg); > > if (zxdh_pci_with_feature(hw, ZXDH_NET_F_STATUS)) > zxdh_pci_read_dev_config(hw, offsetof(struct zxdh_net_config, status), > @@ -295,17 +298,18 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) > zxdh_agent_msg_build(hw, ZXDH_MAC_LINK_GET, &msg_info); > > ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info), > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), > ZXDH_BAR_MODULE_MAC); > if (ret) { > PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", > hw->vport.vport, ZXDH_MAC_LINK_GET); > return -1; > } > - link->link_speed = reply_info.reply_body.link_msg.speed; > - link->link_autoneg = reply_info.reply_body.link_msg.autoneg; > - hw->speed_mode = reply_info.reply_body.link_msg.speed_modes; > - if ((reply_info.reply_body.link_msg.duplex & RTE_ETH_LINK_FULL_DUPLEX) == > + > + link->link_speed = ZXDH_GET(link_info_msg, link_msg_addr, speed); > + link->link_autoneg = ZXDH_GET(link_info_msg, link_msg_addr, autoneg); > + hw->speed_mode = ZXDH_GET(link_info_msg, link_msg_addr, speed_modes); > + if ((ZXDH_GET(link_info_msg, link_msg_addr, duplex) & RTE_ETH_LINK_FULL_DUPLEX) == > RTE_ETH_LINK_FULL_DUPLEX) > link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; > else > @@ -433,7 +437,7 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) > ret = zxdh_del_mac_table(hw, hw->vport.vport, old_addr, > hw->hash_search_index, 0, 0); > if (ret) { > - PMD_DRV_LOG(ERR, "mac_addr_add failed, code:%d", ret); > + PMD_DRV_LOG(ERR, "mac_addr_del failed, code:%d", ret); > return ret; > } > hw->uc_num--; > @@ -467,6 +471,8 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) > hw->uc_num--; > } > rte_ether_addr_copy(addr, (struct rte_ether_addr *)hw->mac_addr); > + zxdh_pci_write_dev_config(hw, offsetof(struct zxdh_net_config, mac), > + &hw->mac_addr, RTE_ETHER_ADDR_LEN); > return ret; > } > > @@ -566,7 +572,7 @@ zxdh_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, > > void zxdh_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) > { > - struct zxdh_hw *hw = dev->data->dev_private; > + struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[index]; > uint16_t ret = 0; > @@ -1072,7 +1078,9 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, > { > struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; > struct zxdh_msg_info msg = {0}; > - struct zxdh_msg_reply_info reply_msg = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_reta_msg); > uint16_t idx; > uint16_t i; > int ret = 0; > @@ -1094,21 +1102,21 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, > zxdh_msg_head_build(hw, ZXDH_RSS_RETA_GET, &msg); > > if (hw->is_pf) { > - ret = zxdh_rss_table_get(hw, hw->vport.vport, &reply_msg.reply_body.rss_reta); > + ret = zxdh_rss_table_get(hw, hw->vport.vport, rss_reta_msg_addr); > if (ret) { > PMD_DRV_LOG(ERR, "rss reta table set failed"); > return -EINVAL; > } > } else { > ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), > - &reply_msg, sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > if (ret) { > PMD_DRV_LOG(ERR, "vf rss reta table get failed"); > return -EINVAL; > } > } > > - struct zxdh_rss_reta *reta_table = &reply_msg.reply_body.rss_reta; > + struct zxdh_rss_reta *reta_table = rss_reta_msg_addr; > > for (idx = 0, i = 0; i < reta_size; ++i) { > idx = i / RTE_ETH_RETA_GROUP_SIZE; > @@ -1232,10 +1240,13 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con > struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; > struct rte_eth_rss_conf *old_rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; > struct zxdh_msg_info msg = {0}; > - struct zxdh_msg_reply_info reply_msg = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_hf_msg); > struct zxdh_port_attr_table port_attr = {0}; > - int ret; > + uint32_t rss_hf; > uint32_t hw_hf; > + int ret; > > if (rss_conf == NULL) { > PMD_DRV_LOG(ERR, "rss conf is NULL"); > @@ -1252,16 +1263,17 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con > PMD_DRV_LOG(ERR, "rss hash factor set failed"); > return -EINVAL; > } > - reply_msg.reply_body.rss_hf.rss_hf = port_attr.rss_hash_factor; > + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, port_attr.rss_hash_factor); > } else { > ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), > - &reply_msg, sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > if (ret) { > PMD_DRV_LOG(ERR, "rss hash factor set failed"); > return -EINVAL; > } > } > - rss_conf->rss_hf = zxdh_rss_hf_to_eth(reply_msg.reply_body.rss_hf.rss_hf); > + rss_hf = ZXDH_GET(rss_hf, rss_hf_msg_addr, rss_hf); > + rss_conf->rss_hf = zxdh_rss_hf_to_eth(rss_hf); > > return 0; > } > @@ -1382,7 +1394,8 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > enum ZXDH_BAR_MODULE_ID module_id; > int ret = 0; > > @@ -1404,14 +1417,15 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, > zxdh_agent_msg_build(hw, opcode, &msg_info); > > ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); > if (ret) { > PMD_DRV_LOG(ERR, "Failed to get hw stats"); > return -1; > } > - struct zxdh_msg_reply_body *reply_body = &reply_info.reply_body; > > - memcpy(hw_stats, &reply_body->vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); > + void *hw_vqm_stats = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, vqm_stats); > + memcpy(hw_stats, hw_vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); > + > return 0; > } > > @@ -1578,7 +1592,9 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *hw_stas_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_stats); > int ret = 0; > > if (hw->is_pf) { > @@ -1590,13 +1606,13 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) > } else { > zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); > ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > if (ret) { > PMD_DRV_LOG(ERR, > "Failed to send msg: port 0x%x msg type", hw->vport.vport); > return -1; > } > - memcpy(np_stats, &reply_info.reply_body.np_stats, sizeof(struct zxdh_hw_np_stats)); > + memcpy(np_stats, hw_stas_addr, sizeof(struct zxdh_hw_np_stats)); > } > return ret; > } > @@ -1666,7 +1682,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > enum ZXDH_BAR_MODULE_ID module_id; > int ret = 0; > > @@ -1685,7 +1701,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) > zxdh_agent_msg_build(hw, opcode, &msg_info); > > ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); > if (ret) { > PMD_DRV_LOG(ERR, "Failed to reset hw stats"); > return -1; > @@ -1767,13 +1783,13 @@ zxdh_hw_np_stats_vf_reset(struct rte_eth_dev *dev) > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > int ret = 0; > > msg_info.data.np_stats_query.clear_mode = 1; > zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); > ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > if (ret) > PMD_DRV_LOG(ERR, "Failed to send ZXDH_PORT_METER_STAT_GET msg. code:%d", ret); > > @@ -2034,29 +2050,24 @@ zxdh_dev_fw_version_get(struct rte_eth_dev *dev, > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *flash_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, flash_msg); > char fw_ver[ZXDH_FWVERS_LEN] = {0}; > uint32_t ret = 0; > > zxdh_agent_msg_build(hw, ZXDH_FLASH_FIR_VERSION_GET, &msg_info); > > - struct zxdh_msg_recviver_mem rsp_data = { > - .recv_buffer = (void *)&reply_info, > - .buffer_len = sizeof(struct zxdh_msg_reply_info), > - }; > - > ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info), > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), > ZXDH_MODULE_FLASH); > if (ret) { > PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", > hw->vport.vport, ZXDH_FLASH_FIR_VERSION_GET); > return -1; > } > - struct zxdh_msg_reply_body *ack_msg = > - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); > > - memcpy(fw_ver, ack_msg->flash_msg.firmware_version, ZXDH_FWVERS_LEN); > + memcpy(fw_ver, flash_msg_addr, ZXDH_FWVERS_LEN); > snprintf(fw_version, ZXDH_FWVERS_LEN - 1, "%s", fw_ver); > > return 0; > @@ -2068,7 +2079,7 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > uint8_t ret = 0; > > zxdh_agent_msg_build(hw, ZXDH_MAC_MODULE_EEPROM_READ, &msg_info); > @@ -2079,26 +2090,24 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, > msg_info.data.module_eeprom_msg.offset = query->offset; > msg_info.data.module_eeprom_msg.length = query->length; > > - struct zxdh_msg_recviver_mem rsp_data = { > - .recv_buffer = (void *)&reply_info, > - .buffer_len = sizeof(struct zxdh_msg_reply_info), > - }; > - > ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), > - &reply_info, sizeof(struct zxdh_msg_reply_info), > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), > ZXDH_BAR_MODULE_MAC); > if (ret) { > PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", > hw->vport.vport, ZXDH_MAC_MODULE_EEPROM_READ); > return -1; > } > - struct zxdh_msg_reply_body *ack_msg = > - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); > - > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *module_eeprom_msg_addr = > + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, module_eeprom_msg); > + void *agent_mac_module_eeprom_msg_data_addr = > + ZXDH_ADDR_OF(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, data); > + uint8_t length = ZXDH_GET(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, length); > if (data) > - memcpy(data, ack_msg->module_eeprom_msg.data, ack_msg->module_eeprom_msg.length); > + memcpy(data, agent_mac_module_eeprom_msg_data_addr, length); > > - return ack_msg->module_eeprom_msg.length; > + return length; > } > > int > diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.h b/drivers/net/zxdh/zxdh_ethdev_ops.h > index a5162a6d6b..97a1eb4532 100644 > --- a/drivers/net/zxdh/zxdh_ethdev_ops.h > +++ b/drivers/net/zxdh/zxdh_ethdev_ops.h > @@ -62,6 +62,30 @@ struct zxdh_hw_np_stats { > uint64_t tx_ssvpc_pkts; > }; > > +struct zxdh_ifc_hw_np_stats_bits { > + uint8_t rx_unicast_pkts[0x40]; > + uint8_t tx_unicast_pkts[0x40]; > + uint8_t rx_unicast_bytes[0x40]; > + uint8_t tx_unicast_bytes[0x40]; > + uint8_t rx_multicast_pkts[0x40]; > + uint8_t tx_multicast_pkts[0x40]; > + uint8_t rx_multicast_bytes[0x40]; > + uint8_t tx_multicast_bytes[0x40]; > + uint8_t rx_broadcast_pkts[0x40]; > + uint8_t tx_broadcast_pkts[0x40]; > + uint8_t rx_broadcast_bytes[0x40]; > + uint8_t tx_broadcast_bytes[0x40]; > + uint8_t rx_mtu_drop_pkts[0x40]; > + uint8_t tx_mtu_drop_pkts[0x40]; > + uint8_t rx_mtu_drop_bytes[0x40]; > + uint8_t tx_mtu_drop_bytes[0x40]; > + uint8_t rx_mtr_drop_pkts[0x40]; > + uint8_t tx_mtr_drop_pkts[0x40]; > + uint8_t rx_mtr_drop_bytes[0x40]; > + uint8_t tx_mtr_drop_bytes[0x40]; > + uint8_t tx_ssvpc_pkts[0x40]; > +}; Seems like 0x40 (ie 64) is a magic constant here. Is it based on number of VF's or other value. Should be defined as constant rather than open coded. > + > struct zxdh_hw_vqm_stats { > uint64_t rx_total; > uint64_t tx_total; > @@ -72,6 +96,17 @@ struct zxdh_hw_vqm_stats { > uint64_t rx_drop; > }; > > +struct zxdh_ifc_hw_vqm_stats_bits { > + uint8_t rx_total[0x40]; > + uint8_t tx_total[0x40]; > + uint8_t rx_bytes[0x40]; > + uint8_t tx_bytes[0x40]; > + uint8_t rx_error[0x40]; > + uint8_t tx_error[0x40]; > + uint8_t rx_drop[0x40]; > +}; > + > + > int zxdh_dev_set_link_up(struct rte_eth_dev *dev); > int zxdh_dev_set_link_down(struct rte_eth_dev *dev); > int32_t zxdh_dev_link_update(struct rte_eth_dev *dev, int32_t wait_to_complete); > diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c > index 96ad638e83..02ecd93b12 100644 > --- a/drivers/net/zxdh/zxdh_msg.c > +++ b/drivers/net/zxdh/zxdh_msg.c > @@ -18,6 +18,7 @@ > #include "zxdh_pci.h" > #include "zxdh_tables.h" > #include "zxdh_np.h" > +#include "zxdh_common.h" > > #define ZXDH_REPS_INFO_FLAG_USABLE 0x00 > #define ZXDH_BAR_SEQID_NUM_MAX 256 > @@ -695,7 +696,7 @@ static uint16_t > zxdh_bar_chan_sync_msg_reps_get(uint64_t subchan_addr, > uint64_t recv_buffer, uint16_t buffer_len) > { > - struct zxdh_bar_msg_header msg_header = {0}; > + struct zxdh_bar_msg_header msg_header; > uint16_t msg_id = 0; > uint16_t msg_len = 0; > > @@ -987,7 +988,7 @@ zxdh_bar_chan_msg_header_check(struct zxdh_bar_msg_header *msg_header) > int > zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev) > { > - struct zxdh_bar_msg_header msg_header = {0}; > + struct zxdh_bar_msg_header msg_header; > uint64_t recv_addr = 0; > uint64_t reps_addr = 0; > uint16_t ret = 0; > @@ -1083,22 +1084,20 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_recviver_mem result = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > int ret = 0; > > if (reply) { > - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); > + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); > result.recv_buffer = reply; > result.buffer_len = reply_len; > } else { > - result.recv_buffer = &reply_info; > - result.buffer_len = sizeof(reply_info); > + result.recv_buffer = zxdh_msg_reply_info; > + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); > } > > - struct zxdh_msg_reply_head *reply_head = > - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); > - struct zxdh_msg_reply_body *reply_body = > - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); > + void *reply_head_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_head); > + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_body); > > struct zxdh_pci_bar_msg in = { > .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + > @@ -1118,12 +1117,16 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, > "vf[%d] send bar msg to pf failed.ret %d", hw->vport.vfid, ret); > return -1; > } > - if (reply_head->flag != ZXDH_MSG_REPS_OK) { > + > + uint8_t flag = ZXDH_GET(msg_reply_head, reply_head_addr, flag); > + uint16_t reps_len = ZXDH_GET(msg_reply_head, reply_head_addr, reps_len); > + if (flag != ZXDH_MSG_REPS_OK) { > PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", > - hw->vport.vfid, reply_head->flag, reply_head->reps_len); > + hw->vport.vfid, flag, reps_len); > return -1; > } > - if (reply_body->flag != ZXDH_REPS_SUCC) { > + uint8_t reply_body_flag = ZXDH_GET(msg_reply_body, reply_body_addr, flag); > + if (reply_body_flag != ZXDH_REPS_SUCC) { > PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); > return -1; > } > @@ -1137,23 +1140,19 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, > { > struct zxdh_hw *hw = dev->data->dev_private; > struct zxdh_msg_recviver_mem result = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > > if (reply) { > - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); > + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); > result.recv_buffer = reply; > result.buffer_len = reply_len; > } else { > - result.recv_buffer = &reply_info; > - result.buffer_len = sizeof(reply_info); > + result.recv_buffer = zxdh_msg_reply_info; > + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); > } > - struct zxdh_msg_reply_head *reply_head = > - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); > - struct zxdh_msg_reply_body *reply_body = > - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); > > struct zxdh_pci_bar_msg in = { > - .payload_addr = &msg_req, > + .payload_addr = msg_req, > .payload_len = msg_req_len, > .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + ZXDH_CTRLCH_OFFSET), > .src = hw->is_pf ? ZXDH_MSG_CHAN_END_PF : ZXDH_MSG_CHAN_END_VF, > @@ -1166,15 +1165,6 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, > PMD_MSG_LOG(ERR, "Failed to send sync messages or receive response"); > return -1; > } > - if (reply_head->flag != ZXDH_MSG_REPS_OK) { > - PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", > - hw->vport.vfid, reply_head->flag, reply_head->reps_len); > - return -1; > - } > - if (reply_body->flag != ZXDH_REPS_SUCC) { > - PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); > - return -1; > - } > > return 0; > } > @@ -1245,7 +1235,7 @@ zxdh_vf_promisc_uninit(struct zxdh_hw *hw, union zxdh_virport_num vport) > > static int > zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > struct zxdh_port_attr_table port_attr = {0}; > union zxdh_virport_num port = {.vport = vport}; > @@ -1275,14 +1265,13 @@ zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, > PMD_DRV_LOG(ERR, "vf_promisc_table_init failed, code:%d", ret); > goto proc_end; > } > - > - res_info->flag = ZXDH_REPS_SUCC; > - *res_len = sizeof(res_info->flag); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > + *res_len = sizeof(uint8_t); > > return ret; > proc_end: > - *res_len = sizeof(res_info->flag); > - res_info->flag = ZXDH_REPS_FAIL; > + *res_len = sizeof(uint8_t); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > return ret; > } > > @@ -1311,11 +1300,12 @@ zxdh_mac_clear(struct zxdh_hw *hw, union zxdh_virport_num vport) > static int > zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, > uint16_t vport, void *cfg_data __rte_unused, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "uninit"; > struct zxdh_port_attr_table port_attr = {0}; > union zxdh_virport_num vport_num = {.vport = vport}; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); > int ret = 0; > > *res_len = ZXDH_MSG_REPLYBODY_HEAD; > @@ -1340,20 +1330,20 @@ zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, > } > > *res_len += strlen(str); > - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); > - res_info->flag = ZXDH_REPS_SUCC; > + rte_memcpy(reply_data_addr, str, strlen(str) + 1); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > return ret; > > proc_end: > *res_len += strlen(str); > - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); > - res_info->flag = ZXDH_REPS_FAIL; > + rte_memcpy(reply_data_addr, str, strlen(str) + 1); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > return ret; > } > > static int > zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply_body, uint16_t *reply_len) > + void *reply_body, uint16_t *reply_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "add mac"; > union zxdh_virport_num port = {0}; > @@ -1362,6 +1352,8 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > int i = 0, ret = 0; > uint16_t vf_id = port.vfid; > port.vport = vport; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, reply_data); > + void *mac_reply_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, mac_reply_msg); > > for (i = 0; i < ZXDH_MAX_MAC_ADDRS; i++) > if (rte_is_same_ether_addr(&hw->vfinfo[vf_id].vf_mac[i], addr)) > @@ -1369,7 +1361,7 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > > ret = zxdh_add_mac_table(hw, vport, addr, hw->hash_search_index, 0, 0); > if (ret == -EADDRINUSE) { > - reply_body->mac_reply_msg.mac_flag = ZXDH_EEXIST_MAC_FLAG; > + ZXDH_SET(mac_reply_msg, mac_reply_msg_addr, mac_flag, ZXDH_EEXIST_MAC_FLAG); > PMD_DRV_LOG(ERR, "vf vport 0x%x set mac ret 0x%x failed. mac is in used.", > port.vport, ret); > goto failure; > @@ -1389,26 +1381,27 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > success: > sprintf(str, " vport 0x%x set mac ret 0x%x\n", port.vport, ret); > *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; > - rte_memcpy(&reply_body->reply_data, str, strlen(str) + 1); > - reply_body->flag = ZXDH_REPS_SUCC; > + rte_memcpy(reply_data_addr, str, strlen(str) + 1); > + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_SUCC); > PMD_DRV_LOG(DEBUG, " reply len %d", *reply_len); > return ret; > > failure: > *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; > - reply_body->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_FAIL); > return ret; > } > > static int > zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > int ret, i = 0; > struct zxdh_mac_filter *mac_filter = (struct zxdh_mac_filter *)cfg_data; > union zxdh_virport_num port = (union zxdh_virport_num)vport; > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "del mac"; > uint16_t vf_id = port.vfid; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); > > PMD_DRV_LOG(DEBUG, "[PF GET MSG FROM VF]--vf mac to del."); > ret = zxdh_del_mac_table(hw, vport, &mac_filter->mac, hw->hash_search_index, 0, 0); > @@ -1428,19 +1421,19 @@ zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > > sprintf(str, "vport 0x%x del mac ret 0x%x\n", port.vport, ret); > *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; > - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); > - res_info->flag = ZXDH_REPS_SUCC; > + rte_memcpy(reply_data_addr, str, strlen(str) + 1); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > return ret; > > proc_end: > *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > return ret; > } > > static int > zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > struct zxdh_port_promisc_msg *promisc_msg = (struct zxdh_port_promisc_msg *)cfg_data; > int ret = 0; > @@ -1458,24 +1451,25 @@ zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > goto proc_end; > } > > - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); > - reply->flag = ZXDH_REPS_SUCC; > + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > > return ret; > > proc_end: > - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); > - reply->flag = ZXDH_REPS_FAIL; > + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > return ret; > } > > static int > zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len, uint8_t enable) > + void *res_info, uint16_t *res_len, uint8_t enable) > { > struct zxdh_vlan_filter *vlan_filter = cfg_data; > uint16_t vlan_id = vlan_filter->vlan_id; > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter table"; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); > int ret = 0; > > ret = zxdh_vlan_filter_table_set(hw, vport, vlan_id, enable); > @@ -1483,33 +1477,38 @@ zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_ > sprintf(str, "vlan filter op-code[%d] vlan id:%d failed, code:%d\n", > enable, vlan_id, ret); > > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - memcpy(&res_info->reply_data, str, strlen(str) + 1); > - res_info->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > + *res_len = strlen(str) + sizeof(uint8_t); > + > + memcpy(reply_data_addr, str, strlen(str) + 1); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > return ret; > } > > static int > zxdh_vf_vlan_filter_table_add(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 1); > } > > static int > zxdh_vf_vlan_filter_table_del(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 0); > } > > static int > zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > struct zxdh_vlan_filter_set *vlan_filter = cfg_data; > union zxdh_virport_num port = (union zxdh_virport_num)vport; > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter"; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int ret = 0; > uint16_t vfid = port.vfid; > > @@ -1517,19 +1516,23 @@ zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > if (ret) > sprintf(str, "[vfid:%d] vlan filter. set failed, ret:%d\n", vfid, ret); > > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > struct zxdh_vlan_offload *vlan_offload = cfg_data; > union zxdh_virport_num port = (union zxdh_virport_num)vport; > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan offload"; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int ret = 0; > uint16_t vfid = port.vfid; > > @@ -1540,18 +1543,23 @@ zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > if (ret) > sprintf(str, "[vfid:%d] vlan offload set failed, ret:%d\n", vfid, ret); > > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; > struct zxdh_port_attr_table vport_att = {0}; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_hf_msg); > int ret = 0; > > ret = zxdh_get_port_attr(hw, vport, &vport_att); > @@ -1561,22 +1569,26 @@ zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unus > goto proc_end; > } > > - reply->rss_hf.rss_hf = vport_att.rss_hash_factor; > + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, vport_att.rss_hash_factor); > > proc_end: > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; > struct zxdh_rss_hf *rss_hf = cfg_data; > struct zxdh_port_attr_table vport_att = {0}; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int ret = 0; > > ret = zxdh_get_port_attr(hw, vport, &vport_att); > @@ -1596,19 +1608,23 @@ zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > } > > proc_end: > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_enable"; > struct zxdh_rss_enable *rss_enable = cfg_data; > struct zxdh_port_attr_table vport_att = {0}; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int ret = 0; > > ret = zxdh_get_port_attr(hw, vport, &vport_att); > @@ -1628,51 +1644,63 @@ zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > } > > proc_end: > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_rss_table_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; > struct zxdh_rss_reta *rss_reta = cfg_data; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int32_t ret = 0; > > ret = zxdh_rss_table_set(hw, vport, rss_reta); > if (ret) > sprintf(str, "set rss reta tbl failed, code:%d", ret); > > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_rss_table_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, > - struct zxdh_msg_reply_body *reply, uint16_t *res_len) > + void *reply, uint16_t *res_len) > { > char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; > - struct zxdh_rss_reta *rss_reta = &reply->rss_reta; > + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_reta_msg); > + struct zxdh_rss_reta *rss_reta = (struct zxdh_rss_reta *)rss_reta_msg_addr; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); > int ret = 0; > > ret = zxdh_rss_table_get(hw, vport, rss_reta); > if (ret) > sprintf(str, "set rss reta tbl failed, code:%d", ret); > > - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); > - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; > - memcpy(&reply->reply_data, str, strlen(str) + 1); > + *res_len = strlen(str) + sizeof(uint8_t); > + if (ret == 0) > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); > + else > + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); > + memcpy(reply_data_addr, str, strlen(str) + 1); > return ret; > } > > static int > zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) > + void *res_info, uint16_t *res_len) > { > RTE_ASSERT(!cfg_data || !pf_hw); > if (res_info) > @@ -1734,7 +1762,7 @@ zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, > > static int > zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > - void *cfg_data, struct zxdh_msg_reply_body *res_info, > + void *cfg_data, void *res_info, > uint16_t *res_len) > { > struct zxdh_np_stats_updata_msg *np_stats_query = > @@ -1745,6 +1773,47 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > uint32_t idx = 0; > int ret = 0; > > + void *hw_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_stats); > + void *tx_unicast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_pkts); > + void *rx_unicast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_pkts); > + void *tx_unicast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_bytes); > + void *rx_unicast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_bytes); > + void *tx_multicast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_pkts); > + void *rx_multicast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_pkts); > + void *tx_multicast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_bytes); > + void *rx_multicast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_bytes); > + void *tx_broadcast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_pkts); > + void *tx_broadcast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_bytes); > + void *rx_broadcast_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_pkts); > + void *rx_broadcast_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_bytes); > + void *tx_mtu_drop_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts); > + void *tx_mtu_drop_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes); > + void *rx_mtu_drop_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts); > + void *rx_mtu_drop_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes); > + void *tx_mtr_drop_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts); > + void *tx_mtr_drop_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes); > + void *rx_mtr_drop_pkts_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts); > + void *rx_mtr_drop_bytes_addr = > + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes); > if (!res_len || !res_info) { > PMD_DRV_LOG(ERR, "get stat invalid inparams"); > return -1; > @@ -1760,8 +1829,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_bytes); > + zxdh_data_hi_to_lo(tx_unicast_pkts_addr); > + zxdh_data_hi_to_lo(tx_unicast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_UNICAST_STATS_INGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1771,8 +1840,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_bytes); > + zxdh_data_hi_to_lo(rx_unicast_pkts_addr); > + zxdh_data_hi_to_lo(rx_unicast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_EGRESS_BASE; > ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, > @@ -1781,8 +1850,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_bytes); > + zxdh_data_hi_to_lo(tx_multicast_pkts_addr); > + zxdh_data_hi_to_lo(tx_multicast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_INGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1792,8 +1861,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_bytes); > + zxdh_data_hi_to_lo(rx_multicast_pkts_addr); > + zxdh_data_hi_to_lo(rx_multicast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_EGRESS_BASE; > ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, > @@ -1802,8 +1871,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_bytes); > + zxdh_data_hi_to_lo(tx_broadcast_pkts_addr); > + zxdh_data_hi_to_lo(tx_broadcast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_INGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1813,8 +1882,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_bytes); > + zxdh_data_hi_to_lo(rx_broadcast_pkts_addr); > + zxdh_data_hi_to_lo(rx_broadcast_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_EGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1824,10 +1893,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - res_info->np_stats.tx_mtu_drop_pkts = stats_data.n_pkts_dropped; > - res_info->np_stats.tx_mtu_drop_bytes = stats_data.n_bytes_dropped; > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_bytes); > + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts, stats_data.n_pkts_dropped); > + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes, stats_data.n_bytes_dropped); > + zxdh_data_hi_to_lo(tx_mtu_drop_pkts_addr); > + zxdh_data_hi_to_lo(tx_mtu_drop_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_INGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1837,10 +1906,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - res_info->np_stats.rx_mtu_drop_pkts = stats_data.n_pkts_dropped; > - res_info->np_stats.rx_mtu_drop_bytes = stats_data.n_bytes_dropped; > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_bytes); > + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts, stats_data.n_pkts_dropped); > + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes, stats_data.n_bytes_dropped); > + zxdh_data_hi_to_lo(rx_mtu_drop_pkts_addr); > + zxdh_data_hi_to_lo(rx_mtu_drop_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_EGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1850,10 +1919,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - res_info->np_stats.tx_mtr_drop_pkts = stats_data.n_pkts_dropped; > - res_info->np_stats.tx_mtr_drop_bytes = stats_data.n_bytes_dropped; > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_bytes); > + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts, stats_data.n_pkts_dropped); > + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes, stats_data.n_bytes_dropped); > + > + zxdh_data_hi_to_lo(tx_mtr_drop_pkts_addr); > + zxdh_data_hi_to_lo(tx_mtr_drop_bytes_addr); > > idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_INGRESS_BASE; > memset(&stats_data, 0, sizeof(stats_data)); > @@ -1863,10 +1933,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); > return ret; > } > - res_info->np_stats.rx_mtr_drop_pkts = stats_data.n_pkts_dropped; > - res_info->np_stats.rx_mtr_drop_bytes = stats_data.n_bytes_dropped; > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_pkts); > - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_bytes); > + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts, stats_data.n_pkts_dropped); > + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes, stats_data.n_bytes_dropped); > + > + zxdh_data_hi_to_lo(rx_mtr_drop_pkts_addr); > + zxdh_data_hi_to_lo(rx_mtr_drop_bytes_addr); > *res_len = sizeof(struct zxdh_hw_np_stats); > > return 0; > @@ -1875,12 +1946,13 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, > static int > zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, > uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, > + void *res_info, > uint16_t *res_len) > { > struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = > (struct zxdh_mtr_stats_query *)cfg_data; > union zxdh_virport_num v_port = {.vport = vport}; > + uint8_t *hw_mtr_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_mtr_stats); > int ret = 0; > > uint32_t stat_baseaddr = zxdh_mtr_stats_query->direction == > @@ -1892,14 +1964,14 @@ zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, > PMD_DRV_LOG(ERR, "get stat invalid in params"); > return -1; > } > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, > - 1, idx, (uint32_t *)&res_info->hw_mtr_stats); > + 1, idx, (uint32_t *)hw_mtr_stats_addr); > if (ret) { > PMD_DRV_LOG(ERR, "get dir %d stats failed", zxdh_mtr_stats_query->direction); > return ret; > } > - res_info->flag = ZXDH_REPS_SUCC; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > *res_len = sizeof(struct zxdh_hw_mtr_stats); > return 0; > } > @@ -1908,7 +1980,7 @@ static int > zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, > uint16_t vport, > void *cfg_data, > - struct zxdh_msg_reply_body *res_info, > + void *res_info, > uint16_t *res_len) > { > if (!cfg_data || !res_len || !res_info) { > @@ -1917,16 +1989,18 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, > } > struct rte_mtr_error error = {0}; > int ret = 0; > - uint64_t profile_id = HW_PROFILE_MAX; > + uint64_t hw_profile_id = HW_PROFILE_MAX; > + void *mtr_profile_info_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, mtr_profile_info); > > struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = > (struct zxdh_plcr_profile_add *)cfg_data; > > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > + > *res_len = sizeof(struct zxdh_mtr_profile_info); > ret = zxdh_hw_profile_alloc_direct(pf_hw->eth_dev, > zxdh_plcr_profile_add->car_type, > - &profile_id, &error); > + &hw_profile_id, &error); > > if (ret) { > PMD_DRV_LOG(ERR, "pf 0x%x for vf 0x%x alloc hw profile failed", > @@ -1935,9 +2009,9 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, > ); > return -1; > } > - zxdh_hw_profile_ref(profile_id); > - res_info->mtr_profile_info.profile_id = profile_id; > - res_info->flag = ZXDH_REPS_SUCC; > + zxdh_hw_profile_ref(hw_profile_id); > + ZXDH_SET(mtr_profile_info, mtr_profile_info_addr, profile_id, hw_profile_id); > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > > return 0; > } > @@ -1946,7 +2020,7 @@ static int > zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, > uint16_t vport, > void *cfg_data, > - struct zxdh_msg_reply_body *res_info, > + void *res_info, > uint16_t *res_len) > { > if (!cfg_data || !res_len || !res_info) { > @@ -1954,7 +2028,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, > return -1; > } > > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > *res_len = 0; > struct zxdh_plcr_profile_free *mtr_profile_free = (struct zxdh_plcr_profile_free *)cfg_data; > uint64_t profile_id = mtr_profile_free->profile_id; > @@ -1980,7 +2054,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, > RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, > "Meter offload del profile failed "); > } > - res_info->flag = ZXDH_REPS_SUCC; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > return 0; > } > > @@ -1988,7 +2062,7 @@ static int > zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, > uint16_t vport, > void *cfg_data, > - struct zxdh_msg_reply_body *res_info, > + void *res_info, > uint16_t *res_len) > { > int ret = 0; > @@ -2000,7 +2074,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, > struct rte_mtr_error error = {0}; > struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = (struct zxdh_plcr_flow_cfg *)cfg_data; > > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > *res_len = 0; > ret = zxdh_np_stat_car_queue_cfg_set(pf_hw->dev_id, > zxdh_plcr_flow_cfg->car_type, > @@ -2019,7 +2093,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, > RTE_MTR_ERROR_TYPE_MTR_PARAMS, > NULL, "Failed to bind plcr flow."); > } > - res_info->flag = ZXDH_REPS_SUCC; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > return 0; > } > > @@ -2027,7 +2101,7 @@ static int > zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, > uint16_t vport, > void *cfg_data, > - struct zxdh_msg_reply_body *res_info, > + void *res_info, > uint16_t *res_len) > { > int ret = 0; > @@ -2036,14 +2110,15 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, > PMD_DRV_LOG(ERR, " cfg profile invalid inparams"); > return -1; > } > - res_info->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); > *res_len = 0; > struct rte_mtr_error error = {0}; > struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = > (struct zxdh_plcr_profile_cfg *)cfg_data; > union zxdh_offload_profile_cfg *plcr_param = &zxdh_plcr_profile_cfg->plcr_param; > > - ret = zxdh_np_car_profile_cfg_set(vport, > + ret = zxdh_np_car_profile_cfg_set(pf_hw->dev_id, > + vport, > zxdh_plcr_profile_cfg->car_type, > zxdh_plcr_profile_cfg->packet_mode, > zxdh_plcr_profile_cfg->hw_profile_id, > @@ -2052,7 +2127,7 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, > PMD_DRV_LOG(ERR, "(vport %d)config hw profilefailed", vport); > return -rte_mtr_error_set(&error, ENOTSUP, RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, "Meter offload cfg profile failed"); > } > - res_info->flag = ZXDH_REPS_SUCC; > + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); > return 0; > } > > @@ -2083,7 +2158,7 @@ static const zxdh_msg_process_callback zxdh_proc_cb[] = { > > static inline int > zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, > - struct zxdh_msg_reply_body *res, uint16_t *res_len) > + void *res, uint16_t *res_len) > { > struct zxdh_msg_head *msghead = &msg_info->msg_head; > int ret = -1; > @@ -2096,13 +2171,13 @@ zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, > ret = zxdh_proc_cb[msghead->msg_type](hw, msghead->vport, > (void *)&msg_info->data, res, res_len); > if (!ret) > - res->flag = ZXDH_REPS_SUCC; > + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_SUCC); > else > - res->flag = ZXDH_REPS_FAIL; > + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_FAIL); > } else { > - res->flag = ZXDH_REPS_INVALID; > + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_INVALID); > } > - *res_len += sizeof(res->flag); > + *res_len += sizeof(uint8_t); > return ret; > } > > @@ -2111,7 +2186,7 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, > uint16_t *reps_len, void *eth_dev) > { > struct zxdh_msg_info *msg_info = (struct zxdh_msg_info *)pay_load; > - struct zxdh_msg_reply_body *reply_body = reps_buffer; > + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reps_buffer, reply_data); > struct rte_eth_dev *dev = (struct rte_eth_dev *)eth_dev; > int32_t ret = 0; > struct zxdh_hw *hw; > @@ -2131,14 +2206,14 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, > goto msg_proc_end; > } > > - ret = zxdh_config_process_callback(hw, msg_info, reply_body, &reply_len); > - *reps_len = reply_len + sizeof(struct zxdh_msg_reply_head); > + ret = zxdh_config_process_callback(hw, msg_info, reps_buffer, &reply_len); > + *reps_len = reply_len + ZXDH_ST_SZ_BYTES(msg_reply_head); > return ret; > > msg_proc_end: > - memcpy(reply_body->reply_data, &ret, sizeof(ret)); > + memcpy(reply_data_addr, &ret, sizeof(ret)); > reply_len = sizeof(ret); > - *reps_len = sizeof(struct zxdh_msg_reply_head) + reply_len; > + *reps_len = ZXDH_ST_SZ_BYTES(msg_reply_head) + reply_len; > return ret; > } > > diff --git a/drivers/net/zxdh/zxdh_msg.h b/drivers/net/zxdh/zxdh_msg.h > index 58836bb4b7..7dad6f7335 100644 > --- a/drivers/net/zxdh/zxdh_msg.h > +++ b/drivers/net/zxdh/zxdh_msg.h > @@ -11,6 +11,7 @@ > > #include "zxdh_ethdev_ops.h" > #include "zxdh_mtr.h" > +#include "zxdh_common.h" > > #define ZXDH_BAR0_INDEX 0 > #define ZXDH_CTRLCH_OFFSET (0x2000) > @@ -46,8 +47,10 @@ > > #define ZXDH_MSG_REPLYBODY_HEAD sizeof(enum zxdh_reps_flag) > #define ZXDH_MSG_HEADER_SIZE 4 > -#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ > - (ZXDH_MSG_PAYLOAD_MAX_LEN - sizeof(struct zxdh_msg_reply_head)) > +#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ > + (ZXDH_MSG_PAYLOAD_MAX_LEN - ZXDH_MSG_HEADER_SIZE) > +#define ZXDH_MSG_REPLY_DATA \ > + (ZXDH_MSG_REPLY_BODY_MAX_LEN - ZXDH_MSG_REPLYBODY_HEAD) > > #define ZXDH_MSG_HEAD_LEN 8 > #define ZXDH_MSG_REQ_BODY_MAX_LEN \ > @@ -329,12 +332,6 @@ struct zxdh_offset_get_msg { > uint16_t type; > }; > > -struct zxdh_msg_reply_head { > - uint8_t flag; > - uint16_t reps_len; > - uint8_t resvd; > -}; > - > enum zxdh_reps_flag { > ZXDH_REPS_FAIL, > ZXDH_REPS_SUCC = 0xaa, > @@ -354,18 +351,39 @@ struct zxdh_link_info_msg { > uint32_t speed; > }; > > +struct zxdh_ifc_link_info_msg_bits { > + uint8_t autoneg[0x8]; > + uint8_t link_state[0x8]; > + uint8_t blink_enable[0x8]; > + uint8_t duplex[0x8]; > + uint8_t speed_modes[0x20]; > + uint8_t speed[0x20]; > +}; > + > struct zxdh_rss_reta { > uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256]; > }; > > +struct zxdh_ifc_rss_reta_bits { > + uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256 * 8]; > +}; > + > struct zxdh_rss_hf { > uint32_t rss_hf; > }; > > +struct zxdh_ifc_rss_hf_bits { > + uint8_t rss_hf[0x20]; > +}; > + > struct zxdh_mac_reply_msg { > uint8_t mac_flag; > }; > > +struct zxdh_ifc_mac_reply_msg_bits { > + uint8_t mac_flag[0x8]; > +}; > + > struct zxdh_mac_module_eeprom_msg { > uint8_t i2c_addr; > uint8_t bank; > @@ -375,34 +393,57 @@ struct zxdh_mac_module_eeprom_msg { > uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN]; > }; > > +struct zxdh_ifc_agent_mac_module_eeprom_msg_bits { > + uint8_t i2c_addr[0x8]; > + uint8_t bank[0x8]; > + uint8_t page[0x8]; > + uint8_t offset[0x8]; > + uint8_t length[0x8]; > + uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN * 8]; > +}; > + > struct zxdh_flash_msg { > uint8_t firmware_version[ZXDH_FWVERS_LEN]; > }; > > +struct zxdh_ifc_agent_flash_msg_bits { > + uint8_t firmware_version[0x100]; > +}; > + > struct zxdh_mtr_profile_info { > uint64_t profile_id; > }; > > -struct zxdh_msg_reply_body { > - enum zxdh_reps_flag flag; > +struct zxdh_ifc_mtr_profile_info_bits { > + uint8_t profile_id[0x40]; > +}; > + > +struct zxdh_ifc_msg_reply_body_bits { > + uint8_t flag[0x8]; > union { > - uint8_t reply_data[ZXDH_MSG_REPLY_BODY_MAX_LEN - sizeof(enum zxdh_reps_flag)]; > - struct zxdh_hw_np_stats np_stats; > - struct zxdh_link_info_msg link_msg; > - struct zxdh_rss_reta rss_reta; > - struct zxdh_rss_hf rss_hf; > - struct zxdh_hw_vqm_stats vqm_stats; > - struct zxdh_mac_reply_msg mac_reply_msg; > - struct zxdh_flash_msg flash_msg; > - struct zxdh_mac_module_eeprom_msg module_eeprom_msg; > - struct zxdh_mtr_profile_info mtr_profile_info; > - struct zxdh_mtr_stats hw_mtr_stats; > + uint8_t reply_data[ZXDH_MSG_REPLY_DATA * 8]; > + struct zxdh_ifc_hw_np_stats_bits hw_stats; > + struct zxdh_ifc_link_info_msg_bits link_msg; > + struct zxdh_ifc_rss_reta_bits rss_reta_msg; > + struct zxdh_ifc_rss_hf_bits rss_hf_msg; > + struct zxdh_ifc_hw_vqm_stats_bits vqm_stats; > + struct zxdh_ifc_mac_reply_msg_bits mac_reply_msg; > + struct zxdh_ifc_agent_flash_msg_bits flash_msg; > + struct zxdh_ifc_agent_mac_module_eeprom_msg_bits module_eeprom_msg; > + struct zxdh_ifc_mtr_profile_info_bits mtr_profile_info; > + struct zxdh_ifc_mtr_stats_bits hw_mtr_stats; > }; > }; > > -struct zxdh_msg_reply_info { > - struct zxdh_msg_reply_head reply_head; > - struct zxdh_msg_reply_body reply_body; > +struct zxdh_ifc_msg_reply_head_bits { > + uint8_t flag[0x8]; > + uint8_t reps_len[0x10]; > + uint8_t resvd[0x8]; > +}; > + > +struct zxdh_ifc_msg_reply_info_bits { > + struct zxdh_ifc_msg_reply_head_bits reply_head; > + struct zxdh_ifc_msg_reply_body_bits reply_body; > }; > > struct zxdh_vf_init_msg { > @@ -412,12 +453,12 @@ struct zxdh_vf_init_msg { > uint8_t rss_enable; > }; > > -struct zxdh_msg_head { > - enum zxdh_msg_type msg_type; > +struct __rte_packed_begin zxdh_msg_head { > + uint8_t msg_type; > uint16_t vport; > uint16_t vf_id; > uint16_t pcieid; > -}; > +} __rte_packed_end; > > struct zxdh_port_attr_set_msg { > uint32_t mode; > @@ -455,7 +496,7 @@ struct zxdh_rss_enable { > }; > > struct zxdh_agent_msg_head { > - enum zxdh_agent_msg_type msg_type; > + uint8_t msg_type; > uint8_t panel_id; > uint8_t phyport; > uint8_t rsv; > @@ -526,7 +567,7 @@ struct zxdh_msg_info { > typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, > void *reps_buffer, uint16_t *reps_len, void *dev); > typedef int (*zxdh_msg_process_callback)(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, > - struct zxdh_msg_reply_body *res_info, uint16_t *res_len); > + void *res_info, uint16_t *res_len); > > typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, > void *reps_buffer, uint16_t *reps_len, void *dev); > diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c > index 3797a5b29b..b23f6535a8 100644 > --- a/drivers/net/zxdh/zxdh_mtr.c > +++ b/drivers/net/zxdh/zxdh_mtr.c > @@ -281,7 +281,7 @@ zxdh_hw_profile_free_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type, > { > struct zxdh_hw *hw = dev->data->dev_private; > uint16_t vport = hw->vport.vport; > - int ret = zxdh_np_car_profile_id_delete(vport, car_type, > + int ret = zxdh_np_car_profile_id_delete(hw->dev_id, vport, car_type, > (uint64_t)hw_profile_id); > if (ret) { > PMD_DRV_LOG(ERR, "port %u free hw profile %u failed", vport, hw_profile_id); > @@ -299,7 +299,7 @@ zxdh_hw_profile_alloc_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type > uint64_t profile_id = HW_PROFILE_MAX; > struct zxdh_hw *hw = dev->data->dev_private; > uint16_t vport = hw->vport.vport; > - int ret = zxdh_np_car_profile_id_add(vport, car_type, &profile_id); > + int ret = zxdh_np_car_profile_id_add(hw->dev_id, vport, car_type, &profile_id); > > if (ret) { > PMD_DRV_LOG(ERR, "port %u alloc hw profile failed", vport); > @@ -326,7 +326,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, > ret = zxdh_hw_profile_free_direct(dev, car_type, (uint64_t)hw_profile_id, error); > } else { > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > struct zxdh_plcr_profile_free *zxdh_plcr_profile_free = > &msg_info.data.zxdh_plcr_profile_free; > > @@ -335,7 +335,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, > zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_DELETE, &msg_info); > ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, > ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_free), > - &reply_info, sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > > if (ret) > return -rte_mtr_error_set(error, ENOTSUP, > @@ -357,15 +357,19 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, > ret = zxdh_hw_profile_alloc_direct(dev, CAR_A, hw_profile_id, error); > } else { > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = > &msg_info.data.zxdh_plcr_profile_add; > + void *reply_body_addr = > + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *mtr_profile_info_addr = > + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, mtr_profile_info); > > zxdh_plcr_profile_add->car_type = CAR_A; > zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_ADD, &msg_info); > ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, > ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_add), > - &reply_info, sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); > > if (ret) { > PMD_DRV_LOG(ERR, > @@ -376,7 +380,7 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, > RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, > "Meter offload alloc profile id msg failed "); > } > - *hw_profile_id = reply_info.reply_body.mtr_profile_info.profile_id; > + *hw_profile_id = ZXDH_GET(mtr_profile_info, mtr_profile_info_addr, profile_id); > if (*hw_profile_id == ZXDH_HW_PROFILE_MAX) { > return -rte_mtr_error_set(error, ENOTSUP, > RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, > @@ -432,7 +436,7 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, > } > } else { /* send msg to pf */ > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = > &msg_info.data.zxdh_mtr_stats_query; > > @@ -442,8 +446,8 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, > ret = zxdh_vf_send_msg_to_pf(dev, > &msg_info, > sizeof(msg_info), > - &reply_info, > - sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, > + ZXDH_ST_SZ_BYTES(msg_reply_info)); > > if (ret) { > PMD_DRV_LOG(ERR, > @@ -451,7 +455,11 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, > hw->vport.vport); > return -rte_mtr_error_set(error, ENOTSUP, RTE_MTR_ERROR_TYPE_STATS, NULL, "Meter offload alloc profile failed"); > } > - struct zxdh_mtr_stats *hw_mtr_stats = &reply_info.reply_body.hw_mtr_stats; > + void *reply_body_addr = > + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); > + void *hw_mtr_stats_addr = > + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_mtr_stats); > + struct zxdh_mtr_stats *hw_mtr_stats = (struct zxdh_mtr_stats *)hw_mtr_stats_addr; > > mtr_stats->n_bytes_dropped = hw_mtr_stats->n_bytes_dropped; > mtr_stats->n_pkts_dropped = hw_mtr_stats->n_pkts_dropped; > @@ -551,7 +559,9 @@ zxdh_hw_profile_config_direct(struct rte_eth_dev *dev __rte_unused, > struct zxdh_meter_profile *mp, > struct rte_mtr_error *error) > { > - int ret = zxdh_np_car_profile_cfg_set(mp->hw_profile_owner_vport, > + struct zxdh_hw *hw = dev->data->dev_private; > + int ret = zxdh_np_car_profile_cfg_set(hw->dev_id, > + mp->hw_profile_owner_vport, > car_type, mp->profile.packet_mode, > (uint32_t)hw_profile_id, &mp->plcr_param); > if (ret) { > @@ -573,7 +583,7 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i > ret = zxdh_hw_profile_config_direct(dev, CAR_A, hw_profile_id, mp, error); > } else { > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = > &msg_info.data.zxdh_plcr_profile_cfg; > > @@ -588,9 +598,9 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i > ret = zxdh_vf_send_msg_to_pf(dev, > &msg_info, > ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_cfg), > - &reply_info, > - sizeof(struct zxdh_msg_reply_info)); > - > + zxdh_msg_reply_info, > + ZXDH_ST_SZ_BYTES(msg_reply_info) > + ); > if (ret) { > PMD_DRV_LOG(ERR, > "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_PROFILE_CFG_SET ", > @@ -874,7 +884,7 @@ zxdh_set_mtr_enable(struct rte_eth_dev *dev, uint8_t dir, bool enable, struct rt > > if (priv->is_pf) { > ret = zxdh_get_port_attr(priv, priv->vport.vport, &port_attr); > - port_attr.ingress_meter_enable = enable; > + port_attr.egress_meter_enable = enable; > ret = zxdh_set_port_attr(priv, priv->vport.vport, &port_attr); > if (ret) { > PMD_DRV_LOG(ERR, "%s set port attr failed", __func__); > @@ -936,7 +946,7 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, > } > } else { > struct zxdh_msg_info msg_info = {0}; > - struct zxdh_msg_reply_info reply_info = {0}; > + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; > struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = &msg_info.data.zxdh_plcr_flow_cfg; > > zxdh_plcr_flow_cfg->car_type = CAR_A; > @@ -947,8 +957,8 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, > zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_QUEUE_CFG_SET, &msg_info); > ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, > ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_flow_cfg), > - &reply_info, > - sizeof(struct zxdh_msg_reply_info)); > + zxdh_msg_reply_info, > + ZXDH_ST_SZ_BYTES(msg_reply_info)); > if (ret) { > PMD_DRV_LOG(ERR, > "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_QUEUE_CFG_SET ", > diff --git a/drivers/net/zxdh/zxdh_mtr.h b/drivers/net/zxdh/zxdh_mtr.h > index 749ceb7479..3efcb6b591 100644 > --- a/drivers/net/zxdh/zxdh_mtr.h > +++ b/drivers/net/zxdh/zxdh_mtr.h > @@ -93,6 +93,11 @@ struct zxdh_mtr_stats { > uint64_t n_bytes_dropped; > }; > > +struct zxdh_ifc_mtr_stats_bits { > + uint8_t n_pkts_dropped[0x40]; > + uint8_t n_bytes_dropped[0x40]; > +}; > + > struct zxdh_hw_mtr_stats { > uint32_t n_pkts_dropped_hi; > uint32_t n_pkts_dropped_lo; > diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c > index ab8b3ae688..66902e7e92 100644 > --- a/drivers/net/zxdh/zxdh_np.c > +++ b/drivers/net/zxdh/zxdh_np.c > @@ -2350,6 +2350,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, > > rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); > > + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); > + > for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) > rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); > > @@ -3391,6 +3393,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, > return rc; > } > > +static uint32_t > +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, > + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) > +{ > + uint32_t rc = 0; > + uint32_t addr = 0; > + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; > + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; > + uint32_t reg_real_no = p_reg_info->reg_no; > + uint32_t reg_type = p_reg_info->flags; > + uint32_t reg_module = p_reg_info->module_no; > + > + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); > + > + if (reg_module == DTB4K) { > + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); > + } else { > + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); > + *p_data = p_buff[0]; > + } > + > + return rc; > +} > + > static uint32_t > zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, > uint32_t queue_id, > @@ -10542,9 +10570,9 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) > uint32_t done_flag = 0; > > while (!done_flag) { > - rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); > + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); > if (rc != 0) { > - PMD_DRV_LOG(ERR, "reg_read fail!"); > + PMD_DRV_LOG(ERR, "reg_read32 fail!"); > return rc; > } > > @@ -10577,10 +10605,17 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > uint32_t temp_data[4] = {0}; > uint32_t *p_temp_data = NULL; > ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; > + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; > + > + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); > + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); > + > + rte_spinlock_lock(&p_ind_spinlock->spinlock); > > rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); > if (rc != ZXDH_OK) { > PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > > @@ -10592,11 +10627,13 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > switch (rd_mode) { > case ZXDH_ERAM128_OPR_128b: > if ((0xFFFFFFFF - (base_addr)) < (index)) { > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); > return ZXDH_PAR_CHK_INVALID_INDEX; > } > if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; > @@ -10604,6 +10641,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_64b: > if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; > @@ -10612,6 +10650,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_32b: > if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; > @@ -10620,6 +10659,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_1b: > if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = index & ZXDH_ERAM128_BADDR_MASK; > @@ -10638,10 +10678,12 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_128b: > if ((0xFFFFFFFF - (base_addr)) < (index)) { > PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_PAR_CHK_INVALID_INDEX; > } > if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 7); > @@ -10650,6 +10692,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_64b: > if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 6); > @@ -10658,6 +10701,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > case ZXDH_ERAM128_OPR_32b: > if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { > PMD_DRV_LOG(ERR, "index out of range!"); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > row_index = (index << 5); > @@ -10665,7 +10709,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > break; > case ZXDH_ERAM128_OPR_1b: > PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", > - rd_clr_mode, rd_mode); > + rd_clr_mode, rd_mode); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > default: > break; > @@ -10680,12 +10725,14 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > &cpu_ind_cmd); > if (rc != ZXDH_OK) { > PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > > rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); > if (rc != ZXDH_OK) { > PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > > @@ -10698,6 +10745,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > p_temp_data + 3 - i); > if (rc != ZXDH_OK) { > PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > return ZXDH_ERR; > } > } > @@ -10736,6 +10784,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, > } > } > > + rte_spinlock_unlock(&p_ind_spinlock->spinlock); > + > return rc; > } > > @@ -10789,7 +10839,7 @@ zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MS > { > uint32_t ret = 0; > ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { > - .msg = (void *)&p_msg, > + .msg = (void *)p_msg, > .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), > }; > > @@ -11012,7 +11062,8 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, > } > > uint32_t > -zxdh_np_car_profile_id_add(uint32_t vport_id, > +zxdh_np_car_profile_id_add(uint32_t dev_id, > + uint32_t vport_id, > uint32_t flags, > uint64_t *p_profile_id) > { > @@ -11027,7 +11078,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, > PMD_DRV_LOG(ERR, "profile_id point null!"); > return ZXDH_PAR_CHK_POINT_NULL; > } > - ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); > + ret = zxdh_np_agent_channel_plcr_profileid_request(dev_id, vport_id, flags, profile_id); > > profile_id_h = *(profile_id + 1); > profile_id_l = *profile_id; > @@ -11045,14 +11096,14 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, > } > > uint32_t > -zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, > +zxdh_np_car_profile_cfg_set(uint32_t dev_id, > + uint32_t vport_id __rte_unused, > uint32_t car_type, > uint32_t pkt_sign, > uint32_t profile_id, > void *p_car_profile_cfg) > { > uint32_t ret = 0; > - uint32_t dev_id = 0; > > ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, > pkt_sign, profile_id, p_car_profile_cfg); > @@ -11065,11 +11116,10 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, > } > > uint32_t > -zxdh_np_car_profile_id_delete(uint32_t vport_id, > +zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, > uint32_t flags, uint64_t profile_id) > { > uint32_t ret = 0; > - uint32_t dev_id = 0; > uint32_t profileid = profile_id & 0xFFFF; > > ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); > diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h > index b1d8b1aef8..1b8f17474d 100644 > --- a/drivers/net/zxdh/zxdh_np.h > +++ b/drivers/net/zxdh/zxdh_np.h > @@ -1934,15 +1934,17 @@ uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, > uint32_t clr_mode, > uint32_t *p_data); > uint32_t > -zxdh_np_car_profile_id_add(uint32_t vport_id, > +zxdh_np_car_profile_id_add(uint32_t dev_id, > + uint32_t vport_id, > uint32_t flags, > uint64_t *p_profile_id); > -uint32_t zxdh_np_car_profile_cfg_set(uint32_t vport_id, > +uint32_t zxdh_np_car_profile_cfg_set(uint32_t dev_id, > + uint32_t vport_id, > uint32_t car_type, > uint32_t pkt_sign, > uint32_t profile_id, > void *p_car_profile_cfg); > -uint32_t zxdh_np_car_profile_id_delete(uint32_t vport_id, > +uint32_t zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, > uint32_t flags, uint64_t profile_id); > uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, > uint32_t car_type, > diff --git a/drivers/net/zxdh/zxdh_pci.c b/drivers/net/zxdh/zxdh_pci.c > index 3d1a3ff0dd..4ff0f065df 100644 > --- a/drivers/net/zxdh/zxdh_pci.c > +++ b/drivers/net/zxdh/zxdh_pci.c > @@ -27,6 +27,23 @@ > 1ULL << ZXDH_F_NOTIFICATION_DATA | \ > 1ULL << ZXDH_NET_F_MAC) > > +#define ZXDH_PMD_DEFAULT_HOST_FEATURES \ > + (1ULL << ZXDH_NET_F_MRG_RXBUF | \ > + 1ULL << ZXDH_NET_F_STATUS | \ > + 1ULL << ZXDH_NET_F_MQ | \ > + 1ULL << ZXDH_F_ANY_LAYOUT | \ > + 1ULL << ZXDH_F_VERSION_1 | \ > + 1ULL << ZXDH_F_RING_PACKED | \ > + 1ULL << ZXDH_F_IN_ORDER | \ > + 1ULL << ZXDH_F_NOTIFICATION_DATA |\ > + 1ULL << ZXDH_NET_F_MAC | \ > + 1ULL << ZXDH_NET_F_CSUM |\ > + 1ULL << ZXDH_NET_F_GUEST_CSUM |\ > + 1ULL << ZXDH_NET_F_GUEST_TSO4 |\ > + 1ULL << ZXDH_NET_F_GUEST_TSO6 |\ > + 1ULL << ZXDH_NET_F_HOST_TSO4 |\ > + 1ULL << ZXDH_NET_F_HOST_TSO6) > + > static void > zxdh_read_dev_config(struct zxdh_hw *hw, size_t offset, > void *dst, int32_t length) > @@ -391,13 +408,18 @@ zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t l > ZXDH_VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length); > } > > +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length) > +{ > + ZXDH_VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length); > +} > + > void > zxdh_get_pci_dev_config(struct zxdh_hw *hw) > { > uint64_t guest_features = 0; > uint64_t nego_features = 0; > > - hw->host_features = zxdh_pci_get_features(hw); > + hw->host_features = ZXDH_PMD_DEFAULT_HOST_FEATURES; > > guest_features = (uint64_t)ZXDH_PMD_DEFAULT_GUEST_FEATURES; > nego_features = guest_features & hw->host_features; > diff --git a/drivers/net/zxdh/zxdh_pci.h b/drivers/net/zxdh/zxdh_pci.h > index 9b8bef6c09..a1834f6615 100644 > --- a/drivers/net/zxdh/zxdh_pci.h > +++ b/drivers/net/zxdh/zxdh_pci.h > @@ -162,7 +162,7 @@ void zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, > > int32_t zxdh_read_pci_caps(struct rte_pci_device *dev, struct zxdh_hw *hw); > void zxdh_get_pci_dev_config(struct zxdh_hw *hw); > - > +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length); > uint16_t zxdh_pci_get_features(struct zxdh_hw *hw); > enum zxdh_msix_status zxdh_pci_msix_detect(struct rte_pci_device *dev); > uint8_t zxdh_pci_isr(struct zxdh_hw *hw); > diff --git a/drivers/net/zxdh/zxdh_rxtx.c b/drivers/net/zxdh/zxdh_rxtx.c > index 1921a23f25..9bb57d4f84 100644 > --- a/drivers/net/zxdh/zxdh_rxtx.c > +++ b/drivers/net/zxdh/zxdh_rxtx.c > @@ -760,7 +760,6 @@ zxdh_rx_update_mbuf(struct rte_mbuf *m, struct zxdh_net_hdr_ul *hdr) > idx = (pkt_type_inner >> 4) & 0xF; > m->packet_type |= zxdh_inner_l4_type[idx]; > } > - > } > > static void zxdh_discard_rxbuf(struct zxdh_virtqueue *vq, struct rte_mbuf *m) > @@ -818,9 +817,14 @@ zxdh_recv_pkts_packed(void *rx_queue, struct rte_mbuf **rx_pkts, > seg_num = header->type_hdr.num_buffers; > > /* Private queue only handle type hdr */ > - hdr_size = ZXDH_TYPE_HDR_SIZE; > - rxm->pkt_len = ((header->type_hdr.port & 0x7f) << 8) + > - header->type_hdr.pd_len; > + hdr_size = header->type_hdr.pd_len << 1; > + if (unlikely(hdr_size > lens[i] || hdr_size < ZXDH_TYPE_HDR_SIZE)) { > + PMD_RX_LOG(ERR, "hdr_size:%u is invalid", hdr_size); > + rte_pktmbuf_free(rxm); > + rxvq->stats.errors++; > + rxvq->stats.invalid_hdr_len_err++; > + continue; > + } > rxm->data_off += hdr_size; > rxm->nb_segs = seg_num; > rxm->ol_flags = 0; > diff --git a/drivers/net/zxdh/zxdh_tables.c b/drivers/net/zxdh/zxdh_tables.c > index 253d9ce438..ab91d51948 100644 > --- a/drivers/net/zxdh/zxdh_tables.c > +++ b/drivers/net/zxdh/zxdh_tables.c > @@ -8,14 +8,7 @@ > #include "zxdh_tables.h" > #include "zxdh_logs.h" > > -#define ZXDH_SDT_VPORT_ATT_TABLE 1 > -#define ZXDH_SDT_PANEL_ATT_TABLE 2 > -#define ZXDH_SDT_RSS_ATT_TABLE 3 > -#define ZXDH_SDT_VLAN_ATT_TABLE 4 > -#define ZXDH_SDT_BROCAST_ATT_TABLE 6 > -#define ZXDH_SDT_UNICAST_ATT_TABLE 10 > -#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 > -#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 > + > > #define ZXDH_MAC_HASH_INDEX_BASE 64 > #define ZXDH_MAC_HASH_INDEX(index) (ZXDH_MAC_HASH_INDEX_BASE + (index)) > @@ -40,15 +33,16 @@ zxdh_set_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab > { > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > int ret = 0; > > - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; > + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; > ZXDH_DTB_USER_ENTRY_T user_entry_write = {ZXDH_SDT_VPORT_ATT_TABLE, (void *)&entry}; > > ret = zxdh_np_dtb_table_entry_write(hw->slot_id, > dtb_data->queueid, 1, &user_entry_write); > if (ret != 0) > - PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vport_num.vfid); > + PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vfid); > > return ret; > } > @@ -72,6 +66,7 @@ zxdh_port_attr_init(struct rte_eth_dev *dev) > port_attr.mtu = dev->data->mtu; > port_attr.mtu_enable = 1; > port_attr.is_up = 0; > + port_attr.hash_search_index = hw->hash_search_index; > if (!port_attr.rss_enable) > port_attr.port_base_qid = 0; > > @@ -144,6 +139,7 @@ int zxdh_panel_table_init(struct rte_eth_dev *dev) > panel.pf_vfid = zxdh_vport_to_vfid(hw->vport); > panel.mtu_enable = 1; > panel.mtu = dev->data->mtu; > + panel.port_vfid_1588 = panel.pf_vfid; > > ZXDH_DTB_ERAM_ENTRY_INFO_T panel_entry = { > .index = hw->phyport, > @@ -212,13 +208,14 @@ zxdh_get_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab > { > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; > ZXDH_DTB_USER_ENTRY_T user_entry_get = {ZXDH_SDT_VPORT_ATT_TABLE, &entry}; > int ret; > > ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry_get, 1); > if (ret != 0) > - PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vport_num.vfid, ret); > + PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vfid, ret); > > return ret; > } > @@ -229,7 +226,8 @@ zxdh_delete_port_attr(struct zxdh_hw *hw, uint16_t vport, > { > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; > ZXDH_DTB_USER_ENTRY_T user_entry = { > .sdt_no = ZXDH_SDT_VPORT_ATT_TABLE, > .p_entry_data = (void *)&entry > @@ -247,9 +245,9 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad > struct zxdh_mac_unicast_table unicast_table = {0}; > struct zxdh_mac_multicast_table multicast_table = {0}; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > uint32_t ret; > uint16_t group_id = 0; > - uint16_t vfid = vport_num.vfid; > > if (rte_is_unicast_ether_addr(addr)) { > rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); > @@ -351,15 +349,17 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad > struct zxdh_mac_unicast_table unicast_table = {0}; > struct zxdh_mac_multicast_table multicast_table = {0}; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > - uint32_t ret, del_flag = 0; > - uint16_t group_id = 0; > union zxdh_virport_num port = (union zxdh_virport_num)vport; > uint16_t vfid = zxdh_vport_to_vfid(port); > + uint32_t ret, del_flag = 0; > + uint16_t group_id = 0; > > if (rte_is_unicast_ether_addr(addr)) { > rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); > unicast_table.key.sriov_vlan_id = srv_vlanid; > unicast_table.key.sriov_vlan_tpid = srv_tpid; > + unicast_table.entry.hit_flag = 0; > + unicast_table.entry.vfid = rte_cpu_to_be_16(vfid & 0x7ff); > > ZXDH_DTB_HASH_ENTRY_INFO_T dtb_hash_entry = { > .p_actu_key = (uint8_t *)&unicast_table.key, > @@ -800,6 +800,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > struct zxdh_rss_to_vqid_table rss_vqid = {0}; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > int ret = 0; > > for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { > @@ -820,7 +821,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss > rss_vqid.vqm_qid[0] |= 0x8000; > #endif > ZXDH_DTB_ERAM_ENTRY_INFO_T entry = { > - .index = vport_num.vfid * 32 + i, > + .index = vfid * 32 + i, > .p_data = (uint32_t *)&rss_vqid > }; > ZXDH_DTB_USER_ENTRY_T user_entry_write = { > @@ -830,7 +831,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss > ret = zxdh_np_dtb_table_entry_write(hw->slot_id, > dtb_data->queueid, 1, &user_entry_write); > if (ret != 0) { > - PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vport_num.vfid); > + PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vfid); > return ret; > } > } > @@ -843,16 +844,17 @@ zxdh_rss_table_get(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss > struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; > struct zxdh_rss_to_vqid_table rss_vqid = {0}; > union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; > + uint16_t vfid = zxdh_vport_to_vfid(vport_num); > int ret = 0; > > for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { > - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid * 32 + i, (uint32_t *)&rss_vqid}; > + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid * 32 + i, (uint32_t *)&rss_vqid}; > ZXDH_DTB_USER_ENTRY_T user_entry = {ZXDH_SDT_RSS_ATT_TABLE, &entry}; > > ret = zxdh_np_dtb_table_entry_get(hw->slot_id, > dtb_data->queueid, &user_entry, 1); > if (ret != 0) { > - PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vport_num.vfid); > + PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vfid); > return -1; > } > > diff --git a/drivers/net/zxdh/zxdh_tables.h b/drivers/net/zxdh/zxdh_tables.h > index 2f2ada3a9f..cb34e38be8 100644 > --- a/drivers/net/zxdh/zxdh_tables.h > +++ b/drivers/net/zxdh/zxdh_tables.h > @@ -9,7 +9,13 @@ > > /* eram */ > #define ZXDH_SDT_VPORT_ATT_TABLE 1 > - > +#define ZXDH_SDT_PANEL_ATT_TABLE 2 > +#define ZXDH_SDT_RSS_ATT_TABLE 3 > +#define ZXDH_SDT_VLAN_ATT_TABLE 4 > +#define ZXDH_SDT_BROCAST_ATT_TABLE 6 > +#define ZXDH_SDT_UNICAST_ATT_TABLE 10 > +#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 > +#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 > /* hash */ > #define ZXDH_SDT_L2_ENTRY_TABLE0 64 > #define ZXDH_SDT_L2_ENTRY_TABLE1 65 > @@ -80,8 +86,6 @@ > #define ZXDH_MTR_STATS_EGRESS_BASE 0x7481 > #define ZXDH_MTR_STATS_INGRESS_BASE 0x7C81 > > -extern struct zxdh_dtb_shared_data g_dtb_data; > - > struct zxdh_port_vlan_table { > #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN > uint16_t business_vlan_tpid:16; > @@ -233,19 +237,51 @@ struct zxdh_port_attr_table { > }; > > struct zxdh_panel_table { > - uint16_t port_vfid_1588 : 11, > - rsv2 : 5; > - uint16_t pf_vfid : 11, > - rsv1 : 1, > - enable_1588_tc : 2, > - trust_mode : 1, > - hit_flag : 1; > - uint32_t mtu : 16, > - mtu_enable : 1, > - rsv : 3, > - tm_base_queue : 12; > - uint32_t rsv_1; > - uint32_t rsv_2; > +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN > + uint16_t port_vfid_1588 : 11, > + rsv2 : 5; > + uint16_t rsv1 : 11, > + tm_shape_enable : 1, > + enable_1588_tc : 2, > + trust_mode : 1, > + hit_flag : 1; > + uint16_t mtu : 16; > + uint16_t mtu_enable : 1, > + rsv : 3, > + tm_base_queue : 12; > + uint16_t lacp_pf_qid : 12, > + rsv5 : 4; > + uint16_t lacp_pf_vfid : 11, > + rsv6 : 2, > + member_port_up : 1, > + bond_link_up : 1, > + hw_bond_enable : 1; > + uint16_t rsv3 : 16; > + uint16_t pf_vfid : 11, > + rsv4 : 5; > +#else > + uint16_t rsv1 : 11, > + tm_shape_enable : 1, > + enable_1588_tc : 2, > + trust_mode : 1, > + hit_flag : 1; > + uint16_t port_vfid_1588 : 11, > + rsv2 : 5; > + uint16_t mtu_enable : 1, > + rsv : 3, > + tm_base_queue : 12; > + uint16_t mtu : 16; > + uint16_t lacp_pf_vfid : 11, > + rsv6 : 2, > + member_port_up : 1, > + bond_link_up : 1, > + hw_bond_enable : 1; > + uint16_t lacp_pf_qid : 12, > + rsv5 : 4; > + uint16_t pf_vfid : 11, > + rsv4 : 5; > + uint16_t rsv3 : 16; > +#endif > }; /* 16B */ > > struct zxdh_mac_unicast_key { ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v5 14/14] net/zxdh: fix debugging errors 2025-03-19 8:58 ` [PATCH v5 14/14] net/zxdh: fix debugging errors Bingbin Chen 2025-03-20 19:50 ` Stephen Hemminger @ 2025-03-21 3:07 ` Bingbin Chen 1 sibling, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 3:07 UTC (permalink / raw) To: stephen; +Cc: dev [-- Attachment #1.1.1: Type: text/plain, Size: 1938 bytes --] >> +struct zxdh_ifc_hw_np_stats_bits { >> + uint8_t rx_unicast_pkts[0x40]; >> + uint8_t tx_unicast_pkts[0x40]; >> + uint8_t rx_unicast_bytes[0x40]; >> + uint8_t tx_unicast_bytes[0x40]; >> + uint8_t rx_multicast_pkts[0x40]; >> + uint8_t tx_multicast_pkts[0x40]; >> + uint8_t rx_multicast_bytes[0x40]; >> + uint8_t tx_multicast_bytes[0x40]; >> + uint8_t rx_broadcast_pkts[0x40]; >> + uint8_t tx_broadcast_pkts[0x40]; >> + uint8_t rx_broadcast_bytes[0x40]; >> + uint8_t tx_broadcast_bytes[0x40]; >> + uint8_t rx_mtu_drop_pkts[0x40]; >> + uint8_t tx_mtu_drop_pkts[0x40]; >> + uint8_t rx_mtu_drop_bytes[0x40]; >> + uint8_t tx_mtu_drop_bytes[0x40]; >> + uint8_t rx_mtr_drop_pkts[0x40]; >> + uint8_t tx_mtr_drop_pkts[0x40]; >> + uint8_t rx_mtr_drop_bytes[0x40]; >> + uint8_t tx_mtr_drop_bytes[0x40]; >> + uint8_t tx_ssvpc_pkts[0x40]; >> +}; > Seems like 0x40 (ie 64) is a magic constant here. Is it based > on number of VF's or other value. Should be defined as constant > rather than open coded. Hi maintainer, it's not based on number of VF's or other value. it is just a uint64_t number. and the number will not be modified in the future. Due to the fact that our PF and VF use message retrieval statistics, when defining the return message result, the firmware did not align the header message according to 4 bytes. Therefore, we used a byte stream approach to retrieve the message by byte here. here is we used to convert struct zxdh_ifc_hw_np_stats_bits to byte stream. #define ZXDH_ST_SZ_BYTES(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 8) #define ZXDH_GET(typ, p, fld) ({ \ BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ zxdh_get_value(fld_sz, addr); \ }) Thanks. [-- Attachment #1.1.2: Type: text/html , Size: 4007 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [v5,00/14] net/zxdh: add network processor ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (13 preceding siblings ...) 2025-03-19 8:58 ` [PATCH v5 14/14] net/zxdh: fix debugging errors Bingbin Chen @ 2025-03-19 9:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen 15 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-19 9:31 UTC (permalink / raw) To: stephen; +Cc: dev [-- Attachment #1.1.1: Type: text/plain, Size: 264 bytes --] Hi, maintainer: This submission has made modifications based on the comments. After this round of submission, the basic functions of the zxdh driver will be complete. Subsequent merges will mainly focus on FD function supplements and bug fixes. Thanks. [-- Attachment #1.1.2: Type: text/html , Size: 470 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v6 00/14] net/zxdh: add network processor ops 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen ` (14 preceding siblings ...) 2025-03-19 9:31 ` [v5,00/14] net/zxdh: add network processor ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (14 more replies) 15 siblings, 15 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 2241 bytes --] v6: - Use byte stream to process bar channel return messages and modify some issues to ensure proper functionality. v5: - the VF read/write table function is fixed. v4: - change some tables to const. - use %u instead of %d. - delete cast of ret_zmalloc() return. - resolve code functionality issues. V3: - resolve code style. - resolve spin lock build issue. - rebase code baseline. - modify parameters of the plcr function. V2: - resolve code style and github-robot build issue. - eliminate commit warning. - remove unnecessary initialization, which first usage will set. - replace mutex lock with spinlock. V1: - updated network processor driver. - improve insert/delete/get table code funcs. Bingbin Chen (14): net/zxdh: add network processor registers ops net/zxdh: support compatibility check net/zxdh: add agent channel net/zxdh: modify dtb queue ops net/zxdh: add tables dump address ops net/zxdh: add eram tables ops net/zxdh: get flow tables resources net/zxdh: support hash resources configuration net/zxdh: implement tables initialization net/zxdh: support hash tables write and delete ops net/zxdh: get hash table entry result net/zxdh: delete all hash entries net/zxdh: add acl tables ops net/zxdh: optimize msg processing ops and modify some issues drivers/net/zxdh/zxdh_common.h | 100 + drivers/net/zxdh/zxdh_ethdev.c | 88 +- drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +- drivers/net/zxdh/zxdh_ethdev_ops.h | 35 + drivers/net/zxdh/zxdh_msg.c | 381 +- drivers/net/zxdh/zxdh_msg.h | 99 +- drivers/net/zxdh/zxdh_mtr.c | 50 +- drivers/net/zxdh/zxdh_mtr.h | 5 + drivers/net/zxdh/zxdh_np.c | 11631 +++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 1243 ++- drivers/net/zxdh/zxdh_pci.c | 24 +- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 12 +- drivers/net/zxdh/zxdh_tables.c | 67 +- drivers/net/zxdh/zxdh_tables.h | 68 +- 16 files changed, 11983 insertions(+), 1932 deletions(-) -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 4607 bytes --] ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v6 01/14] net/zxdh: add network processor registers ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 02/14] net/zxdh: support compatibility check Bingbin Chen ` (13 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 100114 bytes --] Add (np)network processor registers read/write interfaces. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1877 ++++++++++++++++++++++++++---------- drivers/net/zxdh/zxdh_np.h | 226 +++-- 2 files changed, 1511 insertions(+), 592 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 28c9e4c1c1..1534cb2709 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -15,7 +15,6 @@ #include "zxdh_logs.h" #include "zxdh_msg.h" -static uint64_t g_np_bar_offset; static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; static uint32_t g_dpp_dtb_int_enable; @@ -23,32 +22,209 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_REG_T g_dpp_reg_info[4]; -static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; -static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; +static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, +}; + +static const ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, +}; + +static const ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"rw_len", 123, 2}, + {"v46_flag", 121, 1}, + {"lpm_wr_vld", 120, 1}, + {"baddr", 119, 20}, + {"ecc_en", 99, 1}, + {"rw_addr", 29, 30}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 0, 1}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, + {"data_h", 63, 32}, + {"data_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"data_mode", 123, 2}, + {"cpu_wr", 121, 1}, + {"cpu_rd", 120, 1}, + {"cpu_rd_mode", 119, 1}, + {"addr", 113, 26}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"ram_reg_flag", 123, 1}, + {"zgroup_id", 122, 2}, + {"zblock_id", 120, 3}, + {"zcell_id", 117, 2}, + {"mask", 115, 4}, + {"sram_addr", 111, 9}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"block_sel", 123, 3}, + {"init_en", 120, 1}, + {"row_or_col_msk", 119, 1}, + {"vben", 118, 1}, + {"reg_tcam_flag", 117, 1}, + {"uload", 116, 8}, + {"rd_wr", 108, 1}, + {"wr_mode", 107, 8}, + {"data_or_mask", 99, 1}, + {"addr", 98, 9}, + {"vbit", 89, 8}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { + {"valid", 127, 1}, + {"type_mode", 126, 3}, + {"std_h", 63, 32}, + {"std_l", 31, 32}, +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { + { + "ddr", + ZXDH_DTB_TABLE_DDR, + 8, + g_dtb_ddr_table_cmd_info, + }, + { + "eram 1 bit", + ZXDH_DTB_TABLE_ERAM_1, + 8, + g_dtb_eram_table_cmd_1_info, + }, + { + "eram 64 bit", + ZXDH_DTB_TABLE_ERAM_64, + 9, + g_dtb_eram_table_cmd_64_info, + }, + { + "eram 128 bit", + ZXDH_DTB_TABLE_ERAM_128, + 7, + g_dtb_eram_table_cmd_128_info, + }, + { + "zcam", + ZXDH_DTB_TABLE_ZCAM, + 8, + g_dtb_zcam_table_cmd_info, + }, + { + "etcam", + ZXDH_DTB_TABLE_ETCAM, + 13, + g_dtb_etcam_table_cmd_info, + }, + { + "mc_hash", + ZXDH_DTB_TABLE_MC_HASH, + 4, + g_dtb_mc_hash_table_cmd_info + }, +}; #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) + +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ + (((data_len) & 0x3ff) | \ + ((int_en) << 29) | \ + ((cmd_type) << 30)) -#define ZXDH_COMM_MASK_BIT(_bitnum_)\ - (0x1U << (_bitnum_)) +static inline uint32_t +zxdh_np_comm_mask_bit(uint32_t bitnum) { + return (uint32_t)(0x1U << bitnum); +} -#define ZXDH_COMM_GET_BIT_MASK(_inttype_, _bitqnt_)\ - ((_inttype_)(((_bitqnt_) < 32))) +static inline uint32_t +zxdh_np_comm_get_bit_mask(uint32_t bit_quantity) { + if (bit_quantity < 32) + return zxdh_np_comm_mask_bit(bit_quantity & 0x1F) - 1; + else + return 0xFFFFFFFF; +} #define ZXDH_COMM_UINT32_GET_BITS(_uidst_, _uisrc_, _uistartpos_, _uilen_)\ ((_uidst_) = (((_uisrc_) >> (_uistartpos_)) & \ - (ZXDH_COMM_GET_BIT_MASK(uint32_t, (_uilen_))))) + (zxdh_np_comm_get_bit_mask((_uilen_))))) #define ZXDH_REG_DATA_MAX (128) #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\ do {\ if (NULL == (point)) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "dev: %u [POINT NULL]", (dev_id));\ RTE_ASSERT(0);\ } \ } while (0) @@ -56,33 +232,22 @@ do {\ #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d !"\ - "-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "dev: %u, %s failed!", (dev_id), becall);\ RTE_ASSERT(0);\ } \ } while (0) -#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ - } \ -} while (0) - #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d !-- %s Call %s"\ - " Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ } \ } while (0) #define ZXDH_COMM_CHECK_RC(rc, becall)\ do {\ if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d!-- %s Call %s "\ - "Fail!", __FILE__, __LINE__, __func__, becall);\ + PMD_DRV_LOG(ERR, "%s failed!", becall);\ RTE_ASSERT(0);\ } \ } while (0) @@ -90,34 +255,28 @@ do {\ #define ZXDH_COMM_CHECK_POINT(point)\ do {\ if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\ - __FILE__, __LINE__, __func__);\ + PMD_DRV_LOG(ERR, "[POINT NULL]");\ RTE_ASSERT(0);\ } \ } while (0) +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) +{ + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; +} -#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\ -do {\ - if ((point) == NULL) {\ - PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\ - "FUNCTION : %s!", __FILE__, __LINE__, __func__);\ - rte_free(ptr);\ - RTE_ASSERT(0);\ - } \ -} while (0) - -#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\ -do {\ - if ((rc) != 0) {\ - PMD_DRV_LOG(ERR, "ZXICP %s:%d, %s Call"\ - " %s Fail!", __FILE__, __LINE__, __func__, becall);\ - rte_free(ptr);\ - } \ -} while (0) +static inline uint32_t +zxdh_np_comm_convert32(uint32_t dw_data) +{ + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; +} #define ZXDH_COMM_CONVERT16(w_data) \ - (((w_data) & 0xff) << 8) + zxdh_np_comm_convert16(w_data) + +#define ZXDH_COMM_CONVERT32(w_data) \ + zxdh_np_comm_convert32(w_data) #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) @@ -132,10 +291,12 @@ do {\ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.data_len[(INDEX)]) #define ZXDH_DTB_TAB_UP_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) + (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.start_vir_addr + \ + (INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size) #define ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ - ((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.item_size) + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + \ + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size) #define ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.wr_index) @@ -143,7 +304,25 @@ do {\ #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) -ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"cara_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -155,7 +334,7 @@ ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carb_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carb_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -167,7 +346,7 @@ ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = { {"carb_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { +static ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"carc_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, {"carc_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0}, @@ -179,10 +358,69 @@ ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = { {"carc_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0}, }; -ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { +static ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = { {"pktrx_glbal_cfg_0", ZXDH_FIELD_FLAG_RW, 31, 32, 0x0, 0x0}, }; +static uint32_t zxdh_dtb_info_print(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + ZXDH_DTB_QUEUE_ITEM_INFO_T *item_info) +{ + uint64_t element_start_addr = 0; + uint64_t ack_start_addr = 0; + uint64_t data_addr = 0; + uint32_t data = 0; + uint32_t i = 0; + uint32_t j = 0; + + PMD_DRV_LOG(DEBUG, "queue: %u, element:%u, %s table info is:", + queue_id, item_index, (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "cmd_vld : %u", item_info->cmd_vld); + PMD_DRV_LOG(DEBUG, "cmd_type : %s", (item_info->cmd_type) ? "up" : "down"); + PMD_DRV_LOG(DEBUG, "int_en : %u", item_info->int_en); + PMD_DRV_LOG(DEBUG, "data_len : %u", item_info->data_len); + PMD_DRV_LOG(DEBUG, "data_hddr : 0x%x", item_info->data_hddr); + PMD_DRV_LOG(DEBUG, "data_laddr : 0x%x", item_info->data_laddr); + + if (item_info->cmd_type == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + ack_start_addr = + ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, item_index); + } + ack_start_addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index) + ZXDH_DTB_ITEM_ACK_SIZE; + } else { + ack_start_addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index); + element_start_addr = + ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + } + PMD_DRV_LOG(DEBUG, "dtb data:"); + + PMD_DRV_LOG(DEBUG, "ack info:"); + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(ack_start_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + + for (i = 0; i < item_info->data_len; i++) { + data_addr = element_start_addr + 16 * i; + + PMD_DRV_LOG(DEBUG, "row_%u:", i); + + for (j = 0; j < 4; j++) { + data = ZXDH_COMM_CONVERT32(*((uint32_t *)(data_addr + 4 * j))); + PMD_DRV_LOG(DEBUG, "0x%08x ", data); + } + } + + PMD_DRV_LOG(DEBUG, "zxdh dtb info print end."); + return ZXDH_OK; +} + static uint32_t zxdh_np_comm_is_big_endian(void) { @@ -215,7 +453,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) uc_byte_mode = dw_byte_len % 4 & 0xff; for (i = 0; i < dw_byte_num; i++) { - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); p_dw_tmp++; } @@ -239,6 +477,392 @@ zxdh_np_dev_init(void) return 0; } +static uint32_t +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", + dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", + p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", dev_id); + return ZXDH_ERR; + } + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); + } else { + PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", p_dev_info->access_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static void +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + data = *p_data; + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + *((volatile uint32_t *)addr) = data; +} + +static void +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) +{ + uint32_t data = 0; + uint64_t addr = 0; + + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; + data = *((volatile uint32_t *)addr); + + if (zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *p_data = data; +} + +static uint64_t +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + ZXDH_DEV_CFG_T *p_dev_info = NULL; + + p_dev_mgr = &g_dev_mgr; + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) + return ZXDH_DEV_TYPE_INVALID; + + return p_dev_info->pcie_addr; +} + +static void +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); +} + +static void +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) +{ + uint32_t i; + uint64_t abs_addr = 0; + + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; + + for (i = 0; i < size; i++) + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); +} + +static uint32_t +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_write(dev_id, addr, p_data); +} + +static uint32_t +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) +{ + return zxdh_np_read(dev_id, addr, p_data); +} + +static ZXDH_REG_T g_dpp_reg_info[] = { + { + .reg_name = "cpu_ind_cmd", + .reg_no = 669, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 4, + .p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rd_done", + .reg_no = 670, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat0", + .reg_no = 671, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat1", + .reg_no = 672, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat2", + .reg_no = 673, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "cpu_ind_rdat3", + .reg_no = 674, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "wr_arb_cpu_rdy", + .reg_no = 676, + .module_no = SMMU0, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg, + .p_write_fun = zxdh_np_se_smmu0_write, + .p_read_fun = zxdh_np_se_smmu0_read, + }, + { + .reg_name = "info_queue_buf_space_left_0_127", + .reg_no = 820, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 1, + .p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cfg_epid_v_func_num_0_127", + .reg_no = 821, + .module_no = DTB4K, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10, + .width = (32 / 8), + .m_size = 0, + .n_size = 127 + 1, + .m_step = 0, + .n_step = 32, + .field_num = 7, + .p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, + .p_write_fun = zxdh_np_write, + .p_read_fun = zxdh_np_read, + }, + { + .reg_name = "cara_queue_ram0_159_0", + .reg_no = 721, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x000000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x7FFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_cara_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carb_queue_ram0_159_0", + .reg_no = 738, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x100000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0xFFF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carb_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "carc_queue_ram0_159_0", + .reg_no = 755, + .module_no = STAT, + .flags = ZXDH_REG_FLAG_INDIRECT, + .array_type = ZXDH_REG_UNI_ARRAY, + .addr = 0x200000 + 0x14000000, + .width = (160 / 8), + .m_size = 0, + .n_size = 0x3FF + 1, + .m_step = 0, + .n_step = 8, + .field_num = 9, + .p_fields = g_stat_car0_carc_queue_ram0_159_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, + { + .reg_name = "pktrx_glbal_cfg_0", + .reg_no = 448, + .module_no = NPPU, + .flags = ZXDH_REG_FLAG_DIRECT, + .array_type = ZXDH_REG_NUL_ARRAY, + .addr = ZXDH_SYS_NPPU_BASE_ADDR + ZXDH_MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8, + .width = (32 / 8), + .m_size = 0, + .n_size = 0, + .m_step = 0, + .n_step = 0, + .field_num = 1, + .p_fields = g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg, + .p_write_fun = NULL, + .p_read_fun = NULL, + }, +}; + +static uint32_t +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) +{ + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = NULL; + + p_reg_info = &g_dpp_reg_info[reg_no]; + + addr = p_reg_info->addr; + + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { + if (n_offset > (p_reg_info->n_size - 1)) + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%u", reg_no); + + addr += n_offset * p_reg_info->n_step; + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) + PMD_DRV_LOG(ERR, "reg n_offset/m_offset out of range, reg_no:%u", reg_no); + + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; + } + + return addr; +} + static uint32_t zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, @@ -262,7 +886,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, } else { /* device is new. */ p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } p_dev_mgr->p_dev_array[dev_id] = p_dev_info; p_dev_mgr->device_num++; } @@ -275,7 +902,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->dma_vir_addr = dma_vir_addr; p_dev_info->dma_phy_addr = dma_phy_addr; - return 0; + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + + return ZXDH_OK; } static uint32_t @@ -323,8 +953,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id) p_sdt_mgr->channel_num++; } else { - PMD_DRV_LOG(ERR, "Error: %s for dev[%d]" - "is called repeatedly!", __func__, dev_id); + PMD_DRV_LOG(ERR, "called repeatedly!"); return 1; } @@ -367,6 +996,61 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret); + } + + rte_free(recv_buffer); + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -376,6 +1060,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) return p_dpp_dtb_mgr[dev_id]; } +static uint32_t +zxdh_np_dtb_mgr_create(uint32_t dev_id) +{ + if (p_dpp_dtb_mgr[dev_id] != NULL) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); + return ZXDH_RC_DTB_MGR_EXIST; + } + + p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + if (p_dpp_dtb_mgr[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dtb_soft_init(uint32_t dev_id) { @@ -386,10 +1088,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id) p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) { - p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); + zxdh_np_dtb_mgr_create(dev_id); + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); if (p_dtb_mgr == NULL) - return 1; + return ZXDH_RC_DTB_MGR_NOT_EXIST; } return 0; @@ -469,36 +1172,9 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE) ? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0; - g_np_bar_offset = bar_offset; - return np_addr; } -int -zxdh_np_host_init(uint32_t dev_id, - ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) -{ - ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; - uint32_t rc; - uint64_t agent_addr; - - ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl); - - sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); - sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, - p_dev_init_ctrl->np_bar_offset); - sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; - rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); - - zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); - - agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; - zxdh_np_dev_agent_addr_set(dev_id, agent_addr); - - return 0; -} - static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -611,24 +1287,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t rc = 0; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - for (i = 0; i < p_reg_info->field_num; i++) { - rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - (uint32_t *)p_data + i, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset); + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]); + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); } } + + for (i = 0; i < p_reg_info->field_num; i++) { + rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + (uint32_t *)p_data + i, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex"); + PMD_DRV_LOG(DEBUG, "dev_id %u(%u)(%u)is ok!", dev_id, m_offset, n_offset); + } + return rc; } @@ -637,20 +1326,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info) { - ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0}; - uint32_t rc; + uint32_t rc = 0; + uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010; + uint32_t epid_v_func = 0; - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM, - 0, queue_id, &vm_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read"); + rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel"); - p_vm_info->dbi_en = vm_info.dbi_en; - p_vm_info->queue_en = vm_info.queue_en; - p_vm_info->epid = vm_info.cfg_epid; - p_vm_info->vector = vm_info.cfg_vector; - p_vm_info->vfunc_num = vm_info.cfg_vfunc_num; - p_vm_info->func_num = vm_info.cfg_func_num; - p_vm_info->vfunc_active = vm_info.cfg_vfunc_active; + p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1); + p_vm_info->queue_en = (epid_v_func >> 30 & 0x1); + p_vm_info->epid = (epid_v_func >> 24 & 0xF); + p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF); + p_vm_info->vector = (epid_v_func >> 8 & 0x7); + p_vm_info->func_num = (epid_v_func >> 5 & 0x7); + p_vm_info->vfunc_active = (epid_v_func & 0x1); return rc; } @@ -733,32 +1423,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t m_offset, uint32_t n_offset, void *p_data) { uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; - ZXDH_REG_T *p_reg_info = NULL; - ZXDH_FIELD_T *p_field_info = NULL; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields; uint32_t temp_data; - uint32_t rc; + uint32_t rc = ZXDH_OK; uint32_t i; + uint32_t addr = 0; + uint32_t reg_module = p_reg_info->module_no; + + for (i = 0; i < p_reg_info->field_num; i++) { + if (p_field_info[i].len <= 32) { + temp_data = *((uint32_t *)p_data + i) & + zxdh_np_comm_get_bit_mask(p_field_info[i].len); + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, + p_reg_info->width * 8, + temp_data, + p_field_info[i].msb_pos, + p_field_info[i].len); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); + } + } - if (reg_no < 4) { - p_reg_info = &g_dpp_reg_info[reg_no]; - p_field_info = p_reg_info->p_fields; - - for (i = 0; i < p_reg_info->field_num; i++) { - if (p_field_info[i].len <= 32) { - temp_data = *((uint32_t *)p_data + i); - rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff, - p_reg_info->width * 8, - temp_data, - p_field_info[i].msb_pos, - p_field_info[i].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex"); - PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", - dev_id, m_offset, n_offset); - } + PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]); + + if (!zxdh_np_comm_is_big_endian()) { + for (i = 0; i < p_reg_info->width / 4; i++) { + p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]); + + PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.", + p_buff[i]); } } - return 0; + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + PMD_DRV_LOG(DEBUG, "reg_no = %u. m_offset = %u n_offset = %u", + reg_no, m_offset, n_offset); + PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } + + return rc; } static uint32_t @@ -837,11 +1545,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, { uint32_t rc; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) { - *p_item_num = 32; - return 0; - } - rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE, 0, queue_id, p_item_num); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read"); @@ -874,7 +1577,7 @@ zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_DEV_POINT(devid, pname); @@ -891,20 +1594,11 @@ static void zxdh_np_dtb_mgr_destroy(uint32_t dev_id) { if (p_dpp_dtb_mgr[dev_id] != NULL) { - free(p_dpp_dtb_mgr[dev_id]); + rte_free(p_dpp_dtb_mgr[dev_id]); p_dpp_dtb_mgr[dev_id] = NULL; } } -static void -zxdh_np_tlb_mgr_destroy(uint32_t dev_id) -{ - if (g_p_dpp_tlb_mgr[dev_id] != NULL) { - free(g_p_dpp_tlb_mgr[dev_id]); - g_p_dpp_tlb_mgr[dev_id] = NULL; - } -} - static void zxdh_np_sdt_mgr_destroy(uint32_t dev_id) { @@ -914,7 +1608,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id) p_sdt_tbl_temp = ZXDH_SDT_SOFT_TBL_GET(dev_id); p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET(); - free(p_sdt_tbl_temp); + rte_free(p_sdt_tbl_temp); ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL; @@ -931,7 +1625,7 @@ zxdh_np_dev_del(uint32_t dev_id) p_dev_info = p_dev_mgr->p_dev_array[dev_id]; if (p_dev_info != NULL) { - free(p_dev_info); + rte_free(p_dev_info); p_dev_mgr->p_dev_array[dev_id] = NULL; p_dev_mgr->device_num--; } @@ -946,11 +1640,9 @@ zxdh_np_online_uninit(uint32_t dev_id, rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id); if (rc != 0) - PMD_DRV_LOG(ERR, "%s:dtb release error," - "port name %s queue id %d", __func__, port_name, queue_id); + PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); zxdh_np_dtb_mgr_destroy(dev_id); - zxdh_np_tlb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -964,8 +1656,8 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no) } -static ZXDH_DTB_TABLE_T * -zxdh_np_table_info_get(uint32_t table_type) +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_table_info_get(uint32_t table_type) { return &g_dpp_dtb_table_info[table_type]; } @@ -977,20 +1669,20 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, void *p_cmd_buff) { uint32_t field_cnt; - ZXDH_DTB_TABLE_T *p_table_info = NULL; - ZXDH_DTB_FIELD_T *p_field_info = NULL; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; uint32_t temp_data; uint32_t rc = 0; ZXDH_COMM_CHECK_POINT(p_cmd_data); ZXDH_COMM_CHECK_POINT(p_cmd_buff); - p_table_info = zxdh_np_table_info_get(table_type); + p_table_info = zxdh_np_dtb_table_info_get(table_type); p_field_info = p_table_info->p_fields; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { - temp_data = *((uint32_t *)p_cmd_data + field_cnt) & ZXDH_COMM_GET_BIT_MASK(uint32_t, - p_field_info[field_cnt].len); + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, ZXDH_DTB_TABLE_CMD_SIZE_BIT, @@ -998,7 +1690,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, p_field_info[field_cnt].lsb_pos, p_field_info[field_cnt].len); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits"); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex"); } return rc; @@ -1062,17 +1754,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t *p_data, ZXDH_DTB_ENTRY_T *p_entry) { - uint32_t temp_idx; + uint32_t temp_idx = 0; uint32_t dtb_ind_addr; uint32_t rc = 0; switch (wrt_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]" - "INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__, - base_addr, index, __func__); - + PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { @@ -1095,11 +1784,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, } temp_idx = index; + break; + default: + break; } dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx; - PMD_DRV_LOG(INFO, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); + PMD_DRV_LOG(DEBUG, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr); rc = zxdh_np_dtb_smmu0_write_entry_data(dev_id, wrt_mode, @@ -1131,6 +1823,126 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + uint32_t tmp = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32, + ZXDH_SDT_H_ERAM_MODE_BT_POS, ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + p_sdt_eram->eram_clutch_en = clutch_en; + break; + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + p_sdt_hash->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32, + ZXDH_SDT_H_HASH_ID_BT_POS, ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32, + ZXDH_SDT_H_LEARN_EN_BT_POS, ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + p_sdt_hash->keep_alive_baddr += (tmp << ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32, + ZXDH_SDT_L_RSP_MODE_BT_POS, ZXDH_SDT_L_RSP_MODE_BT_LEN); + p_sdt_hash->hash_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + p_sdt_etcam->table_type = tbl_type; + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_ID_BT_POS, ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + p_sdt_etcam->as_eram_baddr += (tmp << ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + p_sdt_etcam->etcam_clutch_en = clutch_en; + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %u ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%u] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -1140,17 +1952,21 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_DTB_ENTRY_T *p_dtb_one_entry) { uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM] = {0}; - ZXDH_SDTTBL_ERAM_T sdt_eram = {0}; + ZXDH_SDT_TBL_ERAM_T sdt_eram = {0}; ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL; uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -1166,8 +1982,19 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, case ZXDH_ERAM128_TBL_1b: opr_mode = ZXDH_ERAM128_OPR_1b; break; + default: + break; } + PMD_DRV_LOG(DEBUG, "std no:0x%x, index:0x%x, base addr:0x%x", sdt_no, index, base_addr); + if (opr_mode == ZXDH_ERAM128_OPR_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1], + peramdata->p_data[2], peramdata->p_data[3]); + else if (opr_mode == ZXDH_ERAM128_OPR_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + peramdata->p_data[0], peramdata->p_data[1]); + if (del_en) { memset((uint8_t *)buff, 0, sizeof(buff)); rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, @@ -1274,6 +2101,9 @@ zxdh_np_dtb_item_ack_rd(uint32_t dev_id, val = *((volatile uint32_t *)(addr)); + if (!zxdh_np_comm_is_big_endian()) + val = ZXDH_COMM_CONVERT32(val); + *p_data = val; return 0; @@ -1294,7 +2124,10 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, else addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; - *((volatile uint32_t *)(addr)) = data; + if (!zxdh_np_comm_is_big_endian()) + data = ZXDH_COMM_CONVERT32(data); + + *((volatile uint32_t *)addr) = data; return 0; } @@ -1304,16 +2137,26 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info) { - ZXDH_DTB_QUEUE_LEN_T dtb_len = {0}; uint32_t rc; - dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type; - dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en; - dtb_len.cfg_queue_dtb_len = p_item_info->data_len; + uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000; + uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004; + uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR + + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008; + uint32_t dtb_len = 0; + + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32, + 1, &p_item_info->data_hddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32, + 1, &p_item_info->data_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); + dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len); + rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail"); - rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN, - 0, queue_id, (void *)&dtb_len); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write"); return rc; } @@ -1335,7 +2178,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t rc; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1344,7 +2187,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } @@ -1383,6 +2226,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, item_info.data_hddr = ((phy_addr >> 4) >> 32) & 0xffffffff; item_info.data_laddr = (phy_addr >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); + rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; @@ -1421,7 +2266,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0}; uint8_t *p_data_buff; - uint8_t *p_data_buff_ex; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; uint32_t dtb_len = 0; @@ -1435,9 +2279,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1446,6 +2287,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, for (entry_index = 0; entry_index < entrynum; entry_index++) { pentry = down_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: @@ -1453,9 +2295,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1463,9 +2304,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry); @@ -1475,7 +2314,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1485,18 +2323,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, p_data_buff, &element_id); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return rc; } -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; -} - int zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint32_t queue_id, @@ -1509,7 +2339,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; uint8_t *p_data_buff = NULL; - uint8_t *p_data_buff_ex = NULL; uint32_t tbl_type = 0; uint32_t element_id = 0xff; uint32_t one_dtb_len = 0; @@ -1525,9 +2354,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); ZXDH_COMM_CHECK_POINT(p_data_buff); - p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); - ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff); - dtb_one_entry.cmd = entry_cmd; dtb_one_entry.data = entry_data; @@ -1537,16 +2363,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, pentry = delete_entries + entry_index; sdt_no = pentry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no); switch (tbl_type) { case ZXDH_SDT_TBLT_ERAM: rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); - rte_free(p_data_buff_ex); return 1; } @@ -1554,9 +2381,7 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, dtb_len += one_dtb_len; if (dtb_len > max_size) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); - PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__, - max_size); + PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } @@ -1567,158 +2392,43 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, if (dtb_len == 0) { rte_free(p_data_buff); - rte_free(p_data_buff_ex); return ZXDH_RC_DTB_DOWN_LEN_INVALID; } rc = zxdh_np_dtb_write_down_table_data(dev_id, queue_id, dtb_len * 16, - p_data_buff_ex, + p_data_buff, &element_id); rte_free(p_data_buff); - ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, - "dpp_dtb_write_down_table_data", p_data_buff_ex); - - rte_free(p_data_buff_ex); - return 0; -} - -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) -{ - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); - - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; - break; - case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; - - switch (eram_mode) { - case ZXDH_ERAM128_TBL_128b: - row_index = index; - break; - case ZXDH_ERAM128_TBL_64b: - row_index = (index >> 1); - col_index = index & 0x1; - break; - case ZXDH_ERAM128_TBL_1b: - row_index = (index >> 7); - col_index = index & 0x7F; - break; - } - *p_row_index = row_index; - *p_col_index = col_index; -} -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - memcpy(p_data, temp_data, (128 / 8)); - break; - case ZXDH_ERAM128_TBL_64b: - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - case ZXDH_ERAM128_TBL_1b: - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - } return rc; } - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc = 0; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) +{ + uint32_t row_index = 0; + uint32_t col_index = 0; + + switch (eram_mode) { + case ZXDH_ERAM128_TBL_128b: + row_index = index; + break; + case ZXDH_ERAM128_TBL_64b: + row_index = (index >> 1); + col_index = index & 0x1; + break; + case ZXDH_ERAM128_TBL_1b: + row_index = (index >> 7); + col_index = index & 0x7F; break; default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; + break; } - - return 0; + *p_row_index = row_index; + *p_col_index = col_index; } static void @@ -1727,10 +2437,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id, { ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg); - p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr; - p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr; - p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth; - p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset; + p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr; + p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr; + p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth; + p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset; } static uint32_t @@ -1748,12 +2458,12 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { - PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1769,6 +2479,11 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.cmd_type = ZXDH_DTB_DIR_UP_TYPE; item_info.int_en = int_flag; item_info.data_len = desc_len / 4; + item_info.data_hddr = + ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) >> 32) & 0xffffffff; + item_info.data_laddr = + (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; + zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) return 0; @@ -1778,6 +2493,33 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -1799,8 +2541,8 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, desc_len, p_dump_info); if (rc != 0) { - PMD_DRV_LOG(ERR, "the queue %d element id %d dump" - " info set failed!", queue_id, queue_element_id); + PMD_DRV_LOG(ERR, "queue %u element %u dump info set failed!", + queue_id, queue_element_id); zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } @@ -1819,7 +2561,7 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t i; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -1849,37 +2591,9 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, *p_item_index = item_index; - return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -1898,7 +2612,7 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); if (rc != 0) { - PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %d!", base_addr); + PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %u!", base_addr); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; } @@ -1918,6 +2632,103 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + eram_base_addr = sdt_eram_info.eram_base_addr; + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_data, temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_TBL_64b: + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + + PMD_DRV_LOG(DEBUG, "[eram_dump]std no:0x%x, index:0x%x, base addr:0x%x", + sdt_no, p_dump_eram_entry->index, eram_dump_base_addr); + if (rd_mode == ZXDH_ERAM128_TBL_128b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1], + p_dump_eram_entry->p_data[2], p_dump_eram_entry->p_data[3]); + else if (rd_mode == ZXDH_ERAM128_TBL_64b) + PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]", + p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1]); + + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, @@ -1945,6 +2756,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, row_index = (index >> 7); col_index = index & 0x7F; break; + default: + break; } eram_dump_base_addr = base_addr + row_index; @@ -1967,6 +2780,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } return rc; @@ -2035,6 +2850,32 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +int +zxdh_np_host_init(uint32_t dev_id, + ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; + uint32_t rc; + uint64_t agent_addr; + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); + + sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10); + sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr, + p_dev_init_ctrl->np_bar_offset); + sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP; + + rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init"); + + zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport); + + agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; + zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + + return 0; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { @@ -2047,7 +2888,7 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) while (!done_flag) { rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read Fail!", rc); + PMD_DRV_LOG(ERR, "reg_read fail!"); return rc; } @@ -2073,7 +2914,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t rd_clr_mode, uint32_t *p_data) { - uint32_t rc = 0; + uint32_t rc = ZXDH_OK; uint32_t i = 0; uint32_t row_index = 0; uint32_t col_index = 0; @@ -2082,6 +2923,10 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; @@ -2090,42 +2935,42 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - if ((0xFFFFFFFF - (base_addr)) < (index)) + if ((0xFFFFFFFF - (base_addr)) < (index)) { + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; - + } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x1; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x3; break; case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x7F; break; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; @@ -2136,56 +2981,69 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 7); cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } - row_index = (index << 6); cpu_ind_cmd.cpu_req_mode = 2; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + return ZXDH_ERR; } row_index = (index << 5); cpu_ind_cmd.cpu_req_mode = 1; break; case ZXDH_ERAM128_OPR_1b: - PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ", - rd_clr_mode, rd_mode); - return -1; + PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", + rd_clr_mode, rd_mode); + return ZXDH_ERR; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; } rc = zxdh_np_reg_write(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, - 0, - 0, - &cpu_ind_cmd); + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } - rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER, 0); + rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + return ZXDH_ERR; + } p_temp_data = temp_data; for (i = 0; i < 4; i++) { rc = zxdh_np_reg_read(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, - 0, - 0, - p_temp_data + 3 - i); + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + return ZXDH_ERR; + } } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { @@ -2203,6 +3061,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } } else { switch (rd_mode) { @@ -2215,6 +3075,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: memcpy(p_data, p_temp_data, (64 / 8)); break; + default: + break; } } @@ -2266,70 +3128,18 @@ zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, } static uint32_t -zxdh_np_agent_channel_sync_send(ZXDH_AGENT_CHANNEL_MSG_T *p_msg, - uint32_t *p_data, - uint32_t rep_len) -{ - uint32_t ret = 0; - uint32_t vport = 0; - struct zxdh_pci_bar_msg in = {0}; - struct zxdh_msg_recviver_mem result = {0}; - uint32_t *recv_buffer; - uint8_t *reply_ptr = NULL; - uint16_t reply_msg_len = 0; - uint64_t agent_addr = 0; - - if (ZXDH_IS_PF(vport)) - in.src = ZXDH_MSG_CHAN_END_PF; - else - in.src = ZXDH_MSG_CHAN_END_VF; - - in.virt_addr = agent_addr; - in.payload_addr = p_msg->msg; - in.payload_len = p_msg->msg_len; - in.dst = ZXDH_MSG_CHAN_END_RISC; - in.module_id = ZXDH_BAR_MDOULE_NPSDK; - - recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); - if (recv_buffer == NULL) { - PMD_DRV_LOG(ERR, "%s point null!", __func__); - return ZXDH_PAR_CHK_POINT_NULL; - } - - result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; - result.recv_buffer = recv_buffer; - - ret = zxdh_bar_chan_sync_msg_send(&in, &result); - if (ret == ZXDH_BAR_MSG_OK) { - reply_ptr = (uint8_t *)(result.recv_buffer); - if (*reply_ptr == 0XFF) { - reply_msg_len = *(uint16_t *)(reply_ptr + 1); - memcpy(p_data, reply_ptr + 4, - ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); - } else { - PMD_DRV_LOG(ERR, "Message not replied"); - } - } else { - PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__); - } - - rte_free(recv_buffer); - return ret; -} - -static uint32_t -zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, +zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) { uint32_t ret = 0; - ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), + }; - agent_msg.msg = (void *)p_msg; - agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T); - - ret = zxdh_np_agent_channel_sync_send(&agent_msg, p_data, rep_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_sync_send failed."); return 1; } @@ -2337,25 +3147,25 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport, uint32_t car_type, uint32_t *p_profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_REQUEST; - msgcfg.vport = vport; - msgcfg.car_type = car_type; - msgcfg.profile_id = 0xFFFF; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_REQUEST, + .vport = vport, + .car_type = car_type, + .profile_id = 0xFFFF, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2365,7 +3175,8 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, } static uint32_t -zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, +zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, + uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id __rte_unused, void *p_car_profile_cfg) @@ -2395,9 +3206,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgpktcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_a_type failed."); return 1; } @@ -2429,9 +3240,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_b_type failed."); return 1; } @@ -2442,25 +3253,25 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport, uint32_t car_type __rte_unused, uint32_t profileid) { uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_RELEASE; - msgcfg.vport = vport; - msgcfg.profile_id = profileid; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_RELEASE, + .vport = vport, + .profile_id = profileid, + }; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -2478,11 +3289,12 @@ zxdh_np_stat_cara_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { + .cara_drop = drop_flag, + .cara_plcr_en = plcr_en, + .cara_profile_id = profile_id, + }; - queue_cfg.cara_drop = drop_flag; - queue_cfg.cara_plcr_en = plcr_en; - queue_cfg.cara_profile_id = profile_id; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0, 0, @@ -2502,11 +3314,11 @@ zxdh_np_stat_carb_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; - - queue_cfg.carb_drop = drop_flag; - queue_cfg.carb_plcr_en = plcr_en; - queue_cfg.carb_profile_id = profile_id; + ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { + .carb_drop = drop_flag, + .carb_plcr_en = plcr_en, + .carb_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0, @@ -2527,10 +3339,11 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; - queue_cfg.carc_drop = drop_flag; - queue_cfg.carc_plcr_en = plcr_en; - queue_cfg.carc_profile_id = profile_id; + ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { + .carc_drop = drop_flag, + .carc_plcr_en = plcr_en, + .carc_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0, @@ -2553,12 +3366,12 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, uint32_t profile_id_l = 0; uint64_t temp_profile_id = 0; - profile_id = (uint32_t *)rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); + profile_id = rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); if (profile_id == NULL) { - PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__); + PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -2566,7 +3379,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, temp_profile_id = (((uint64_t)profile_id_l) << 32) | ((uint64_t)profile_id_h); if (0 != (uint32_t)(temp_profile_id >> 56)) { - PMD_DRV_LOG(ERR, "%s: profile_id is overflow!", __func__); + PMD_DRV_LOG(ERR, "profile_id is overflow!"); return 1; } @@ -2583,11 +3396,12 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, void *p_car_profile_cfg) { uint32_t ret = 0; + uint32_t dev_id = 0; - ret = zxdh_np_agent_channel_plcr_car_rate(car_type, + ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__); + PMD_DRV_LOG(ERR, "plcr_car_rate set failed!"); return 1; } @@ -2599,13 +3413,12 @@ zxdh_np_car_profile_id_delete(uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t profileid = 0; - - profileid = profile_id & 0xFFFF; + uint32_t dev_id = 0; + uint32_t profileid = profile_id & 0xFFFF; - ret = zxdh_np_agent_channel_plcr_profileid_release(vport_id, flags, profileid); + ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__); + PMD_DRV_LOG(ERR, "plcr profiled id release failed!"); return 1; } @@ -2624,32 +3437,32 @@ zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, if (car_type == ZXDH_STAT_CAR_A_TYPE) { if (flow_id > ZXDH_CAR_A_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_A_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else if (car_type == ZXDH_STAT_CAR_B_TYPE) { if (flow_id > ZXDH_CAR_B_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_B_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else { if (flow_id > ZXDH_CAR_C_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_C_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 7ff5c34c73..6d2c7aa976 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -6,14 +6,16 @@ #define ZXDH_NP_H #include <stdint.h> +#include <rte_spinlock.h> +#define ZXDH_OK (0) +#define ZXDH_ERR (1) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) #define ZXDH_DEV_CHANNEL_MAX (2) #define ZXDH_DEV_SDT_ID_MAX (256U) -#define ZXDH_RD_CNT_MAX (128) /*DTB*/ #define ZXDH_DTB_QUEUE_ITEM_NUM_MAX (32) @@ -54,11 +56,23 @@ #define ZXDH_INIT_FLAG_TM_IMEM_FLAG (1 << 9) #define ZXDH_INIT_FLAG_AGENT_FLAG (1 << 10) +#define ZXDH_REG_NUL_ARRAY (0 << 0) +#define ZXDH_REG_UNI_ARRAY (1 << 0) +#define ZXDH_REG_BIN_ARRAY (1 << 1) +#define ZXDH_REG_FLAG_INDIRECT (1 << 0) +#define ZXDH_REG_FLAG_DIRECT (0 << 0) +#define ZXDH_FIELD_FLAG_RO (1 << 0) +#define ZXDH_FIELD_FLAG_RW (1 << 1) + +#define ZXDH_SYS_NP_BASE_ADDR0 (0x00000000) +#define ZXDH_SYS_NP_BASE_ADDR1 (0x02000000) + #define ZXDH_ACL_TBL_ID_MIN (0) #define ZXDH_ACL_TBL_ID_MAX (7) #define ZXDH_ACL_TBL_ID_NUM (8U) #define ZXDH_ACL_BLOCK_NUM (8U) +#define ZXDH_RD_CNT_MAX (100) #define ZXDH_SMMU0_READ_REG_MAX_NUM (4) #define ZXDH_DTB_ITEM_ACK_SIZE (16) @@ -98,6 +112,57 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -206,11 +271,15 @@ typedef enum zxdh_dev_type_e { } ZXDH_DEV_TYPE_E; typedef enum zxdh_reg_info_e { - ZXDH_DTB_CFG_QUEUE_DTB_HADDR = 0, - ZXDH_DTB_CFG_QUEUE_DTB_LADDR = 1, - ZXDH_DTB_CFG_QUEUE_DTB_LEN = 2, - ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3, - ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 0, + ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER = 1, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R = 3, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R = 4, + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R = 5, + ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 6, + ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 7, + ZXDH_DTB_CFG_EPID_V_FUNC_NUM = 8, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0 = 9, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0 = 10, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0 = 11, @@ -218,6 +287,12 @@ typedef enum zxdh_reg_info_e { ZXDH_REG_ENUM_MAX_VALUE } ZXDH_REG_INFO_E; +typedef enum zxdh_dev_spinlock_type_e { + ZXDH_DEV_SPINLOCK_T_SMMU0 = 0, + ZXDH_DEV_SPINLOCK_T_DTB = 1, + ZXDH_DEV_SPINLOCK_T_MAX +} ZXDH_DEV_SPINLOCK_TYPE_E; + typedef enum zxdh_dev_access_type_e { ZXDH_DEV_ACCESS_TYPE_PCIE = 0, ZXDH_DEV_ACCESS_TYPE_RISCV = 1, @@ -237,6 +312,29 @@ typedef enum zxdh_acl_pri_mode_e { ZXDH_ACL_PRI_INVALID, } ZXDH_ACL_PRI_MODE_E; +typedef enum zxdh_module_e { + CFG = 1, + NPPU, + PPU, + ETM, + STAT, + CAR, + SE, + SMMU0 = SE, + SMMU1 = SE, + DTB, + TRPG, + TSN, + AXI, + PTPTM, + DTB4K, + STAT4K, + PPU4K, + SE4K, + SMMU14K, + MODULE_MAX +} ZXDH_MODULE_E; + typedef struct zxdh_d_node { void *data; struct zxdh_d_node *prev; @@ -301,6 +399,49 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef struct zxdh_spin_lock_t { + rte_spinlock_t spinlock; +} ZXDH_SPINLOCK_T; + +typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); +typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id, + uint32_t addr, uint32_t size, uint32_t *p_data); + typedef struct zxdh_sys_init_ctrl_t { ZXDH_DEV_TYPE_E device_type; uint32_t flags; @@ -327,6 +468,8 @@ typedef struct dpp_dev_cfg_t { uint64_t dma_phy_addr; uint64_t agent_addr; uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; + ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; + ZXDH_DEV_READ_FUNC p_pcie_read_fun; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -338,8 +481,8 @@ typedef struct zxdh_dev_mngr_t { typedef struct zxdh_dtb_addr_info_t { uint32_t sdt_no; uint32_t size; - uint32_t phy_addr; - uint32_t vir_addr; + uint64_t phy_addr; + uint64_t vir_addr; } ZXDH_DTB_ADDR_INFO_T; typedef struct zxdh_dev_init_ctrl_t { @@ -349,12 +492,12 @@ typedef struct zxdh_dev_init_ctrl_t { uint32_t queue_id; uint32_t np_bar_offset; uint32_t np_bar_len; - uint32_t pcie_vir_addr; - uint32_t down_phy_addr; - uint32_t down_vir_addr; - uint32_t dump_phy_addr; - uint32_t dump_vir_addr; - uint32_t dump_sdt_num; + uint64_t pcie_vir_addr; + uint64_t down_phy_addr; + uint64_t down_vir_addr; + uint64_t dump_phy_addr; + uint64_t dump_vir_addr; + uint64_t dump_sdt_num; ZXDH_DTB_ADDR_INFO_T dump_addr_info[]; } ZXDH_DEV_INIT_CTRL_T; @@ -424,7 +567,7 @@ typedef struct zxdh_reg_t { uint32_t m_step; uint32_t n_step; uint32_t field_num; - ZXDH_FIELD_T *p_fields; + const ZXDH_FIELD_T *p_fields; ZXDH_REG_WRITE p_write_fun; ZXDH_REG_READ p_read_fun; @@ -515,14 +658,6 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDTTBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -538,7 +673,7 @@ typedef struct zxdh_dtb_table_t { const char *table_type; uint32_t table_no; uint32_t field_num; - ZXDH_DTB_FIELD_T *p_fields; + const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; typedef struct zxdh_dtb_queue_item_info_t { @@ -550,12 +685,6 @@ typedef struct zxdh_dtb_queue_item_info_t { uint32_t data_hddr; } ZXDH_DTB_QUEUE_ITEM_INFO_T; -typedef struct zxdh_dtb_queue_len_t { - uint32_t cfg_dtb_cmd_type; - uint32_t cfg_dtb_cmd_int_en; - uint32_t cfg_queue_dtb_len; -} ZXDH_DTB_QUEUE_LEN_T; - typedef struct zxdh_dtb_eram_entry_info_t { uint32_t index; uint32_t *p_data; @@ -571,23 +700,10 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDTTBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; -} ZXDH_SDTTBL_PORTTBL_T; +} ZXDH_SDT_TBL_PORTTBL_T; typedef struct zxdh_dtb_hash_entry_info_t { uint8_t *p_actu_key; @@ -614,15 +730,6 @@ typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_addr; } ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T; -typedef enum zxdh_smmu0_smmu0_type_e { - ZXDH_DEV_MUTEX_T_SMMU0 = 0, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR = 1, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R = 2, - ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER = 3, - ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR = 4, - ZXDH_SMMU0_SMMU0_ED_ARB_CPU_RDYR = 5, -} ZXDH_SEMMU0_SEMMU0_TYPE_E; - typedef enum zxdh_stat_rd_clr_mode_e { ZXDH_STAT_RD_CLR_MODE_UNCLR = 0, ZXDH_STAT_RD_CLR_MODE_CLR = 1, @@ -635,8 +742,8 @@ typedef enum zxdh_eram128_rd_clr_mode_e { } ZXDH_ERAM128_RD_CLR_MODE_E; typedef enum zxdh_se_opr_mode_e { - ZXDH_SE_OPR_RD = 0, - ZXDH_SE_OPR_WR = 1, + ZXDH_SE_OPR_WR = 0, + ZXDH_SE_OPR_RD = 1, } ZXDH_SE_OPR_MODE_E; typedef enum zxdh_stat_car_type_e { @@ -730,11 +837,6 @@ typedef struct dpp_agent_car_pkt_profile_msg { uint32_t pri[ZXDH_CAR_PRI_MAX]; } ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T; -typedef struct zxdh_agent_channel_msg_t { - uint32_t msg_len; - void *msg; -} ZXDH_AGENT_CHANNEL_MSG_T; - typedef struct zxdh_agent_channel_plcr_msg { uint8_t dev_id; uint8_t type; @@ -803,6 +905,10 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 244256 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 02/14] net/zxdh: support compatibility check 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 03/14] net/zxdh: add agent channel Bingbin Chen ` (12 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5360 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 +++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1534cb2709..f0848658ac 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -24,6 +24,9 @@ static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -1175,6 +1178,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2873,6 +2961,11 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6d2c7aa976..11eb7e15d5 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -905,6 +908,15 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 9875 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 03/14] net/zxdh: add agent channel 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (11 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16208 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 315 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 53 +++++++ 2 files changed, 367 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index f0848658ac..00e02cb36f 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -480,6 +480,70 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %u ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_spinlock; + break; + case ZXDH_DEV_SPINLOCK_T_SMMU0: + *p_spinlock_out = &p_dev_info->smmu0_spinlock; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -908,6 +972,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + return ZXDH_OK; } @@ -999,6 +1066,48 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_DROP: + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_agent_channel_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg, @@ -1014,7 +1123,14 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, uint16_t reply_msg_len = 0; uint64_t agent_addr = 0; - PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); if (ZXDH_IS_PF(vport)) in.src = ZXDH_MSG_CHAN_END_PF; @@ -1054,6 +1170,165 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T), + }; + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PCIE_BAR_MSG, + .oper = ZXDH_BAR_MSG_NUM_REQ, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_RD, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent read resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_WR, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent write resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1263,6 +1538,24 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_pcie_bar_request"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1381,12 +1674,19 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1518,6 +1818,9 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1552,6 +1855,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -2945,6 +3252,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); @@ -2966,6 +3274,11 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 11eb7e15d5..a692eca9aa 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,9 +112,17 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_CHANNEL_REPS_LEN (4) + #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -178,6 +186,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_SPIN_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_SPIN_LOCK_INIT_FAIL (ZXDH_SPIN_LOCK_BASE | 0x001) +#define ZXDH_SPIN_LOCK_LOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0x002) +#define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) +#define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -215,6 +229,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -465,6 +486,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -473,6 +495,8 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_SPINLOCK_T dtb_spinlock; + ZXDH_SPINLOCK_T smmu0_spinlock; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -726,6 +750,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -917,6 +952,24 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 37167 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 04/14] net/zxdh: modify dtb queue ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (2 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (10 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 26076 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 491 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 ++++++++ 2 files changed, 482 insertions(+), 106 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 00e02cb36f..3f5d286ffe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -17,16 +17,15 @@ static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; -static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -544,6 +543,25 @@ zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_queue_spinlock[index]; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -938,6 +956,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -973,7 +992,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); - rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); return ZXDH_OK; } @@ -1329,6 +1350,89 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_REQUEST, + .vport = vport_info, + }; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %u, msg_result: %u", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %u, queue_id: %u", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_RELEASE, + .queue_id = queue_id, + }; + + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %u", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1556,48 +1660,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1887,52 +1949,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1967,20 +1983,74 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + uint32_t vport_info = (uint32_t)vport; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", + dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(devid, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %u not request.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } + + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %u name error.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "release queueid %u", queueid); return rc; } @@ -2571,24 +2641,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2603,8 +2683,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2626,6 +2708,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2639,8 +2723,6 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, uint32_t rc = 0; uint32_t dtb_interrupt_status = 0; - dtb_interrupt_status = g_dpp_dtb_int_enable; - rc = zxdh_np_dtb_tab_down_info_set(dev_id, queue_id, dtb_interrupt_status, @@ -2850,20 +2932,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2880,11 +2970,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2954,16 +3043,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2978,14 +3074,18 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return 0; } @@ -3245,6 +3345,181 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = { + .down_start_phy_addr = phy_addr, + .down_start_vir_addr = vir_addr, + .down_item_size = size, + }; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = { + .up_start_phy_addr = phy_addr, + .up_start_vir_addr = vir_addr, + .up_item_size = size, + }; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -3279,6 +3554,10 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + PMD_DRV_LOG(INFO, "host init done, queue_id = %u", p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a692eca9aa..6cf8653670 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -497,6 +497,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; + ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -685,6 +686,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -703,6 +776,15 @@ typedef struct zxdh_dtb_table_t { const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -761,6 +843,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -975,6 +1062,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56114 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 05/14] net/zxdh: add tables dump address ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (3 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (9 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 39968 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1137 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1228 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 3f5d286ffe..98135b37a7 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -26,6 +26,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -324,6 +325,51 @@ zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, #define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) +static inline void +zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) +{ + ptr->data = pdata; + ptr->prev = NULL; + ptr->next = NULL; +} + +static inline void +zxdh_np_init_rbt_tn(ZXDH_RB_TN *p_tn, void *p_newkey) +{ + p_tn->p_key = p_newkey; + p_tn->color_lsv = 0; + p_tn->p_left = NULL; + p_tn->p_right = NULL; + p_tn->p_parent = NULL; + zxdh_np_init_d_node(&p_tn->tn_ln, p_tn); +} + +static inline uint32_t +zxdh_np_get_tn_lsv(ZXDH_RB_TN *p_tn) +{ + return p_tn->color_lsv >> 2; +} + +static inline void +zxdh_np_set_tn_lsv(ZXDH_RB_TN *p_tn, uint32_t list_val) +{ + p_tn->color_lsv &= 0x3; + p_tn->color_lsv |= (list_val << 2); +} + +static inline void +zxdh_np_set_tn_color(ZXDH_RB_TN *p_tn, uint32_t color) +{ + p_tn->color_lsv &= 0xfffffffc; + p_tn->color_lsv |= (color & 0x3); +} + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -465,6 +511,945 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_create(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(ERR, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(ERR, "dw_index is invalid"); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_switch_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = zxdh_np_get_tn_color(p_tn1); + color2 = zxdh_np_get_tn_color(p_tn2); + + zxdh_np_set_tn_color(p_tn1, color2); + zxdh_np_set_tn_color(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (zxdh_np_get_tn_color(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + zxdh_np_set_tn_color(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + zxdh_np_set_tn_color(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " p_rb_cfg already init!"); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_create(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_create"); + + p_rb_cfg->p_keybase = rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + zxdh_np_init_rbt_tn(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + zxdh_np_set_tn_lsv(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + zxdh_np_init_d_node(&p_ins_tn->tn_ln, p_ins_tn); + } + + zxdh_np_set_tn_color(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(ERR, "rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = zxdh_np_get_tn_lsv(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(zxdh_np_get_tn_color(p_par_tn) == ZXDH_RBT_RED); + + zxdh_np_set_tn_color(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + } else { + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (zxdh_np_get_tn_color(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_switch_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (zxdh_np_get_tn_color(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + zxdh_np_set_tn_color(p_del_tn, zxdh_np_get_tn_color(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (zxdh_np_get_tn_color(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (zxdh_np_get_tn_color(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + zxdh_np_set_tn_color(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, zxdh_np_get_tn_lsv(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(ERR, "p_list point null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + memcpy(p_rb_key, p_data, len); + + p_rb_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1976,10 +2961,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%u", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -2009,6 +3096,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", @@ -2047,6 +3137,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3494,12 +4587,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = { + .sdt_no = sdt_no, + .phy_addr = phy_addr, + .vir_addr = vir_addr, + .size = size, + }; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3517,6 +4641,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6cf8653670..36b7628bb7 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -123,6 +123,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -192,6 +199,26 @@ #define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) #define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -236,6 +263,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -372,6 +427,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 108876 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 06/14] net/zxdh: add eram tables ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (4 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (8 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 22262 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 545 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 15 + 2 files changed, 558 insertions(+), 2 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 98135b37a7..fd9c7b47c9 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -196,6 +200,81 @@ static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +static const ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -314,6 +393,17 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + static inline uint64_t zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, uint32_t INDEX) @@ -3220,6 +3310,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3254,6 +3350,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3304,6 +3433,39 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ERAM, + .base_addr = base_addr, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + PMD_DRV_LOG(DEBUG, "valid: %u", dtb_eram_dump_form_info.valid); + PMD_DRV_LOG(DEBUG, "up_type: %u", dtb_eram_dump_form_info.up_type); + PMD_DRV_LOG(DEBUG, "base_addr: 0x%x", dtb_eram_dump_form_info.base_addr); + PMD_DRV_LOG(DEBUG, "tb_depth: %u", dtb_eram_dump_form_info.tb_depth); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_h: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_h); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_l: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_l); + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -3690,6 +3852,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(DEBUG, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(DEBUG, "[index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(ERR, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + + PMD_DRV_LOG(DEBUG, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3825,6 +4079,121 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) { + PMD_DRV_LOG(ERR, "down queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3894,6 +4263,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -3972,6 +4343,8 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -4070,6 +4443,36 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + static uint32_t zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -4081,7 +4484,7 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint64_t addr; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -4089,7 +4492,8 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); else - addr = ZXDH_DTB_ITEM_ACK_SIZE; + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; *p_phy_haddr = (addr >> 32) & 0xffffffff; *p_phy_laddr = addr & 0xffffffff; @@ -4097,6 +4501,125 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(DEBUG, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) { + PMD_DRV_LOG(ERR, "dump queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -4124,6 +4647,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %u element %u dump done.", queue_id, queue_element_id); + return rc; } @@ -4210,6 +4743,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 36b7628bb7..d4a940b038 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -227,6 +227,13 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) + +#define ZXDH_DTB_DELAY_TIME (50) +#define ZXDH_DTB_DOWN_OVER_TIME (2000) +#define ZXDH_DTB_DUMP_OVER_TIME (200000) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -728,6 +735,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56696 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 07/14] net/zxdh: get flow tables resources 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (5 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (7 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 29861 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 13 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 492 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 282 +++++++++++++++++++ 4 files changed, 788 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index e683cbd616..ea34b9229b 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1809,6 +1809,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(hw->dev_id, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index 04b0b58c74..261acd17c3 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -44,6 +44,7 @@ #define ZXDH_MAX_NAME_LEN 32 #define ZXDH_SLOT_MAX 256 #define ZXDH_MAX_VF 256 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fd9c7b47c9..c93f8eb0fb 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2508,6 +2508,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5239,6 +5273,464 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} + +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + PMD_DRV_LOG(DEBUG, "se res get success."); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d4a940b038..b204889c9a 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -130,6 +130,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -521,6 +527,33 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -555,6 +588,113 @@ typedef struct zxdh_sdt_tbl_hash_t { uint32_t hash_clutch_en; } ZXDH_SDT_TBL_HASH_T; +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -596,6 +736,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -954,6 +1095,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -1178,6 +1342,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1213,5 +1494,6 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t drop_flag, uint32_t plcr_en, uint32_t profile_id); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 61852 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 08/14] net/zxdh: support hash resources configuration 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (6 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (6 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 34513 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 774 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 260 +++++++++++++ 2 files changed, 1034 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index c93f8eb0fb..22c30313fe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -31,6 +31,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +static ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static const uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +static uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -460,6 +477,20 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); } +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -819,6 +850,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -844,6 +902,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5719,6 +5817,678 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + zxdh_np_init_d_node(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + zxdh_np_init_d_node(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + break; + default: + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %u]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlock[%u] is already used", zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlk[%u], ZCell[%u] is already used", + zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %u!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = rte_zmalloc(NULL, sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %u ] is not init", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input zcell_num is %u, bulk %u monopolize zcells is %u", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %u ] is not init", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input zreg_num' is %u, actually bulk %u monopolize zregs is %u", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "dev_id[0x%x],se_type[0x%x] invalid!", dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5728,6 +6498,10 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); PMD_DRV_LOG(DEBUG, "se res get success."); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + PMD_DRV_LOG(DEBUG, "se res init success."); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b204889c9a..8937e24def 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -136,6 +136,43 @@ #define ZXDH_ERAM_MAX_NUM (60) #define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -304,6 +341,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -463,6 +505,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -476,6 +525,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89111 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 09/14] net/zxdh: implement tables initialization 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (7 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (5 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 32052 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 670 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 136 ++++++++ 2 files changed, 806 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 22c30313fe..689ec08344 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -22,6 +22,9 @@ static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +static ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -49,6 +52,10 @@ static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +static ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -491,6 +498,48 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, + uint32_t start_pos, uint32_t len) +{ + uint32_t mask = zxdh_np_comm_get_bit_mask(len); + *dst = (*dst & ~(mask << start_pos)) | ((src & mask) << start_pos); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ + zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -2240,6 +2289,232 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "soft sdt table not init!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft sdt table item invalid!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "0x%08x 0x%08x", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft table item invalid !"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "sdt_no: 0x%08x", sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + PMD_DRV_LOG(DEBUG, "sdt: %u", sdt_no); + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", + table_type); + return ZXDH_ERR; + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -6453,12 +6728,381 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + case ZXDH_SDT_TBLT_HASH: + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + case ZXDH_SDT_TBLT_ETCAM: + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + default: + PMD_DRV_LOG(ERR, "table_type[ %u ] is invalid!", table_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + uint32_t entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%u] not match to key_type[%u].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%u], table_id[%u] is already init", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %u ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode %u, etcam block_num %u is not enough for entry_num 0x%x", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is more than entry_num 0x%x", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is match with entry_num 0x%x", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + zxdh_np_init_d_node(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_tbls[table_id]); + rc = zxdh_comm_double_link_insert_last(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %u ] is already used by table[ %u ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6468,8 +7112,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6486,6 +7136,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 8937e24def..320af0573c 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -103,6 +103,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -346,6 +350,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -532,6 +558,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -955,6 +996,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 79363 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 10/14] net/zxdh: support hash tables write and delete ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (8 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (4 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35069 bytes --] Implement hash tables write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 930 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 17 + 2 files changed, 947 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 689ec08344..67edf581e2 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -540,6 +540,76 @@ zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, #define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) +static inline uint32_t +zxdh_np_zblk_addr_conv(uint32_t zblk_idx) +{ + uint32_t group_size = 1 << ZXDH_ZBLK_IDX_BT_WIDTH; + uint32_t group_number = zblk_idx / ZXDH_ZBLK_NUM_PER_ZGRP; + uint32_t offset_in_group = zblk_idx % ZXDH_ZBLK_NUM_PER_ZGRP; + + return group_number * group_size + offset_in_group; +} + +static inline uint32_t +zxdh_np_zcell_addr_conv(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (zxdh_np_zblk_addr_conv(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | \ + (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) | \ + ((zxdh_np_zblk_addr_conv(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | \ + ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((zxdh_np_zcell_addr_conv(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -1784,6 +1854,16 @@ zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_spinlock_get(uint32_t dev_id, + uint32_t fun_id, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *p_spinlock_out = &p_dev_info->hash_spinlock[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2218,6 +2298,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + rte_spinlock_init(&p_dev_info->hash_spinlock[i].spinlock); + return ZXDH_OK; } @@ -3840,6 +3923,65 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ZCAM, + .ram_reg_flag = reg_sram_flag, + .zgroup_id = zgroup_id, + .zblock_id = zblock_id, + .zcell_id = zcell_id, + .mask = mask, + .sram_addr = sram_addr & 0x1FF, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = (addr >> 16) & 0x1; + uint32_t zgroup_id = (addr >> 14) & 0x3; + uint32_t zblock_id = (addr >> 11) & 0x7; + uint32_t zcell_id = (addr >> 9) & 0x3; + uint32_t mask = (addr >> 17) & 0xF; + uint32_t sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4601,6 +4743,783 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "sdt_partner:%u", sdt_partner); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_init_rbt_tn(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint32_t rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + zxdh_np_init_d_node(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t item_entry_max = 4; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "pos is[%u], size is[%u]", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + HASH_DDR_CFG *p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + uint8_t key_type = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "hash ddr width mode is not match to the key type."); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx:[0x%x] hash_arg:[0x%x] crc_value:[0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id:[0x%x] item_idx:[0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_D_NODE *p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = p_hash_entry_cfg->table_id; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + ZXDH_SE_ITEM_CFG *p_item_info = p_rbkey_new->p_item_info; + + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(ERR, "Error!there is not item in hash!"); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_comm_double_link_del failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_hash_red_black_node_alloc failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_ddr failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zcell failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash form write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + p_hash_cfg->hash_stat.insert_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = temp_key; + entry.p_rst = temp_rst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} + + + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -4640,6 +5559,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -4719,6 +5642,13 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 320af0573c..5ca8053d5e 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -94,6 +96,12 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -573,6 +581,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1132,6 +1148,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_SPINLOCK_T hash_spinlock[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90330 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 11/14] net/zxdh: get hash table entry result 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (9 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (3 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16703 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 482 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 488 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 67edf581e2..fb61e0f99c 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1371,6 +1371,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -4015,6 +4049,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ZCAM, + .tb_width = tb_width, + .sram_addr = addr & 0x1FF, + .ram_reg_flag = (addr >> 16) & 0x1, + .z_reg_cell_id = (addr >> 9) & 0x3, + .zblock_id = (addr >> 11) & 0x7, + .zgroup_id = (addr >> 14) & 0x3, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -6160,6 +6226,399 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %u.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "hash search failed!"); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_OK; + } + + p_rbkey = p_rb_tn_rtn->p_key; + p_item = p_rbkey->p_item_info; + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + + PMD_DRV_LOG(DEBUG, "hash get sdt_no:%u", sdt_no); + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = temp_key; + hash_entry.p_rst = temp_rst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6170,10 +6629,12 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); - PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); @@ -6187,6 +6648,25 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; + case ZXDH_SDT_TBLT_HASH: + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, "hash search failed"); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 5ca8053d5e..3b66cf0b9f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1320,6 +1320,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 47918 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 12/14] net/zxdh: delete all hash entries 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (10 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 13/14] net/zxdh: add acl tables ops Bingbin Chen ` (2 subsequent siblings) 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 37909 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 57 ++ drivers/net/zxdh/zxdh_np.c | 1055 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 10 + 3 files changed, 1122 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea34b9229b..ea8b18e5e1 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1119,6 +1119,30 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + uint32_t sdt_no; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -1130,6 +1154,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!dtb_data->init_done && !dtb_data->dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--dtb_data->dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1796,12 +1822,42 @@ zxdh_init_once(struct rte_eth_dev *eth_dev) return ret; } +static int +zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; + if (hw->is_pf && dtb_data->init_done) { + dtb_data->dev_refcnt++; + zxdh_tbl_entry_offline_destroy(hw); + PMD_DRV_LOG(INFO, "no need to init dtb dtb chanenl %d devref %d", + dtb_data->queueid, dtb_data->dev_refcnt); + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { @@ -1820,6 +1876,7 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); return -1; } + zxdh_tbl_entry_offline_destroy(hw); } if (zxdh_shared_data != NULL) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fb61e0f99c..1cfaee240a 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -519,6 +519,8 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) + static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) { @@ -1791,6 +1793,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3803,6 +3819,219 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_HASH_CFG *p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_D_HEAD *p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%u] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + break; + default: + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %u] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = dpp_se_cfg[dev_id]; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3814,6 +4043,10 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != 0) PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4081,6 +4314,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5904,6 +6156,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -6118,6 +6393,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %u success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %u fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8585,6 +8955,691 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + + if (srh_succ) { + zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zcell_id :%u", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zreg_id :%u", + zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = rte_zmalloc(NULL, max_item_num * sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_rst = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + rte_free(p_key); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(dev_id, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(dev_id, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 3b66cf0b9f..aedc34b193 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1879,6 +1879,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1915,5 +1920,10 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t plcr_en, uint32_t profile_id); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 107615 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 13/14] net/zxdh: add acl tables ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (11 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-03-21 7:31 ` Bingbin Chen 2025-03-21 7:32 ` [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues Bingbin Chen 2025-03-27 18:12 ` [PATCH v6 00/14] net/zxdh: add network processor ops Stephen Hemminger 14 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:31 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 42803 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_msg.c | 3 +- drivers/net/zxdh/zxdh_mtr.c | 8 +- drivers/net/zxdh/zxdh_np.c | 962 +++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 39 +- 4 files changed, 995 insertions(+), 17 deletions(-) diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c index 96ad638e83..f43f272cff 100644 --- a/drivers/net/zxdh/zxdh_msg.c +++ b/drivers/net/zxdh/zxdh_msg.c @@ -2043,7 +2043,8 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, (struct zxdh_plcr_profile_cfg *)cfg_data; union zxdh_offload_profile_cfg *plcr_param = &zxdh_plcr_profile_cfg->plcr_param; - ret = zxdh_np_car_profile_cfg_set(vport, + ret = zxdh_np_car_profile_cfg_set(pf_hw->dev_id, + vport, zxdh_plcr_profile_cfg->car_type, zxdh_plcr_profile_cfg->packet_mode, zxdh_plcr_profile_cfg->hw_profile_id, diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c index 3797a5b29b..809456d73f 100644 --- a/drivers/net/zxdh/zxdh_mtr.c +++ b/drivers/net/zxdh/zxdh_mtr.c @@ -281,7 +281,7 @@ zxdh_hw_profile_free_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type, { struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_delete(vport, car_type, + int ret = zxdh_np_car_profile_id_delete(hw->dev_id, vport, car_type, (uint64_t)hw_profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u free hw profile %u failed", vport, hw_profile_id); @@ -299,7 +299,7 @@ zxdh_hw_profile_alloc_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type uint64_t profile_id = HW_PROFILE_MAX; struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_add(vport, car_type, &profile_id); + int ret = zxdh_np_car_profile_id_add(hw->dev_id, vport, car_type, &profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u alloc hw profile failed", vport); @@ -551,7 +551,9 @@ zxdh_hw_profile_config_direct(struct rte_eth_dev *dev __rte_unused, struct zxdh_meter_profile *mp, struct rte_mtr_error *error) { - int ret = zxdh_np_car_profile_cfg_set(mp->hw_profile_owner_vport, + struct zxdh_hw *hw = dev->data->dev_private; + int ret = zxdh_np_car_profile_cfg_set(hw->dev_id, + mp->hw_profile_owner_vport, car_type, mp->profile.packet_mode, (uint32_t)hw_profile_id, &mp->plcr_param); if (ret) { diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1cfaee240a..66902e7e92 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -612,6 +612,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -2345,6 +2350,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); @@ -3386,6 +3393,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -4032,6 +4065,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "etcam_is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %u ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -4047,6 +4139,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4249,6 +4342,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ETCAM, + .block_sel = block_idx, + .init_en = 0, + .row_or_col_msk = row_or_col_msk, + .vben = vben, + .reg_tcam_flag = reg_tcam_flag, + .uload = flush, + .rd_wr = rd_wr, + .wr_mode = wr_mode, + .data_or_mask = data_or_mask, + .addr = ram_addr, + .vbit = vbit, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4314,6 +4471,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ETCAM, + .block_sel = p_etcam_dump_info->block_sel, + .addr = p_etcam_dump_info->addr, + .rd_mode = p_etcam_dump_info->rd_mode, + .data_or_mask = p_etcam_dump_info->data_or_mask, + .tb_depth = p_etcam_dump_info->tb_depth, + .tb_width = p_etcam_dump_info->tb_width, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4333,6 +4519,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5836,7 +6054,318 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + uint32_t entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_TBL_64b: + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + case ZXDH_ERAM128_TBL_1b: + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + default: + break; + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} int zxdh_np_dtb_table_entry_write(uint32_t dev_id, @@ -5881,6 +6410,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -6989,6 +7522,386 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "get done, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "get fail, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + + case ZXDH_ERAM128_TBL_64b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -7037,6 +7950,13 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; @@ -9650,9 +10570,9 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) uint32_t done_flag = 0; while (!done_flag) { - rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, "reg_read fail!"); + PMD_DRV_LOG(ERR, "reg_read32 fail!"); return rc; } @@ -9685,10 +10605,17 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t temp_data[4] = {0}; uint32_t *p_temp_data = NULL; ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_ind_spinlock->spinlock); rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -9700,11 +10627,13 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { + rte_spinlock_unlock(&p_ind_spinlock->spinlock); PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; @@ -9712,6 +10641,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; @@ -9720,6 +10650,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; @@ -9728,6 +10659,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; @@ -9746,10 +10678,12 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7); @@ -9758,6 +10692,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6); @@ -9766,6 +10701,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5); @@ -9773,7 +10709,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, break; case ZXDH_ERAM128_OPR_1b: PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", - rd_clr_mode, rd_mode); + rd_clr_mode, rd_mode); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; default: break; @@ -9788,12 +10725,14 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, &cpu_ind_cmd); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -9806,6 +10745,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, p_temp_data + 3 - i); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } } @@ -9844,6 +10784,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, } } + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return rc; } @@ -9897,7 +10839,7 @@ zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MS { uint32_t ret = 0; ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { - .msg = (void *)&p_msg, + .msg = (void *)p_msg, .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), }; @@ -10120,7 +11062,8 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, } uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id) { @@ -10135,7 +11078,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(dev_id, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -10153,14 +11096,14 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, } uint32_t -zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, +zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id __rte_unused, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg) { uint32_t ret = 0; - uint32_t dev_id = 0; ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); @@ -10173,11 +11116,10 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, } uint32_t -zxdh_np_car_profile_id_delete(uint32_t vport_id, +zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t dev_id = 0; uint32_t profileid = profile_id & 0xFFFF; ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index aedc34b193..1b8f17474d 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1327,6 +1327,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1341,6 +1359,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; @@ -1903,15 +1934,17 @@ uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, uint32_t clr_mode, uint32_t *p_data); uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id); -uint32_t zxdh_np_car_profile_cfg_set(uint32_t vport_id, +uint32_t zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg); -uint32_t zxdh_np_car_profile_id_delete(uint32_t vport_id, +uint32_t zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id); uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t car_type, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 118466 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (12 preceding siblings ...) 2025-03-21 7:31 ` [PATCH v6 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-03-21 7:32 ` Bingbin Chen 2025-04-08 13:34 ` Stephen Hemminger 2025-03-27 18:12 ` [PATCH v6 00/14] net/zxdh: add network processor ops Stephen Hemminger 14 siblings, 1 reply; 114+ messages in thread From: Bingbin Chen @ 2025-03-21 7:32 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 90576 bytes --] In order to accommodate previous firmware versions, this patch has optimized the message processing ops, and modify some issues. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_common.h | 100 ++++++++ drivers/net/zxdh/zxdh_ethdev.c | 18 +- drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +++++---- drivers/net/zxdh/zxdh_ethdev_ops.h | 35 +++ drivers/net/zxdh/zxdh_msg.c | 378 +++++++++++++++++------------ drivers/net/zxdh/zxdh_msg.h | 99 +++++--- drivers/net/zxdh/zxdh_mtr.c | 42 ++-- drivers/net/zxdh/zxdh_mtr.h | 5 + drivers/net/zxdh/zxdh_pci.c | 24 +- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 12 +- drivers/net/zxdh/zxdh_tables.c | 67 ++--- drivers/net/zxdh/zxdh_tables.h | 68 ++++-- 13 files changed, 649 insertions(+), 310 deletions(-) diff --git a/drivers/net/zxdh/zxdh_common.h b/drivers/net/zxdh/zxdh_common.h index d78a822ebf..aaf4e0bedb 100644 --- a/drivers/net/zxdh/zxdh_common.h +++ b/drivers/net/zxdh/zxdh_common.h @@ -9,6 +9,7 @@ #include <rte_ethdev.h> #include "zxdh_ethdev.h" +#include "zxdh_logs.h" #define ZXDH_VF_LOCK_REG 0x90 #define ZXDH_VF_LOCK_ENABLE_MASK 0x1 @@ -20,6 +21,105 @@ struct zxdh_res_para { uint16_t src_type; /* refer to BAR_DRIVER_TYPE */ }; +static inline size_t +zxdh_get_value(uint32_t fld_sz, uint8_t *addr) { + size_t result = 0; + switch (fld_sz) { + case 1: + result = *((uint8_t *)addr); + break; + case 2: + result = *((uint16_t *)addr); + break; + case 4: + result = *((uint32_t *)addr); + break; + case 8: + result = *((uint64_t *)addr); + break; + default: + PMD_MSG_LOG(ERR, "unreachable field size %u", fld_sz); + break; + } + return result; +} + +static inline void +zxdh_set_value(uint32_t fld_sz, uint8_t *addr, size_t value) { + switch (fld_sz) { + case 1: + *(uint8_t *)addr = (uint8_t)value; + break; + case 2: + *(uint16_t *)addr = (uint16_t)value; + break; + case 4: + *(uint32_t *)addr = (uint32_t)value; + break; + case 8: + *(uint64_t *)addr = (uint64_t)value; + break; + default: + PMD_MSG_LOG(ERR, "unreachable field size %u", fld_sz); + break; + } +} + +#define __zxdh_nullp(typ) ((struct zxdh_ifc_##typ##_bits *)0) +#define __zxdh_bit_sz(typ, fld) sizeof(__zxdh_nullp(typ)->fld) +#define __zxdh_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ + (&(__zxdh_nullp(typ)->fld))) +#define __zxdh_dw_bit_off(typ, fld) (32 - __zxdh_bit_sz(typ, fld) - \ + (__zxdh_bit_off(typ, fld) & 0x1f)) +#define __zxdh_dw_off(typ, fld) (__zxdh_bit_off(typ, fld) / 32) +#define __zxdh_64_off(typ, fld) (__zxdh_bit_off(typ, fld) / 64) +#define __zxdh_dw_mask(typ, fld) (__zxdh_mask(typ, fld) << \ + __zxdh_dw_bit_off(typ, fld)) +#define __zxdh_mask(typ, fld) ((uint32_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) +#define __zxdh_16_off(typ, fld) (__zxdh_bit_off(typ, fld) / 16) +#define __zxdh_16_bit_off(typ, fld) (16 - __zxdh_bit_sz(typ, fld) - \ + (__zxdh_bit_off(typ, fld) & 0xf)) +#define __zxdh_mask16(typ, fld) ((uint16_t)((1ull << __zxdh_bit_sz(typ, fld)) - 1)) +#define __zxdh_16_mask(typ, fld) (__zxdh_mask16(typ, fld) << \ + __zxdh_16_bit_off(typ, fld)) +#define ZXDH_ST_SZ_BYTES(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 8) +#define ZXDH_ST_SZ_DW(typ) (sizeof(struct zxdh_ifc_##typ##_bits) / 32) +#define ZXDH_BYTE_OFF(typ, fld) (__zxdh_bit_off(typ, fld) / 8) +#define ZXDH_ADDR_OF(typ, p, fld) ((uint8_t *)(p) + ZXDH_BYTE_OFF(typ, fld)) + +#define BUILD_BUG_ON(condition) do { \ + if (condition) \ + __builtin_unreachable(); \ + } while (0) + +#define ZXDH_SET(typ, p, fld, v) do { \ + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ + zxdh_set_value(fld_sz, addr, v); \ +} while (0) + +#define ZXDH_GET(typ, p, fld) ({ \ + BUILD_BUG_ON(__zxdh_bit_sz(typ, fld) % 8); \ + uint32_t fld_sz = __zxdh_bit_sz(typ, fld) / 8; \ + uint8_t *addr = ZXDH_ADDR_OF(typ, p, fld); \ + zxdh_get_value(fld_sz, addr); \ +}) + +#define ZXDH_SET_ARRAY(typ, p, fld, index, value, type) \ + do { \ + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ + (index) * sizeof(type)); \ + *addr = (type)(value); \ + } while (0) + +#define ZXDH_GET_ARRAY(typ, p, fld, index, type) \ + ({ \ + type *addr = (type *)((uint8_t *)ZXDH_ADDR_OF(typ, p, fld) + \ + (index) * sizeof(type)); \ + *addr; \ + }) + int32_t zxdh_phyport_get(struct rte_eth_dev *dev, uint8_t *phyport); int32_t zxdh_panelid_get(struct rte_eth_dev *dev, uint8_t *pannelid); int32_t zxdh_hashidx_get(struct rte_eth_dev *dev, uint8_t *hash_idx); diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea8b18e5e1..a0cea32b87 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1250,10 +1250,6 @@ zxdh_set_rxtx_funcs(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; - if (!zxdh_pci_packed_queue(hw)) { - PMD_DRV_LOG(ERR, "port %u not support packed queue", eth_dev->data->port_id); - return -1; - } if (!zxdh_pci_with_feature(hw, ZXDH_NET_F_MRG_RXBUF)) { PMD_DRV_LOG(ERR, "port %u not support rx mergeable", eth_dev->data->port_id); return -1; @@ -1498,6 +1494,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) struct zxdh_dtb_bulk_dump_info dtb_dump_baseres[] = { {"sdt_vport_att_table", 4 * 1024 * 1024, ZXDH_SDT_VPORT_ATT_TABLE, NULL}, + {"sdt_vlan_att_table", 4 * 1024 * 1024, ZXDH_SDT_VLAN_ATT_TABLE, NULL}, + {"sdt_rss_table", 4 * 1024 * 1024, ZXDH_SDT_RSS_ATT_TABLE, NULL}, {"sdt_l2_entry_table0", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE0, NULL}, {"sdt_l2_entry_table1", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE1, NULL}, {"sdt_l2_entry_table2", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE2, NULL}, @@ -1514,7 +1512,7 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) for (i = 0; i < (int)RTE_DIM(dtb_dump_baseres); i++) { struct zxdh_dtb_bulk_dump_info *p = dtb_dump_baseres + i; char buf[ZXDH_MAX_NAME_LEN] = {0}; - + snprintf(buf, sizeof(buf), "%s_%x", p->mz_name, hw->dev_id); p->mz_name = buf; const struct rte_memzone *generic_dump_mz = @@ -1544,6 +1542,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_bar_offset_params param = {0}; struct zxdh_bar_offset_res res = {0}; + char buf[ZXDH_MAX_NAME_LEN] = {0}; struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; @@ -1569,7 +1568,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->vport = hw->vport.vport; dpp_ctrl->vector = ZXDH_MSIX_INTR_DTB_VEC; strlcpy(dpp_ctrl->port_name, dev->device->name, sizeof(dpp_ctrl->port_name)); - dpp_ctrl->pcie_vir_addr = (uint32_t)hw->bar_addr[0]; + dpp_ctrl->pcie_vir_addr = hw->bar_addr[0]; param.pcie_id = hw->pcie_id; param.virt_addr = hw->bar_addr[0] + ZXDH_CTRLCH_OFFSET; @@ -1584,7 +1583,8 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->np_bar_offset = res.bar_offset; if (!dtb_data->dtb_table_conf_mz) { - const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_conf_mz", + snprintf(buf, sizeof(buf), "%s_%x", "zxdh_dtb_table_conf_mz", hw->dev_id); + const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_CONF_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (conf_mz == NULL) { @@ -1600,7 +1600,9 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) } if (!dtb_data->dtb_table_dump_mz) { - const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_dump_mz", + memset(buf, '\0', sizeof(buf)); + snprintf(buf, sizeof(buf), "%s_%x", "zxdh_dtb_table_dump_mz", hw->dev_id); + const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_DUMP_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (dump_mz == NULL) { diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c index 2b02734c62..f8e8d26c50 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.c +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c @@ -15,6 +15,7 @@ #include "zxdh_np.h" #include "zxdh_queue.h" #include "zxdh_mtr.h" +#include "zxdh_common.h" #define ZXDH_VLAN_FILTER_GROUPS 64 #define ZXDH_INVALID_LOGIC_QID 0xFFFFU @@ -278,9 +279,11 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; uint16_t status = 0; int32_t ret = 0; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *link_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, link_msg); if (zxdh_pci_with_feature(hw, ZXDH_NET_F_STATUS)) zxdh_pci_read_dev_config(hw, offsetof(struct zxdh_net_config, status), @@ -295,17 +298,18 @@ zxdh_link_info_get(struct rte_eth_dev *dev, struct rte_eth_link *link) zxdh_agent_msg_build(hw, ZXDH_MAC_LINK_GET, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_BAR_MODULE_MAC); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_MAC_LINK_GET); return -1; } - link->link_speed = reply_info.reply_body.link_msg.speed; - link->link_autoneg = reply_info.reply_body.link_msg.autoneg; - hw->speed_mode = reply_info.reply_body.link_msg.speed_modes; - if ((reply_info.reply_body.link_msg.duplex & RTE_ETH_LINK_FULL_DUPLEX) == + + link->link_speed = ZXDH_GET(link_info_msg, link_msg_addr, speed); + link->link_autoneg = ZXDH_GET(link_info_msg, link_msg_addr, autoneg); + hw->speed_mode = ZXDH_GET(link_info_msg, link_msg_addr, speed_modes); + if ((ZXDH_GET(link_info_msg, link_msg_addr, duplex) & RTE_ETH_LINK_FULL_DUPLEX) == RTE_ETH_LINK_FULL_DUPLEX) link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; else @@ -433,7 +437,7 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) ret = zxdh_del_mac_table(hw, hw->vport.vport, old_addr, hw->hash_search_index, 0, 0); if (ret) { - PMD_DRV_LOG(ERR, "mac_addr_add failed, code:%d", ret); + PMD_DRV_LOG(ERR, "mac_addr_del failed, code:%d", ret); return ret; } hw->uc_num--; @@ -467,6 +471,8 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) hw->uc_num--; } rte_ether_addr_copy(addr, (struct rte_ether_addr *)hw->mac_addr); + zxdh_pci_write_dev_config(hw, offsetof(struct zxdh_net_config, mac), + &hw->mac_addr, RTE_ETHER_ADDR_LEN); return ret; } @@ -566,7 +572,7 @@ zxdh_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, void zxdh_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) { - struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[index]; uint16_t ret = 0; @@ -1072,7 +1078,9 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, { struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; struct zxdh_msg_info msg = {0}; - struct zxdh_msg_reply_info reply_msg = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_reta_msg); uint16_t idx; uint16_t i; int ret = 0; @@ -1094,21 +1102,21 @@ zxdh_dev_rss_reta_query(struct rte_eth_dev *dev, zxdh_msg_head_build(hw, ZXDH_RSS_RETA_GET, &msg); if (hw->is_pf) { - ret = zxdh_rss_table_get(hw, hw->vport.vport, &reply_msg.reply_body.rss_reta); + ret = zxdh_rss_table_get(hw, hw->vport.vport, rss_reta_msg_addr); if (ret) { PMD_DRV_LOG(ERR, "rss reta table set failed"); return -EINVAL; } } else { ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), - &reply_msg, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "vf rss reta table get failed"); return -EINVAL; } } - struct zxdh_rss_reta *reta_table = &reply_msg.reply_body.rss_reta; + struct zxdh_rss_reta *reta_table = rss_reta_msg_addr; for (idx = 0, i = 0; i < reta_size; ++i) { idx = i / RTE_ETH_RETA_GROUP_SIZE; @@ -1232,10 +1240,13 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con struct zxdh_hw *hw = (struct zxdh_hw *)dev->data->dev_private; struct rte_eth_rss_conf *old_rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf; struct zxdh_msg_info msg = {0}; - struct zxdh_msg_reply_info reply_msg = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, rss_hf_msg); struct zxdh_port_attr_table port_attr = {0}; - int ret; + uint32_t rss_hf; uint32_t hw_hf; + int ret; if (rss_conf == NULL) { PMD_DRV_LOG(ERR, "rss conf is NULL"); @@ -1252,16 +1263,17 @@ zxdh_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_con PMD_DRV_LOG(ERR, "rss hash factor set failed"); return -EINVAL; } - reply_msg.reply_body.rss_hf.rss_hf = port_attr.rss_hash_factor; + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, port_attr.rss_hash_factor); } else { ret = zxdh_vf_send_msg_to_pf(dev, &msg, sizeof(struct zxdh_msg_info), - &reply_msg, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "rss hash factor set failed"); return -EINVAL; } } - rss_conf->rss_hf = zxdh_rss_hf_to_eth(reply_msg.reply_body.rss_hf.rss_hf); + rss_hf = ZXDH_GET(rss_hf, rss_hf_msg_addr, rss_hf); + rss_conf->rss_hf = zxdh_rss_hf_to_eth(rss_hf); return 0; } @@ -1382,7 +1394,8 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); enum ZXDH_BAR_MODULE_ID module_id; int ret = 0; @@ -1404,14 +1417,15 @@ zxdh_hw_vqm_stats_get(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode, zxdh_agent_msg_build(hw, opcode, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); if (ret) { PMD_DRV_LOG(ERR, "Failed to get hw stats"); return -1; } - struct zxdh_msg_reply_body *reply_body = &reply_info.reply_body; - memcpy(hw_stats, &reply_body->vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); + void *hw_vqm_stats = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, vqm_stats); + memcpy(hw_stats, hw_vqm_stats, sizeof(struct zxdh_hw_vqm_stats)); + return 0; } @@ -1578,7 +1592,9 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *hw_stas_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_stats); int ret = 0; if (hw->is_pf) { @@ -1590,13 +1606,13 @@ zxdh_hw_np_stats_get(struct rte_eth_dev *dev, struct zxdh_hw_np_stats *np_stats) } else { zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type", hw->vport.vport); return -1; } - memcpy(np_stats, &reply_info.reply_body.np_stats, sizeof(struct zxdh_hw_np_stats)); + memcpy(np_stats, hw_stas_addr, sizeof(struct zxdh_hw_np_stats)); } return ret; } @@ -1666,7 +1682,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; enum ZXDH_BAR_MODULE_ID module_id; int ret = 0; @@ -1685,7 +1701,7 @@ zxdh_hw_stats_reset(struct rte_eth_dev *dev, enum zxdh_agent_msg_type opcode) zxdh_agent_msg_build(hw, opcode, &msg_info); ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), module_id); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), module_id); if (ret) { PMD_DRV_LOG(ERR, "Failed to reset hw stats"); return -1; @@ -1767,13 +1783,13 @@ zxdh_hw_np_stats_vf_reset(struct rte_eth_dev *dev) { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; int ret = 0; msg_info.data.np_stats_query.clear_mode = 1; zxdh_msg_head_build(hw, ZXDH_GET_NP_STATS, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) PMD_DRV_LOG(ERR, "Failed to send ZXDH_PORT_METER_STAT_GET msg. code:%d", ret); @@ -2034,29 +2050,24 @@ zxdh_dev_fw_version_get(struct rte_eth_dev *dev, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *flash_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, flash_msg); char fw_ver[ZXDH_FWVERS_LEN] = {0}; uint32_t ret = 0; zxdh_agent_msg_build(hw, ZXDH_FLASH_FIR_VERSION_GET, &msg_info); - struct zxdh_msg_recviver_mem rsp_data = { - .recv_buffer = (void *)&reply_info, - .buffer_len = sizeof(struct zxdh_msg_reply_info), - }; - ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_MODULE_FLASH); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_FLASH_FIR_VERSION_GET); return -1; } - struct zxdh_msg_reply_body *ack_msg = - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); - memcpy(fw_ver, ack_msg->flash_msg.firmware_version, ZXDH_FWVERS_LEN); + memcpy(fw_ver, flash_msg_addr, ZXDH_FWVERS_LEN); snprintf(fw_version, ZXDH_FWVERS_LEN - 1, "%s", fw_ver); return 0; @@ -2068,7 +2079,7 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; uint8_t ret = 0; zxdh_agent_msg_build(hw, ZXDH_MAC_MODULE_EEPROM_READ, &msg_info); @@ -2079,26 +2090,24 @@ zxdh_en_module_eeprom_read(struct rte_eth_dev *dev, msg_info.data.module_eeprom_msg.offset = query->offset; msg_info.data.module_eeprom_msg.length = query->length; - struct zxdh_msg_recviver_mem rsp_data = { - .recv_buffer = (void *)&reply_info, - .buffer_len = sizeof(struct zxdh_msg_reply_info), - }; - ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), - &reply_info, sizeof(struct zxdh_msg_reply_info), + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info), ZXDH_BAR_MODULE_MAC); if (ret) { PMD_DRV_LOG(ERR, "Failed to send msg: port 0x%x msg type %d", hw->vport.vport, ZXDH_MAC_MODULE_EEPROM_READ); return -1; } - struct zxdh_msg_reply_body *ack_msg = - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); - + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *module_eeprom_msg_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, module_eeprom_msg); + void *agent_mac_module_eeprom_msg_data_addr = + ZXDH_ADDR_OF(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, data); + uint8_t length = ZXDH_GET(agent_mac_module_eeprom_msg, module_eeprom_msg_addr, length); if (data) - memcpy(data, ack_msg->module_eeprom_msg.data, ack_msg->module_eeprom_msg.length); + memcpy(data, agent_mac_module_eeprom_msg_data_addr, length); - return ack_msg->module_eeprom_msg.length; + return length; } int diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.h b/drivers/net/zxdh/zxdh_ethdev_ops.h index a5162a6d6b..97a1eb4532 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.h +++ b/drivers/net/zxdh/zxdh_ethdev_ops.h @@ -62,6 +62,30 @@ struct zxdh_hw_np_stats { uint64_t tx_ssvpc_pkts; }; +struct zxdh_ifc_hw_np_stats_bits { + uint8_t rx_unicast_pkts[0x40]; + uint8_t tx_unicast_pkts[0x40]; + uint8_t rx_unicast_bytes[0x40]; + uint8_t tx_unicast_bytes[0x40]; + uint8_t rx_multicast_pkts[0x40]; + uint8_t tx_multicast_pkts[0x40]; + uint8_t rx_multicast_bytes[0x40]; + uint8_t tx_multicast_bytes[0x40]; + uint8_t rx_broadcast_pkts[0x40]; + uint8_t tx_broadcast_pkts[0x40]; + uint8_t rx_broadcast_bytes[0x40]; + uint8_t tx_broadcast_bytes[0x40]; + uint8_t rx_mtu_drop_pkts[0x40]; + uint8_t tx_mtu_drop_pkts[0x40]; + uint8_t rx_mtu_drop_bytes[0x40]; + uint8_t tx_mtu_drop_bytes[0x40]; + uint8_t rx_mtr_drop_pkts[0x40]; + uint8_t tx_mtr_drop_pkts[0x40]; + uint8_t rx_mtr_drop_bytes[0x40]; + uint8_t tx_mtr_drop_bytes[0x40]; + uint8_t tx_ssvpc_pkts[0x40]; +}; + struct zxdh_hw_vqm_stats { uint64_t rx_total; uint64_t tx_total; @@ -72,6 +96,17 @@ struct zxdh_hw_vqm_stats { uint64_t rx_drop; }; +struct zxdh_ifc_hw_vqm_stats_bits { + uint8_t rx_total[0x40]; + uint8_t tx_total[0x40]; + uint8_t rx_bytes[0x40]; + uint8_t tx_bytes[0x40]; + uint8_t rx_error[0x40]; + uint8_t tx_error[0x40]; + uint8_t rx_drop[0x40]; +}; + + int zxdh_dev_set_link_up(struct rte_eth_dev *dev); int zxdh_dev_set_link_down(struct rte_eth_dev *dev); int32_t zxdh_dev_link_update(struct rte_eth_dev *dev, int32_t wait_to_complete); diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c index f43f272cff..02ecd93b12 100644 --- a/drivers/net/zxdh/zxdh_msg.c +++ b/drivers/net/zxdh/zxdh_msg.c @@ -18,6 +18,7 @@ #include "zxdh_pci.h" #include "zxdh_tables.h" #include "zxdh_np.h" +#include "zxdh_common.h" #define ZXDH_REPS_INFO_FLAG_USABLE 0x00 #define ZXDH_BAR_SEQID_NUM_MAX 256 @@ -695,7 +696,7 @@ static uint16_t zxdh_bar_chan_sync_msg_reps_get(uint64_t subchan_addr, uint64_t recv_buffer, uint16_t buffer_len) { - struct zxdh_bar_msg_header msg_header = {0}; + struct zxdh_bar_msg_header msg_header; uint16_t msg_id = 0; uint16_t msg_len = 0; @@ -987,7 +988,7 @@ zxdh_bar_chan_msg_header_check(struct zxdh_bar_msg_header *msg_header) int zxdh_bar_irq_recv(uint8_t src, uint8_t dst, uint64_t virt_addr, void *dev) { - struct zxdh_bar_msg_header msg_header = {0}; + struct zxdh_bar_msg_header msg_header; uint64_t recv_addr = 0; uint64_t reps_addr = 0; uint16_t ret = 0; @@ -1083,22 +1084,20 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_recviver_mem result = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; int ret = 0; if (reply) { - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); result.recv_buffer = reply; result.buffer_len = reply_len; } else { - result.recv_buffer = &reply_info; - result.buffer_len = sizeof(reply_info); + result.recv_buffer = zxdh_msg_reply_info; + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); } - struct zxdh_msg_reply_head *reply_head = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); - struct zxdh_msg_reply_body *reply_body = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); + void *reply_head_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_head); + void *reply_body_addr = ZXDH_ADDR_OF(msg_reply_info, result.recv_buffer, reply_body); struct zxdh_pci_bar_msg in = { .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + @@ -1118,12 +1117,16 @@ zxdh_vf_send_msg_to_pf(struct rte_eth_dev *dev, void *msg_req, "vf[%d] send bar msg to pf failed.ret %d", hw->vport.vfid, ret); return -1; } - if (reply_head->flag != ZXDH_MSG_REPS_OK) { + + uint8_t flag = ZXDH_GET(msg_reply_head, reply_head_addr, flag); + uint16_t reps_len = ZXDH_GET(msg_reply_head, reply_head_addr, reps_len); + if (flag != ZXDH_MSG_REPS_OK) { PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", - hw->vport.vfid, reply_head->flag, reply_head->reps_len); + hw->vport.vfid, flag, reps_len); return -1; } - if (reply_body->flag != ZXDH_REPS_SUCC) { + uint8_t reply_body_flag = ZXDH_GET(msg_reply_body, reply_body_addr, flag); + if (reply_body_flag != ZXDH_REPS_SUCC) { PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); return -1; } @@ -1137,23 +1140,19 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, { struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_recviver_mem result = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; if (reply) { - RTE_ASSERT(reply_len < sizeof(struct zxdh_msg_reply_info)); + RTE_ASSERT(reply_len < ZXDH_ST_SZ_BYTES(msg_reply_info)); result.recv_buffer = reply; result.buffer_len = reply_len; } else { - result.recv_buffer = &reply_info; - result.buffer_len = sizeof(reply_info); + result.recv_buffer = zxdh_msg_reply_info; + result.buffer_len = ZXDH_ST_SZ_BYTES(msg_reply_info); } - struct zxdh_msg_reply_head *reply_head = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); - struct zxdh_msg_reply_body *reply_body = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); struct zxdh_pci_bar_msg in = { - .payload_addr = &msg_req, + .payload_addr = msg_req, .payload_len = msg_req_len, .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + ZXDH_CTRLCH_OFFSET), .src = hw->is_pf ? ZXDH_MSG_CHAN_END_PF : ZXDH_MSG_CHAN_END_VF, @@ -1166,15 +1165,6 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, PMD_MSG_LOG(ERR, "Failed to send sync messages or receive response"); return -1; } - if (reply_head->flag != ZXDH_MSG_REPS_OK) { - PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", - hw->vport.vfid, reply_head->flag, reply_head->reps_len); - return -1; - } - if (reply_body->flag != ZXDH_REPS_SUCC) { - PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); - return -1; - } return 0; } @@ -1245,7 +1235,7 @@ zxdh_vf_promisc_uninit(struct zxdh_hw *hw, union zxdh_virport_num vport) static int zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { struct zxdh_port_attr_table port_attr = {0}; union zxdh_virport_num port = {.vport = vport}; @@ -1275,14 +1265,13 @@ zxdh_vf_port_init(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, PMD_DRV_LOG(ERR, "vf_promisc_table_init failed, code:%d", ret); goto proc_end; } - - res_info->flag = ZXDH_REPS_SUCC; - *res_len = sizeof(res_info->flag); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); + *res_len = sizeof(uint8_t); return ret; proc_end: - *res_len = sizeof(res_info->flag); - res_info->flag = ZXDH_REPS_FAIL; + *res_len = sizeof(uint8_t); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } @@ -1311,11 +1300,12 @@ zxdh_mac_clear(struct zxdh_hw *hw, union zxdh_virport_num vport) static int zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "uninit"; struct zxdh_port_attr_table port_attr = {0}; union zxdh_virport_num vport_num = {.vport = vport}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); int ret = 0; *res_len = ZXDH_MSG_REPLYBODY_HEAD; @@ -1340,20 +1330,20 @@ zxdh_vf_port_uninit(struct zxdh_hw *pf_hw, } *res_len += strlen(str); - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return ret; proc_end: *res_len += strlen(str); - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_FAIL; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply_body, uint16_t *reply_len) + void *reply_body, uint16_t *reply_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "add mac"; union zxdh_virport_num port = {0}; @@ -1362,6 +1352,8 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, int i = 0, ret = 0; uint16_t vf_id = port.vfid; port.vport = vport; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, reply_data); + void *mac_reply_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply_body, mac_reply_msg); for (i = 0; i < ZXDH_MAX_MAC_ADDRS; i++) if (rte_is_same_ether_addr(&hw->vfinfo[vf_id].vf_mac[i], addr)) @@ -1369,7 +1361,7 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, ret = zxdh_add_mac_table(hw, vport, addr, hw->hash_search_index, 0, 0); if (ret == -EADDRINUSE) { - reply_body->mac_reply_msg.mac_flag = ZXDH_EEXIST_MAC_FLAG; + ZXDH_SET(mac_reply_msg, mac_reply_msg_addr, mac_flag, ZXDH_EEXIST_MAC_FLAG); PMD_DRV_LOG(ERR, "vf vport 0x%x set mac ret 0x%x failed. mac is in used.", port.vport, ret); goto failure; @@ -1389,26 +1381,27 @@ zxdh_add_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, success: sprintf(str, " vport 0x%x set mac ret 0x%x\n", port.vport, ret); *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - rte_memcpy(&reply_body->reply_data, str, strlen(str) + 1); - reply_body->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_SUCC); PMD_DRV_LOG(DEBUG, " reply len %d", *reply_len); return ret; failure: *reply_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - reply_body->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, reply_body, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { int ret, i = 0; struct zxdh_mac_filter *mac_filter = (struct zxdh_mac_filter *)cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "del mac"; uint16_t vf_id = port.vfid; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); PMD_DRV_LOG(DEBUG, "[PF GET MSG FROM VF]--vf mac to del."); ret = zxdh_del_mac_table(hw, vport, &mac_filter->mac, hw->hash_search_index, 0, 0); @@ -1428,19 +1421,19 @@ zxdh_del_vf_mac_table(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, sprintf(str, "vport 0x%x del mac ret 0x%x\n", port.vport, ret); *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - rte_memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = ZXDH_REPS_SUCC; + rte_memcpy(reply_data_addr, str, strlen(str) + 1); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return ret; proc_end: *res_len = strlen(str) + ZXDH_MSG_REPLYBODY_HEAD; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_port_promisc_msg *promisc_msg = (struct zxdh_port_promisc_msg *)cfg_data; int ret = 0; @@ -1458,24 +1451,25 @@ zxdh_vf_promisc_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, goto proc_end; } - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); - reply->flag = ZXDH_REPS_SUCC; + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); return ret; proc_end: - *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(enum zxdh_reps_flag); - reply->flag = ZXDH_REPS_FAIL; + *res_len = sizeof(struct zxdh_port_attr_set_msg) + sizeof(uint8_t); + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len, uint8_t enable) + void *res_info, uint16_t *res_len, uint8_t enable) { struct zxdh_vlan_filter *vlan_filter = cfg_data; uint16_t vlan_id = vlan_filter->vlan_id; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter table"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, reply_data); int ret = 0; ret = zxdh_vlan_filter_table_set(hw, vport, vlan_id, enable); @@ -1483,33 +1477,38 @@ zxdh_vf_vlan_filter_table_process(struct zxdh_hw *hw, uint16_t vport, void *cfg_ sprintf(str, "vlan filter op-code[%d] vlan id:%d failed, code:%d\n", enable, vlan_id, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - memcpy(&res_info->reply_data, str, strlen(str) + 1); - res_info->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; + *res_len = strlen(str) + sizeof(uint8_t); + + memcpy(reply_data_addr, str, strlen(str) + 1); + if (ret == 0) + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); return ret; } static int zxdh_vf_vlan_filter_table_add(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 1); } static int zxdh_vf_vlan_filter_table_del(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { return zxdh_vf_vlan_filter_table_process(hw, vport, cfg_data, res_info, res_len, 0); } static int zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_vlan_filter_set *vlan_filter = cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan filter"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; uint16_t vfid = port.vfid; @@ -1517,19 +1516,23 @@ zxdh_vf_set_vlan_filter(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, if (ret) sprintf(str, "[vfid:%d] vlan filter. set failed, ret:%d\n", vfid, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { struct zxdh_vlan_offload *vlan_offload = cfg_data; union zxdh_virport_num port = (union zxdh_virport_num)vport; char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "vlan offload"; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; uint16_t vfid = port.vfid; @@ -1540,18 +1543,23 @@ zxdh_vf_set_vlan_offload(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, if (ret) sprintf(str, "[vfid:%d] vlan offload set failed, ret:%d\n", vfid, ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); + void *rss_hf_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_hf_msg); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1561,22 +1569,26 @@ zxdh_vf_rss_hf_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unus goto proc_end; } - reply->rss_hf.rss_hf = vport_att.rss_hash_factor; + ZXDH_SET(rss_hf, rss_hf_msg_addr, rss_hf, vport_att.rss_hash_factor); proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_hf"; struct zxdh_rss_hf *rss_hf = cfg_data; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1596,19 +1608,23 @@ zxdh_vf_rss_hf_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, } proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_enable"; struct zxdh_rss_enable *rss_enable = cfg_data; struct zxdh_port_attr_table vport_att = {0}; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_get_port_attr(hw, vport, &vport_att); @@ -1628,51 +1644,63 @@ zxdh_vf_rss_enable(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, } proc_end: - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_table_set(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; struct zxdh_rss_reta *rss_reta = cfg_data; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int32_t ret = 0; ret = zxdh_rss_table_set(hw, vport, rss_reta); if (ret) sprintf(str, "set rss reta tbl failed, code:%d", ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_rss_table_get(struct zxdh_hw *hw, uint16_t vport, void *cfg_data __rte_unused, - struct zxdh_msg_reply_body *reply, uint16_t *res_len) + void *reply, uint16_t *res_len) { char str[ZXDH_MSG_REPLY_BODY_MAX_LEN] = "rss_table"; - struct zxdh_rss_reta *rss_reta = &reply->rss_reta; + void *rss_reta_msg_addr = ZXDH_ADDR_OF(msg_reply_body, reply, rss_reta_msg); + struct zxdh_rss_reta *rss_reta = (struct zxdh_rss_reta *)rss_reta_msg_addr; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reply, reply_data); int ret = 0; ret = zxdh_rss_table_get(hw, vport, rss_reta); if (ret) sprintf(str, "set rss reta tbl failed, code:%d", ret); - *res_len = strlen(str) + sizeof(enum zxdh_reps_flag); - reply->flag = (ret == 0) ? ZXDH_REPS_SUCC : ZXDH_REPS_FAIL; - memcpy(&reply->reply_data, str, strlen(str) + 1); + *res_len = strlen(str) + sizeof(uint8_t); + if (ret == 0) + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_SUCC); + else + ZXDH_SET(msg_reply_body, reply, flag, ZXDH_REPS_FAIL); + memcpy(reply_data_addr, str, strlen(str) + 1); return ret; } static int zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len) + void *res_info, uint16_t *res_len) { RTE_ASSERT(!cfg_data || !pf_hw); if (res_info) @@ -1734,7 +1762,7 @@ zxdh_vf_port_attr_set(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, static int zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, - void *cfg_data, struct zxdh_msg_reply_body *res_info, + void *cfg_data, void *res_info, uint16_t *res_len) { struct zxdh_np_stats_updata_msg *np_stats_query = @@ -1745,6 +1773,47 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, uint32_t idx = 0; int ret = 0; + void *hw_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_stats); + void *tx_unicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_pkts); + void *rx_unicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_pkts); + void *tx_unicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_unicast_bytes); + void *rx_unicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_unicast_bytes); + void *tx_multicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_pkts); + void *rx_multicast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_pkts); + void *tx_multicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_multicast_bytes); + void *rx_multicast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_multicast_bytes); + void *tx_broadcast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_pkts); + void *tx_broadcast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_broadcast_bytes); + void *rx_broadcast_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_pkts); + void *rx_broadcast_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_broadcast_bytes); + void *tx_mtu_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts); + void *tx_mtu_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes); + void *rx_mtu_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts); + void *rx_mtu_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes); + void *tx_mtr_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts); + void *tx_mtr_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes); + void *rx_mtr_drop_pkts_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts); + void *rx_mtr_drop_bytes_addr = + ZXDH_ADDR_OF(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes); if (!res_len || !res_info) { PMD_DRV_LOG(ERR, "get stat invalid inparams"); return -1; @@ -1760,8 +1829,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_unicast_bytes); + zxdh_data_hi_to_lo(tx_unicast_pkts_addr); + zxdh_data_hi_to_lo(tx_unicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_UNICAST_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1771,8 +1840,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_unicast_bytes); + zxdh_data_hi_to_lo(rx_unicast_pkts_addr); + zxdh_data_hi_to_lo(rx_unicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_EGRESS_BASE; ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, @@ -1781,8 +1850,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_multicast_bytes); + zxdh_data_hi_to_lo(tx_multicast_pkts_addr); + zxdh_data_hi_to_lo(tx_multicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MULTICAST_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1792,8 +1861,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_multicast_bytes); + zxdh_data_hi_to_lo(rx_multicast_pkts_addr); + zxdh_data_hi_to_lo(rx_multicast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_EGRESS_BASE; ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, @@ -1802,8 +1871,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_broadcast_bytes); + zxdh_data_hi_to_lo(tx_broadcast_pkts_addr); + zxdh_data_hi_to_lo(tx_broadcast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_BROAD_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1813,8 +1882,8 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_broadcast_bytes); + zxdh_data_hi_to_lo(rx_broadcast_pkts_addr); + zxdh_data_hi_to_lo(rx_broadcast_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_EGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1824,10 +1893,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.tx_mtu_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.tx_mtu_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtu_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtu_drop_bytes, stats_data.n_bytes_dropped); + zxdh_data_hi_to_lo(tx_mtu_drop_pkts_addr); + zxdh_data_hi_to_lo(tx_mtu_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTU_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1837,10 +1906,10 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.rx_mtu_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.rx_mtu_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtu_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtu_drop_bytes, stats_data.n_bytes_dropped); + zxdh_data_hi_to_lo(rx_mtu_drop_pkts_addr); + zxdh_data_hi_to_lo(rx_mtu_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_EGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1850,10 +1919,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.tx_mtr_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.tx_mtr_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.tx_mtr_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, tx_mtr_drop_bytes, stats_data.n_bytes_dropped); + + zxdh_data_hi_to_lo(tx_mtr_drop_pkts_addr); + zxdh_data_hi_to_lo(tx_mtr_drop_bytes_addr); idx = zxdh_vport_to_vfid(vport_num) + ZXDH_MTR_STATS_INGRESS_BASE; memset(&stats_data, 0, sizeof(stats_data)); @@ -1863,10 +1933,11 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, PMD_DRV_LOG(ERR, "get stats failed. code:%d", ret); return ret; } - res_info->np_stats.rx_mtr_drop_pkts = stats_data.n_pkts_dropped; - res_info->np_stats.rx_mtr_drop_bytes = stats_data.n_bytes_dropped; - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_pkts); - zxdh_data_hi_to_lo(&res_info->np_stats.rx_mtr_drop_bytes); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_pkts, stats_data.n_pkts_dropped); + ZXDH_SET(hw_np_stats, hw_stats_addr, rx_mtr_drop_bytes, stats_data.n_bytes_dropped); + + zxdh_data_hi_to_lo(rx_mtr_drop_pkts_addr); + zxdh_data_hi_to_lo(rx_mtr_drop_bytes_addr); *res_len = sizeof(struct zxdh_hw_np_stats); return 0; @@ -1875,12 +1946,13 @@ zxdh_vf_np_stats_update(struct zxdh_hw *pf_hw, uint16_t vport, static int zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = (struct zxdh_mtr_stats_query *)cfg_data; union zxdh_virport_num v_port = {.vport = vport}; + uint8_t *hw_mtr_stats_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, hw_mtr_stats); int ret = 0; uint32_t stat_baseaddr = zxdh_mtr_stats_query->direction == @@ -1892,14 +1964,14 @@ zxdh_vf_mtr_hw_stats_get(struct zxdh_hw *pf_hw, PMD_DRV_LOG(ERR, "get stat invalid in params"); return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); ret = zxdh_np_dtb_stats_get(pf_hw->dev_id, pf_hw->dev_sd->dtb_sd.queueid, - 1, idx, (uint32_t *)&res_info->hw_mtr_stats); + 1, idx, (uint32_t *)hw_mtr_stats_addr); if (ret) { PMD_DRV_LOG(ERR, "get dir %d stats failed", zxdh_mtr_stats_query->direction); return ret; } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); *res_len = sizeof(struct zxdh_hw_mtr_stats); return 0; } @@ -1908,7 +1980,7 @@ static int zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { if (!cfg_data || !res_len || !res_info) { @@ -1917,16 +1989,18 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, } struct rte_mtr_error error = {0}; int ret = 0; - uint64_t profile_id = HW_PROFILE_MAX; + uint64_t hw_profile_id = HW_PROFILE_MAX; + void *mtr_profile_info_addr = ZXDH_ADDR_OF(msg_reply_body, res_info, mtr_profile_info); struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = (struct zxdh_plcr_profile_add *)cfg_data; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); + *res_len = sizeof(struct zxdh_mtr_profile_info); ret = zxdh_hw_profile_alloc_direct(pf_hw->eth_dev, zxdh_plcr_profile_add->car_type, - &profile_id, &error); + &hw_profile_id, &error); if (ret) { PMD_DRV_LOG(ERR, "pf 0x%x for vf 0x%x alloc hw profile failed", @@ -1935,9 +2009,9 @@ zxdh_vf_mtr_hw_profile_add(struct zxdh_hw *pf_hw, ); return -1; } - zxdh_hw_profile_ref(profile_id); - res_info->mtr_profile_info.profile_id = profile_id; - res_info->flag = ZXDH_REPS_SUCC; + zxdh_hw_profile_ref(hw_profile_id); + ZXDH_SET(mtr_profile_info, mtr_profile_info_addr, profile_id, hw_profile_id); + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -1946,7 +2020,7 @@ static int zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { if (!cfg_data || !res_len || !res_info) { @@ -1954,7 +2028,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; struct zxdh_plcr_profile_free *mtr_profile_free = (struct zxdh_plcr_profile_free *)cfg_data; uint64_t profile_id = mtr_profile_free->profile_id; @@ -1980,7 +2054,7 @@ zxdh_vf_mtr_hw_profile_del(struct zxdh_hw *pf_hw, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, "Meter offload del profile failed "); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -1988,7 +2062,7 @@ static int zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { int ret = 0; @@ -2000,7 +2074,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, struct rte_mtr_error error = {0}; struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = (struct zxdh_plcr_flow_cfg *)cfg_data; - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; ret = zxdh_np_stat_car_queue_cfg_set(pf_hw->dev_id, zxdh_plcr_flow_cfg->car_type, @@ -2019,7 +2093,7 @@ zxdh_vf_mtr_hw_plcrflow_cfg(struct zxdh_hw *pf_hw, RTE_MTR_ERROR_TYPE_MTR_PARAMS, NULL, "Failed to bind plcr flow."); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -2027,7 +2101,7 @@ static int zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, + void *res_info, uint16_t *res_len) { int ret = 0; @@ -2036,7 +2110,7 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, PMD_DRV_LOG(ERR, " cfg profile invalid inparams"); return -1; } - res_info->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_FAIL); *res_len = 0; struct rte_mtr_error error = {0}; struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = @@ -2053,7 +2127,7 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, PMD_DRV_LOG(ERR, "(vport %d)config hw profilefailed", vport); return -rte_mtr_error_set(&error, ENOTSUP, RTE_MTR_ERROR_TYPE_METER_PROFILE, NULL, "Meter offload cfg profile failed"); } - res_info->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res_info, flag, ZXDH_REPS_SUCC); return 0; } @@ -2084,7 +2158,7 @@ static const zxdh_msg_process_callback zxdh_proc_cb[] = { static inline int zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, - struct zxdh_msg_reply_body *res, uint16_t *res_len) + void *res, uint16_t *res_len) { struct zxdh_msg_head *msghead = &msg_info->msg_head; int ret = -1; @@ -2097,13 +2171,13 @@ zxdh_config_process_callback(struct zxdh_hw *hw, struct zxdh_msg_info *msg_info, ret = zxdh_proc_cb[msghead->msg_type](hw, msghead->vport, (void *)&msg_info->data, res, res_len); if (!ret) - res->flag = ZXDH_REPS_SUCC; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_SUCC); else - res->flag = ZXDH_REPS_FAIL; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_FAIL); } else { - res->flag = ZXDH_REPS_INVALID; + ZXDH_SET(msg_reply_body, res, flag, ZXDH_REPS_INVALID); } - *res_len += sizeof(res->flag); + *res_len += sizeof(uint8_t); return ret; } @@ -2112,7 +2186,7 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *eth_dev) { struct zxdh_msg_info *msg_info = (struct zxdh_msg_info *)pay_load; - struct zxdh_msg_reply_body *reply_body = reps_buffer; + void *reply_data_addr = ZXDH_ADDR_OF(msg_reply_body, reps_buffer, reply_data); struct rte_eth_dev *dev = (struct rte_eth_dev *)eth_dev; int32_t ret = 0; struct zxdh_hw *hw; @@ -2132,14 +2206,14 @@ pf_recv_bar_msg(void *pay_load, uint16_t len, void *reps_buffer, goto msg_proc_end; } - ret = zxdh_config_process_callback(hw, msg_info, reply_body, &reply_len); - *reps_len = reply_len + sizeof(struct zxdh_msg_reply_head); + ret = zxdh_config_process_callback(hw, msg_info, reps_buffer, &reply_len); + *reps_len = reply_len + ZXDH_ST_SZ_BYTES(msg_reply_head); return ret; msg_proc_end: - memcpy(reply_body->reply_data, &ret, sizeof(ret)); + memcpy(reply_data_addr, &ret, sizeof(ret)); reply_len = sizeof(ret); - *reps_len = sizeof(struct zxdh_msg_reply_head) + reply_len; + *reps_len = ZXDH_ST_SZ_BYTES(msg_reply_head) + reply_len; return ret; } diff --git a/drivers/net/zxdh/zxdh_msg.h b/drivers/net/zxdh/zxdh_msg.h index 58836bb4b7..7dad6f7335 100644 --- a/drivers/net/zxdh/zxdh_msg.h +++ b/drivers/net/zxdh/zxdh_msg.h @@ -11,6 +11,7 @@ #include "zxdh_ethdev_ops.h" #include "zxdh_mtr.h" +#include "zxdh_common.h" #define ZXDH_BAR0_INDEX 0 #define ZXDH_CTRLCH_OFFSET (0x2000) @@ -46,8 +47,10 @@ #define ZXDH_MSG_REPLYBODY_HEAD sizeof(enum zxdh_reps_flag) #define ZXDH_MSG_HEADER_SIZE 4 -#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ - (ZXDH_MSG_PAYLOAD_MAX_LEN - sizeof(struct zxdh_msg_reply_head)) +#define ZXDH_MSG_REPLY_BODY_MAX_LEN \ + (ZXDH_MSG_PAYLOAD_MAX_LEN - ZXDH_MSG_HEADER_SIZE) +#define ZXDH_MSG_REPLY_DATA \ + (ZXDH_MSG_REPLY_BODY_MAX_LEN - ZXDH_MSG_REPLYBODY_HEAD) #define ZXDH_MSG_HEAD_LEN 8 #define ZXDH_MSG_REQ_BODY_MAX_LEN \ @@ -329,12 +332,6 @@ struct zxdh_offset_get_msg { uint16_t type; }; -struct zxdh_msg_reply_head { - uint8_t flag; - uint16_t reps_len; - uint8_t resvd; -}; - enum zxdh_reps_flag { ZXDH_REPS_FAIL, ZXDH_REPS_SUCC = 0xaa, @@ -354,18 +351,39 @@ struct zxdh_link_info_msg { uint32_t speed; }; +struct zxdh_ifc_link_info_msg_bits { + uint8_t autoneg[0x8]; + uint8_t link_state[0x8]; + uint8_t blink_enable[0x8]; + uint8_t duplex[0x8]; + uint8_t speed_modes[0x20]; + uint8_t speed[0x20]; +}; + struct zxdh_rss_reta { uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256]; }; +struct zxdh_ifc_rss_reta_bits { + uint32_t reta[RTE_ETH_RSS_RETA_SIZE_256 * 8]; +}; + struct zxdh_rss_hf { uint32_t rss_hf; }; +struct zxdh_ifc_rss_hf_bits { + uint8_t rss_hf[0x20]; +}; + struct zxdh_mac_reply_msg { uint8_t mac_flag; }; +struct zxdh_ifc_mac_reply_msg_bits { + uint8_t mac_flag[0x8]; +}; + struct zxdh_mac_module_eeprom_msg { uint8_t i2c_addr; uint8_t bank; @@ -375,34 +393,57 @@ struct zxdh_mac_module_eeprom_msg { uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN]; }; +struct zxdh_ifc_agent_mac_module_eeprom_msg_bits { + uint8_t i2c_addr[0x8]; + uint8_t bank[0x8]; + uint8_t page[0x8]; + uint8_t offset[0x8]; + uint8_t length[0x8]; + uint8_t data[ZXDH_MODULE_EEPROM_DATA_LEN * 8]; +}; + struct zxdh_flash_msg { uint8_t firmware_version[ZXDH_FWVERS_LEN]; }; +struct zxdh_ifc_agent_flash_msg_bits { + uint8_t firmware_version[0x100]; +}; + struct zxdh_mtr_profile_info { uint64_t profile_id; }; -struct zxdh_msg_reply_body { - enum zxdh_reps_flag flag; +struct zxdh_ifc_mtr_profile_info_bits { + uint8_t profile_id[0x40]; +}; + +struct zxdh_ifc_msg_reply_body_bits { + uint8_t flag[0x8]; union { - uint8_t reply_data[ZXDH_MSG_REPLY_BODY_MAX_LEN - sizeof(enum zxdh_reps_flag)]; - struct zxdh_hw_np_stats np_stats; - struct zxdh_link_info_msg link_msg; - struct zxdh_rss_reta rss_reta; - struct zxdh_rss_hf rss_hf; - struct zxdh_hw_vqm_stats vqm_stats; - struct zxdh_mac_reply_msg mac_reply_msg; - struct zxdh_flash_msg flash_msg; - struct zxdh_mac_module_eeprom_msg module_eeprom_msg; - struct zxdh_mtr_profile_info mtr_profile_info; - struct zxdh_mtr_stats hw_mtr_stats; + uint8_t reply_data[ZXDH_MSG_REPLY_DATA * 8]; + struct zxdh_ifc_hw_np_stats_bits hw_stats; + struct zxdh_ifc_link_info_msg_bits link_msg; + struct zxdh_ifc_rss_reta_bits rss_reta_msg; + struct zxdh_ifc_rss_hf_bits rss_hf_msg; + struct zxdh_ifc_hw_vqm_stats_bits vqm_stats; + struct zxdh_ifc_mac_reply_msg_bits mac_reply_msg; + struct zxdh_ifc_agent_flash_msg_bits flash_msg; + struct zxdh_ifc_agent_mac_module_eeprom_msg_bits module_eeprom_msg; + struct zxdh_ifc_mtr_profile_info_bits mtr_profile_info; + struct zxdh_ifc_mtr_stats_bits hw_mtr_stats; }; }; -struct zxdh_msg_reply_info { - struct zxdh_msg_reply_head reply_head; - struct zxdh_msg_reply_body reply_body; +struct zxdh_ifc_msg_reply_head_bits { + uint8_t flag[0x8]; + uint8_t reps_len[0x10]; + uint8_t resvd[0x8]; +}; + +struct zxdh_ifc_msg_reply_info_bits { + struct zxdh_ifc_msg_reply_head_bits reply_head; + struct zxdh_ifc_msg_reply_body_bits reply_body; }; struct zxdh_vf_init_msg { @@ -412,12 +453,12 @@ struct zxdh_vf_init_msg { uint8_t rss_enable; }; -struct zxdh_msg_head { - enum zxdh_msg_type msg_type; +struct __rte_packed_begin zxdh_msg_head { + uint8_t msg_type; uint16_t vport; uint16_t vf_id; uint16_t pcieid; -}; +} __rte_packed_end; struct zxdh_port_attr_set_msg { uint32_t mode; @@ -455,7 +496,7 @@ struct zxdh_rss_enable { }; struct zxdh_agent_msg_head { - enum zxdh_agent_msg_type msg_type; + uint8_t msg_type; uint8_t panel_id; uint8_t phyport; uint8_t rsv; @@ -526,7 +567,7 @@ struct zxdh_msg_info { typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); typedef int (*zxdh_msg_process_callback)(struct zxdh_hw *hw, uint16_t vport, void *cfg_data, - struct zxdh_msg_reply_body *res_info, uint16_t *res_len); + void *res_info, uint16_t *res_len); typedef int (*zxdh_bar_chan_msg_recv_callback)(void *pay_load, uint16_t len, void *reps_buffer, uint16_t *reps_len, void *dev); diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c index 809456d73f..b23f6535a8 100644 --- a/drivers/net/zxdh/zxdh_mtr.c +++ b/drivers/net/zxdh/zxdh_mtr.c @@ -326,7 +326,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, ret = zxdh_hw_profile_free_direct(dev, car_type, (uint64_t)hw_profile_id, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_free *zxdh_plcr_profile_free = &msg_info.data.zxdh_plcr_profile_free; @@ -335,7 +335,7 @@ zxdh_hw_profile_free(struct rte_eth_dev *dev, uint8_t car_type, zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_DELETE, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_free), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) return -rte_mtr_error_set(error, ENOTSUP, @@ -357,15 +357,19 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, ret = zxdh_hw_profile_alloc_direct(dev, CAR_A, hw_profile_id, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_add *zxdh_plcr_profile_add = &msg_info.data.zxdh_plcr_profile_add; + void *reply_body_addr = + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *mtr_profile_info_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, mtr_profile_info); zxdh_plcr_profile_add->car_type = CAR_A; zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_PROFILE_ID_ADD, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_add), - &reply_info, sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, @@ -376,7 +380,7 @@ zxdh_hw_profile_alloc(struct rte_eth_dev *dev, uint64_t *hw_profile_id, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, "Meter offload alloc profile id msg failed "); } - *hw_profile_id = reply_info.reply_body.mtr_profile_info.profile_id; + *hw_profile_id = ZXDH_GET(mtr_profile_info, mtr_profile_info_addr, profile_id); if (*hw_profile_id == ZXDH_HW_PROFILE_MAX) { return -rte_mtr_error_set(error, ENOTSUP, RTE_MTR_ERROR_TYPE_METER_PROFILE_ID, NULL, @@ -432,7 +436,7 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, } } else { /* send msg to pf */ struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_mtr_stats_query *zxdh_mtr_stats_query = &msg_info.data.zxdh_mtr_stats_query; @@ -442,8 +446,8 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, sizeof(msg_info), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, @@ -451,7 +455,11 @@ zxdh_mtr_hw_counter_query(struct rte_eth_dev *dev, hw->vport.vport); return -rte_mtr_error_set(error, ENOTSUP, RTE_MTR_ERROR_TYPE_STATS, NULL, "Meter offload alloc profile failed"); } - struct zxdh_mtr_stats *hw_mtr_stats = &reply_info.reply_body.hw_mtr_stats; + void *reply_body_addr = + ZXDH_ADDR_OF(msg_reply_info, zxdh_msg_reply_info, reply_body); + void *hw_mtr_stats_addr = + ZXDH_ADDR_OF(msg_reply_body, reply_body_addr, hw_mtr_stats); + struct zxdh_mtr_stats *hw_mtr_stats = (struct zxdh_mtr_stats *)hw_mtr_stats_addr; mtr_stats->n_bytes_dropped = hw_mtr_stats->n_bytes_dropped; mtr_stats->n_pkts_dropped = hw_mtr_stats->n_pkts_dropped; @@ -575,7 +583,7 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i ret = zxdh_hw_profile_config_direct(dev, CAR_A, hw_profile_id, mp, error); } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_profile_cfg *zxdh_plcr_profile_cfg = &msg_info.data.zxdh_plcr_profile_cfg; @@ -590,9 +598,9 @@ static int zxdh_hw_profile_config(struct rte_eth_dev *dev, uint16_t hw_profile_i ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_profile_cfg), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); - + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info) + ); if (ret) { PMD_DRV_LOG(ERR, "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_PROFILE_CFG_SET ", @@ -876,7 +884,7 @@ zxdh_set_mtr_enable(struct rte_eth_dev *dev, uint8_t dir, bool enable, struct rt if (priv->is_pf) { ret = zxdh_get_port_attr(priv, priv->vport.vport, &port_attr); - port_attr.ingress_meter_enable = enable; + port_attr.egress_meter_enable = enable; ret = zxdh_set_port_attr(priv, priv->vport.vport, &port_attr); if (ret) { PMD_DRV_LOG(ERR, "%s set port attr failed", __func__); @@ -938,7 +946,7 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, } } else { struct zxdh_msg_info msg_info = {0}; - struct zxdh_msg_reply_info reply_info = {0}; + uint8_t zxdh_msg_reply_info[ZXDH_ST_SZ_BYTES(msg_reply_info)] = {0}; struct zxdh_plcr_flow_cfg *zxdh_plcr_flow_cfg = &msg_info.data.zxdh_plcr_flow_cfg; zxdh_plcr_flow_cfg->car_type = CAR_A; @@ -949,8 +957,8 @@ zxdh_hw_plcrflow_config(struct rte_eth_dev *dev, uint16_t hw_flow_id, zxdh_msg_head_build(hw, ZXDH_PLCR_CAR_QUEUE_CFG_SET, &msg_info); ret = zxdh_vf_send_msg_to_pf(dev, &msg_info, ZXDH_MSG_HEAD_LEN + sizeof(struct zxdh_plcr_flow_cfg), - &reply_info, - sizeof(struct zxdh_msg_reply_info)); + zxdh_msg_reply_info, + ZXDH_ST_SZ_BYTES(msg_reply_info)); if (ret) { PMD_DRV_LOG(ERR, "Failed msg: port 0x%x msg type ZXDH_PLCR_CAR_QUEUE_CFG_SET ", diff --git a/drivers/net/zxdh/zxdh_mtr.h b/drivers/net/zxdh/zxdh_mtr.h index 749ceb7479..3efcb6b591 100644 --- a/drivers/net/zxdh/zxdh_mtr.h +++ b/drivers/net/zxdh/zxdh_mtr.h @@ -93,6 +93,11 @@ struct zxdh_mtr_stats { uint64_t n_bytes_dropped; }; +struct zxdh_ifc_mtr_stats_bits { + uint8_t n_pkts_dropped[0x40]; + uint8_t n_bytes_dropped[0x40]; +}; + struct zxdh_hw_mtr_stats { uint32_t n_pkts_dropped_hi; uint32_t n_pkts_dropped_lo; diff --git a/drivers/net/zxdh/zxdh_pci.c b/drivers/net/zxdh/zxdh_pci.c index 3d1a3ff0dd..4ff0f065df 100644 --- a/drivers/net/zxdh/zxdh_pci.c +++ b/drivers/net/zxdh/zxdh_pci.c @@ -27,6 +27,23 @@ 1ULL << ZXDH_F_NOTIFICATION_DATA | \ 1ULL << ZXDH_NET_F_MAC) +#define ZXDH_PMD_DEFAULT_HOST_FEATURES \ + (1ULL << ZXDH_NET_F_MRG_RXBUF | \ + 1ULL << ZXDH_NET_F_STATUS | \ + 1ULL << ZXDH_NET_F_MQ | \ + 1ULL << ZXDH_F_ANY_LAYOUT | \ + 1ULL << ZXDH_F_VERSION_1 | \ + 1ULL << ZXDH_F_RING_PACKED | \ + 1ULL << ZXDH_F_IN_ORDER | \ + 1ULL << ZXDH_F_NOTIFICATION_DATA |\ + 1ULL << ZXDH_NET_F_MAC | \ + 1ULL << ZXDH_NET_F_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_TSO4 |\ + 1ULL << ZXDH_NET_F_GUEST_TSO6 |\ + 1ULL << ZXDH_NET_F_HOST_TSO4 |\ + 1ULL << ZXDH_NET_F_HOST_TSO6) + static void zxdh_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t length) @@ -391,13 +408,18 @@ zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t l ZXDH_VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length); } +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length) +{ + ZXDH_VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length); +} + void zxdh_get_pci_dev_config(struct zxdh_hw *hw) { uint64_t guest_features = 0; uint64_t nego_features = 0; - hw->host_features = zxdh_pci_get_features(hw); + hw->host_features = ZXDH_PMD_DEFAULT_HOST_FEATURES; guest_features = (uint64_t)ZXDH_PMD_DEFAULT_GUEST_FEATURES; nego_features = guest_features & hw->host_features; diff --git a/drivers/net/zxdh/zxdh_pci.h b/drivers/net/zxdh/zxdh_pci.h index 9b8bef6c09..a1834f6615 100644 --- a/drivers/net/zxdh/zxdh_pci.h +++ b/drivers/net/zxdh/zxdh_pci.h @@ -162,7 +162,7 @@ void zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, int32_t zxdh_read_pci_caps(struct rte_pci_device *dev, struct zxdh_hw *hw); void zxdh_get_pci_dev_config(struct zxdh_hw *hw); - +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length); uint16_t zxdh_pci_get_features(struct zxdh_hw *hw); enum zxdh_msix_status zxdh_pci_msix_detect(struct rte_pci_device *dev); uint8_t zxdh_pci_isr(struct zxdh_hw *hw); diff --git a/drivers/net/zxdh/zxdh_rxtx.c b/drivers/net/zxdh/zxdh_rxtx.c index 1921a23f25..9bb57d4f84 100644 --- a/drivers/net/zxdh/zxdh_rxtx.c +++ b/drivers/net/zxdh/zxdh_rxtx.c @@ -760,7 +760,6 @@ zxdh_rx_update_mbuf(struct rte_mbuf *m, struct zxdh_net_hdr_ul *hdr) idx = (pkt_type_inner >> 4) & 0xF; m->packet_type |= zxdh_inner_l4_type[idx]; } - } static void zxdh_discard_rxbuf(struct zxdh_virtqueue *vq, struct rte_mbuf *m) @@ -818,9 +817,14 @@ zxdh_recv_pkts_packed(void *rx_queue, struct rte_mbuf **rx_pkts, seg_num = header->type_hdr.num_buffers; /* Private queue only handle type hdr */ - hdr_size = ZXDH_TYPE_HDR_SIZE; - rxm->pkt_len = ((header->type_hdr.port & 0x7f) << 8) + - header->type_hdr.pd_len; + hdr_size = header->type_hdr.pd_len << 1; + if (unlikely(hdr_size > lens[i] || hdr_size < ZXDH_TYPE_HDR_SIZE)) { + PMD_RX_LOG(ERR, "hdr_size:%u is invalid", hdr_size); + rte_pktmbuf_free(rxm); + rxvq->stats.errors++; + rxvq->stats.invalid_hdr_len_err++; + continue; + } rxm->data_off += hdr_size; rxm->nb_segs = seg_num; rxm->ol_flags = 0; diff --git a/drivers/net/zxdh/zxdh_tables.c b/drivers/net/zxdh/zxdh_tables.c index 253d9ce438..29741e53ed 100644 --- a/drivers/net/zxdh/zxdh_tables.c +++ b/drivers/net/zxdh/zxdh_tables.c @@ -8,17 +8,8 @@ #include "zxdh_tables.h" #include "zxdh_logs.h" -#define ZXDH_SDT_VPORT_ATT_TABLE 1 -#define ZXDH_SDT_PANEL_ATT_TABLE 2 -#define ZXDH_SDT_RSS_ATT_TABLE 3 -#define ZXDH_SDT_VLAN_ATT_TABLE 4 -#define ZXDH_SDT_BROCAST_ATT_TABLE 6 -#define ZXDH_SDT_UNICAST_ATT_TABLE 10 -#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 -#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 - -#define ZXDH_MAC_HASH_INDEX_BASE 64 -#define ZXDH_MAC_HASH_INDEX(index) (ZXDH_MAC_HASH_INDEX_BASE + (index)) +#define ZXDH_UNIMAC_HASH_INDEX(index) (ZXDH_SDT_L2_ENTRY_TABLE0 + (index)) +#define ZXDH_MULTIMAC_HASH_INDEX(index) (ZXDH_SDT_MC_TABLE0 + (index)) #define ZXDH_MC_GROUP_NUM 4 #define ZXDH_BASE_VFID 1152 #define ZXDH_TABLE_HIT_FLAG 128 @@ -40,15 +31,16 @@ zxdh_set_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_write = {ZXDH_SDT_VPORT_ATT_TABLE, (void *)&entry}; ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) - PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vport_num.vfid); + PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vfid); return ret; } @@ -72,6 +64,7 @@ zxdh_port_attr_init(struct rte_eth_dev *dev) port_attr.mtu = dev->data->mtu; port_attr.mtu_enable = 1; port_attr.is_up = 0; + port_attr.hash_search_index = hw->hash_search_index; if (!port_attr.rss_enable) port_attr.port_base_qid = 0; @@ -144,6 +137,7 @@ int zxdh_panel_table_init(struct rte_eth_dev *dev) panel.pf_vfid = zxdh_vport_to_vfid(hw->vport); panel.mtu_enable = 1; panel.mtu = dev->data->mtu; + panel.port_vfid_1588 = panel.pf_vfid; ZXDH_DTB_ERAM_ENTRY_INFO_T panel_entry = { .index = hw->phyport, @@ -212,13 +206,14 @@ zxdh_get_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_get = {ZXDH_SDT_VPORT_ATT_TABLE, &entry}; int ret; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry_get, 1); if (ret != 0) - PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vport_num.vfid, ret); + PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vfid, ret); return ret; } @@ -229,7 +224,8 @@ zxdh_delete_port_attr(struct zxdh_hw *hw, uint16_t vport, { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry = { .sdt_no = ZXDH_SDT_VPORT_ATT_TABLE, .p_entry_data = (void *)&entry @@ -247,9 +243,9 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); uint32_t ret; uint16_t group_id = 0; - uint16_t vfid = vport_num.vfid; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); @@ -261,7 +257,7 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad .p_rst = (uint8_t *)&unicast_table.entry }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_UNIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; @@ -298,7 +294,7 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_MULTIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; @@ -351,15 +347,17 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - uint32_t ret, del_flag = 0; - uint16_t group_id = 0; union zxdh_virport_num port = (union zxdh_virport_num)vport; uint16_t vfid = zxdh_vport_to_vfid(port); + uint32_t ret, del_flag = 0; + uint16_t group_id = 0; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); unicast_table.key.sriov_vlan_id = srv_vlanid; unicast_table.key.sriov_vlan_tpid = srv_tpid; + unicast_table.entry.hit_flag = 0; + unicast_table.entry.vfid = rte_cpu_to_be_16(vfid & 0x7ff); ZXDH_DTB_HASH_ENTRY_INFO_T dtb_hash_entry = { .p_actu_key = (uint8_t *)&unicast_table.key, @@ -367,7 +365,7 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_UNIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, hw->dev_sd->dtb_sd.queueid, @@ -395,7 +393,7 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_MULTIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; @@ -424,7 +422,7 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad .p_rst = (uint8_t *)&multicast_table.entry }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_MULTIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; @@ -449,7 +447,7 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad .p_rst = (uint8_t *)&multicast_table.entry }; ZXDH_DTB_USER_ENTRY_T entry_get = { - .sdt_no = ZXDH_MAC_HASH_INDEX(hash_search_idx), + .sdt_no = ZXDH_MULTIMAC_HASH_INDEX(hash_search_idx), .p_entry_data = (void *)&dtb_hash_entry }; @@ -743,11 +741,12 @@ zxdh_vlan_filter_table_set(struct zxdh_hw *hw, uint16_t vport, uint16_t vlan_id, struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_vlan_filter_table vlan_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; memset(&vlan_table, 0, sizeof(struct zxdh_vlan_filter_table)); int table_num = vlan_id / ZXDH_VLAN_FILTER_VLANID_STEP; - uint32_t index = (table_num << 11) | vport_num.vfid; + uint32_t index = (table_num << 11) | vfid; uint16_t group = (vlan_id - table_num * ZXDH_VLAN_FILTER_VLANID_STEP) / 8 + 1; uint8_t val = sizeof(struct zxdh_vlan_filter_table) / sizeof(uint32_t); @@ -800,6 +799,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { @@ -820,7 +820,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss rss_vqid.vqm_qid[0] |= 0x8000; #endif ZXDH_DTB_ERAM_ENTRY_INFO_T entry = { - .index = vport_num.vfid * 32 + i, + .index = vfid * 32 + i, .p_data = (uint32_t *)&rss_vqid }; ZXDH_DTB_USER_ENTRY_T user_entry_write = { @@ -830,7 +830,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) { - PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vfid); return ret; } } @@ -843,16 +843,17 @@ zxdh_rss_table_get(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid * 32 + i, (uint32_t *)&rss_vqid}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid * 32 + i, (uint32_t *)&rss_vqid}; ZXDH_DTB_USER_ENTRY_T user_entry = {ZXDH_SDT_RSS_ATT_TABLE, &entry}; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry, 1); if (ret != 0) { - PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vfid); return -1; } @@ -952,10 +953,11 @@ zxdh_set_port_vlan_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_vlan_table *port_vlan) { union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; ZXDH_DTB_ERAM_ENTRY_INFO_T port_entry = { - .index = vport_num.vfid, + .index = vfid, .p_data = (uint32_t *)port_vlan }; ZXDH_DTB_USER_ENTRY_T entry = { @@ -974,10 +976,11 @@ zxdh_get_port_vlan_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_vlan_table *port_vlan) { union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; ZXDH_DTB_ERAM_ENTRY_INFO_T port_entry = { - .index = vport_num.vfid, + .index = vfid, .p_data = (uint32_t *)port_vlan }; ZXDH_DTB_USER_ENTRY_T entry = { diff --git a/drivers/net/zxdh/zxdh_tables.h b/drivers/net/zxdh/zxdh_tables.h index 2f2ada3a9f..cb34e38be8 100644 --- a/drivers/net/zxdh/zxdh_tables.h +++ b/drivers/net/zxdh/zxdh_tables.h @@ -9,7 +9,13 @@ /* eram */ #define ZXDH_SDT_VPORT_ATT_TABLE 1 - +#define ZXDH_SDT_PANEL_ATT_TABLE 2 +#define ZXDH_SDT_RSS_ATT_TABLE 3 +#define ZXDH_SDT_VLAN_ATT_TABLE 4 +#define ZXDH_SDT_BROCAST_ATT_TABLE 6 +#define ZXDH_SDT_UNICAST_ATT_TABLE 10 +#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 +#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 /* hash */ #define ZXDH_SDT_L2_ENTRY_TABLE0 64 #define ZXDH_SDT_L2_ENTRY_TABLE1 65 @@ -80,8 +86,6 @@ #define ZXDH_MTR_STATS_EGRESS_BASE 0x7481 #define ZXDH_MTR_STATS_INGRESS_BASE 0x7C81 -extern struct zxdh_dtb_shared_data g_dtb_data; - struct zxdh_port_vlan_table { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint16_t business_vlan_tpid:16; @@ -233,19 +237,51 @@ struct zxdh_port_attr_table { }; struct zxdh_panel_table { - uint16_t port_vfid_1588 : 11, - rsv2 : 5; - uint16_t pf_vfid : 11, - rsv1 : 1, - enable_1588_tc : 2, - trust_mode : 1, - hit_flag : 1; - uint32_t mtu : 16, - mtu_enable : 1, - rsv : 3, - tm_base_queue : 12; - uint32_t rsv_1; - uint32_t rsv_2; +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t mtu : 16; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t rsv3 : 16; + uint16_t pf_vfid : 11, + rsv4 : 5; +#else + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t mtu : 16; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t pf_vfid : 11, + rsv4 : 5; + uint16_t rsv3 : 16; +#endif }; /* 16B */ struct zxdh_mac_unicast_key { -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 199818 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues 2025-03-21 7:32 ` [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues Bingbin Chen @ 2025-04-08 13:34 ` Stephen Hemminger 0 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-04-08 13:34 UTC (permalink / raw) To: Bingbin Chen; +Cc: wang.junlong1, yang.yonggang, dev On Fri, 21 Mar 2025 15:32:00 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > + > +#define BUILD_BUG_ON(condition) do { \ > + if (condition) \ > + __builtin_unreachable(); \ > + } while (0) > + This should be using static_assert() please send a follow up patch. ^ permalink raw reply [flat|nested] 114+ messages in thread
* Re: [PATCH v6 00/14] net/zxdh: add network processor ops 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen ` (13 preceding siblings ...) 2025-03-21 7:32 ` [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues Bingbin Chen @ 2025-03-27 18:12 ` Stephen Hemminger 14 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-03-27 18:12 UTC (permalink / raw) To: Bingbin Chen; +Cc: wang.junlong1, yang.yonggang, dev On Fri, 21 Mar 2025 15:31:46 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > v6: > - Use byte stream to process bar channel return messages > and modify some issues to ensure proper functionality. > > v5: > - the VF read/write table function is fixed. > > v4: > - change some tables to const. > - use %u instead of %d. > - delete cast of ret_zmalloc() return. > - resolve code functionality issues. > > V3: > - resolve code style. > - resolve spin lock build issue. > - rebase code baseline. > - modify parameters of the plcr function. > > V2: > - resolve code style and github-robot build issue. > - eliminate commit warning. > - remove unnecessary initialization, which first usage will set. > - replace mutex lock with spinlock. > > V1: > - updated network processor driver. > - improve insert/delete/get table code funcs. > > Bingbin Chen (14): > net/zxdh: add network processor registers ops > net/zxdh: support compatibility check > net/zxdh: add agent channel > net/zxdh: modify dtb queue ops > net/zxdh: add tables dump address ops > net/zxdh: add eram tables ops > net/zxdh: get flow tables resources > net/zxdh: support hash resources configuration > net/zxdh: implement tables initialization > net/zxdh: support hash tables write and delete ops > net/zxdh: get hash table entry result > net/zxdh: delete all hash entries > net/zxdh: add acl tables ops > net/zxdh: optimize msg processing ops and modify some issues > > drivers/net/zxdh/zxdh_common.h | 100 + > drivers/net/zxdh/zxdh_ethdev.c | 88 +- > drivers/net/zxdh/zxdh_ethdev.h | 1 + > drivers/net/zxdh/zxdh_ethdev_ops.c | 109 +- > drivers/net/zxdh/zxdh_ethdev_ops.h | 35 + > drivers/net/zxdh/zxdh_msg.c | 381 +- > drivers/net/zxdh/zxdh_msg.h | 99 +- > drivers/net/zxdh/zxdh_mtr.c | 50 +- > drivers/net/zxdh/zxdh_mtr.h | 5 + > drivers/net/zxdh/zxdh_np.c | 11631 +++++++++++++++++++++++---- > drivers/net/zxdh/zxdh_np.h | 1243 ++- > drivers/net/zxdh/zxdh_pci.c | 24 +- > drivers/net/zxdh/zxdh_pci.h | 2 +- > drivers/net/zxdh/zxdh_rxtx.c | 12 +- > drivers/net/zxdh/zxdh_tables.c | 67 +- > drivers/net/zxdh/zxdh_tables.h | 68 +- > 16 files changed, 11983 insertions(+), 1932 deletions(-) > Applied to next-net with a couple of small additions: 1. Added Bingbing Chen to mailmap 2. Removed unnecessary usage of VLA and enabled warning ^ permalink raw reply [flat|nested] 114+ messages in thread
* [PATCH v4 02/14] net/zxdh: support compatibility check 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 03/14] net/zxdh: add agent channel Bingbin Chen ` (11 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5360 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 12 +++++ 2 files changed, 105 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1534cb2709..f0848658ac 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -24,6 +24,9 @@ static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -1175,6 +1178,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2873,6 +2961,11 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6d2c7aa976..11eb7e15d5 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -905,6 +908,15 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 9875 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 03/14] net/zxdh: add agent channel 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (10 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16208 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 315 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 53 +++++++ 2 files changed, 367 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index f0848658ac..00e02cb36f 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -480,6 +480,70 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %u ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_spinlock; + break; + case ZXDH_DEV_SPINLOCK_T_SMMU0: + *p_spinlock_out = &p_dev_info->smmu0_spinlock; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -908,6 +972,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + return ZXDH_OK; } @@ -999,6 +1066,48 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_DROP: + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_agent_channel_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg, @@ -1014,7 +1123,14 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, uint16_t reply_msg_len = 0; uint64_t agent_addr = 0; - PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id); + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); if (ZXDH_IS_PF(vport)) in.src = ZXDH_MSG_CHAN_END_PF; @@ -1054,6 +1170,165 @@ zxdh_np_agent_channel_sync_send(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T), + }; + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PCIE_BAR_MSG, + .oper = ZXDH_BAR_MSG_NUM_REQ, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_RD, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent read resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_WR, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %u reg_no %u agent write resp err %u .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1263,6 +1538,24 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_pcie_bar_request"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1381,12 +1674,19 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1518,6 +1818,9 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1552,6 +1855,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -2945,6 +3252,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); @@ -2966,6 +3274,11 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 11eb7e15d5..a692eca9aa 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,9 +112,17 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_CHANNEL_REPS_LEN (4) + #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -178,6 +186,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_SPIN_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_SPIN_LOCK_INIT_FAIL (ZXDH_SPIN_LOCK_BASE | 0x001) +#define ZXDH_SPIN_LOCK_LOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0x002) +#define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) +#define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -215,6 +229,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -465,6 +486,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -473,6 +495,8 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_SPINLOCK_T dtb_spinlock; + ZXDH_SPINLOCK_T smmu0_spinlock; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -726,6 +750,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -917,6 +952,24 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { uint32_t msg_len; void *msg; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 37167 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 04/14] net/zxdh: modify dtb queue ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (2 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (9 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 26076 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 491 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 ++++++++ 2 files changed, 482 insertions(+), 106 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 00e02cb36f..3f5d286ffe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -17,16 +17,15 @@ static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; -static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -544,6 +543,25 @@ zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_queue_spinlock[index]; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -938,6 +956,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -973,7 +992,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); - rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); return ZXDH_OK; } @@ -1329,6 +1350,89 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_REQUEST, + .vport = vport_info, + }; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %u, msg_result: %u", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %u, queue_id: %u", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_RELEASE, + .queue_id = queue_id, + }; + + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %u", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1556,48 +1660,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1887,52 +1949,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1967,20 +1983,74 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + uint32_t vport_info = (uint32_t)vport; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", + dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(devid, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %u not request.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } + + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %u name error.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "release queueid %u", queueid); return rc; } @@ -2571,24 +2641,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2603,8 +2683,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2626,6 +2708,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2639,8 +2723,6 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, uint32_t rc = 0; uint32_t dtb_interrupt_status = 0; - dtb_interrupt_status = g_dpp_dtb_int_enable; - rc = zxdh_np_dtb_tab_down_info_set(dev_id, queue_id, dtb_interrupt_status, @@ -2850,20 +2932,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2880,11 +2970,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff; zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info); - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2954,16 +3043,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2978,14 +3074,18 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return 0; } @@ -3245,6 +3345,181 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%u] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%u] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = { + .down_start_phy_addr = phy_addr, + .down_start_vir_addr = vir_addr, + .down_item_size = size, + }; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = { + .up_start_phy_addr = phy_addr, + .up_start_vir_addr = vir_addr, + .up_item_size = size, + }; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -3279,6 +3554,10 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + PMD_DRV_LOG(INFO, "host init done, queue_id = %u", p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index a692eca9aa..6cf8653670 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -497,6 +497,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; + ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -685,6 +686,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -703,6 +776,15 @@ typedef struct zxdh_dtb_table_t { const ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -761,6 +843,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -975,6 +1062,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56114 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 05/14] net/zxdh: add tables dump address ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (3 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (8 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 39968 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1137 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1228 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 3f5d286ffe..98135b37a7 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -26,6 +26,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -324,6 +325,51 @@ zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, #define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) +static inline void +zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) +{ + ptr->data = pdata; + ptr->prev = NULL; + ptr->next = NULL; +} + +static inline void +zxdh_np_init_rbt_tn(ZXDH_RB_TN *p_tn, void *p_newkey) +{ + p_tn->p_key = p_newkey; + p_tn->color_lsv = 0; + p_tn->p_left = NULL; + p_tn->p_right = NULL; + p_tn->p_parent = NULL; + zxdh_np_init_d_node(&p_tn->tn_ln, p_tn); +} + +static inline uint32_t +zxdh_np_get_tn_lsv(ZXDH_RB_TN *p_tn) +{ + return p_tn->color_lsv >> 2; +} + +static inline void +zxdh_np_set_tn_lsv(ZXDH_RB_TN *p_tn, uint32_t list_val) +{ + p_tn->color_lsv &= 0x3; + p_tn->color_lsv |= (list_val << 2); +} + +static inline void +zxdh_np_set_tn_color(ZXDH_RB_TN *p_tn, uint32_t color) +{ + p_tn->color_lsv &= 0xfffffffc; + p_tn->color_lsv |= (color & 0x3); +} + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -465,6 +511,945 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_create(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(ERR, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(ERR, " p_list is null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(ERR, "dw_index is invalid"); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_switch_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = zxdh_np_get_tn_color(p_tn1); + color2 = zxdh_np_get_tn_color(p_tn2); + + zxdh_np_set_tn_color(p_tn1, color2); + zxdh_np_set_tn_color(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (zxdh_np_get_tn_color(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + zxdh_np_set_tn_color(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + zxdh_np_set_tn_color(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " p_rb_cfg already init!"); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_create(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_create"); + + p_rb_cfg->p_keybase = rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + zxdh_np_init_rbt_tn(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + zxdh_np_set_tn_lsv(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + zxdh_np_init_d_node(&p_ins_tn->tn_ln, p_ins_tn); + } + + zxdh_np_set_tn_color(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(ERR, "rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = zxdh_np_get_tn_lsv(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(zxdh_np_get_tn_color(p_par_tn) == ZXDH_RBT_RED); + + zxdh_np_set_tn_color(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + } else { + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (zxdh_np_get_tn_color(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_switch_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (zxdh_np_get_tn_color(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + zxdh_np_set_tn_color(p_del_tn, zxdh_np_get_tn_color(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (zxdh_np_get_tn_color(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (zxdh_np_get_tn_color(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + zxdh_np_set_tn_color(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, zxdh_np_get_tn_lsv(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(ERR, "p_list point null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + memcpy(p_rb_key, p_data, len); + + p_rb_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1976,10 +2961,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%u", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -2009,6 +3096,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %u.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "dev_id %u vport 0x%x name %s queue_id %u done.", @@ -2047,6 +3137,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3494,12 +4587,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = { + .sdt_no = sdt_no, + .phy_addr = phy_addr, + .vir_addr = vir_addr, + .size = size, + }; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3517,6 +4641,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 6cf8653670..36b7628bb7 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -123,6 +123,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -192,6 +199,26 @@ #define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) #define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -236,6 +263,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -372,6 +427,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 108876 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 06/14] net/zxdh: add eram tables ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (4 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (7 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 22262 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 545 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 15 + 2 files changed, 558 insertions(+), 2 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 98135b37a7..fd9c7b47c9 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -196,6 +200,81 @@ static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +static const ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +static const ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static const ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -314,6 +393,17 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + static inline uint64_t zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, uint32_t INDEX) @@ -3220,6 +3310,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static const ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3254,6 +3350,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + const ZXDH_DTB_TABLE_T *p_table_info = NULL; + const ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3304,6 +3433,39 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ERAM, + .base_addr = base_addr, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + PMD_DRV_LOG(DEBUG, "valid: %u", dtb_eram_dump_form_info.valid); + PMD_DRV_LOG(DEBUG, "up_type: %u", dtb_eram_dump_form_info.up_type); + PMD_DRV_LOG(DEBUG, "base_addr: 0x%x", dtb_eram_dump_form_info.base_addr); + PMD_DRV_LOG(DEBUG, "tb_depth: %u", dtb_eram_dump_form_info.tb_depth); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_h: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_h); + PMD_DRV_LOG(DEBUG, "tb_dst_addr_l: 0x%x", dtb_eram_dump_form_info.tb_dst_addr_l); + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -3690,6 +3852,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(DEBUG, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(DEBUG, "[index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(ERR, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + + PMD_DRV_LOG(DEBUG, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(DEBUG, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3825,6 +4079,121 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) { + PMD_DRV_LOG(ERR, "down queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3894,6 +4263,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -3972,6 +4343,8 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } @@ -4070,6 +4443,36 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + static uint32_t zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -4081,7 +4484,7 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, uint64_t addr; if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } @@ -4089,7 +4492,8 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); else - addr = ZXDH_DTB_ITEM_ACK_SIZE; + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; *p_phy_haddr = (addr >> 32) & 0xffffffff; *p_phy_laddr = addr & 0xffffffff; @@ -4097,6 +4501,125 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(DEBUG, "queue_id %u.", queue_id); + PMD_DRV_LOG(DEBUG, "element_id %u.", element_id); + PMD_DRV_LOG(DEBUG, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(DEBUG, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(DEBUG, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(DEBUG, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(DEBUG, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) { + PMD_DRV_LOG(ERR, "dump queue %u item %u overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -4124,6 +4647,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %u element %u dump done.", queue_id, queue_element_id); + return rc; } @@ -4210,6 +4743,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 36b7628bb7..d4a940b038 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -227,6 +227,13 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) + +#define ZXDH_DTB_DELAY_TIME (50) +#define ZXDH_DTB_DOWN_OVER_TIME (2000) +#define ZXDH_DTB_DUMP_OVER_TIME (200000) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -728,6 +735,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56696 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 07/14] net/zxdh: get flow tables resources 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (5 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (6 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 29861 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 13 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 492 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 282 +++++++++++++++++++ 4 files changed, 788 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index e683cbd616..ea34b9229b 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1809,6 +1809,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(hw->dev_id, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index 04b0b58c74..261acd17c3 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -44,6 +44,7 @@ #define ZXDH_MAX_NAME_LEN 32 #define ZXDH_SLOT_MAX 256 #define ZXDH_MAX_VF 256 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fd9c7b47c9..c93f8eb0fb 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2508,6 +2508,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5239,6 +5273,464 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} + +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + PMD_DRV_LOG(DEBUG, "se res get success."); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d4a940b038..b204889c9a 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -130,6 +130,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -521,6 +527,33 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -555,6 +588,113 @@ typedef struct zxdh_sdt_tbl_hash_t { uint32_t hash_clutch_en; } ZXDH_SDT_TBL_HASH_T; +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -596,6 +736,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -954,6 +1095,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -1178,6 +1342,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1213,5 +1494,6 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t drop_flag, uint32_t plcr_en, uint32_t profile_id); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 61852 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 08/14] net/zxdh: support hash resources configuration 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (6 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (5 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 34513 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 774 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 260 +++++++++++++ 2 files changed, 1034 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index c93f8eb0fb..22c30313fe 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -31,6 +31,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +static ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static const uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +static uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -460,6 +477,20 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); } +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -819,6 +850,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -844,6 +902,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5719,6 +5817,678 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + zxdh_np_init_d_node(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + zxdh_np_init_d_node(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + break; + default: + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %u]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlock[%u] is already used", zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ZBlk[%u], ZCell[%u] is already used", + zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %u!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = rte_zmalloc(NULL, sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %u ] is not init", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input zcell_num is %u, bulk %u monopolize zcells is %u", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %u ] is not init", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input zreg_num' is %u, actually bulk %u monopolize zregs is %u", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "dev_id[0x%x],se_type[0x%x] invalid!", dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5728,6 +6498,10 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); PMD_DRV_LOG(DEBUG, "se res get success."); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + PMD_DRV_LOG(DEBUG, "se res init success."); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b204889c9a..8937e24def 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -136,6 +136,43 @@ #define ZXDH_ERAM_MAX_NUM (60) #define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + #define ZXDH_SDT_CFG_LEN (2) #define ZXDH_SDT_VALID (1) #define ZXDH_SDT_INVALID (0) @@ -304,6 +341,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -463,6 +505,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -476,6 +525,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89111 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 09/14] net/zxdh: implement tables initialization 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (7 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (4 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 32052 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 670 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 136 ++++++++ 2 files changed, 806 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 22c30313fe..689ec08344 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -22,6 +22,9 @@ static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +static ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -49,6 +52,10 @@ static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +static ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -491,6 +498,48 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, + uint32_t start_pos, uint32_t len) +{ + uint32_t mask = zxdh_np_comm_get_bit_mask(len); + *dst = (*dst & ~(mask << start_pos)) | ((src & mask) << start_pos); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ + zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -2240,6 +2289,232 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "soft sdt table not init!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft sdt table item invalid!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "0x%08x 0x%08x", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft table item invalid !"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "sdt_no: 0x%08x", sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + PMD_DRV_LOG(DEBUG, "sdt: %u", sdt_no); + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", + table_type); + return ZXDH_ERR; + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -6453,12 +6728,381 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + case ZXDH_SDT_TBLT_HASH: + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + case ZXDH_SDT_TBLT_ETCAM: + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + default: + PMD_DRV_LOG(ERR, "table_type[ %u ] is invalid!", table_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + uint32_t entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%u] not match to key_type[%u].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%u], table_id[%u] is already init", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %u ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode %u, etcam block_num %u is not enough for entry_num 0x%x", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is more than entry_num 0x%x", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode %u, etcam block_num %u is match with entry_num 0x%x", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + zxdh_np_init_d_node(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_tbls[table_id]); + rc = zxdh_comm_double_link_insert_last(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %u ] is already used by table[ %u ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6468,8 +7112,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6486,6 +7136,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 8937e24def..320af0573c 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -103,6 +103,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -346,6 +350,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -532,6 +558,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -955,6 +996,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 79363 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 10/14] net/zxdh: support hash tables write and delete ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (8 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (3 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35069 bytes --] Implement hash tables write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 930 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 17 + 2 files changed, 947 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 689ec08344..67edf581e2 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -540,6 +540,76 @@ zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, #define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) +static inline uint32_t +zxdh_np_zblk_addr_conv(uint32_t zblk_idx) +{ + uint32_t group_size = 1 << ZXDH_ZBLK_IDX_BT_WIDTH; + uint32_t group_number = zblk_idx / ZXDH_ZBLK_NUM_PER_ZGRP; + uint32_t offset_in_group = zblk_idx % ZXDH_ZBLK_NUM_PER_ZGRP; + + return group_number * group_size + offset_in_group; +} + +static inline uint32_t +zxdh_np_zcell_addr_conv(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (zxdh_np_zblk_addr_conv(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | \ + (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) | \ + ((zxdh_np_zblk_addr_conv(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | \ + ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((zxdh_np_zcell_addr_conv(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -1784,6 +1854,16 @@ zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_spinlock_get(uint32_t dev_id, + uint32_t fun_id, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *p_spinlock_out = &p_dev_info->hash_spinlock[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2218,6 +2298,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + rte_spinlock_init(&p_dev_info->hash_spinlock[i].spinlock); + return ZXDH_OK; } @@ -3840,6 +3923,65 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ZCAM, + .ram_reg_flag = reg_sram_flag, + .zgroup_id = zgroup_id, + .zblock_id = zblock_id, + .zcell_id = zcell_id, + .mask = mask, + .sram_addr = sram_addr & 0x1FF, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = (addr >> 16) & 0x1; + uint32_t zgroup_id = (addr >> 14) & 0x3; + uint32_t zblock_id = (addr >> 11) & 0x7; + uint32_t zcell_id = (addr >> 9) & 0x3; + uint32_t mask = (addr >> 17) & 0xF; + uint32_t sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4601,6 +4743,783 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + PMD_DRV_LOG(DEBUG, "sdt_partner:%u", sdt_partner); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_init_rbt_tn(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint32_t rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + zxdh_np_init_d_node(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t item_entry_max = 4; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "pos is[%u], size is[%u]", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + HASH_DDR_CFG *p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + uint8_t key_type = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "hash ddr width mode is not match to the key type."); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s, item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx:[0x%x] hash_arg:[0x%x] crc_value:[0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id:[0x%x] item_idx:[0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_D_NODE *p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = p_hash_entry_cfg->table_id; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + ZXDH_SE_ITEM_CFG *p_item_info = p_rbkey_new->p_item_info; + + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(ERR, "Error!there is not item in hash!"); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_comm_double_link_del failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_hash_red_black_node_alloc failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_ddr failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zcell failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash form write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + p_hash_cfg->hash_stat.insert_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = temp_key; + entry.p_rst = temp_rst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} + + + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -4640,6 +5559,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -4719,6 +5642,13 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 320af0573c..5ca8053d5e 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -94,6 +96,12 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -573,6 +581,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1132,6 +1148,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_SPINLOCK_T hash_spinlock[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90330 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 11/14] net/zxdh: get hash table entry result 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (9 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-03-17 14:57 ` Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (2 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:57 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16703 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 482 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 488 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 67edf581e2..fb61e0f99c 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1371,6 +1371,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -4015,6 +4049,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ZCAM, + .tb_width = tb_width, + .sram_addr = addr & 0x1FF, + .ram_reg_flag = (addr >> 16) & 0x1, + .z_reg_cell_id = (addr >> 9) & 0x3, + .zblock_id = (addr >> 11) & 0x7, + .zgroup_id = (addr >> 14) & 0x3, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -6160,6 +6226,399 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %u.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "hash search failed!"); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_OK; + } + + p_rbkey = p_rb_tn_rtn->p_key; + p_item = p_rbkey->p_item_info; + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + + PMD_DRV_LOG(DEBUG, "hash get sdt_no:%u", sdt_no); + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = temp_key; + hash_entry.p_rst = temp_rst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6170,10 +6629,12 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); - PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode); zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); @@ -6187,6 +6648,25 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; + case ZXDH_SDT_TBLT_HASH: + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, "hash search failed"); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 5ca8053d5e..3b66cf0b9f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1320,6 +1320,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 47918 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 12/14] net/zxdh: delete all hash entries 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (10 preceding siblings ...) 2025-03-17 14:57 ` [PATCH v4 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-03-17 14:58 ` Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 14/14] net/zxdh: fix debugging errors Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 37909 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 57 ++ drivers/net/zxdh/zxdh_np.c | 1055 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 10 + 3 files changed, 1122 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea34b9229b..ea8b18e5e1 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1119,6 +1119,30 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + uint32_t sdt_no; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -1130,6 +1154,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!dtb_data->init_done && !dtb_data->dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--dtb_data->dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1796,12 +1822,42 @@ zxdh_init_once(struct rte_eth_dev *eth_dev) return ret; } +static int +zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; + if (hw->is_pf && dtb_data->init_done) { + dtb_data->dev_refcnt++; + zxdh_tbl_entry_offline_destroy(hw); + PMD_DRV_LOG(INFO, "no need to init dtb dtb chanenl %d devref %d", + dtb_data->queueid, dtb_data->dev_refcnt); + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { @@ -1820,6 +1876,7 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); return -1; } + zxdh_tbl_entry_offline_destroy(hw); } if (zxdh_shared_data != NULL) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index fb61e0f99c..1cfaee240a 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -519,6 +519,8 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) + static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) { @@ -1791,6 +1793,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3803,6 +3819,219 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_HASH_CFG *p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_D_HEAD *p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%u] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + break; + default: + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %u] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = dpp_se_cfg[dev_id]; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%u] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3814,6 +4043,10 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != 0) PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4081,6 +4314,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5904,6 +6156,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -6118,6 +6393,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %u success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %u fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8585,6 +8955,691 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + + if (srh_succ) { + zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zcell_id :%u", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%u]'s bulk_id:%u Mono Zreg_id :%u", + zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = rte_zmalloc(NULL, max_item_num * sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_rst = rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + rte_free(p_key); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(dev_id, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(dev_id, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 3b66cf0b9f..aedc34b193 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1879,6 +1879,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1915,5 +1920,10 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t plcr_en, uint32_t profile_id); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 107615 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 13/14] net/zxdh: add acl tables ops 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (11 preceding siblings ...) 2025-03-17 14:58 ` [PATCH v4 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-03-17 14:58 ` Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 14/14] net/zxdh: fix debugging errors Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31167 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 892 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 31 ++ 2 files changed, 923 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 1cfaee240a..ab8b3ae688 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -612,6 +612,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -4032,6 +4037,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "etcam_is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %u ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -4047,6 +4111,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4249,6 +4314,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ETCAM, + .block_sel = block_idx, + .init_en = 0, + .row_or_col_msk = row_or_col_msk, + .vben = vben, + .reg_tcam_flag = reg_tcam_flag, + .uload = flush, + .rd_wr = rd_wr, + .wr_mode = wr_mode, + .data_or_mask = data_or_mask, + .addr = ram_addr, + .vbit = vbit, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4314,6 +4443,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ETCAM, + .block_sel = p_etcam_dump_info->block_sel, + .addr = p_etcam_dump_info->addr, + .rd_mode = p_etcam_dump_info->rd_mode, + .data_or_mask = p_etcam_dump_info->data_or_mask, + .tb_depth = p_etcam_dump_info->tb_depth, + .tb_width = p_etcam_dump_info->tb_width, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4333,6 +4491,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5836,7 +6026,318 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + uint32_t entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_TBL_64b: + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + case ZXDH_ERAM128_TBL_1b: + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + default: + break; + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} int zxdh_np_dtb_table_entry_write(uint32_t dev_id, @@ -5881,6 +6382,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -6989,6 +7494,386 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %u ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "get done, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "get fail, handle:0x%x block:%u ram_addr:%u rd_mode:%x", + p_dump_acl_entry->handle, block_idx, ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + + case ZXDH_ERAM128_TBL_64b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -7037,6 +7922,13 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index aedc34b193..b1d8b1aef8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1327,6 +1327,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1341,6 +1359,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 89996 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v4 14/14] net/zxdh: fix debugging errors 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen ` (12 preceding siblings ...) 2025-03-17 14:58 ` [PATCH v4 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-03-17 14:58 ` Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-17 14:58 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 33881 bytes --] Fix zxdh driver packet sending and receiving errors. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 19 +++++---- drivers/net/zxdh/zxdh_ethdev_ops.c | 15 +++---- drivers/net/zxdh/zxdh_msg.c | 20 ++------- drivers/net/zxdh/zxdh_msg.h | 12 +++--- drivers/net/zxdh/zxdh_mtr.c | 8 ++-- drivers/net/zxdh/zxdh_np.c | 68 ++++++++++++++++++++++++++---- drivers/net/zxdh/zxdh_np.h | 8 ++-- drivers/net/zxdh/zxdh_pci.c | 24 ++++++++++- drivers/net/zxdh/zxdh_pci.h | 2 +- drivers/net/zxdh/zxdh_rxtx.c | 11 +++-- drivers/net/zxdh/zxdh_tables.c | 42 +++++++++--------- drivers/net/zxdh/zxdh_tables.h | 68 +++++++++++++++++++++++------- 12 files changed, 201 insertions(+), 96 deletions(-) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea8b18e5e1..ba7ea52d20 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1250,10 +1250,6 @@ zxdh_set_rxtx_funcs(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; - if (!zxdh_pci_packed_queue(hw)) { - PMD_DRV_LOG(ERR, "port %u not support packed queue", eth_dev->data->port_id); - return -1; - } if (!zxdh_pci_with_feature(hw, ZXDH_NET_F_MRG_RXBUF)) { PMD_DRV_LOG(ERR, "port %u not support rx mergeable", eth_dev->data->port_id); return -1; @@ -1498,6 +1494,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) struct zxdh_dtb_bulk_dump_info dtb_dump_baseres[] = { {"sdt_vport_att_table", 4 * 1024 * 1024, ZXDH_SDT_VPORT_ATT_TABLE, NULL}, + {"sdt_vlan_att_table", 4 * 1024 * 1024, ZXDH_SDT_VLAN_ATT_TABLE, NULL}, + {"sdt_rss_table", 4 * 1024 * 1024, ZXDH_SDT_RSS_ATT_TABLE, NULL}, {"sdt_l2_entry_table0", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE0, NULL}, {"sdt_l2_entry_table1", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE1, NULL}, {"sdt_l2_entry_table2", 5 * 1024 * 1024, ZXDH_SDT_L2_ENTRY_TABLE2, NULL}, @@ -1514,7 +1512,8 @@ zxdh_dtb_dump_res_init(struct zxdh_hw *hw, ZXDH_DEV_INIT_CTRL_T *dpp_ctrl) for (i = 0; i < (int)RTE_DIM(dtb_dump_baseres); i++) { struct zxdh_dtb_bulk_dump_info *p = dtb_dump_baseres + i; char buf[ZXDH_MAX_NAME_LEN] = {0}; - + memset(buf, '\0', sizeof(buf)); + sprintf(buf, "%s_%x", p->mz_name, hw->dev_id); p->mz_name = buf; const struct rte_memzone *generic_dump_mz = @@ -1544,6 +1543,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_bar_offset_params param = {0}; struct zxdh_bar_offset_res res = {0}; + char buf[ZXDH_MAX_NAME_LEN] = {0}; struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; @@ -1569,7 +1569,7 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->vport = hw->vport.vport; dpp_ctrl->vector = ZXDH_MSIX_INTR_DTB_VEC; strlcpy(dpp_ctrl->port_name, dev->device->name, sizeof(dpp_ctrl->port_name)); - dpp_ctrl->pcie_vir_addr = (uint32_t)hw->bar_addr[0]; + dpp_ctrl->pcie_vir_addr = (uint64_t)hw->bar_addr[0]; param.pcie_id = hw->pcie_id; param.virt_addr = hw->bar_addr[0] + ZXDH_CTRLCH_OFFSET; @@ -1584,7 +1584,8 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) dpp_ctrl->np_bar_offset = res.bar_offset; if (!dtb_data->dtb_table_conf_mz) { - const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_conf_mz", + sprintf(buf, "%s_%x", "zxdh_dtb_table_conf_mz", hw->dev_id); + const struct rte_memzone *conf_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_CONF_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (conf_mz == NULL) { @@ -1600,7 +1601,9 @@ zxdh_np_dtb_res_init(struct rte_eth_dev *dev) } if (!dtb_data->dtb_table_dump_mz) { - const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned("zxdh_dtb_table_dump_mz", + memset(buf, '\0', sizeof(buf)); + sprintf(buf, "%s_%x", "zxdh_dtb_table_dump_mz", hw->dev_id); + const struct rte_memzone *dump_mz = rte_memzone_reserve_aligned(buf, ZXDH_DTB_TABLE_DUMP_SIZE, SOCKET_ID_ANY, 0, RTE_CACHE_LINE_SIZE); if (dump_mz == NULL) { diff --git a/drivers/net/zxdh/zxdh_ethdev_ops.c b/drivers/net/zxdh/zxdh_ethdev_ops.c index 2b02734c62..aa1001da01 100644 --- a/drivers/net/zxdh/zxdh_ethdev_ops.c +++ b/drivers/net/zxdh/zxdh_ethdev_ops.c @@ -433,7 +433,7 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) ret = zxdh_del_mac_table(hw, hw->vport.vport, old_addr, hw->hash_search_index, 0, 0); if (ret) { - PMD_DRV_LOG(ERR, "mac_addr_add failed, code:%d", ret); + PMD_DRV_LOG(ERR, "mac_addr_del failed, code:%d", ret); return ret; } hw->uc_num--; @@ -467,6 +467,8 @@ zxdh_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) hw->uc_num--; } rte_ether_addr_copy(addr, (struct rte_ether_addr *)hw->mac_addr); + zxdh_pci_write_dev_config(hw, offsetof(struct zxdh_net_config, mac), + &hw->mac_addr, RTE_ETHER_ADDR_LEN); return ret; } @@ -566,7 +568,7 @@ zxdh_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, void zxdh_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) { - struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_hw *hw = dev->data->dev_private; struct zxdh_msg_info msg_info = {0}; struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[index]; uint16_t ret = 0; @@ -2040,11 +2042,6 @@ zxdh_dev_fw_version_get(struct rte_eth_dev *dev, zxdh_agent_msg_build(hw, ZXDH_FLASH_FIR_VERSION_GET, &msg_info); - struct zxdh_msg_recviver_mem rsp_data = { - .recv_buffer = (void *)&reply_info, - .buffer_len = sizeof(struct zxdh_msg_reply_info), - }; - ret = zxdh_send_msg_to_riscv(dev, &msg_info, sizeof(struct zxdh_msg_info), &reply_info, sizeof(struct zxdh_msg_reply_info), ZXDH_MODULE_FLASH); @@ -2053,10 +2050,8 @@ zxdh_dev_fw_version_get(struct rte_eth_dev *dev, hw->vport.vport, ZXDH_FLASH_FIR_VERSION_GET); return -1; } - struct zxdh_msg_reply_body *ack_msg = - &(((struct zxdh_msg_reply_info *)rsp_data.recv_buffer)->reply_body); - memcpy(fw_ver, ack_msg->flash_msg.firmware_version, ZXDH_FWVERS_LEN); + memcpy(fw_ver, &reply_info.reply_body.flash_msg, ZXDH_FWVERS_LEN); snprintf(fw_version, ZXDH_FWVERS_LEN - 1, "%s", fw_ver); return 0; diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c index 96ad638e83..fac08fc30c 100644 --- a/drivers/net/zxdh/zxdh_msg.c +++ b/drivers/net/zxdh/zxdh_msg.c @@ -695,7 +695,7 @@ static uint16_t zxdh_bar_chan_sync_msg_reps_get(uint64_t subchan_addr, uint64_t recv_buffer, uint16_t buffer_len) { - struct zxdh_bar_msg_header msg_header = {0}; + struct zxdh_bar_msg_header msg_header; uint16_t msg_id = 0; uint16_t msg_len = 0; @@ -1147,13 +1147,9 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, result.recv_buffer = &reply_info; result.buffer_len = sizeof(reply_info); } - struct zxdh_msg_reply_head *reply_head = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_head); - struct zxdh_msg_reply_body *reply_body = - &(((struct zxdh_msg_reply_info *)result.recv_buffer)->reply_body); struct zxdh_pci_bar_msg in = { - .payload_addr = &msg_req, + .payload_addr = msg_req, .payload_len = msg_req_len, .virt_addr = (uint64_t)(hw->bar_addr[ZXDH_BAR0_INDEX] + ZXDH_CTRLCH_OFFSET), .src = hw->is_pf ? ZXDH_MSG_CHAN_END_PF : ZXDH_MSG_CHAN_END_VF, @@ -1166,15 +1162,6 @@ zxdh_send_msg_to_riscv(struct rte_eth_dev *dev, void *msg_req, PMD_MSG_LOG(ERR, "Failed to send sync messages or receive response"); return -1; } - if (reply_head->flag != ZXDH_MSG_REPS_OK) { - PMD_MSG_LOG(ERR, "vf[%d] get pf reply failed: reply_head flag : 0x%x(0xff is OK).replylen %d", - hw->vport.vfid, reply_head->flag, reply_head->reps_len); - return -1; - } - if (reply_body->flag != ZXDH_REPS_SUCC) { - PMD_MSG_LOG(ERR, "vf[%d] msg processing failed", hw->vfid); - return -1; - } return 0; } @@ -2043,7 +2030,8 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, (struct zxdh_plcr_profile_cfg *)cfg_data; union zxdh_offload_profile_cfg *plcr_param = &zxdh_plcr_profile_cfg->plcr_param; - ret = zxdh_np_car_profile_cfg_set(vport, + ret = zxdh_np_car_profile_cfg_set(pf_hw->dev_id, + vport, zxdh_plcr_profile_cfg->car_type, zxdh_plcr_profile_cfg->packet_mode, zxdh_plcr_profile_cfg->hw_profile_id, diff --git a/drivers/net/zxdh/zxdh_msg.h b/drivers/net/zxdh/zxdh_msg.h index 58836bb4b7..ffe2c9472f 100644 --- a/drivers/net/zxdh/zxdh_msg.h +++ b/drivers/net/zxdh/zxdh_msg.h @@ -384,9 +384,9 @@ struct zxdh_mtr_profile_info { }; struct zxdh_msg_reply_body { - enum zxdh_reps_flag flag; + uint8_t flag; union { - uint8_t reply_data[ZXDH_MSG_REPLY_BODY_MAX_LEN - sizeof(enum zxdh_reps_flag)]; + uint8_t reply_data[ZXDH_MSG_REPLY_BODY_MAX_LEN - sizeof(uint8_t)]; struct zxdh_hw_np_stats np_stats; struct zxdh_link_info_msg link_msg; struct zxdh_rss_reta rss_reta; @@ -412,12 +412,12 @@ struct zxdh_vf_init_msg { uint8_t rss_enable; }; -struct zxdh_msg_head { - enum zxdh_msg_type msg_type; +struct __rte_packed_begin zxdh_msg_head { + uint8_t msg_type; uint16_t vport; uint16_t vf_id; uint16_t pcieid; -}; +} __rte_packed_end; struct zxdh_port_attr_set_msg { uint32_t mode; @@ -455,7 +455,7 @@ struct zxdh_rss_enable { }; struct zxdh_agent_msg_head { - enum zxdh_agent_msg_type msg_type; + uint8_t msg_type; uint8_t panel_id; uint8_t phyport; uint8_t rsv; diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c index 3797a5b29b..809456d73f 100644 --- a/drivers/net/zxdh/zxdh_mtr.c +++ b/drivers/net/zxdh/zxdh_mtr.c @@ -281,7 +281,7 @@ zxdh_hw_profile_free_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type, { struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_delete(vport, car_type, + int ret = zxdh_np_car_profile_id_delete(hw->dev_id, vport, car_type, (uint64_t)hw_profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u free hw profile %u failed", vport, hw_profile_id); @@ -299,7 +299,7 @@ zxdh_hw_profile_alloc_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type uint64_t profile_id = HW_PROFILE_MAX; struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_add(vport, car_type, &profile_id); + int ret = zxdh_np_car_profile_id_add(hw->dev_id, vport, car_type, &profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u alloc hw profile failed", vport); @@ -551,7 +551,9 @@ zxdh_hw_profile_config_direct(struct rte_eth_dev *dev __rte_unused, struct zxdh_meter_profile *mp, struct rte_mtr_error *error) { - int ret = zxdh_np_car_profile_cfg_set(mp->hw_profile_owner_vport, + struct zxdh_hw *hw = dev->data->dev_private; + int ret = zxdh_np_car_profile_cfg_set(hw->dev_id, + mp->hw_profile_owner_vport, car_type, mp->profile.packet_mode, (uint32_t)hw_profile_id, &mp->plcr_param); if (ret) { diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index ab8b3ae688..640c835b8e 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2350,6 +2350,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); @@ -3391,6 +3393,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -10542,9 +10570,9 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) uint32_t done_flag = 0; while (!done_flag) { - rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, "reg_read fail!"); + PMD_DRV_LOG(ERR, "reg_read32 fail!"); return rc; } @@ -10577,10 +10605,17 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t temp_data[4] = {0}; uint32_t *p_temp_data = NULL; ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_ind_spinlock->spinlock); rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -10592,11 +10627,13 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { + rte_spinlock_unlock(&p_ind_spinlock->spinlock); PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; @@ -10604,6 +10641,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; @@ -10612,6 +10650,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; @@ -10620,6 +10659,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; @@ -10638,10 +10678,12 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 7); @@ -10650,6 +10692,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 6); @@ -10658,6 +10701,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } row_index = (index << 5); @@ -10665,7 +10709,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, break; case ZXDH_ERAM128_OPR_1b: PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!", - rd_clr_mode, rd_mode); + rd_clr_mode, rd_mode); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; default: break; @@ -10680,12 +10725,14 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, &cpu_ind_cmd); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } @@ -10698,6 +10745,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, p_temp_data + 3 - i); if (rc != ZXDH_OK) { PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_ERR; } } @@ -10736,6 +10784,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, } } + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return rc; } @@ -11012,7 +11062,8 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, } uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id) { @@ -11027,7 +11078,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(dev_id, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -11045,14 +11096,14 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, } uint32_t -zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, +zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id __rte_unused, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg) { uint32_t ret = 0; - uint32_t dev_id = 0; ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); @@ -11065,11 +11116,10 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, } uint32_t -zxdh_np_car_profile_id_delete(uint32_t vport_id, +zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t dev_id = 0; uint32_t profileid = profile_id & 0xFFFF; ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index b1d8b1aef8..1b8f17474d 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1934,15 +1934,17 @@ uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, uint32_t clr_mode, uint32_t *p_data); uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id); -uint32_t zxdh_np_car_profile_cfg_set(uint32_t vport_id, +uint32_t zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg); -uint32_t zxdh_np_car_profile_id_delete(uint32_t vport_id, +uint32_t zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id); uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t car_type, diff --git a/drivers/net/zxdh/zxdh_pci.c b/drivers/net/zxdh/zxdh_pci.c index 3d1a3ff0dd..4ff0f065df 100644 --- a/drivers/net/zxdh/zxdh_pci.c +++ b/drivers/net/zxdh/zxdh_pci.c @@ -27,6 +27,23 @@ 1ULL << ZXDH_F_NOTIFICATION_DATA | \ 1ULL << ZXDH_NET_F_MAC) +#define ZXDH_PMD_DEFAULT_HOST_FEATURES \ + (1ULL << ZXDH_NET_F_MRG_RXBUF | \ + 1ULL << ZXDH_NET_F_STATUS | \ + 1ULL << ZXDH_NET_F_MQ | \ + 1ULL << ZXDH_F_ANY_LAYOUT | \ + 1ULL << ZXDH_F_VERSION_1 | \ + 1ULL << ZXDH_F_RING_PACKED | \ + 1ULL << ZXDH_F_IN_ORDER | \ + 1ULL << ZXDH_F_NOTIFICATION_DATA |\ + 1ULL << ZXDH_NET_F_MAC | \ + 1ULL << ZXDH_NET_F_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_CSUM |\ + 1ULL << ZXDH_NET_F_GUEST_TSO4 |\ + 1ULL << ZXDH_NET_F_GUEST_TSO6 |\ + 1ULL << ZXDH_NET_F_HOST_TSO4 |\ + 1ULL << ZXDH_NET_F_HOST_TSO6) + static void zxdh_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t length) @@ -391,13 +408,18 @@ zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, void *dst, int32_t l ZXDH_VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length); } +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length) +{ + ZXDH_VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length); +} + void zxdh_get_pci_dev_config(struct zxdh_hw *hw) { uint64_t guest_features = 0; uint64_t nego_features = 0; - hw->host_features = zxdh_pci_get_features(hw); + hw->host_features = ZXDH_PMD_DEFAULT_HOST_FEATURES; guest_features = (uint64_t)ZXDH_PMD_DEFAULT_GUEST_FEATURES; nego_features = guest_features & hw->host_features; diff --git a/drivers/net/zxdh/zxdh_pci.h b/drivers/net/zxdh/zxdh_pci.h index 9b8bef6c09..a1834f6615 100644 --- a/drivers/net/zxdh/zxdh_pci.h +++ b/drivers/net/zxdh/zxdh_pci.h @@ -162,7 +162,7 @@ void zxdh_pci_read_dev_config(struct zxdh_hw *hw, size_t offset, int32_t zxdh_read_pci_caps(struct rte_pci_device *dev, struct zxdh_hw *hw); void zxdh_get_pci_dev_config(struct zxdh_hw *hw); - +void zxdh_pci_write_dev_config(struct zxdh_hw *hw, size_t offset, const void *src, int32_t length); uint16_t zxdh_pci_get_features(struct zxdh_hw *hw); enum zxdh_msix_status zxdh_pci_msix_detect(struct rte_pci_device *dev); uint8_t zxdh_pci_isr(struct zxdh_hw *hw); diff --git a/drivers/net/zxdh/zxdh_rxtx.c b/drivers/net/zxdh/zxdh_rxtx.c index 1921a23f25..4c79b9e75b 100644 --- a/drivers/net/zxdh/zxdh_rxtx.c +++ b/drivers/net/zxdh/zxdh_rxtx.c @@ -818,9 +818,14 @@ zxdh_recv_pkts_packed(void *rx_queue, struct rte_mbuf **rx_pkts, seg_num = header->type_hdr.num_buffers; /* Private queue only handle type hdr */ - hdr_size = ZXDH_TYPE_HDR_SIZE; - rxm->pkt_len = ((header->type_hdr.port & 0x7f) << 8) + - header->type_hdr.pd_len; + hdr_size = header->type_hdr.pd_len << 1; + if (unlikely(hdr_size > lens[i] || hdr_size < ZXDH_TYPE_HDR_SIZE)) { + PMD_RX_LOG(ERR, "hdr_size:%u is invalid", hdr_size); + rte_pktmbuf_free(rxm); + rxvq->stats.errors++; + rxvq->stats.invalid_hdr_len_err++; + continue; + } rxm->data_off += hdr_size; rxm->nb_segs = seg_num; rxm->ol_flags = 0; diff --git a/drivers/net/zxdh/zxdh_tables.c b/drivers/net/zxdh/zxdh_tables.c index 253d9ce438..ab91d51948 100644 --- a/drivers/net/zxdh/zxdh_tables.c +++ b/drivers/net/zxdh/zxdh_tables.c @@ -8,14 +8,7 @@ #include "zxdh_tables.h" #include "zxdh_logs.h" -#define ZXDH_SDT_VPORT_ATT_TABLE 1 -#define ZXDH_SDT_PANEL_ATT_TABLE 2 -#define ZXDH_SDT_RSS_ATT_TABLE 3 -#define ZXDH_SDT_VLAN_ATT_TABLE 4 -#define ZXDH_SDT_BROCAST_ATT_TABLE 6 -#define ZXDH_SDT_UNICAST_ATT_TABLE 10 -#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 -#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 + #define ZXDH_MAC_HASH_INDEX_BASE 64 #define ZXDH_MAC_HASH_INDEX(index) (ZXDH_MAC_HASH_INDEX_BASE + (index)) @@ -40,15 +33,16 @@ zxdh_set_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_write = {ZXDH_SDT_VPORT_ATT_TABLE, (void *)&entry}; ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) - PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vport_num.vfid); + PMD_DRV_LOG(ERR, "write vport_att failed vfid:%d failed", vfid); return ret; } @@ -72,6 +66,7 @@ zxdh_port_attr_init(struct rte_eth_dev *dev) port_attr.mtu = dev->data->mtu; port_attr.mtu_enable = 1; port_attr.is_up = 0; + port_attr.hash_search_index = hw->hash_search_index; if (!port_attr.rss_enable) port_attr.port_base_qid = 0; @@ -144,6 +139,7 @@ int zxdh_panel_table_init(struct rte_eth_dev *dev) panel.pf_vfid = zxdh_vport_to_vfid(hw->vport); panel.mtu_enable = 1; panel.mtu = dev->data->mtu; + panel.port_vfid_1588 = panel.pf_vfid; ZXDH_DTB_ERAM_ENTRY_INFO_T panel_entry = { .index = hw->phyport, @@ -212,13 +208,14 @@ zxdh_get_port_attr(struct zxdh_hw *hw, uint16_t vport, struct zxdh_port_attr_tab { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry_get = {ZXDH_SDT_VPORT_ATT_TABLE, &entry}; int ret; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry_get, 1); if (ret != 0) - PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vport_num.vfid, ret); + PMD_DRV_LOG(ERR, "get port_attr vfid:%d failed, ret:%d", vfid, ret); return ret; } @@ -229,7 +226,8 @@ zxdh_delete_port_attr(struct zxdh_hw *hw, uint16_t vport, { struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid, (uint32_t *)port_attr}; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid, (uint32_t *)port_attr}; ZXDH_DTB_USER_ENTRY_T user_entry = { .sdt_no = ZXDH_SDT_VPORT_ATT_TABLE, .p_entry_data = (void *)&entry @@ -247,9 +245,9 @@ zxdh_add_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); uint32_t ret; uint16_t group_id = 0; - uint16_t vfid = vport_num.vfid; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); @@ -351,15 +349,17 @@ zxdh_del_mac_table(struct zxdh_hw *hw, uint16_t vport, struct rte_ether_addr *ad struct zxdh_mac_unicast_table unicast_table = {0}; struct zxdh_mac_multicast_table multicast_table = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; - uint32_t ret, del_flag = 0; - uint16_t group_id = 0; union zxdh_virport_num port = (union zxdh_virport_num)vport; uint16_t vfid = zxdh_vport_to_vfid(port); + uint32_t ret, del_flag = 0; + uint16_t group_id = 0; if (rte_is_unicast_ether_addr(addr)) { rte_memcpy(unicast_table.key.dmac_addr, addr, sizeof(struct rte_ether_addr)); unicast_table.key.sriov_vlan_id = srv_vlanid; unicast_table.key.sriov_vlan_tpid = srv_tpid; + unicast_table.entry.hit_flag = 0; + unicast_table.entry.vfid = rte_cpu_to_be_16(vfid & 0x7ff); ZXDH_DTB_HASH_ENTRY_INFO_T dtb_hash_entry = { .p_actu_key = (uint8_t *)&unicast_table.key, @@ -800,6 +800,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { @@ -820,7 +821,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss rss_vqid.vqm_qid[0] |= 0x8000; #endif ZXDH_DTB_ERAM_ENTRY_INFO_T entry = { - .index = vport_num.vfid * 32 + i, + .index = vfid * 32 + i, .p_data = (uint32_t *)&rss_vqid }; ZXDH_DTB_USER_ENTRY_T user_entry_write = { @@ -830,7 +831,7 @@ zxdh_rss_table_set(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss ret = zxdh_np_dtb_table_entry_write(hw->slot_id, dtb_data->queueid, 1, &user_entry_write); if (ret != 0) { - PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "write rss base qid failed vfid:%d", vfid); return ret; } } @@ -843,16 +844,17 @@ zxdh_rss_table_get(struct zxdh_hw *hw, uint16_t vport, struct zxdh_rss_reta *rss struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; struct zxdh_rss_to_vqid_table rss_vqid = {0}; union zxdh_virport_num vport_num = (union zxdh_virport_num)vport; + uint16_t vfid = zxdh_vport_to_vfid(vport_num); int ret = 0; for (uint16_t i = 0; i < RTE_ETH_RSS_RETA_SIZE_256 / 8; i++) { - ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vport_num.vfid * 32 + i, (uint32_t *)&rss_vqid}; + ZXDH_DTB_ERAM_ENTRY_INFO_T entry = {vfid * 32 + i, (uint32_t *)&rss_vqid}; ZXDH_DTB_USER_ENTRY_T user_entry = {ZXDH_SDT_RSS_ATT_TABLE, &entry}; ret = zxdh_np_dtb_table_entry_get(hw->slot_id, dtb_data->queueid, &user_entry, 1); if (ret != 0) { - PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vport_num.vfid); + PMD_DRV_LOG(ERR, "get rss tbl failed, vfid:%d", vfid); return -1; } diff --git a/drivers/net/zxdh/zxdh_tables.h b/drivers/net/zxdh/zxdh_tables.h index 2f2ada3a9f..cb34e38be8 100644 --- a/drivers/net/zxdh/zxdh_tables.h +++ b/drivers/net/zxdh/zxdh_tables.h @@ -9,7 +9,13 @@ /* eram */ #define ZXDH_SDT_VPORT_ATT_TABLE 1 - +#define ZXDH_SDT_PANEL_ATT_TABLE 2 +#define ZXDH_SDT_RSS_ATT_TABLE 3 +#define ZXDH_SDT_VLAN_ATT_TABLE 4 +#define ZXDH_SDT_BROCAST_ATT_TABLE 6 +#define ZXDH_SDT_UNICAST_ATT_TABLE 10 +#define ZXDH_SDT_MULTICAST_ATT_TABLE 11 +#define ZXDH_SDT_PORT_VLAN_ATT_TABLE 16 /* hash */ #define ZXDH_SDT_L2_ENTRY_TABLE0 64 #define ZXDH_SDT_L2_ENTRY_TABLE1 65 @@ -80,8 +86,6 @@ #define ZXDH_MTR_STATS_EGRESS_BASE 0x7481 #define ZXDH_MTR_STATS_INGRESS_BASE 0x7C81 -extern struct zxdh_dtb_shared_data g_dtb_data; - struct zxdh_port_vlan_table { #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN uint16_t business_vlan_tpid:16; @@ -233,19 +237,51 @@ struct zxdh_port_attr_table { }; struct zxdh_panel_table { - uint16_t port_vfid_1588 : 11, - rsv2 : 5; - uint16_t pf_vfid : 11, - rsv1 : 1, - enable_1588_tc : 2, - trust_mode : 1, - hit_flag : 1; - uint32_t mtu : 16, - mtu_enable : 1, - rsv : 3, - tm_base_queue : 12; - uint32_t rsv_1; - uint32_t rsv_2; +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t mtu : 16; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t rsv3 : 16; + uint16_t pf_vfid : 11, + rsv4 : 5; +#else + uint16_t rsv1 : 11, + tm_shape_enable : 1, + enable_1588_tc : 2, + trust_mode : 1, + hit_flag : 1; + uint16_t port_vfid_1588 : 11, + rsv2 : 5; + uint16_t mtu_enable : 1, + rsv : 3, + tm_base_queue : 12; + uint16_t mtu : 16; + uint16_t lacp_pf_vfid : 11, + rsv6 : 2, + member_port_up : 1, + bond_link_up : 1, + hw_bond_enable : 1; + uint16_t lacp_pf_qid : 12, + rsv5 : 4; + uint16_t pf_vfid : 11, + rsv4 : 5; + uint16_t rsv3 : 16; +#endif }; /* 16B */ struct zxdh_mac_unicast_key { -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 80320 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 02/14] net/zxdh: support compatibility check 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 03/14] net/zxdh: add agent channel Bingbin Chen ` (11 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 5422 bytes --] Add compatibility check between (np)network processor software and firmware. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 11 +++++ 2 files changed, 104 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 946e987a34..5ed78fde82 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -24,6 +24,9 @@ static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; +static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { + ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -1040,6 +1043,91 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset) return np_addr; } +static uint64_t +zxdh_np_fw_compatible_addr_calc(uint64_t pcie_vir_baddr, uint64_t compatible_offset) +{ + return (pcie_vir_baddr + compatible_offset); +} + +static void +zxdh_np_pf_fw_compatible_addr_set(uint32_t dev_id, uint64_t pcie_vir_baddr) +{ + uint64_t compatible_offset = ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET; + uint64_t compatible_addr = 0; + + compatible_addr = zxdh_np_fw_compatible_addr_calc(pcie_vir_baddr, compatible_offset); + + g_np_fw_compat_addr[dev_id] = compatible_addr; +} + +static void +zxdh_np_fw_compatible_addr_get(uint32_t dev_id, uint64_t *p_compatible_addr) +{ + *p_compatible_addr = g_np_fw_compat_addr[dev_id]; +} + +static void +zxdh_np_fw_version_data_read(uint64_t compatible_base_addr, + ZXDH_VERSION_COMPATIBLE_REG_T *p_fw_version_data, uint32_t module_id) +{ + void *fw_addr = NULL; + uint64_t module_compatible_addr = 0; + + module_compatible_addr = compatible_base_addr + + sizeof(ZXDH_VERSION_COMPATIBLE_REG_T) * (module_id - 1); + + fw_addr = (void *)module_compatible_addr; + + memcpy(p_fw_version_data, fw_addr, sizeof(ZXDH_VERSION_COMPATIBLE_REG_T)); +} + +static void +zxdh_np_fw_version_compatible_data_get(uint32_t dev_id, + ZXDH_VERSION_COMPATIBLE_REG_T *p_version_compatible_value, + uint32_t module_id) +{ + uint64_t compatible_addr = 0; + + zxdh_np_fw_compatible_addr_get(dev_id, &compatible_addr); + + zxdh_np_fw_version_data_read(compatible_addr, p_version_compatible_value, module_id); +} + +static uint32_t +zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) +{ + ZXDH_VERSION_COMPATIBLE_REG_T fw_version = {0}; + + zxdh_np_fw_version_compatible_data_get(dev_id, &fw_version, ZXDH_NPSDK_COMPAT_ITEM_ID); + + if (fw_version.version_compatible_item != ZXDH_NPSDK_COMPAT_ITEM_ID) { + PMD_DRV_LOG(ERR, "version_compatible_item is not DH_NPSDK."); + return ZXDH_ERR; + } + + if (g_np_sdk_version.major != fw_version.major) { + PMD_DRV_LOG(ERR, "dh_npsdk major:%hhu: is not match fw:%hhu!", + g_np_sdk_version.major, fw_version.major); + return ZXDH_ERR; + } + + if (g_np_sdk_version.fw_minor > fw_version.fw_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk fw_minor:%hhu is higher than fw:%hhu!", + g_np_sdk_version.fw_minor, fw_version.fw_minor); + return ZXDH_ERR; + } + + if (g_np_sdk_version.drv_minor < fw_version.drv_minor) { + PMD_DRV_LOG(ERR, "dh_npsdk drv_minor:%hhu is lower than fw:%hhu!", + g_np_sdk_version.drv_minor, fw_version.drv_minor); + return ZXDH_ERR; + } + + PMD_DRV_LOG(INFO, "dh_npsdk compatible check success!"); + + return ZXDH_OK; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -2615,6 +2703,11 @@ zxdh_np_host_init(uint32_t dev_id, agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr; zxdh_np_dev_agent_addr_set(dev_id, agent_addr); + zxdh_np_pf_fw_compatible_addr_set(dev_id, p_dev_init_ctrl->pcie_vir_addr); + + rc = zxdh_np_np_sdk_version_compatible_check(dev_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 90847284fe..d6ceecf3f8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,6 +112,9 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_NPSDK_COMPAT_ITEM_ID (10) +#define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -846,6 +849,14 @@ typedef enum zxdh_profile_type { CAR_MAX } ZXDH_PROFILE_TYPE; +typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { + uint8_t version_compatible_item; + uint8_t major; + uint8_t fw_minor; + uint8_t drv_minor; + uint16_t patch; + uint8_t rsv[2]; +} ZXDH_VERSION_COMPATIBLE_REG_T; int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 9828 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 03/14] net/zxdh: add agent channel 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 02/14] net/zxdh: support compatibility check Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 04/14] net/zxdh: modify dtb queue ops Bingbin Chen ` (10 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 24384 bytes --] Add agent channel to access (np)network processor registers that are not mapped by PCIE. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 449 +++++++++++++++++++++++++++++++------ drivers/net/zxdh/zxdh_np.h | 63 +++++- 2 files changed, 442 insertions(+), 70 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 5ed78fde82..8113332310 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -394,6 +394,70 @@ zxdh_np_dev_init(void) return 0; } +static void +zxdh_np_dev_vport_get(uint32_t dev_id, uint32_t *vport) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *vport = p_dev_info->vport; +} + +static void +zxdh_np_dev_agent_addr_get(uint32_t dev_id, uint64_t *agent_addr) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *agent_addr = p_dev_info->agent_addr; +} + +static void +zxdh_np_dev_fw_bar_msg_num_set(uint32_t dev_id, uint32_t bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + p_dev_info->fw_bar_msg_num = bar_msg_num; + + PMD_DRV_LOG(INFO, "fw_bar_msg_num_set:fw support agent msg num = %u!", bar_msg_num); +} + +static void +zxdh_np_dev_fw_bar_msg_num_get(uint32_t dev_id, uint32_t *bar_msg_num) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *bar_msg_num = p_dev_info->fw_bar_msg_num; +} + +static uint32_t +zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (p_dev_info == NULL) { + PMD_DRV_LOG(ERR, "Get dev_info[ %d ] fail!", dev_id); + return ZXDH_DEV_TYPE_INVALID; + } + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_spinlock; + break; + case ZXDH_DEV_SPINLOCK_T_SMMU0: + *p_spinlock_out = &p_dev_info->smmu0_spinlock; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -827,6 +891,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; + rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + return 0; } @@ -918,6 +985,269 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, } } +static void +zxdh_np_agent_msg_prt(uint8_t type, uint32_t rtn) +{ + switch (rtn) { + case ZXDH_RC_CTRLCH_MSG_LEN_ZERO: + PMD_DRV_LOG(ERR, "type[%u]:msg len is zero!", type); + break; + case ZXDH_RC_CTRLCH_MSG_PRO_ERR: + PMD_DRV_LOG(ERR, "type[%u]:msg process error!", type); + break; + case ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT: + PMD_DRV_LOG(ERR, "type[%u]:fw not support opr of the msg!", type); + break; + case ZXDH_RC_CTRLCH_MSG_DROP: + PMD_DRV_LOG(ERR, "type[%u]:fw not support,drop msg!", type); + break; + default: + break; + } +} + +static uint32_t +zxdh_np_agent_bar_msg_check(uint32_t dev_id, ZXDH_AGENT_CHANNEL_MSG_T *p_msg) +{ + uint8_t type = 0; + uint32_t bar_msg_num = 0; + + type = *((uint8_t *)(p_msg->msg) + 1); + if (type != ZXDH_PCIE_BAR_MSG) { + zxdh_np_dev_fw_bar_msg_num_get(dev_id, &bar_msg_num); + if (type >= bar_msg_num) { + PMD_DRV_LOG(ERR, "type[%u] > fw_bar_msg_num[%u]!", type, bar_msg_num); + return ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + uint32_t vport = 0; + struct zxdh_pci_bar_msg in = {0}; + struct zxdh_msg_recviver_mem result = {0}; + uint32_t *recv_buffer = NULL; + uint8_t *reply_ptr = NULL; + uint16_t reply_msg_len = 0; + uint64_t agent_addr = 0; + + ret = zxdh_np_agent_bar_msg_check(dev_id, p_msg); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_bar_msg_check failed!"); + return ret; + } + + zxdh_np_dev_vport_get(dev_id, &vport); + zxdh_np_dev_agent_addr_get(dev_id, &agent_addr); + + if (ZXDH_IS_PF(vport)) + in.src = ZXDH_MSG_CHAN_END_PF; + else + in.src = ZXDH_MSG_CHAN_END_VF; + + in.virt_addr = agent_addr; + in.payload_addr = p_msg->msg; + in.payload_len = p_msg->msg_len; + in.dst = ZXDH_MSG_CHAN_END_RISC; + in.module_id = ZXDH_BAR_MDOULE_NPSDK; + + recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); + if (recv_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; + result.recv_buffer = recv_buffer; + + ret = zxdh_bar_chan_sync_msg_send(&in, &result); + if (ret == ZXDH_BAR_MSG_OK) { + reply_ptr = (uint8_t *)(result.recv_buffer); + if (*reply_ptr == 0XFF) { + reply_msg_len = *(uint16_t *)(reply_ptr + 1); + memcpy(p_data, reply_ptr + 4, + ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); + } else { + PMD_DRV_LOG(ERR, "Message not replied"); + } + } else { + PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret); + } + + rte_free(recv_buffer); + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_REG_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_msg); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_REG_MSG_T), + }; + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + ret = *p_data; + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed in buffer"); + return ZXDH_ERR; + } + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_pcie_bar_request(uint32_t dev_id, + uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t bar_msg_num = 0; + ZXDH_AGENT_PCIE_BAR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PCIE_BAR_MSG, + .oper = ZXDH_BAR_MSG_NUM_REQ, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_PCIE_BAR_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, rsp_buff, sizeof(rsp_buff)); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed!"); + return rc; + } + + msg_result = rsp_buff[0]; + bar_msg_num = rsp_buff[1]; + + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + *p_bar_msg_num = bar_msg_num; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_reg_read(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = 0; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_RD, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent read failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent read resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + +static uint32_t +zxdh_np_agent_channel_reg_write(uint32_t dev_id, + uint32_t reg_type, + uint32_t reg_no, + uint32_t reg_width, + uint32_t addr, + uint32_t *p_data) +{ + uint32_t ret = ZXDH_OK; + ZXDH_AGENT_CHANNEL_REG_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_REG_MSG, + .subtype = reg_type, + .oper = ZXDH_WR, + .reg_no = reg_no, + .addr = addr, + .val_len = reg_width / 4, + }; + + memcpy(msgcfg.val, p_data, reg_width); + + uint32_t resp_len = reg_width + 4; + uint8_t *resp_buffer = (uint8_t *)rte_zmalloc(NULL, resp_len, 0); + if (resp_buffer == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + ret = zxdh_np_agent_channel_reg_sync_send(dev_id, + &msgcfg, (uint32_t *)resp_buffer, resp_len); + + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d send agent write failed.", dev_id, reg_no); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + if (*((uint32_t *)resp_buffer) != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dev id %d reg_no %d agent write resp err %d .", + dev_id, reg_no, *((uint32_t *)resp_buffer)); + rte_free(resp_buffer); + return ZXDH_ERR; + } + + memcpy(p_data, resp_buffer + 4, reg_width); + + rte_free(resp_buffer); + + return ret; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1128,6 +1458,24 @@ zxdh_np_np_sdk_version_compatible_check(uint32_t dev_id) return ZXDH_OK; } +static uint32_t +zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) +{ + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_agent_channel_pcie_bar_request(dev_id, p_bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_pcie_bar_request"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + return rc; +} + static ZXDH_RISCV_DTB_MGR * zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) { @@ -1246,12 +1594,19 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); if (reg_module == DTB4K) { rc = p_reg_info->p_read_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); } if (!zxdh_np_comm_is_big_endian()) { @@ -1383,6 +1738,9 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, uint32_t i; uint32_t addr = 0; uint32_t reg_module = p_reg_info->module_no; + uint32_t reg_width = p_reg_info->width; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_real_no = p_reg_info->reg_no; for (i = 0; i < p_reg_info->field_num; i++) { if (p_field_info[i].len <= 32) { @@ -1417,6 +1775,10 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no, if (reg_module == DTB4K) { rc = p_reg_info->p_write_fun(dev_id, addr, p_buff); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun"); + } else { + rc = zxdh_np_agent_channel_reg_write(dev_id, + reg_type, reg_real_no, reg_width, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_write"); } return rc; @@ -1790,7 +2152,7 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t base_addr; uint32_t index; uint32_t opr_mode; - uint32_t rc; + uint32_t rc = ZXDH_OK; ZXDH_COMM_CHECK_POINT(pdata); ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); @@ -2687,6 +3049,7 @@ zxdh_np_host_init(uint32_t dev_id, ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0}; uint32_t rc; uint64_t agent_addr; + uint32_t bar_msg_num = 0; ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl); @@ -2708,6 +3071,11 @@ zxdh_np_host_init(uint32_t dev_id, rc = zxdh_np_np_sdk_version_compatible_check(dev_id); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_np_sdk_version_compatible_check"); + rc = zxdh_np_pcie_bar_msg_num_get(dev_id, &bar_msg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_pcie_bar_msg_num_get"); + + zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + return 0; } @@ -2942,59 +3310,7 @@ zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, } static uint32_t -zxdh_np_agent_channel_sync_send(ZXDH_AGENT_CHANNEL_MSG_T *p_msg, - uint32_t *p_data, - uint32_t rep_len) -{ - uint32_t ret = 0; - uint32_t vport = 0; - struct zxdh_pci_bar_msg in = {0}; - struct zxdh_msg_recviver_mem result = {0}; - uint32_t *recv_buffer; - uint8_t *reply_ptr = NULL; - uint16_t reply_msg_len = 0; - uint64_t agent_addr = 0; - - if (ZXDH_IS_PF(vport)) - in.src = ZXDH_MSG_CHAN_END_PF; - else - in.src = ZXDH_MSG_CHAN_END_VF; - - in.virt_addr = agent_addr; - in.payload_addr = p_msg->msg; - in.payload_len = p_msg->msg_len; - in.dst = ZXDH_MSG_CHAN_END_RISC; - in.module_id = ZXDH_BAR_MDOULE_NPSDK; - - recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0); - if (recv_buffer == NULL) { - PMD_DRV_LOG(ERR, "%s point null!", __func__); - return ZXDH_PAR_CHK_POINT_NULL; - } - - result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN; - result.recv_buffer = recv_buffer; - - ret = zxdh_bar_chan_sync_msg_send(&in, &result); - if (ret == ZXDH_BAR_MSG_OK) { - reply_ptr = (uint8_t *)(result.recv_buffer); - if (*reply_ptr == 0XFF) { - reply_msg_len = *(uint16_t *)(reply_ptr + 1); - memcpy(p_data, reply_ptr + 4, - ((reply_msg_len > rep_len) ? rep_len : reply_msg_len)); - } else { - PMD_DRV_LOG(ERR, "Message not replied"); - } - } else { - PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__); - } - - rte_free(recv_buffer); - return ret; -} - -static uint32_t -zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, +zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, uint32_t *p_data, uint32_t rep_len) { uint32_t ret = 0; @@ -3003,7 +3319,7 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, agent_msg.msg = (void *)p_msg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, p_data, rep_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__); return 1; @@ -3013,7 +3329,7 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport, uint32_t car_type, uint32_t *p_profileid) { uint32_t ret = 0; @@ -3028,7 +3344,7 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, msgcfg.car_type = car_type; msgcfg.profile_id = 0xFFFF; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); @@ -3041,7 +3357,8 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport, } static uint32_t -zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, +zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, + uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id __rte_unused, void *p_car_profile_cfg) @@ -3071,7 +3388,7 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgpktcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__); return 1; @@ -3105,7 +3422,7 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, agent_msg.msg = (void *)&msgcfg; agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PROFILE_MSG_T); - ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len); + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__); return 1; @@ -3118,7 +3435,7 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type, } static uint32_t -zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport, +zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport, uint32_t car_type __rte_unused, uint32_t profileid) { @@ -3133,7 +3450,7 @@ zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport, msgcfg.vport = vport; msgcfg.profile_id = profileid; - ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg, + ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); @@ -3234,7 +3551,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -3259,8 +3576,9 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, void *p_car_profile_cfg) { uint32_t ret = 0; + uint32_t dev_id = 0; - ret = zxdh_np_agent_channel_plcr_car_rate(car_type, + ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__); @@ -3276,10 +3594,11 @@ zxdh_np_car_profile_id_delete(uint32_t vport_id, { uint32_t ret = 0; uint32_t profileid = 0; + uint32_t dev_id = 0; profileid = profile_id & 0xFFFF; - ret = zxdh_np_agent_channel_plcr_profileid_release(vport_id, flags, profileid); + ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); if (ret != 0) { PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index d6ceecf3f8..c8fc8ea613 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -112,9 +112,17 @@ #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL \ (ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK) +#define ZXDH_CHANNEL_REPS_LEN (4) + #define ZXDH_NPSDK_COMPAT_ITEM_ID (10) #define ZXDH_DPU_NO_DEBUG_PF_COMPAT_REG_OFFSET (0x5400) +#define ZXDH_VF_ACTIVE(VPORT) (((VPORT) & 0x0800) >> 11) +#define ZXDH_EPID_BY(VPORT) (((VPORT) & 0x7000) >> 12) +#define ZXDH_FUNC_NUM(VPORT) (((VPORT) & 0x0700) >> 8) +#define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) +#define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -127,6 +135,12 @@ #define ZXDH_PAR_CHK_INVALID_DEV_ID (ZXDH_PARAMETER_CHK_BASE | 0x007) #define ZXDH_PAR_CHK_INVALID_PARA (ZXDH_PARAMETER_CHK_BASE | 0x008) +#define ZXDH_SPIN_LOCK_BASE (ZXDH_RC_BASE | 0x300) +#define ZXDH_SPIN_LOCK_INIT_FAIL (ZXDH_SPIN_LOCK_BASE | 0x001) +#define ZXDH_SPIN_LOCK_LOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0x002) +#define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) +#define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -164,6 +178,13 @@ #define ZXDH_RC_DTB_SEARCH_VPORT_QUEUE_ZERO (ZXDH_RC_DTB_BASE | 0x17) #define ZXDH_RC_DTB_QUEUE_NOT_ENABLE (ZXDH_RC_DTB_BASE | 0x18) +#define ZXDH_RC_CTRLCH_BASE (0xf00) +#define ZXDH_RC_CTRLCH_MSG_LEN_ZERO (ZXDH_RC_CTRLCH_BASE | 0x0) +#define ZXDH_RC_CTRLCH_MSG_PRO_ERR (ZXDH_RC_CTRLCH_BASE | 0x1) +#define ZXDH_RC_CTRLCH_MSG_TYPE_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x2) +#define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) +#define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -380,6 +401,7 @@ typedef struct dpp_dev_cfg_t { uint32_t access_type; uint32_t agent_flag; uint32_t vport; + uint32_t fw_bar_msg_num; uint64_t pcie_addr; uint64_t riscv_addr; uint64_t dma_vir_addr; @@ -388,6 +410,8 @@ typedef struct dpp_dev_cfg_t { uint32_t init_flags[ZXDH_MODULE_INIT_MAX]; ZXDH_DEV_WRITE_FUNC p_pcie_write_fun; ZXDH_DEV_READ_FUNC p_pcie_read_fun; + ZXDH_SPINLOCK_T dtb_spinlock; + ZXDH_SPINLOCK_T smmu0_spinlock; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -662,6 +686,17 @@ typedef enum zxdh_stat_cnt_mode_e { ZXDH_STAT_MAX_MODE, } ZXDH_STAT_CNT_MODE_E; +typedef enum zxdh_agent_pcie_bar_e { + ZXDH_BAR_MSG_NUM_REQ = 0, + ZXDH_PCIE_BAR_MAX +} ZXDH_MSG_PCIE_BAR_E; + +typedef enum zxdh_agent_msg_oper_e { + ZXDH_WR = 0, + ZXDH_RD, + ZXDH_WR_RD_MAX +} ZXDH_MSG_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -776,11 +811,6 @@ typedef struct dpp_agent_car_pkt_profile_msg { uint32_t pri[ZXDH_CAR_PRI_MAX]; } ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T; -typedef struct zxdh_agent_channel_msg_t { - uint32_t msg_len; - void *msg; -} ZXDH_AGENT_CHANNEL_MSG_T; - typedef struct zxdh_agent_channel_plcr_msg { uint8_t dev_id; uint8_t type; @@ -858,6 +888,29 @@ typedef struct __rte_aligned(2) zxdh_version_compatible_reg_t { uint8_t rsv[2]; } ZXDH_VERSION_COMPATIBLE_REG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_pcie_bar_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; +} ZXDH_AGENT_PCIE_BAR_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_reg_msg { + uint8_t dev_id; + uint8_t type; + uint8_t subtype; + uint8_t oper; + uint32_t reg_no; + uint32_t addr; + uint32_t val_len; + uint32_t val[32]; +} ZXDH_AGENT_CHANNEL_REG_MSG_T; + +typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { + uint32_t msg_len; + void *msg; +} ZXDH_AGENT_CHANNEL_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 55065 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 04/14] net/zxdh: modify dtb queue ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (2 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 03/14] net/zxdh: add agent channel Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 05/14] net/zxdh: add tables dump address ops Bingbin Chen ` (9 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 26049 bytes --] Modify the implementation of the dtb queue request and release interfaces, and add the implementation of queue initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 494 +++++++++++++++++++++++++++++-------- drivers/net/zxdh/zxdh_np.h | 97 ++++++++ 2 files changed, 483 insertions(+), 108 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 8113332310..0763dd3310 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -17,16 +17,15 @@ static ZXDH_DEV_MGR_T g_dev_mgr; static ZXDH_SDT_MGR_T g_sdt_mgr; -static uint32_t g_dpp_dtb_int_enable; static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; -static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; +static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -458,6 +457,25 @@ zxdh_np_dev_opr_spinlock_get(uint32_t dev_id, uint32_t type, ZXDH_SPINLOCK_T **p return ZXDH_OK; } +static uint32_t +zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, + uint32_t index, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + switch (type) { + case ZXDH_DEV_SPINLOCK_T_DTB: + *p_spinlock_out = &p_dev_info->dtb_queue_spinlock[index]; + break; + default: + PMD_DRV_LOG(ERR, "spinlock type is invalid!"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -857,6 +875,7 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, { ZXDH_DEV_CFG_T *p_dev_info = NULL; ZXDH_DEV_MGR_T *p_dev_mgr = NULL; + uint32_t i = 0; p_dev_mgr = &g_dev_mgr; if (!p_dev_mgr->is_init) { @@ -892,7 +911,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); - rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) + rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); return 0; } @@ -1248,6 +1269,89 @@ zxdh_np_agent_channel_reg_write(uint32_t dev_id, return ret; } +static uint32_t +zxdh_np_agent_channel_dtb_sync_send(uint32_t dev_id, + ZXDH_AGENT_CHANNEL_DTB_MSG_T *p_msg, + uint32_t *p_data, + uint32_t rep_len) +{ + uint32_t ret = ZXDH_OK; + + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; + agent_msg.msg = (void *)p_msg; + agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_DTB_MSG_T); + + ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); + if (ret != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_agent_channel_sync_send failed"); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_request(uint32_t dev_id, + char p_name[32], + uint32_t vport_info, + uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t rsp_buff[2] = {0}; + uint32_t msg_result = 0; + uint32_t queue_id = 0; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_REQUEST, + .vport = vport_info, + }; + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + PMD_DRV_LOG(DEBUG, "msgcfg.name=%s", msgcfg.name); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + queue_id = rsp_buff[1]; + + PMD_DRV_LOG(DEBUG, "dev_id: %d, msg_result: %d", dev_id, msg_result); + PMD_DRV_LOG(DEBUG, "dev_id: %d, queue_id: %d", dev_id, queue_id); + + *p_queue_id = queue_id; + + return msg_result; +} + +static uint32_t +zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, + char p_name[32], + __rte_unused uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + uint32_t rsp_buff[2] = {0}; + ZXDH_AGENT_CHANNEL_DTB_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_DTB_MSG, + .oper = ZXDH_QUEUE_RELEASE, + .queue_id = queue_id, + }; + + memcpy(msgcfg.name, p_name, strnlen(p_name, ZXDH_PORT_NAME_MAX)); + + rc = zxdh_np_agent_channel_dtb_sync_send(dev_id, &msgcfg, rsp_buff, sizeof(rsp_buff)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_dtb_sync_send"); + + msg_result = rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: %d", msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -1476,48 +1580,6 @@ zxdh_np_pcie_bar_msg_num_get(uint32_t dev_id, uint32_t *p_bar_msg_num) return rc; } -static ZXDH_RISCV_DTB_MGR * -zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id) -{ - if (dev_id >= ZXDH_DEV_CHANNEL_MAX) - return NULL; - else - return p_riscv_dtb_queue_mgr[dev_id]; -} - -static uint32_t -zxdh_np_riscv_dtb_mgr_queue_info_delete(uint32_t dev_id, uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - p_riscv_dtb_mgr->queue_alloc_count--; - p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag = 0; - p_riscv_dtb_mgr->queue_user_info[queue_id].queue_id = 0xFF; - p_riscv_dtb_mgr->queue_user_info[queue_id].vport = 0; - memset(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, 0, ZXDH_PORT_NAME_MAX); - - return 0; -} - -static uint32_t -zxdh_np_dev_get_dev_type(uint32_t dev_id) -{ - ZXDH_DEV_MGR_T *p_dev_mgr = NULL; - ZXDH_DEV_CFG_T *p_dev_info = NULL; - - p_dev_mgr = &g_dev_mgr; - p_dev_info = p_dev_mgr->p_dev_array[dev_id]; - - if (p_dev_info == NULL) - return 0xffff; - - return p_dev_info->dev_type; -} - static uint32_t zxdh_np_comm_read_bits(uint8_t *p_base, uint32_t base_size_bit, uint32_t *p_data, uint32_t start_bit, uint32_t end_bit) @@ -1807,52 +1869,6 @@ zxdh_np_dtb_queue_vm_info_set(uint32_t dev_id, return rc; } -static uint32_t -zxdh_np_dtb_queue_enable_set(uint32_t dev_id, - uint32_t queue_id, - uint32_t enable) -{ - ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; - uint32_t rc; - - rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_get"); - - vm_info.queue_en = enable; - rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_vm_info_set"); - - return rc; -} - -static uint32_t -zxdh_np_riscv_dpp_dtb_queue_id_release(uint32_t dev_id, - char name[ZXDH_PORT_NAME_MAX], uint32_t queue_id) -{ - ZXDH_RISCV_DTB_MGR *p_riscv_dtb_mgr = NULL; - - p_riscv_dtb_mgr = zxdh_np_riscv_dtb_queue_mgr_get(dev_id); - if (p_riscv_dtb_mgr == NULL) - return 1; - - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - - if (p_riscv_dtb_mgr->queue_user_info[queue_id].alloc_flag != 1) { - PMD_DRV_LOG(ERR, "queue %d not alloc!", queue_id); - return 2; - } - - if (strcmp(p_riscv_dtb_mgr->queue_user_info[queue_id].user_name, name) != 0) { - PMD_DRV_LOG(ERR, "queue %d name %s error!", queue_id, name); - return 3; - } - zxdh_np_dtb_queue_enable_set(dev_id, queue_id, 0); - zxdh_np_riscv_dtb_mgr_queue_info_delete(dev_id, queue_id); - - return 0; -} - static uint32_t zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id, uint32_t queue_id, @@ -1887,20 +1903,74 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], + uint16_t vport, uint32_t *p_queue_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t queue_id = 0xFF; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + uint32_t vport_info = (uint32_t)vport; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_request(dev_id, p_name, vport_info, &queue_id); + if (rc == ZXDH_RC_DTB_QUEUE_RES_EMPTY) { + PMD_DRV_LOG(ERR, "dtb queue is locked full."); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_RES_EMPTY; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + + *p_queue_id = queue_id; + + PMD_DRV_LOG(INFO, "dev_id %d vport 0x%x name %s queue_id %d done.", + dev_id, vport_info, p_name, queue_id); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_release(uint32_t devid, char pname[32], uint32_t queueid) { - uint32_t rc; + uint32_t rc = ZXDH_OK; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(devid, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + rc = zxdh_np_agent_channel_dtb_queue_release(devid, pname, queueid); + + if (rc == ZXDH_RC_DTB_QUEUE_NOT_ALLOC) { + PMD_DRV_LOG(ERR, "dtb queue id %d not request.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NOT_ALLOC; + } - ZXDH_COMM_CHECK_DEV_POINT(devid, pname); + if (rc == ZXDH_RC_DTB_QUEUE_NAME_ERROR) { + PMD_DRV_LOG(ERR, "dtb queue %d name error.", queueid); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_RC_DTB_QUEUE_NAME_ERROR; + } - rc = zxdh_np_riscv_dpp_dtb_queue_id_release(devid, pname, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_riscv_dpp_dtb_queue_id_release"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); rc = zxdh_np_dtb_queue_id_free(devid, queueid); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_dtb_queue_id_free"); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); + + PMD_DRV_LOG(INFO, "queueid %d", queueid); return rc; } @@ -2352,24 +2422,34 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, uint32_t item_index; uint32_t i; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (data_len % 4 != 0) + if (data_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(dev_id, queue_id) % @@ -2384,8 +2464,10 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } rc = zxdh_np_dtb_item_buff_wr(dev_id, queue_id, 0, item_index, 0, data_len, p_data); @@ -2405,6 +2487,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id, rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2418,8 +2502,6 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, uint32_t rc = 0; uint32_t dtb_interrupt_status = 0; - dtb_interrupt_status = g_dpp_dtb_int_enable; - rc = zxdh_np_dtb_tab_down_info_set(dev_id, queue_id, dtb_interrupt_status, @@ -2748,20 +2830,28 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, ZXDH_DTB_QUEUE_ITEM_INFO_T item_info = {0}; uint32_t queue_en = 0; uint32_t rc; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en); if (!queue_en) { PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_NOT_ENABLE; } if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } - if (desc_len % 4 != 0) + if (desc_len % 4 != 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_PARA_INVALID; + } zxdh_np_dtb_item_buff_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, desc_len, p_desc_data); @@ -2773,11 +2863,10 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, item_info.int_en = int_flag; item_info.data_len = desc_len / 4; - if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) - return 0; - rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info); + rte_spinlock_unlock(&p_spinlock->spinlock); + return rc; } @@ -2820,16 +2909,23 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, uint32_t item_index = 0; uint32_t unused_item_num = 0; uint32_t i; + ZXDH_SPINLOCK_T *p_spinlock = NULL; + + zxdh_np_dev_dtb_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_DTB, queue_id, &p_spinlock); + rte_spinlock_lock(&p_spinlock->spinlock); if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; } zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &unused_item_num); - if (unused_item_num == 0) + if (unused_item_num == 0) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_HW_EMPTY; + } for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { item_index = ZXDH_DTB_TAB_UP_WR_INDEX_GET(dev_id, queue_id) % @@ -2844,14 +2940,17 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, break; } - if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + if (i == ZXDH_DTB_QUEUE_ITEM_NUM_MAX) { + rte_spinlock_unlock(&p_spinlock->spinlock); return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, item_index, 0, ZXDH_DTB_TAB_ACK_IS_USING_MASK); *p_item_index = item_index; + rte_spinlock_unlock(&p_spinlock->spinlock); return 0; } @@ -3042,6 +3141,181 @@ zxdh_np_dtb_stats_get(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_queue_down_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_down_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_down_item_size = (p_queue_cfg->down_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->down_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_down.item_size = tab_down_item_size; + p_dtb_mgr->queue_info[queue_id].tab_down.start_phy_addr = p_queue_cfg->down_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.start_vir_addr = p_queue_cfg->down_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_down.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_down.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_DOWN_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] down init failed!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->down_start_vir_addr), 0, + tab_down_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] down init success!!!", queue_id); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_queue_dump_init(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_QUEUE_CFG_T *p_queue_cfg) +{ + uint32_t i = 0; + uint32_t ack_vale = 0; + uint32_t tab_up_item_size = 0; + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + p_dtb_mgr->queue_info[queue_id].init_flag = 1; + + tab_up_item_size = (p_queue_cfg->up_item_size == 0) ? + ZXDH_DTB_ITEM_SIZE : p_queue_cfg->up_item_size; + + p_dtb_mgr->queue_info[queue_id].tab_up.item_size = tab_up_item_size; + p_dtb_mgr->queue_info[queue_id].tab_up.start_phy_addr = p_queue_cfg->up_start_phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.start_vir_addr = p_queue_cfg->up_start_vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.wr_index = 0; + p_dtb_mgr->queue_info[queue_id].tab_up.rd_index = 0; + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_wr(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, ZXDH_DTB_TAB_ACK_CHECK_VALUE); + } + + for (i = 0; i < ZXDH_DTB_QUEUE_ITEM_NUM_MAX; i++) { + zxdh_np_dtb_item_ack_rd(dev_id, queue_id, + ZXDH_DTB_DIR_UP_TYPE, i, 0, &ack_vale); + if (ack_vale != ZXDH_DTB_TAB_ACK_CHECK_VALUE) { + PMD_DRV_LOG(ERR, "dtb queue [%d] dump init failed!!!", queue_id); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + } + + memset((uint8_t *)(p_queue_cfg->up_start_vir_addr), 0, + tab_up_item_size * ZXDH_DTB_QUEUE_ITEM_NUM_MAX); + + PMD_DRV_LOG(INFO, "dtb queue [%d] up init success!!!", queue_id); + + return ZXDH_OK; +} + +static void +zxdh_np_dtb_down_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T down_queue_cfg = { + .down_start_phy_addr = phy_addr, + .down_start_vir_addr = vir_addr, + .down_item_size = size, + }; + + zxdh_np_dtb_queue_down_init(dev_id, channel_id, &down_queue_cfg); +} + +static void +zxdh_np_dtb_dump_channel_addr_set(uint32_t dev_id, + uint32_t channel_id, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + ZXDH_DTB_QUEUE_CFG_T dump_queue_cfg = { + .up_start_phy_addr = phy_addr, + .up_start_vir_addr = vir_addr, + .up_item_size = size, + }; + + zxdh_np_dtb_queue_dump_init(dev_id, channel_id, &dump_queue_cfg); +} + +static uint32_t +zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, uint32_t vector) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_QUEUE_VM_INFO_T vm_info = {0}; + ZXDH_DTB_MGR_T *p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + + rc = zxdh_np_dtb_queue_vm_info_get(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_get"); + + vm_info.dbi_en = 1; + vm_info.epid = hardware_ep_id[ZXDH_EPID_BY(vport)]; + vm_info.vfunc_num = ZXDH_VFUNC_NUM(vport); + vm_info.func_num = ZXDH_FUNC_NUM(vport); + vm_info.vfunc_active = ZXDH_VF_ACTIVE(vport); + vm_info.vector = vector; + + p_dtb_mgr->queue_info[queue_id].vport = vport; + p_dtb_mgr->queue_info[queue_id].vector = vector; + + rc = zxdh_np_dtb_queue_vm_info_set(dev_id, queue_id, &vm_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_vm_info_set"); + + return rc; +} + +static uint32_t +zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) +{ + uint32_t rc = ZXDH_OK; + + uint32_t queue_id = 0; + + rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, + p_dev_init_ctrl->vport, &queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_queue_request"); + + p_dev_init_ctrl->queue_id = queue_id; + + rc = zxdh_np_dtb_user_info_set(dev_id, queue_id, + p_dev_init_ctrl->vport, p_dev_init_ctrl->vector); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_user_info_set"); + + zxdh_np_dtb_down_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->down_phy_addr, p_dev_init_ctrl->down_vir_addr, 0); + + zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, + p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + + return ZXDH_OK; +} + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) @@ -3076,6 +3350,10 @@ zxdh_np_host_init(uint32_t dev_id, zxdh_np_dev_fw_bar_msg_num_set(dev_id, bar_msg_num); + rc = zxdh_np_apt_dtb_res_init(dev_id, p_dev_init_ctrl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_dtb_res_init"); + PMD_DRV_LOG(INFO, "host init done, queue_id = %u", p_dev_init_ctrl->queue_id); + return 0; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index c8fc8ea613..5b187b97fb 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -412,6 +412,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_DEV_READ_FUNC p_pcie_read_fun; ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; + ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -600,6 +601,78 @@ typedef struct zxdh_dtb_eram_table_form_t { uint32_t data_l; } ZXDH_DTB_ERAM_TABLE_FORM_T; +typedef struct zxdh_dtb_zcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t ram_reg_flag; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t zcell_id; + uint32_t mask; + uint32_t sram_addr; +} ZXDH_DTB_ZCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_etcam_table_form_t { + uint32_t valid; + uint32_t type_mode; + uint32_t block_sel; + uint32_t init_en; + uint32_t row_or_col_msk; + uint32_t vben; + uint32_t reg_tcam_flag; + uint32_t uload; + uint32_t rd_wr; + uint32_t wr_mode; + uint32_t data_or_mask; + uint32_t addr; + uint32_t vbit; +} ZXDH_DTB_ETCAM_TABLE_FORM_T; + +typedef struct zxdh_dtb_eram_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t base_addr; + uint32_t tb_depth; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ERAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_zcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t zgroup_id; + uint32_t zblock_id; + uint32_t ram_reg_flag; + uint32_t z_reg_cell_id; + uint32_t sram_addr; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ZCAM_DUMP_FORM_T; + +typedef struct zxdh_dtb_etcam_dump_form_t { + uint32_t valid; + uint32_t up_type; + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; + uint32_t tb_dst_addr_h; + uint32_t tb_dst_addr_l; +} ZXDH_DTB_ETCAM_DUMP_FORM_T; + +typedef struct zxdh_etcam_dump_info_t { + uint32_t block_sel; + uint32_t addr; + uint32_t rd_mode; + uint32_t data_or_mask; + uint32_t tb_depth; + uint32_t tb_width; +} ZXDH_ETCAM_DUMP_INFO_T; + typedef struct zxdh_sdt_tbl_eram_t { uint32_t table_type; uint32_t eram_mode; @@ -626,6 +699,15 @@ typedef struct zxdh_dtb_table_t { ZXDH_DTB_FIELD_T *p_fields; } ZXDH_DTB_TABLE_T; +typedef struct zxdh_dtb_queue_cfg_t { + uint64_t up_start_phy_addr; + uint64_t up_start_vir_addr; + uint64_t down_start_phy_addr; + uint64_t down_start_vir_addr; + uint32_t up_item_size; + uint32_t down_item_size; +} ZXDH_DTB_QUEUE_CFG_T; + typedef struct zxdh_dtb_queue_item_info_t { uint32_t cmd_vld; uint32_t cmd_type; @@ -697,6 +779,11 @@ typedef enum zxdh_agent_msg_oper_e { ZXDH_WR_RD_MAX } ZXDH_MSG_OPER_E; +typedef enum zxdh_msg_dtb_oper_e { + ZXDH_QUEUE_REQUEST = 0, + ZXDH_QUEUE_RELEASE = 1, +} ZXDH_MSG_DTB_OPER_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -911,6 +998,16 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t { void *msg; } ZXDH_AGENT_CHANNEL_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t oper; + uint8_t rsv; + char name[32]; + uint32_t vport; + uint32_t queue_id; +} ZXDH_AGENT_CHANNEL_DTB_MSG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 56083 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 05/14] net/zxdh: add tables dump address ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (3 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 04/14] net/zxdh: modify dtb queue ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 06/14] net/zxdh: add eram tables ops Bingbin Chen ` (8 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 40387 bytes --] Configure the storage address for the dtb queue to save tables contents. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 1144 ++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 91 +++ 2 files changed, 1235 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 0763dd3310..09aa38958c 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -26,6 +26,7 @@ static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; +static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -297,6 +298,58 @@ zxdh_np_comm_convert32(uint32_t dw_data) #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID) \ (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag) +#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr) + +#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL) \ + (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ + VAL) + +static inline void +zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) +{ + ptr->data = pdata; + ptr->prev = NULL; + ptr->next = NULL; +} + +static inline void +zxdh_np_init_rbt_tn(ZXDH_RB_TN *p_tn, void *p_newkey) +{ + p_tn->p_key = p_newkey; + p_tn->color_lsv = 0; + p_tn->p_left = NULL; + p_tn->p_right = NULL; + p_tn->p_parent = NULL; + zxdh_np_init_d_node(&p_tn->tn_ln, p_tn); +} + +static inline uint32_t +zxdh_np_get_tn_lsv(ZXDH_RB_TN *p_tn) +{ + return p_tn->color_lsv >> 2; +} + +static inline void +zxdh_np_set_tn_lsv(ZXDH_RB_TN *p_tn, uint32_t list_val) +{ + p_tn->color_lsv &= 0x3; + p_tn->color_lsv |= (list_val << 2); +} + +static inline void +zxdh_np_set_tn_color(ZXDH_RB_TN *p_tn, uint32_t color) +{ + p_tn->color_lsv &= 0xfffffffc; + p_tn->color_lsv |= (color & 0x3); +} + +static inline uint32_t +zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) +{ + return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); +} + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -379,6 +432,945 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) } } +static uint32_t +zxdh_comm_double_link_init(uint32_t elmemtnum, ZXDH_D_HEAD *p_head) +{ + uint32_t err_code = 0; + + if (elmemtnum == 0) { + err_code = ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR; + PMD_DRV_LOG(ERR, "Error:[0x%x] doule_link_init Element Num Err !", + err_code); + return err_code; + } + + p_head->maxnum = elmemtnum; + p_head->used = 0; + p_head->p_next = NULL; + p_head->p_prev = NULL; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_create(uint32_t element_num, ZXDH_LISTSTACK_MANAGER **p_list) +{ + ZXDH_LISTSTACK_MANAGER *p_local_list = NULL; + uint32_t dw_list_size = 0; + uint32_t dw_manage_size = 0; + uint32_t dw_actual_element_num = 0; + uint32_t i = 0; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " p_list is NULL!"); + return ZXDH_LIST_STACK_POINT_NULL; + } + if (element_num <= 0) { + *p_list = NULL; + PMD_DRV_LOG(INFO, " FtmComm_ListStackCreat_dwElementNum <=0"); + return ZXDH_LIST_STACK_ELEMENT_NUM_ERR; + } + + if (element_num > ZXDH_LISTSTACK_MAX_ELEMENT - 1) + dw_actual_element_num = ZXDH_LISTSTACK_MAX_ELEMENT; + else + dw_actual_element_num = element_num + 1; + + dw_list_size = (dw_actual_element_num * sizeof(ZXDH_COMM_FREELINK)) & 0xffffffff; + dw_manage_size = ((sizeof(ZXDH_LISTSTACK_MANAGER) & 0xFFFFFFFFU) + dw_list_size) & + 0xffffffff; + + p_local_list = (ZXDH_LISTSTACK_MANAGER *)rte_zmalloc(NULL, dw_manage_size, 0); + if (p_local_list == NULL) { + *p_list = NULL; + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL; + } + + p_local_list->p_array = (ZXDH_COMM_FREELINK *)((uint8_t *)p_local_list + + sizeof(ZXDH_LISTSTACK_MANAGER)); + + p_local_list->capacity = dw_actual_element_num; + p_local_list->free_num = dw_actual_element_num - 1; + p_local_list->used_num = 0; + + for (i = 1; i < (dw_actual_element_num - 1); i++) { + p_local_list->p_array[i].index = i; + p_local_list->p_array[i].next = i + 1; + } + + p_local_list->p_array[0].index = 0; + p_local_list->p_array[0].next = 0; + + p_local_list->p_array[dw_actual_element_num - 1].index = dw_actual_element_num - 1; + p_local_list->p_array[dw_actual_element_num - 1].next = 0xffffffff; + + p_local_list->p_head = p_local_list->p_array[1].index; + + *p_list = p_local_list; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_comm_liststack_alloc(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t *p_index) +{ + uint32_t dw_alloc_index = 0; + uint32_t dw_next_free = 0; + + if (p_list == NULL) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (p_list->p_head == ZXDH_LISTSTACK_INVALID_INDEX) { + *p_index = ZXDH_LISTSTACK_INVALID_INDEX; + return ZXDH_LIST_STACK_ISEMPTY_ERR; + } + + dw_alloc_index = p_list->p_head; + + dw_next_free = p_list->p_array[dw_alloc_index].next; + p_list->p_array[dw_alloc_index].next = ZXDH_LISTSTACK_INVALID_INDEX; + + if (dw_next_free != 0xffffffff) + p_list->p_head = p_list->p_array[dw_next_free].index; + else + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + *p_index = dw_alloc_index - 1; + + p_list->free_num--; + p_list->used_num++; + + if (p_list->free_num == 0 || (p_list->used_num == (p_list->capacity - 1))) + p_list->p_head = ZXDH_LISTSTACK_INVALID_INDEX; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_free(ZXDH_LISTSTACK_MANAGER *p_list, uint32_t index) +{ + uint32_t dw_free_index = 0; + uint32_t dw_prev_free = 0; + uint32_t dw_index = 0; + + dw_index = index + 1; + + if (p_list == NULL) { + PMD_DRV_LOG(INFO, " p_list is null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + + if (dw_index >= p_list->capacity) { + PMD_DRV_LOG(INFO, "dw_index is invalid"); + return ZXDH_LIST_STACK_FREE_INDEX_INVALID; + } + + if (p_list->p_array[dw_index].next != ZXDH_LISTSTACK_INVALID_INDEX) + return ZXDH_OK; + + dw_free_index = dw_index; + dw_prev_free = p_list->p_head; + + if (dw_prev_free != 0) + p_list->p_array[dw_free_index].next = p_list->p_array[dw_prev_free].index; + else + p_list->p_array[dw_free_index].next = 0xffffffff; + + p_list->p_head = p_list->p_array[dw_free_index].index; + + p_list->free_num++; + p_list->used_num--; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_1st(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_head->p_next; + p_newnode->prev = NULL; + + if (p_head->p_next) + p_head->p_next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_head->p_next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_aft(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, + ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode->next; + p_newnode->prev = p_oldnode; + + if (p_oldnode->next) + p_oldnode->next->prev = p_newnode; + else + p_head->p_prev = p_newnode; + + p_oldnode->next = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, + ZXDH_D_NODE *p_oldnode, ZXDH_D_HEAD *p_head) +{ + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_newnode->next = p_oldnode; + p_newnode->prev = p_oldnode->prev; + + if (p_oldnode->prev) + p_oldnode->prev->next = p_newnode; + else + p_head->p_next = p_newnode; + + p_oldnode->prev = p_newnode; + p_head->used++; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *next = NULL; + ZXDH_D_NODE *pre = NULL; + + next = delnode->next; + pre = delnode->prev; + + if (next) + next->prev = delnode->prev; + else + p_head->p_prev = delnode->prev; + + if (pre) + pre->next = delnode->next; + else + p_head->p_next = delnode->next; + + p_head->used--; + delnode->next = NULL; + delnode->prev = NULL; + return ZXDH_OK; +} + +static int32_t +zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) +{ + return memcmp(p_new, p_old, key_size); +} + +static void +zxdh_comm_rb_switch_color(ZXDH_RB_TN *p_tn1, ZXDH_RB_TN *p_tn2) +{ + uint32_t color1, color2; + + color1 = zxdh_np_get_tn_color(p_tn1); + color2 = zxdh_np_get_tn_color(p_tn2); + + zxdh_np_set_tn_color(p_tn1, color2); + zxdh_np_set_tn_color(p_tn2, color1); +} + +static ZXDH_RB_TN * +zxdh_comm_rb_get_brotn(ZXDH_RB_TN *p_cur_tn) +{ + return (p_cur_tn->p_parent->p_left == p_cur_tn) ? p_cur_tn->p_parent->p_right : + p_cur_tn->p_parent->p_left; +} + +static uint32_t +zxdh_comm_rb_handle_ins(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_tmp_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + + while (stack_top > 0) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn->p_parent) { + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + break; + } else if (zxdh_np_get_tn_color(p_cur_tn->p_parent) == ZXDH_RBT_RED) { + ZXDH_RB_TN *p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn->p_parent); + + RTE_ASSERT(p_cur_tn->p_parent == *stack_tn[stack_top - 1]); + + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + RTE_ASSERT(p_unc_tn); + zxdh_np_set_tn_color(p_cur_tn->p_parent, ZXDH_RBT_BLACK); + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_BLACK); + + RTE_ASSERT(p_cur_tn->p_parent->p_parent == + *stack_tn[stack_top - 2]); + + zxdh_np_set_tn_color(p_cur_tn->p_parent->p_parent, ZXDH_RBT_RED); + stack_top -= 2; + } else { + ZXDH_RB_TN *p_bro_tn = NULL; + + pp_tmp_tn = stack_tn[stack_top - 2]; + p_tmp_tn = *pp_tmp_tn; + + if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_left) { + *pp_tmp_tn = p_cur_tn->p_parent; + + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_left = p_bro_tn; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_right = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_left && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn; + + p_cur_tn->p_parent->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_tmp_tn; + + p_cur_tn->p_left = p_cur_tn->p_parent; + p_cur_tn->p_right = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else if (p_cur_tn->p_parent == p_tmp_tn->p_right && p_cur_tn == + p_cur_tn->p_parent->p_right) { + *pp_tmp_tn = p_cur_tn->p_parent; + p_bro_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + + p_cur_tn->p_parent->p_parent = p_tmp_tn->p_parent; + + p_tmp_tn->p_right = p_cur_tn->p_parent->p_left; + p_tmp_tn->p_parent = p_cur_tn->p_parent; + p_cur_tn->p_parent->p_left = p_tmp_tn; + + if (p_bro_tn) + p_bro_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } else { + *pp_tmp_tn = p_cur_tn; + p_cur_tn->p_parent->p_left = p_cur_tn->p_right; + + if (p_cur_tn->p_right) + p_cur_tn->p_right->p_parent = p_cur_tn->p_parent; + + p_cur_tn->p_parent->p_parent = p_cur_tn; + p_tmp_tn->p_right = p_cur_tn->p_left; + + if (p_cur_tn->p_left) + p_cur_tn->p_left->p_parent = p_tmp_tn; + + p_cur_tn->p_right = p_cur_tn->p_parent; + p_cur_tn->p_left = p_tmp_tn; + + p_cur_tn->p_parent = p_tmp_tn->p_parent; + p_tmp_tn->p_parent = p_cur_tn; + + zxdh_comm_rb_switch_color(*pp_tmp_tn, p_tmp_tn); + } + break; + } + } else { + break; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_init(ZXDH_RB_CFG *p_rb_cfg, + uint32_t total_num, + uint32_t key_size, + ZXDH_RB_CMPFUN cmpfun) +{ + uint32_t rtn = ZXDH_OK; + uint32_t malloc_size = 0; + + if (p_rb_cfg->is_init) { + PMD_DRV_LOG(ERR, " p_rb_cfg already init!"); + return ZXDH_OK; + } + + p_rb_cfg->key_size = key_size; + p_rb_cfg->p_root = NULL; + + if (cmpfun) + p_rb_cfg->p_cmpfun = cmpfun; + else + p_rb_cfg->p_cmpfun = zxdh_comm_rb_def_cmp; + + if (total_num) { + p_rb_cfg->is_dynamic = 0; + + rtn = zxdh_comm_double_link_init(total_num, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + + rtn = zxdh_np_comm_liststack_create(total_num, &p_rb_cfg->p_lsm); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_create"); + + p_rb_cfg->p_keybase = (uint8_t *)rte_zmalloc(NULL, + total_num * p_rb_cfg->key_size, 0); + if (p_rb_cfg->p_keybase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + malloc_size = ((sizeof(ZXDH_RB_TN) & 0xFFFFFFFFU) * total_num) & UINT32_MAX; + + p_rb_cfg->p_tnbase = (ZXDH_RB_TN *)rte_zmalloc(NULL, malloc_size, 0); + if (p_rb_cfg->p_tnbase == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } else { + p_rb_cfg->is_dynamic = 1; + + rtn = zxdh_comm_double_link_init(0xFFFFFFFF, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_init"); + } + p_rb_cfg->is_init = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t lsm_out = 0; + + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_pre_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_ins_tn = p_key; + + p_cur_key = p_rb_cfg->is_dynamic ? ((ZXDH_RB_TN *)p_key)->p_key : p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) { + if (p_rb_cfg->is_dynamic == 0) { + rtn = zxdh_np_comm_liststack_alloc(p_rb_cfg->p_lsm, &lsm_out); + + if (rtn == ZXDH_LIST_STACK_ISEMPTY_ERR) + return ZXDH_RBT_RC_FULL; + + ZXDH_COMM_CHECK_RC(rtn, "zxdh_np_comm_liststack_alloc"); + + p_ins_tn = p_rb_cfg->p_tnbase + lsm_out; + + zxdh_np_init_rbt_tn(p_ins_tn, p_rb_cfg->key_size * lsm_out + + p_rb_cfg->p_keybase); + + memcpy(p_ins_tn->p_key, p_key, p_rb_cfg->key_size); + + zxdh_np_set_tn_lsv(p_ins_tn, lsm_out); + + if (out_val) + *((uint32_t *)out_val) = lsm_out; + } else { + zxdh_np_init_d_node(&p_ins_tn->tn_ln, p_ins_tn); + } + + zxdh_np_set_tn_color(p_ins_tn, ZXDH_RBT_RED); + + if (cmprtn < 0) { + rtn = zxdh_comm_double_link_insert_pre(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_pre"); + } else if (cmprtn > 0) { + rtn = zxdh_comm_double_link_insert_aft(&p_ins_tn->tn_ln, + &p_pre_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_aft"); + } else { + RTE_ASSERT(!p_pre_tn); + + rtn = zxdh_comm_double_link_insert_1st(&p_ins_tn->tn_ln, + &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_insert_1st"); + } + + break; + } + + stack_tn[stack_top++] = pp_cur_tn; + p_pre_tn = p_cur_tn; + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(INFO, "info , rb_key is same"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_cur_tn; + } else { + if (out_val) + *((uint32_t *)out_val) = zxdh_np_get_tn_lsv(p_cur_tn); + } + + return ZXDH_RBT_RC_UPDATE; + } + } + + p_ins_tn->p_parent = (stack_top > 1) ? *stack_tn[stack_top - 1] : NULL; + stack_tn[stack_top] = pp_cur_tn; + + *pp_cur_tn = p_ins_tn; + + rtn = zxdh_comm_rb_handle_ins(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_ins"); + + if (p_rb_cfg->is_dynamic) { + if (out_val) + *((ZXDH_RB_TN **)out_val) = p_ins_tn; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, + ZXDH_RB_TN ***stack_tn, + uint32_t stack_top) +{ + ZXDH_RB_TN **pp_cur_tn = NULL; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN *p_tmp_tn = NULL; + ZXDH_RB_TN *p_unc_tn = NULL; + ZXDH_RB_TN *p_par_tn = NULL; + + while (stack_top > 1) { + pp_cur_tn = stack_tn[stack_top]; + p_cur_tn = *pp_cur_tn; + + p_par_tn = *stack_tn[stack_top - 1]; + + if (p_cur_tn && p_cur_tn->p_parent) { + p_unc_tn = zxdh_comm_rb_get_brotn(p_cur_tn); + } else if (p_cur_tn && !p_cur_tn->p_parent) { + RTE_ASSERT(p_par_tn == p_cur_tn->p_parent); + + zxdh_np_set_tn_color(p_cur_tn, ZXDH_RBT_BLACK); + + break; + } + if (!p_cur_tn) { + RTE_ASSERT(!p_cur_tn); + + if (p_par_tn) + p_unc_tn = p_par_tn->p_left ? p_par_tn->p_left : p_par_tn->p_right; + else + break; + } + + if (p_unc_tn) + RTE_ASSERT(p_unc_tn->p_parent == p_par_tn); + + if (!p_unc_tn) { + RTE_ASSERT(0); + RTE_ASSERT(zxdh_np_get_tn_color(p_par_tn) == ZXDH_RBT_RED); + + zxdh_np_set_tn_color(p_par_tn, ZXDH_RBT_BLACK); + + break; + } + if (zxdh_np_get_tn_color(p_unc_tn) == ZXDH_RBT_RED) { + if (p_unc_tn == p_par_tn->p_left) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_right; + stack_tn[stack_top] = &p_par_tn->p_right; + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_right); + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + stack_tn[stack_top++] = &p_unc_tn->p_left; + stack_tn[stack_top] = &p_par_tn->p_left; + } + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + } else { + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_BLACK && + zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_BLACK) { + if (zxdh_np_get_tn_color(p_unc_tn->p_parent) == ZXDH_RBT_BLACK) { + zxdh_np_set_tn_color(p_unc_tn, ZXDH_RBT_RED); + stack_top--; + } else { + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_parent) + == ZXDH_RBT_RED); + + zxdh_comm_rb_switch_color(p_unc_tn->p_parent, p_unc_tn); + + break; + } + } else if (p_unc_tn == p_par_tn->p_right) { + if (zxdh_np_get_tn_color(p_unc_tn->p_right) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_right = p_unc_tn->p_left; + + if (p_unc_tn->p_left) + p_unc_tn->p_left->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_left = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_right, ZXDH_RBT_BLACK); + + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_left) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_left; + + p_par_tn->p_right = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_left = p_tmp_tn->p_right; + + if (p_tmp_tn->p_right) + p_tmp_tn->p_right->p_parent = p_unc_tn; + + p_tmp_tn->p_right = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } else { + RTE_ASSERT(p_unc_tn == p_par_tn->p_left); + + if (zxdh_np_get_tn_color(p_unc_tn->p_left) == ZXDH_RBT_RED) { + *stack_tn[stack_top - 1] = p_unc_tn; + p_unc_tn->p_parent = p_par_tn->p_parent; + p_par_tn->p_left = p_unc_tn->p_right; + + if (p_unc_tn->p_right) + p_unc_tn->p_right->p_parent = p_par_tn; + + p_par_tn->p_parent = p_unc_tn; + p_unc_tn->p_right = p_par_tn; + + zxdh_comm_rb_switch_color(p_unc_tn, p_par_tn); + + zxdh_np_set_tn_color(p_unc_tn->p_left, ZXDH_RBT_BLACK); + break; + } + RTE_ASSERT(zxdh_np_get_tn_color(p_unc_tn->p_right) + == ZXDH_RBT_RED); + + p_tmp_tn = p_unc_tn->p_right; + + p_par_tn->p_left = p_tmp_tn; + p_tmp_tn->p_parent = p_par_tn; + p_unc_tn->p_right = p_tmp_tn->p_left; + + if (p_tmp_tn->p_left) + p_tmp_tn->p_left->p_parent = p_unc_tn; + + p_tmp_tn->p_left = p_unc_tn; + p_unc_tn->p_parent = p_tmp_tn; + + zxdh_comm_rb_switch_color(p_tmp_tn, p_unc_tn); + } + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_delete(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + uint32_t rtn = 0; + uint32_t stack_top = 1; + int32_t cmprtn = 0; + uint32_t rsv_stack = 0; + uint32_t del_is_red = 0; + ZXDH_RB_TN **stack_tn[ZXDH_RBT_MAX_DEPTH] = {0}; + ZXDH_RB_TN *p_cur_tn = NULL; + ZXDH_RB_TN **pp_cur_tn = NULL; + void *p_cur_key = NULL; + ZXDH_RB_TN *p_rsv_tn = NULL; + ZXDH_RB_TN *p_del_tn = NULL; + + p_cur_key = p_key; + + pp_cur_tn = &p_rb_cfg->p_root; + + for (;;) { + p_cur_tn = *pp_cur_tn; + + if (!p_cur_tn) + return ZXDH_RBT_RC_SRHFAIL; + + stack_tn[stack_top++] = pp_cur_tn; + + cmprtn = p_rb_cfg->p_cmpfun(p_cur_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) { + pp_cur_tn = &p_cur_tn->p_right; + } else if (cmprtn < 0) { + pp_cur_tn = &p_cur_tn->p_left; + } else { + PMD_DRV_LOG(DEBUG, " find the key!"); + + break; + } + } + + rsv_stack = stack_top - 1; + p_rsv_tn = p_cur_tn; + + pp_cur_tn = &p_cur_tn->p_right; + p_cur_tn = *pp_cur_tn; + + if (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + + while (p_cur_tn) { + stack_tn[stack_top++] = pp_cur_tn; + pp_cur_tn = &p_cur_tn->p_left; + p_cur_tn = *pp_cur_tn; + } + + p_del_tn = *stack_tn[stack_top - 1]; + + *stack_tn[stack_top - 1] = p_del_tn->p_right; + + if (p_del_tn->p_right) + p_del_tn->p_right->p_parent = p_del_tn->p_parent; + + if (zxdh_np_get_tn_color(p_del_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[rsv_stack] = p_del_tn; + + stack_tn[rsv_stack + 1] = &p_del_tn->p_right; + + zxdh_np_set_tn_color(p_del_tn, zxdh_np_get_tn_color(p_rsv_tn)); + p_del_tn->p_parent = p_rsv_tn->p_parent; + + p_del_tn->p_left = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_del_tn; + + p_del_tn->p_right = p_rsv_tn->p_right; + + if (p_rsv_tn->p_right) + p_rsv_tn->p_right->p_parent = p_del_tn; + } else { + if (zxdh_np_get_tn_color(p_rsv_tn) == ZXDH_RBT_RED) + del_is_red = 1; + + *stack_tn[stack_top - 1] = p_rsv_tn->p_left; + + if (p_rsv_tn->p_left) + p_rsv_tn->p_left->p_parent = p_rsv_tn->p_parent; + } + + stack_top--; + if (zxdh_np_get_tn_color(*stack_tn[stack_top]) == ZXDH_RBT_RED) { + zxdh_np_set_tn_color(*stack_tn[stack_top], ZXDH_RBT_BLACK); + } else if (!del_is_red) { + rtn = zxdh_comm_rb_handle_del(p_rb_cfg, stack_tn, stack_top); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_rb_handle_del"); + } + + rtn = zxdh_comm_double_link_del(&p_rsv_tn->tn_ln, &p_rb_cfg->tn_list); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_double_link_del"); + + if (p_rb_cfg->is_dynamic) { + *(ZXDH_RB_TN **)out_val = p_rsv_tn; + } else { + rtn = zxdh_comm_liststack_free(p_rb_cfg->p_lsm, zxdh_np_get_tn_lsv(p_rsv_tn)); + ZXDH_COMM_CHECK_RC(rtn, "zxdh_comm_liststack_free"); + + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_rsv_tn); + + memset(p_rsv_tn->p_key, 0, p_rb_cfg->key_size); + memset(p_rsv_tn, 0, sizeof(ZXDH_RB_TN)); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_liststack_destroy(ZXDH_LISTSTACK_MANAGER *p_list) +{ + if (p_list == NULL) { + PMD_DRV_LOG(INFO, "p_list point null"); + return ZXDH_LIST_STACK_POINT_NULL; + } + rte_free(p_list); + + return ZXDH_OK; +} + +static uint32_t +zxdh_comm_rb_destroy(ZXDH_RB_CFG *p_rb_cfg) +{ + uint32_t rtn = 0; + + if (p_rb_cfg->is_dynamic == 0) + zxdh_comm_liststack_destroy(p_rb_cfg->p_lsm); + + if (p_rb_cfg->p_keybase != NULL) { + rte_free(p_rb_cfg->p_keybase); + p_rb_cfg->p_keybase = NULL; + } + + if (p_rb_cfg->p_tnbase != NULL) { + rte_free(p_rb_cfg->p_tnbase); + p_rb_cfg->p_tnbase = NULL; + } + + memset(p_rb_cfg, 0, sizeof(ZXDH_RB_CFG)); + + return rtn; +} + +static int +zxdh_np_se_apt_key_default_cmp(void *p_new_key, + void *p_old_key, __rte_unused uint32_t key_len) +{ + return memcmp((uint32_t *)p_new_key, (uint32_t *)p_old_key, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_se_apt_rb_insert(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint8_t *p_rb_key = NULL; + ZXDH_RB_TN *p_rb_new = NULL; + ZXDH_RB_TN *p_rb_rtn = NULL; + uint32_t rc = ZXDH_OK; + + p_rb_key = (uint8_t *)rte_zmalloc(NULL, len, 0); + if (p_rb_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + memcpy(p_rb_key, p_data, len); + + p_rb_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (NULL == (p_rb_new)) { + rte_free(p_rb_key); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_new, p_rb_key); + + rc = zxdh_comm_rb_insert(rb_cfg, p_rb_new, &p_rb_rtn); + if (rc == ZXDH_RBT_RC_UPDATE) { + if (p_rb_rtn == NULL) { + PMD_DRV_LOG(ERR, "p_rb_rtn point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + memcpy(p_rb_rtn->p_key, p_data, len); + rte_free(p_rb_new); + rte_free(p_rb_key); + PMD_DRV_LOG(DEBUG, "update exist entry!"); + return ZXDH_OK; + } + + return rc; +} + +static uint32_t +zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_delete(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + rte_free(p_rb_rtn->p_key); + rte_free(p_rb_rtn); + + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -1896,10 +2888,112 @@ zxdh_np_dtb_queue_id_free(uint32_t dev_id, rc = zxdh_np_dtb_queue_unused_item_num_get(dev_id, queue_id, &item_num); + if (item_num != ZXDH_DTB_QUEUE_ITEM_NUM_MAX) + return ZXDH_RC_DTB_QUEUE_IS_WORKING; + p_dtb_mgr->queue_info[queue_id].init_flag = 0; p_dtb_mgr->queue_info[queue_id].vport = 0; p_dtb_mgr->queue_info[queue_id].vector = 0; + memset(&p_dtb_mgr->queue_info[queue_id].tab_up, 0, sizeof(ZXDH_DTB_TAB_UP_INFO_T)); + memset(&p_dtb_mgr->queue_info[queue_id].tab_down, 0, sizeof(ZXDH_DTB_TAB_DOWN_INFO_T)); + + return rc; +} + +static ZXDH_RB_CFG * +zxdh_np_dtb_dump_addr_rb_get(uint32_t dev_id, uint32_t queue_id) +{ + return g_dtb_dump_addr_rb[dev_id][queue_id]; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_set(uint32_t dev_id, uint32_t queue_id, ZXDH_RB_CFG *p_dump_addr_rb) +{ + g_dtb_dump_addr_rb[dev_id][queue_id] = p_dump_addr_rb; + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_clear(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_delete(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_delete"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_destroy(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_DTB_ADDR_INFO_T *p_rbkey = NULL; + ZXDH_D_HEAD *p_head_dtb_rb = NULL; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + uint32_t sdt_no = 0; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + p_head_dtb_rb = &p_dtb_dump_addr_rb->tn_list; + + while (p_head_dtb_rb->used) { + p_node = p_head_dtb_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_DTB_ADDR_INFO_T *)p_rb_tn->p_key; + + sdt_no = p_rbkey->sdt_no; + rc = zxdh_np_dtb_dump_sdt_addr_clear(dev_id, queue_id, sdt_no); + + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + PMD_DRV_LOG(ERR, "dtb dump delete key is not exist," + "std:%d", sdt_no); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_clear"); + } + + rc = zxdh_comm_rb_destroy(p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_rb_init(uint32_t dev_id, uint32_t queue_id) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + + if (p_dtb_dump_addr_rb == NULL) { + p_dtb_dump_addr_rb = (ZXDH_RB_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_RB_CFG), 0); + if (p_dtb_dump_addr_rb == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + rc = zxdh_np_dtb_dump_addr_rb_set(dev_id, queue_id, p_dtb_dump_addr_rb); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_set"); + } + + rc = zxdh_comm_rb_init(p_dtb_dump_addr_rb, 0, + sizeof(ZXDH_DTB_ADDR_INFO_T), zxdh_np_se_apt_key_default_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + return rc; } @@ -1929,6 +3023,9 @@ zxdh_np_dtb_queue_request(uint32_t dev_id, char p_name[32], PMD_DRV_LOG(DEBUG, "dtb request queue is %d.", queue_id); + rc = zxdh_np_dtb_dump_addr_rb_init(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_rb_init"); + *p_queue_id = queue_id; PMD_DRV_LOG(INFO, "dev_id %d vport 0x%x name %s queue_id %d done.", @@ -1967,6 +3064,9 @@ zxdh_np_dtb_queue_release(uint32_t devid, rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + rc = zxdh_np_dtb_dump_addr_rb_destroy(devid, queueid); + ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_dump_addr_rb_destroy"); + rc = zxdh_np_dtb_queue_id_free(devid, queueid); ZXDH_COMM_CHECK_DEV_RC(devid, rc, "zxdh_np_dtb_queue_id_free"); @@ -3290,12 +4390,43 @@ zxdh_np_dtb_user_info_set(uint32_t dev_id, uint32_t queue_id, uint16_t vport, ui return rc; } +static uint32_t +zxdh_np_dtb_dump_sdt_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t phy_addr, + uint64_t vir_addr, + uint32_t size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = { + .sdt_no = sdt_no, + .phy_addr = phy_addr, + .vir_addr = vir_addr, + .size = size, + }; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dtb_dump_addr_rb); + + rc = zxdh_np_se_apt_rb_insert(p_dtb_dump_addr_rb, + &dtb_dump_addr_info, sizeof(ZXDH_DTB_ADDR_INFO_T)); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_apt_rb_insert"); + + return rc; +} + static uint32_t zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) { uint32_t rc = ZXDH_OK; uint32_t queue_id = 0; + uint32_t index = 0; + uint32_t dump_sdt_num = 0; + ZXDH_DTB_ADDR_INFO_T *p_dump_info = NULL; rc = zxdh_np_dtb_queue_request(dev_id, p_dev_init_ctrl->port_name, p_dev_init_ctrl->vport, &queue_id); @@ -3313,6 +4444,19 @@ zxdh_np_apt_dtb_res_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl) zxdh_np_dtb_dump_channel_addr_set(dev_id, queue_id, p_dev_init_ctrl->dump_phy_addr, p_dev_init_ctrl->dump_vir_addr, 0); + dump_sdt_num = p_dev_init_ctrl->dump_sdt_num; + for (index = 0; index < dump_sdt_num; index++) { + p_dump_info = p_dev_init_ctrl->dump_addr_info + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dump_info); + rc = zxdh_np_dtb_dump_sdt_addr_set(dev_id, + queue_id, + p_dump_info->sdt_no, + p_dump_info->phy_addr, + p_dump_info->vir_addr, + p_dump_info->size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_set"); + } + return ZXDH_OK; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 5b187b97fb..989185bd40 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -123,6 +123,13 @@ #define ZXDH_VFUNC_NUM(VPORT) (((VPORT) & 0x00FF)) #define ZXDH_IS_PF(VPORT) (!ZXDH_VF_ACTIVE(VPORT)) +#define ZXDH_RBT_RED (0x1) +#define ZXDH_RBT_BLACK (0x2) +#define ZXDH_RBT_MAX_DEPTH (128) + +#define ZXDH_LISTSTACK_INVALID_INDEX (0) +#define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -141,6 +148,26 @@ #define ZXDH_SPIN_LOCK_ULOCK_FAIL (ZXDH_SPIN_LOCK_BASE | 0X003) #define ZXDH_SPIN_LOCK_DESTROY_FAIL (ZXDH_SPIN_LOCK_BASE | 0X004) +#define ZXDH_DOUBLE_LINK_BASE (ZXDH_RC_BASE | 0x500) +#define ZXDH_DOUBLE_LINK_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x001) +#define ZXDH_DOUBLE_LINK_MALLOC_FAIL (ZXDH_DOUBLE_LINK_BASE | 0x002) +#define ZXDH_DOUBLE_LINK_POINT_NULL (ZXDH_DOUBLE_LINK_BASE | 0x003) +#define ZXDH_DOUBLE_LINK_CHK_SUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x004) +#define ZXDH_DOUBLE_LINK_NO_EXIST_FREENODE (ZXDH_DOUBLE_LINK_BASE | 0x005) +#define ZXDH_DOUBLE_LINK_FREE_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x006) +#define ZXDH_DOUBLE_LINK_NO_EXIST_PRENODE (ZXDH_DOUBLE_LINK_BASE | 0x007) +#define ZXDH_DOUBLE_LINK_INPUT_INDX_INVALID (ZXDH_DOUBLE_LINK_BASE | 0x008) +#define ZXDH_DOUBLE_LINK_INIT_ELEMENT_NUM_ERR (ZXDH_DOUBLE_LINK_BASE | 0x009) + +#define ZXDH_LIST_STACK_BASE (ZXDH_RC_BASE | 0x800) +#define ZXDH_LIST_STACK_ELEMENT_NUM_ERR (ZXDH_LIST_STACK_BASE | 0x001) +#define ZXDH_LIST_STACK_POINT_NULL (ZXDH_LIST_STACK_BASE | 0x002) +#define ZXDH_LIST_STACK_ALLOC_MEMORY_FAIL (ZXDH_LIST_STACK_BASE | 0x003) +#define ZXDH_LIST_STACK_ISEMPTY_ERR (ZXDH_LIST_STACK_BASE | 0x004) +#define ZXDH_LIST_STACK_FREE_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x005) +#define ZXDH_LIST_STACK_ALLOC_INDEX_INVALID (ZXDH_LIST_STACK_BASE | 0x006) +#define ZXDH_LIST_STACK_ALLOC_INDEX_USED (ZXDH_LIST_STACK_BASE | 0x007) + #define ZXDH_ERAM128_BADDR_MASK (0x3FFFF80) #define ZXDH_DTB_TABLE_MODE_ERAM (0) @@ -185,6 +212,34 @@ #define ZXDH_RC_CTRLCH_MSG_OPER_NOT_SUPPORT (ZXDH_RC_CTRLCH_BASE | 0x3) #define ZXDH_RC_CTRLCH_MSG_DROP (ZXDH_RC_CTRLCH_BASE | 0x4) +#define ZXDH_RBT_RC_BASE (0x1000) +#define ZXDH_RBT_RC_UPDATE (ZXDH_RBT_RC_BASE | 0x1) +#define ZXDH_RBT_RC_SRHFAIL (ZXDH_RBT_RC_BASE | 0x2) +#define ZXDH_RBT_RC_FULL (ZXDH_RBT_RC_BASE | 0x3) +#define ZXDH_RBT_ISEMPTY_ERR (ZXDH_RBT_RC_BASE | 0x4) +#define ZXDH_RBT_PARA_INVALID (ZXDH_RBT_RC_BASE | 0x5) + +#define ZXDH_SE_RC_BASE (0x50000) +#define ZXDH_SE_RC_HASH_BASE (ZXDH_SE_RC_BASE | 0x4000) +#define ZXDH_HASH_RC_INVALID_FUNCINFO (ZXDH_SE_RC_HASH_BASE | 0x1) +#define ZXDH_HASH_RC_INVALID_ZBLCK (ZXDH_SE_RC_HASH_BASE | 0x2) +#define ZXDH_HASH_RC_INVALID_ZCELL (ZXDH_SE_RC_HASH_BASE | 0x3) +#define ZXDH_HASH_RC_INVALID_KEY (ZXDH_SE_RC_HASH_BASE | 0x4) +#define ZXDH_HASH_RC_INVALID_TBL_ID_INFO (ZXDH_SE_RC_HASH_BASE | 0x5) +#define ZXDH_HASH_RC_RB_TREE_FULL (ZXDH_SE_RC_HASH_BASE | 0x6) +#define ZXDH_HASH_RC_INVALID_KEY_TYPE (ZXDH_SE_RC_HASH_BASE | 0x7) +#define ZXDH_HASH_RC_ADD_UPDATE (ZXDH_SE_RC_HASH_BASE | 0x8) +#define ZXDH_HASH_RC_DEL_SRHFAIL (ZXDH_SE_RC_HASH_BASE | 0x9) +#define ZXDH_HASH_RC_ITEM_FULL (ZXDH_SE_RC_HASH_BASE | 0xa) +#define ZXDH_HASH_RC_INVALID_DDR_WIDTH_MODE (ZXDH_SE_RC_HASH_BASE | 0xb) +#define ZXDH_HASH_RC_INVALID_PARA (ZXDH_SE_RC_HASH_BASE | 0xc) +#define ZXDH_HASH_RC_TBL_FULL (ZXDH_SE_RC_HASH_BASE | 0xd) +#define ZXDH_HASH_RC_SRH_FAIL (ZXDH_SE_RC_HASH_BASE | 0xe) +#define ZXDH_HASH_RC_MATCH_ITEM_FAIL (ZXDH_SE_RC_HASH_BASE | 0xf) +#define ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR (ZXDH_SE_RC_HASH_BASE | 0x10) +#define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) +#define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -321,6 +376,42 @@ typedef struct zxdh_d_head { ZXDH_D_NODE *p_prev; } ZXDH_D_HEAD; +typedef struct zxdh_s_freelink { + uint32_t index; + uint32_t next; +} ZXDH_COMM_FREELINK; + +typedef struct zxdh_s_list_stack_manager { + ZXDH_COMM_FREELINK *p_array; + uint32_t capacity; + uint32_t p_head; + uint32_t free_num; + uint32_t used_num; +} ZXDH_LISTSTACK_MANAGER; + +typedef struct zxdh_rb_tn { + void *p_key; + uint32_t color_lsv; + struct zxdh_rb_tn *p_left; + struct zxdh_rb_tn *p_right; + struct zxdh_rb_tn *p_parent; + ZXDH_D_NODE tn_ln; +} ZXDH_RB_TN; + +typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); + +typedef struct _rb_cfg { + uint32_t key_size; + uint32_t is_dynamic; + ZXDH_RB_TN *p_root; + ZXDH_D_HEAD tn_list; + ZXDH_RB_CMPFUN p_cmpfun; + ZXDH_LISTSTACK_MANAGER *p_lsm; + uint8_t *p_keybase; + ZXDH_RB_TN *p_tnbase; + uint32_t is_init; +} ZXDH_RB_CFG; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 109586 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 06/14] net/zxdh: add eram tables ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (4 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 05/14] net/zxdh: add tables dump address ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 07/14] net/zxdh: get flow tables resources Bingbin Chen ` (7 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31926 bytes --] Implement the eram tables read and write operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 878 ++++++++++++++++++++++++++++++------- drivers/net/zxdh/zxdh_np.h | 15 + 2 files changed, 736 insertions(+), 157 deletions(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 09aa38958c..6808222ebc 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9}; static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX]; +static const char * const g_dpp_dtb_name[] = { + "DOWN TAB", + "UP TAB", +}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -196,6 +200,81 @@ static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { }, }; +static ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 106, 19}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, +}; + +static ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"base_addr", 117, 30}, + {"tb_depth", 83, 20}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"zgroup_id", 124, 2}, + {"zblock_id", 122, 3}, + {"ram_reg_flag", 119, 1}, + {"z_reg_cell_id", 118, 2}, + {"sram_addr", 116, 9}, + {"tb_depth", 97, 10}, + {"tb_width", 65, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = { + {"valid", 127, 1}, + {"up_type", 126, 2}, + {"block_sel", 124, 3}, + {"addr", 121, 9}, + {"rd_mode", 112, 8}, + {"data_or_mask", 104, 1}, + {"tb_depth", 91, 10}, + {"tb_width", 81, 2}, + {"tb_dst_addr_h", 63, 32}, + {"tb_dst_addr_l", 31, 32}, + +}; + +static ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = { + { + "eram", + ZXDH_DTB_DUMP_ERAM, + 6, + g_dtb_eram_dump_cmd_info, + }, + { + "ddr", + ZXDH_DTB_DUMP_DDR, + 6, + g_dtb_ddr_dump_cmd_info, + }, + { + "zcam", + ZXDH_DTB_DUMP_ZCAM, + 11, + g_dtb_zcam_dump_cmd_info, + }, + { + "etcam", + ZXDH_DTB_DUMP_ETCAM, + 10, + g_dtb_etcam_dump_cmd_info, + }, +}; + #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) #define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) @@ -305,6 +384,28 @@ zxdh_np_comm_convert32(uint32_t dw_data) (p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \ VAL) +static inline uint64_t +zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size; +} + +#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + +static inline uint64_t +zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID, + uint32_t INDEX) +{ + return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr + + INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size; +} + +#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \ + zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX) + static inline void zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata) { @@ -3147,6 +3248,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type) return &g_dpp_dtb_table_info[table_type]; } +static ZXDH_DTB_TABLE_T * +zxdh_np_dtb_dump_info_get(uint32_t up_type) +{ + return &g_dpp_dtb_dump_info[up_type]; +} + static uint32_t zxdh_np_dtb_write_table_cmd(uint32_t dev_id, ZXDH_DTB_TABLE_INFO_E table_type, @@ -3181,6 +3288,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_write_dump_cmd(uint32_t dev_id, + ZXDH_DTB_DUMP_INFO_E dump_type, + void *p_cmd_data, + void *p_cmd_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t field_cnt = 0; + ZXDH_DTB_TABLE_T *p_table_info; + ZXDH_DTB_FIELD_T *p_field_info = NULL; + uint32_t temp_data = 0; + + p_table_info = zxdh_np_dtb_dump_info_get(dump_type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info); + p_field_info = p_table_info->p_fields; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info); + + for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) { + temp_data = *((uint32_t *)p_cmd_data + field_cnt) & + ZXDH_COMM_GET_BIT_MASK(uint32_t, p_field_info[field_cnt].len); + + rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff, + ZXDH_DTB_TABLE_CMD_SIZE_BIT, + temp_data, + p_field_info[field_cnt].lsb_pos, + p_field_info[field_cnt].len); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits"); + } + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, uint32_t mode, @@ -3231,6 +3371,32 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ERAM, + .base_addr = base_addr, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM, + &dtb_eram_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -3308,6 +3474,65 @@ zxdh_np_eram_dtb_len_get(uint32_t mode) return dtb_len; } +static void +zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) +{ + p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; + p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +{ + uint32_t tbl_type = 0; + uint32_t clutch_en = 0; + + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + p_sdt_eram->table_type = tbl_type; + p_sdt_eram->eram_clutch_en = clutch_en; + break; + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + p_sdt_porttbl->table_type = tbl_type; + p_sdt_porttbl->porttbl_clutch_en = clutch_en; + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + +static uint32_t +zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t rc; + + if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) { + PMD_DRV_LOG(ERR, "SDT NO [ %d ] is invalid!", sdt_no); + return ZXDH_PAR_CHK_INVALID_PARA; + } + + zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); + + rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); + if (rc != 0) + PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error.", sdt_no); + + return rc; +} + static uint32_t zxdh_np_dtb_eram_one_entry(uint32_t dev_id, uint32_t sdt_no, @@ -3328,6 +3553,9 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id, ZXDH_COMM_CHECK_POINT(p_dtb_one_entry); ZXDH_COMM_CHECK_POINT(p_dtb_len); + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata; index = peramdata->index; base_addr = sdt_eram.eram_base_addr; @@ -3478,6 +3706,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_item_ack_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t ack_data[4] = {0}; + + for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + } + + PMD_DRV_LOG(INFO, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]); + PMD_DRV_LOG(INFO, "[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index, + ack_data[0], ack_data[1], ack_data[2], ack_data[3]); + + return rc; +} + +static uint32_t +zxdh_np_dtb_item_buff_rd(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t pos, + uint32_t len, + uint32_t *p_data) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) { + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) { + addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4; + ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0); + } else { + addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + } else { + addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + + ZXDH_DTB_ITEM_ACK_SIZE + pos * 4; + } + + memcpy(p_data, (uint8_t *)(addr), len * 4); + + zxdh_np_comm_swap((uint8_t *)p_data, len * 4); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_item_buff_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t dir_flag, + uint32_t index, + uint32_t len) +{ + uint32_t rc = 0; + uint32_t i = 0; + uint32_t j = 0; + uint32_t *p_item_buff = NULL; + + p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0); + if (p_item_buff == NULL) { + PMD_DRV_LOG(INFO, "Alloc dtb item buffer failed!!!"); + return ZXDH_RC_DTB_MEMORY_ALLOC_ERR; + } + + zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff); + + PMD_DRV_LOG(INFO, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]); + for (i = 0, j = 0; i < len; i++, j++) { + if (j % 4 == 0) + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + else + PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i))); + } + + rte_free(p_item_buff); + + return rc; +} + static uint32_t zxdh_np_dtb_queue_item_info_set(uint32_t dev_id, uint32_t queue_id, @@ -3611,6 +3931,121 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_table_addr_h, + uint32_t *p_element_table_addr_l) +{ + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff; + addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_table_addr_h = addr_h; + *p_element_table_addr_l = addr_l; +} + +static uint32_t +zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_table_addr_h = 0; + uint32_t element_table_addr_l = 0; + + zxdh_np_dtb_down_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_table_addr_h, + &element_table_addr_l); + + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_table_addr_h 0x%x..", element_table_addr_h); + PMD_DRV_LOG(INFO, "element_table_addr_l 0x%x.", element_table_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value); + + if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) { + PMD_DRV_LOG(ERR, "down queue %d item %d overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) { + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + return ack_value & 0xff; + } + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -3679,14 +4114,9 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, &element_id); rte_free(p_data_buff); - return rc; -} + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); -static void -zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data) -{ - p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32; - p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32; + return rc; } int @@ -3762,66 +4192,21 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, &element_id); rte_free(p_data_buff); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id); + return rc; } -static uint32_t -zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info) +static void +zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, + uint32_t *p_row_index, uint32_t *p_col_index) { - uint32_t tbl_type = 0; - uint32_t clutch_en = 0; - - ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; - ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1); + uint32_t row_index = 0; + uint32_t col_index = 0; - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; - p_sdt_eram->table_type = tbl_type; - p_sdt_eram->eram_clutch_en = clutch_en; - break; - case ZXDH_SDT_TBLT_PORTTBL: - p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; - p_sdt_porttbl->table_type = tbl_type; - p_sdt_porttbl->porttbl_clutch_en = clutch_en; - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - -static uint32_t -zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t rc; - - zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl); - - rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info); - if (rc != 0) - PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no); - - return rc; -} - -static void -zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, - uint32_t *p_row_index, uint32_t *p_col_index) -{ - uint32_t row_index = 0; - uint32_t col_index = 0; - - switch (eram_mode) { - case ZXDH_ERAM128_TBL_128b: - row_index = index; + switch (eram_mode) { + case ZXDH_ERAM128_TBL_128b: + row_index = index; break; case ZXDH_ERAM128_TBL_64b: row_index = (index >> 1); @@ -3838,74 +4223,6 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index, *p_col_index = col_index; } -static uint32_t -zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, - ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) -{ - uint32_t index = p_dump_eram_entry->index; - uint32_t *p_data = p_dump_eram_entry->p_data; - ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; - uint32_t temp_data[4] = {0}; - uint32_t row_index = 0; - uint32_t col_index = 0; - uint32_t rd_mode; - uint32_t rc; - - rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); - ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); - rd_mode = sdt_eram_info.eram_mode; - - zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); - - switch (rd_mode) { - case ZXDH_ERAM128_TBL_128b: - memcpy(p_data, temp_data, (128 / 8)); - break; - case ZXDH_ERAM128_TBL_64b: - memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); - break; - case ZXDH_ERAM128_TBL_1b: - ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + - (3 - col_index / 32)), (col_index % 32), 1); - break; - default: - break; - } - return rc; -} - -int -zxdh_np_dtb_table_entry_get(uint32_t dev_id, - uint32_t queue_id, - ZXDH_DTB_USER_ENTRY_T *get_entry, - uint32_t srh_mode) -{ - ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; - uint32_t tbl_type = 0; - uint32_t rc = 0; - uint32_t sdt_no; - - sdt_no = get_entry->sdt_no; - zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); - - ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, - ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); - switch (tbl_type) { - case ZXDH_SDT_TBLT_ERAM: - rc = zxdh_np_dtb_eram_data_get(dev_id, - queue_id, - sdt_no, - (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); - ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); - break; - default: - PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); - return 1; - } - - return 0; -} - static void zxdh_np_stat_cfg_soft_get(uint32_t dev_id, ZXDH_PPU_STAT_CFG_T *p_stat_cfg) @@ -3970,6 +4287,181 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_tab_up_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t data_len, + uint32_t *p_data) +{ + uint32_t rc = 0; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + rc = zxdh_np_dtb_item_buff_rd(dev_id, + queue_id, + ZXDH_DTB_DIR_UP_TYPE, + item_index, + 0, + data_len, + p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint32_t rc = 0; + uint64_t addr; + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_ITEM_ACK_SIZE; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id, + uint32_t *p_element_start_addr_h, + uint32_t *p_element_start_addr_l, + uint32_t *p_element_dump_addr_h, + uint32_t *p_element_dump_addr_l, + uint32_t *p_element_table_info_addr_h, + uint32_t *p_element_table_info_addr_l) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_h = 0; + uint32_t addr_l = 0; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff; + + *p_element_start_addr_h = addr_h; + *p_element_start_addr_l = addr_l; + + addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff; + addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) + + ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff; + + *p_element_dump_addr_h = addr_h; + *p_element_dump_addr_l = addr_l; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id, + p_element_table_info_addr_h, p_element_table_info_addr_l); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + + uint32_t element_start_addr_h = 0; + uint32_t element_start_addr_l = 0; + uint32_t element_dump_addr_h = 0; + uint32_t element_dump_addr_l = 0; + uint32_t element_table_info_addr_h = 0; + uint32_t element_table_info_addr_l = 0; + + zxdh_np_dtb_dump_table_element_addr_get(dev_id, + queue_id, + element_id, + &element_start_addr_h, + &element_start_addr_l, + &element_dump_addr_h, + &element_dump_addr_l, + &element_table_info_addr_h, + &element_table_info_addr_l); + PMD_DRV_LOG(INFO, "queue_id %d.", queue_id); + PMD_DRV_LOG(INFO, "element_id %d.", element_id); + PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h); + PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l); + PMD_DRV_LOG(INFO, "element_dump_addr_h 0x%x.", element_dump_addr_h); + PMD_DRV_LOG(INFO, "element_dump_addr_l 0x%x.", element_dump_addr_l); + PMD_DRV_LOG(INFO, "element_table_info_addr_h 0x%x.", element_table_info_addr_h); + PMD_DRV_LOG(INFO, "element_table_info_addr_l 0x%x.", element_table_info_addr_l); + + rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id, + uint32_t queue_id, + uint32_t element_id) +{ + uint32_t rc = 0; + uint32_t rd_cnt = 0; + uint32_t ack_value = 0; + uint32_t success_flag = 0; + + while (!success_flag) { + rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, &ack_value); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd"); + + if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) && + ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) { + success_flag = 1; + break; + } + + if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) { + PMD_DRV_LOG(ERR, "dump queue %d item %d overtime!", queue_id, element_id); + + rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt"); + + rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, + element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr"); + + return ZXDH_ERR; + } + + rd_cnt++; + rte_delay_us(ZXDH_DTB_DELAY_TIME); + } + + return rc; +} + static uint32_t zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, uint32_t queue_id, @@ -3997,6 +4489,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id, queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK); } + rc = zxdh_np_dtb_tab_up_success_status_check(dev_id, + queue_id, queue_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check"); + + rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id, + data_len, p_dump_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get"); + + PMD_DRV_LOG(DEBUG, "queue %d element %d dump done.", queue_id, queue_element_id); + return rc; } @@ -4055,33 +4557,6 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } -static uint32_t -zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, - uint32_t queue_id, - uint32_t item_index, - uint32_t *p_phy_haddr, - uint32_t *p_phy_laddr) -{ - uint32_t rc = 0; - uint64_t addr; - - if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { - PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id); - return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; - } - - if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == - ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) - addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); - else - addr = ZXDH_DTB_ITEM_ACK_SIZE; - - *p_phy_haddr = (addr >> 32) & 0xffffffff; - *p_phy_laddr = addr & 0xffffffff; - - return rc; -} - static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -4110,6 +4585,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, &dump_dst_phy_haddr, &dump_dst_phy_laddr); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get"); + rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write"); + data_len = depth * 128 / 32; desc_len = ZXDH_DTB_LEN_POS_SETP / 4; @@ -4120,6 +4603,87 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, + ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry) +{ + uint32_t index = p_dump_eram_entry->index; + uint32_t *p_data = p_dump_eram_entry->p_data; + ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0}; + uint32_t temp_data[4] = {0}; + uint32_t row_index = 0; + uint32_t col_index = 0; + uint32_t rd_mode; + uint32_t rc; + uint32_t eram_dump_base_addr = 0; + uint32_t eram_base_addr = 0; + uint32_t element_id = 0; + + rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get"); + rd_mode = sdt_eram_info.eram_mode; + + zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index); + + eram_dump_base_addr = eram_base_addr + row_index; + + rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id, + queue_id, + eram_dump_base_addr, + 1, + temp_data, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump"); + + switch (rd_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_data, temp_data, (128 / 8)); + break; + case ZXDH_ERAM128_TBL_64b: + memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8)); + break; + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data + + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + return rc; +} + +int +zxdh_np_dtb_table_entry_get(uint32_t dev_id, + uint32_t queue_id, + ZXDH_DTB_USER_ENTRY_T *get_entry, + uint32_t srh_mode) +{ + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + uint32_t tbl_type = 0; + uint32_t rc; + uint32_t sdt_no; + + sdt_no = get_entry->sdt_no; + zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); + + ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + switch (tbl_type) { + case ZXDH_SDT_TBLT_ERAM: + rc = zxdh_np_dtb_eram_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); + break; + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); + return 1; + } + + return 0; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id, uint32_t queue_id, diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 989185bd40..59ed9b8fb2 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -176,6 +176,13 @@ #define ZXDH_DTB_TABLE_MODE_ETCAM (3) #define ZXDH_DTB_TABLE_MODE_MC_HASH (4) #define ZXDH_DTB_TABLE_VALID (1) +#define ZXDH_DTB_DUMP_MODE_ERAM (0) +#define ZXDH_DTB_DUMP_MODE_ZCAM (2) +#define ZXDH_DTB_DUMP_MODE_ETCAM (3) + +#define ZXDH_DTB_DELAY_TIME (50) +#define ZXDH_DTB_DOWN_OVER_TIME (2000) +#define ZXDH_DTB_DUMP_OVER_TIME (0x4c4b40) /* DTB module error code */ #define ZXDH_RC_DTB_BASE (0xd00) @@ -643,6 +650,14 @@ typedef enum zxdh_dtb_table_info_e { ZXDH_DTB_TABLE_ENUM_MAX } ZXDH_DTB_TABLE_INFO_E; +typedef enum zxdh_dtb_dump_info_e { + ZXDH_DTB_DUMP_ERAM = 0, + ZXDH_DTB_DUMP_DDR = 1, + ZXDH_DTB_DUMP_ZCAM = 2, + ZXDH_DTB_DUMP_ETCAM = 3, + ZXDH_DTB_DUMP_ENUM_MAX +} ZXDH_DTB_DUMP_INFO_E; + typedef enum zxdh_sdt_table_type_e { ZXDH_SDT_TBLT_INVALID = 0, ZXDH_SDT_TBLT_ERAM = 1, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 79646 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 07/14] net/zxdh: get flow tables resources 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (5 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 06/14] net/zxdh: add eram tables ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 08/14] net/zxdh: support hash resources configuration Bingbin Chen ` (6 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31472 bytes --] Implement the flow tables resources get operation by agent channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 13 + drivers/net/zxdh/zxdh_ethdev.h | 1 + drivers/net/zxdh/zxdh_np.c | 490 +++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 337 +++++++++++++++++++++-- 4 files changed, 820 insertions(+), 21 deletions(-) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index e683cbd616..ea34b9229b 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1809,6 +1809,19 @@ zxdh_np_init(struct rte_eth_dev *eth_dev) return ret; } } + + if (hw->is_pf) { + ret = zxdh_np_se_res_get_and_init(hw->dev_id, ZXDH_SE_STD_NIC_RES_TYPE); + if (ret) { + PMD_DRV_LOG(ERR, "dpp apt init failed, code:%d ", ret); + return -ret; + } + if (hw->hash_search_index >= ZXDH_HASHIDX_MAX) { + PMD_DRV_LOG(ERR, "invalid hash idx %d", hw->hash_search_index); + return -1; + } + } + if (zxdh_shared_data != NULL) zxdh_shared_data->np_init_done = 1; diff --git a/drivers/net/zxdh/zxdh_ethdev.h b/drivers/net/zxdh/zxdh_ethdev.h index 04b0b58c74..261acd17c3 100644 --- a/drivers/net/zxdh/zxdh_ethdev.h +++ b/drivers/net/zxdh/zxdh_ethdev.h @@ -44,6 +44,7 @@ #define ZXDH_MAX_NAME_LEN 32 #define ZXDH_SLOT_MAX 256 #define ZXDH_MAX_VF 256 +#define ZXDH_HASHIDX_MAX 6 union zxdh_virport_num { uint16_t vport; diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 6808222ebc..e11004183d 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2445,6 +2445,40 @@ zxdh_np_agent_channel_dtb_queue_release(uint32_t dev_id, return msg_result; } +static uint32_t +zxdh_np_agent_channel_se_res_get(uint32_t dev_id, + uint32_t sub_type, + uint32_t opr, + uint32_t *p_rsp_buff, + uint32_t buff_size) +{ + uint32_t rc = ZXDH_OK; + + uint32_t msg_result = 0; + ZXDH_AGENT_SE_RES_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_RES_MSG, + .sub_type = sub_type, + .oper = opr, + }; + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&msgcfg, + .msg_len = sizeof(ZXDH_AGENT_SE_RES_MSG_T), + }; + + rc = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "agent send msg failed"); + return ZXDH_ERR; + } + + msg_result = p_rsp_buff[0]; + PMD_DRV_LOG(DEBUG, "msg_result: 0x%x", msg_result); + zxdh_np_agent_msg_prt(msgcfg.type, msg_result); + + return msg_result; +} + static ZXDH_DTB_MGR_T * zxdh_np_dtb_mgr_get(uint32_t dev_id) { @@ -5065,6 +5099,462 @@ zxdh_np_host_init(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_get_se_buff_size(uint32_t opr) +{ + uint32_t buff_size = 0; + + switch (opr) { + case ZXDH_HASH_FUNC_BULK_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_FUNC_BULK_T); + break; + case ZXDH_HASH_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_HASH_TBL_T); + break; + case ZXDH_ERAM_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ERAM_TBL_T); + break; + case ZXDH_ACL_TBL_REQ: + buff_size = sizeof(ZXDH_NP_SE_ACL_TBL_T); + break; + case ZXDH_STAT_CFG_REQ: + buff_size = sizeof(ZXDH_NP_SE_STAT_CFG_T); + break; + default: + break; + } + + return buff_size; +} + +static void +zxdh_np_hash_func_bulk_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk) +{ + uint32_t index = 0; + ZXDH_APT_HASH_FUNC_RES_T *p_func_res = NULL; + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res = NULL; + + p_hash_res_init->func_num = p_func_bulk->func_num; + p_hash_res_init->bulk_num = p_func_bulk->bulk_num; + for (index = 0; index < (p_hash_res_init->func_num); index++) { + p_func_res = p_hash_res_init->func_res + index; + + p_func_res->func_id = p_func_bulk->fun[index].func_id; + p_func_res->ddr_dis = p_func_bulk->fun[index].ddr_dis; + p_func_res->zblk_num = p_func_bulk->fun[index].zblk_num; + p_func_res->zblk_bitmap = p_func_bulk->fun[index].zblk_bitmap; + } + + for (index = 0; index < (p_hash_res_init->bulk_num); index++) { + p_bulk_res = p_hash_res_init->bulk_res + index; + + p_bulk_res->func_id = p_func_bulk->bulk[index].func_id; + p_bulk_res->bulk_id = p_func_bulk->bulk[index].bulk_id; + p_bulk_res->zcell_num = p_func_bulk->bulk[index].zcell_num; + p_bulk_res->zreg_num = p_func_bulk->bulk[index].zreg_num; + p_bulk_res->ddr_baddr = p_func_bulk->bulk[index].ddr_baddr; + p_bulk_res->ddr_item_num = p_func_bulk->bulk[index].ddr_item_num; + p_bulk_res->ddr_width_mode = p_func_bulk->bulk[index].ddr_width_mode; + p_bulk_res->ddr_crc_sel = p_func_bulk->bulk[index].ddr_crc_sel; + p_bulk_res->ddr_ecc_en = p_func_bulk->bulk[index].ddr_ecc_en; + } +} + +static void +zxdh_np_hash_tbl_set(ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init, ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl) +{ + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_tbl_res = NULL; + + p_hash_res_init->tbl_num = p_hash_tbl->tbl_num; + for (index = 0; index < (p_hash_res_init->tbl_num); index++) { + p_tbl_res = p_hash_res_init->tbl_res + index; + + p_tbl_res->sdt_no = p_hash_tbl->table[index].sdt_no; + p_tbl_res->sdt_partner = p_hash_tbl->table[index].sdt_partner; + p_tbl_res->tbl_flag = p_hash_tbl->table[index].tbl_flag; + p_tbl_res->hash_sdt.table_type = + p_hash_tbl->table[index].hash_sdt.table_type; + p_tbl_res->hash_sdt.hash_id = p_hash_tbl->table[index].hash_sdt.hash_id; + p_tbl_res->hash_sdt.hash_table_width = + p_hash_tbl->table[index].hash_sdt.hash_table_width; + p_tbl_res->hash_sdt.key_size = p_hash_tbl->table[index].hash_sdt.key_size; + p_tbl_res->hash_sdt.hash_table_id = + p_hash_tbl->table[index].hash_sdt.hash_table_id; + p_tbl_res->hash_sdt.learn_en = p_hash_tbl->table[index].hash_sdt.learn_en; + p_tbl_res->hash_sdt.keep_alive = + p_hash_tbl->table[index].hash_sdt.keep_alive; + p_tbl_res->hash_sdt.keep_alive_baddr = + p_hash_tbl->table[index].hash_sdt.keep_alive_baddr; + p_tbl_res->hash_sdt.rsp_mode = + p_hash_tbl->table[index].hash_sdt.rsp_mode; + p_tbl_res->hash_sdt.hash_clutch_en = + p_hash_tbl->table[index].hash_sdt.hash_clutch_en; + } +} + +static void +zxdh_np_eram_tbl_set(ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init, ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_eram_res = NULL; + + p_eam_res_init->tbl_num = p_eram_tbl->tbl_num; + for (index = 0; index < (p_eam_res_init->tbl_num); index++) { + p_eram_res = p_eam_res_init->eram_res + index; + + p_eram_res->sdt_no = p_eram_tbl->eram[index].sdt_no; + p_eram_res->opr_mode = p_eram_tbl->eram[index].opr_mode; + p_eram_res->rd_mode = p_eram_tbl->eram[index].rd_mode; + p_eram_res->eram_sdt.table_type = p_eram_tbl->eram[index].eram_sdt.table_type; + p_eram_res->eram_sdt.eram_mode = p_eram_tbl->eram[index].eram_sdt.eram_mode; + p_eram_res->eram_sdt.eram_base_addr = + p_eram_tbl->eram[index].eram_sdt.eram_base_addr; + p_eram_res->eram_sdt.eram_table_depth = + p_eram_tbl->eram[index].eram_sdt.eram_table_depth; + p_eram_res->eram_sdt.eram_clutch_en = + p_eram_tbl->eram[index].eram_sdt.eram_clutch_en; + } +} + +static void +zxdh_np_acl_tbl_set(ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init, ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl) +{ + uint32_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_acl_res = NULL; + + p_acl_res_init->tbl_num = p_acl_tbl->tbl_num; + for (index = 0; index < (p_acl_tbl->tbl_num); index++) { + p_acl_res = p_acl_res_init->acl_res + index; + + p_acl_res->sdt_no = p_acl_tbl->acl[index].sdt_no; + p_acl_res->sdt_partner = p_acl_tbl->acl[index].sdt_partner; + p_acl_res->acl_res.block_num = p_acl_tbl->acl[index].acl_res.block_num; + p_acl_res->acl_res.entry_num = p_acl_tbl->acl[index].acl_res.entry_num; + p_acl_res->acl_res.pri_mode = p_acl_tbl->acl[index].acl_res.pri_mode; + memcpy(p_acl_res->acl_res.block_index, + p_acl_tbl->acl[index].acl_res.block_index, + sizeof(uint32_t) * ZXDH_ETCAM_BLOCK_NUM); + p_acl_res->acl_sdt.table_type = p_acl_tbl->acl[index].acl_sdt.table_type; + p_acl_res->acl_sdt.etcam_id = p_acl_tbl->acl[index].acl_sdt.etcam_id; + p_acl_res->acl_sdt.etcam_key_mode = p_acl_tbl->acl[index].acl_sdt.etcam_key_mode; + p_acl_res->acl_sdt.etcam_table_id = p_acl_tbl->acl[index].acl_sdt.etcam_table_id; + p_acl_res->acl_sdt.no_as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.no_as_rsp_mode; + p_acl_res->acl_sdt.as_en = p_acl_tbl->acl[index].acl_sdt.as_en; + p_acl_res->acl_sdt.as_eram_baddr = p_acl_tbl->acl[index].acl_sdt.as_eram_baddr; + p_acl_res->acl_sdt.as_rsp_mode = p_acl_tbl->acl[index].acl_sdt.as_rsp_mode; + p_acl_res->acl_sdt.etcam_table_depth = + p_acl_tbl->acl[index].acl_sdt.etcam_table_depth; + p_acl_res->acl_sdt.etcam_clutch_en = p_acl_tbl->acl[index].acl_sdt.etcam_clutch_en; + } +} + +static void +zxdh_np_stat_cfg_set(ZXDH_APT_STAT_RES_INIT_T *p_stat_res_init, ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg) +{ + p_stat_res_init->eram_baddr = p_stat_cfg->eram_baddr; + p_stat_res_init->eram_depth = p_stat_cfg->eram_depth; + p_stat_res_init->ddr_baddr = p_stat_cfg->ddr_baddr; + p_stat_res_init->ppu_ddr_offset = p_stat_cfg->ppu_ddr_offset; +} + +static uint32_t +zxdh_np_agent_hash_func_bulk_get(uint32_t dev_id, uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_FUNC_BULK_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_FUNC_BULK_T *p_func_bulk = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash func&bulk res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_func_bulk = (ZXDH_NP_SE_HASH_FUNC_BULK_T *)(p_rsp_buff + 1); + zxdh_np_hash_func_bulk_set(p_hash_res_init, p_func_bulk); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_hash_tbl_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_HASH_RES_INIT_T *p_hash_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_HASH_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_HASH_TBL_T *p_hash_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "hash table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_hash_tbl = (ZXDH_NP_SE_HASH_TBL_T *)(p_rsp_buff + 1); + zxdh_np_hash_tbl_set(p_hash_res_init, p_hash_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_eram_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ERAM_RES_INIT_T *p_eam_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ERAM_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ERAM_TBL_T *p_eram_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "eram table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_eram_tbl = (ZXDH_NP_SE_ERAM_TBL_T *)(p_rsp_buff + 1); + zxdh_np_eram_tbl_set(p_eam_res_init, p_eram_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_acl_tbl_get(uint32_t dev_id, uint32_t type, ZXDH_APT_ACL_RES_INIT_T *p_acl_res_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_ACL_TBL_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_ACL_TBL_T *p_acl_tbl = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? + ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "acl table res get fail rc=0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_acl_tbl = (ZXDH_NP_SE_ACL_TBL_T *)(p_rsp_buff + 1); + zxdh_np_acl_tbl_set(p_acl_res_init, p_acl_tbl); + rte_free(p_rsp_buff); + + return rc; +} + +static uint32_t +zxdh_np_agent_stat_cfg_get(uint32_t dev_id, + uint32_t type, + ZXDH_APT_STAT_RES_INIT_T *p_stat_cfg_init) +{ + uint32_t rc = ZXDH_OK; + uint32_t opr = ZXDH_STAT_CFG_REQ; + uint32_t sub_type = ZXDH_RES_STD_NIC_MSG; + uint32_t buff_size = 0; + ZXDH_SPINLOCK_T *p_dtb_spinlock = NULL; + uint32_t *p_rsp_buff = NULL; + ZXDH_NP_SE_STAT_CFG_T *p_stat_cfg = NULL; + ZXDH_DEV_SPINLOCK_TYPE_E spinlock = ZXDH_DEV_SPINLOCK_T_DTB; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, (uint32_t)spinlock, &p_dtb_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_dtb_spinlock->spinlock); + + buff_size = zxdh_np_get_se_buff_size(opr) + sizeof(uint32_t); + p_rsp_buff = (uint32_t *)rte_zmalloc(NULL, buff_size, 0); + if (p_rsp_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_PAR_CHK_POINT_NULL; + } + + sub_type = (type == ZXDH_SE_STD_NIC_RES_TYPE) ? ZXDH_RES_STD_NIC_MSG : ZXDH_RES_OFFLOAD_MSG; + + rc = zxdh_np_agent_channel_se_res_get(dev_id, sub_type, opr, p_rsp_buff, buff_size); + if (rc != ZXDH_OK) { + rte_free(p_rsp_buff); + PMD_DRV_LOG(ERR, "ddr table res get fail rc = 0x%x.", rc); + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + return ZXDH_ERR; + } + + rte_spinlock_unlock(&p_dtb_spinlock->spinlock); + + p_stat_cfg = (ZXDH_NP_SE_STAT_CFG_T *)(p_rsp_buff + 1); + zxdh_np_stat_cfg_set(p_stat_cfg_init, p_stat_cfg); + rte_free(p_rsp_buff); + + return rc; +} + +static void * +zxdh_np_dev_get_se_res_ptr(uint32_t dev_id, uint32_t type) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + if (type == ZXDH_SE_STD_NIC_RES_TYPE) + return (void *)&p_dev_info->dev_apt_se_tbl_res.std_nic_res; + else + return (void *)&p_dev_info->dev_apt_se_tbl_res.offload_res; +} + +static uint32_t +zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_res); + + if (p_se_res->valid) { + PMD_DRV_LOG(INFO, "dev_id [0x%x] res_type [%u] status ready", dev_id, type); + return ZXDH_OK; + } + + hash_res.func_res = p_se_res->hash_func; + hash_res.bulk_res = p_se_res->hash_bulk; + hash_res.tbl_res = p_se_res->hash_tbl; + rc = zxdh_np_agent_hash_func_bulk_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_func_bulk_get"); + + rc = zxdh_np_agent_hash_tbl_get(dev_id, type, &hash_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_hash_tbl_get"); + p_se_res->hash_func_num = hash_res.func_num; + p_se_res->hash_bulk_num = hash_res.bulk_num; + p_se_res->hash_tbl_num = hash_res.tbl_num; + + eram_res.eram_res = p_se_res->eram_tbl; + rc = zxdh_np_agent_eram_tbl_get(dev_id, type, &eram_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_eram_tbl_get"); + p_se_res->eram_num = eram_res.tbl_num; + + acl_res.acl_res = p_se_res->acl_tbl; + rc = zxdh_np_agent_acl_tbl_get(dev_id, type, &acl_res); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_acl_tbl_get"); + p_se_res->acl_num = acl_res.tbl_num; + + rc = zxdh_np_agent_stat_cfg_get(dev_id, type, &p_se_res->stat_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_stat_cfg_get"); + + p_se_res->valid = 1; + return rc; +} +uint32_t +zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_agent_se_res_get(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 59ed9b8fb2..23acce3a70 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -130,6 +130,12 @@ #define ZXDH_LISTSTACK_INVALID_INDEX (0) #define ZXDH_LISTSTACK_MAX_ELEMENT (0x0ffffffe) +#define ZXDH_HASH_FUNC_MAX_NUM (4) +#define ZXDH_HASH_BULK_MAX_NUM (32) +#define ZXDH_HASH_TABLE_MAX_NUM (38) +#define ZXDH_ERAM_MAX_NUM (60) +#define ZXDH_ETCAM_MAX_NUM (8) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -470,6 +476,174 @@ typedef struct dpp_sdt_soft_table_t { ZXDH_SDT_ITEM_T sdt_array[ZXDH_DEV_SDT_ID_MAX]; } ZXDH_SDT_SOFT_TABLE_T; +typedef enum zxdh_hash_srh_mode { + ZXDH_HASH_SRH_MODE_SOFT = 1, + ZXDH_HASH_SRH_MODE_HDW = 2, +} ZXDH_HASH_SRH_MODE; + +typedef struct zxdh_hash_entry { + uint8_t *p_key; + uint8_t *p_rst; +} ZXDH_HASH_ENTRY; + +typedef struct zxdh_acl_entry_ex_t { + uint32_t idx_val; + ZXDH_D_HEAD idx_list; + uint32_t pri; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_ACL_ENTRY_EX_T; + +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_SET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ACL_ENTRY_GET_FUNC)(void *p_data, ZXDH_ACL_ENTRY_EX_T *acl_entry); +typedef uint32_t (*ZXDH_APT_ERAM_SET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_ERAM_GET_FUNC)(void *p_data, uint32_t buf[4]); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_SET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef uint32_t (*ZXDH_APT_HASH_ENTRY_GET_FUNC)(void *p_data, ZXDH_HASH_ENTRY *p_entry); +typedef int32_t (*ZXDH_KEY_CMP_FUNC)(void *p_new_key, void *p_old_key, uint32_t key_len); + +typedef struct zxdh_sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_SDT_TBL_ERAM_T; + +typedef struct zxdh_sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_SDT_TBL_ETCAM_T; + +typedef struct zxdh_sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_SDT_TBL_HASH_T; + +typedef enum zxdh_hash_ddr_width_mode_e { + ZXDH_DDR_WIDTH_INVALID = 0, + ZXDH_DDR_WIDTH_256b, + ZXDH_DDR_WIDTH_512b, +} ZXDH_HASH_DDR_WIDTH_MODE; + +typedef struct zxdh_apt_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_APT_ACL_RES_T; + +typedef struct zxdh_apt_hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + ZXDH_HASH_DDR_WIDTH_MODE ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_APT_HASH_BULK_RES_T; + +typedef struct zxdh_apt_hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_APT_HASH_FUNC_RES_T; + +typedef struct zxdh_apt_eram_table_t { + uint32_t sdt_no; + ZXDH_SDT_TBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_APT_ERAM_TABLE_T; + +typedef struct zxdh_apt_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_ETCAM_T acl_sdt; + ZXDH_APT_ACL_RES_T acl_res; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_APT_ACL_TABLE_T; + +typedef struct zxdh_apt_hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_SDT_TBL_HASH_T hash_sdt; + uint32_t tbl_flag; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_APT_HASH_TABLE_T; + +typedef struct zxdh_apt_eram_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ERAM_TABLE_T *eram_res; +} ZXDH_APT_ERAM_RES_INIT_T; + +typedef struct zxdh_apt_hash_res_init_t { + uint32_t func_num; + uint32_t bulk_num; + uint32_t tbl_num; + ZXDH_APT_HASH_FUNC_RES_T *func_res; + ZXDH_APT_HASH_BULK_RES_T *bulk_res; + ZXDH_APT_HASH_TABLE_T *tbl_res; +} ZXDH_APT_HASH_RES_INIT_T; + +typedef struct zxdh_apt_acl_res_init_t { + uint32_t tbl_num; + ZXDH_APT_ACL_TABLE_T *acl_res; +} ZXDH_APT_ACL_RES_INIT_T; + +typedef struct zxdh_apt_stat_res_init_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_APT_STAT_RES_INIT_T; + +typedef struct zxdh_apt_se_res_t { + uint32_t valid; + uint32_t hash_func_num; + uint32_t hash_bulk_num; + uint32_t hash_tbl_num; + uint32_t eram_num; + uint32_t acl_num; + uint32_t lpm_num; + uint32_t ddr_num; + ZXDH_APT_HASH_FUNC_RES_T hash_func[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_APT_HASH_BULK_RES_T hash_bulk[ZXDH_HASH_BULK_MAX_NUM]; + ZXDH_APT_HASH_TABLE_T hash_tbl[ZXDH_HASH_TABLE_MAX_NUM]; + ZXDH_APT_ERAM_TABLE_T eram_tbl[ZXDH_ERAM_MAX_NUM]; + ZXDH_APT_ACL_TABLE_T acl_tbl[ZXDH_ETCAM_MAX_NUM]; + ZXDH_APT_STAT_RES_INIT_T stat_cfg; +} ZXDH_APT_SE_RES_T; + +typedef struct zxdh_dev_apt_se_tbl_res_t { + ZXDH_APT_SE_RES_T std_nic_res; + ZXDH_APT_SE_RES_T offload_res; +} ZXDH_DEV_APT_SE_TBL_RES_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; @@ -511,6 +685,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; typedef struct zxdh_dev_mngr_t { @@ -779,14 +954,6 @@ typedef struct zxdh_etcam_dump_info_t { uint32_t tb_width; } ZXDH_ETCAM_DUMP_INFO_T; -typedef struct zxdh_sdt_tbl_eram_t { - uint32_t table_type; - uint32_t eram_mode; - uint32_t eram_base_addr; - uint32_t eram_table_depth; - uint32_t eram_clutch_en; -} ZXDH_SDT_TBL_ERAM_T; - typedef union zxdh_endian_u { unsigned int a; unsigned char b; @@ -838,19 +1005,6 @@ typedef struct zxdh_sdt_tbl_data_t { uint32_t data_low32; } ZXDH_SDT_TBL_DATA_T; -typedef struct zxdh_sdt_tbl_etcam_t { - uint32_t table_type; - uint32_t etcam_id; - uint32_t etcam_key_mode; - uint32_t etcam_table_id; - uint32_t no_as_rsp_mode; - uint32_t as_en; - uint32_t as_eram_baddr; - uint32_t as_rsp_mode; - uint32_t etcam_table_depth; - uint32_t etcam_clutch_en; -} ZXDH_SDT_TBL_ETCAM_T; - typedef struct zxdh_sdt_tbl_porttbl_t { uint32_t table_type; uint32_t porttbl_clutch_en; @@ -890,6 +1044,29 @@ typedef enum zxdh_msg_dtb_oper_e { ZXDH_QUEUE_RELEASE = 1, } ZXDH_MSG_DTB_OPER_E; +typedef enum zxdh_se_res_oper_e { + ZXDH_HASH_FUNC_BULK_REQ = 0, + ZXDH_HASH_TBL_REQ = 1, + ZXDH_ERAM_TBL_REQ = 2, + ZXDH_ACL_TBL_REQ = 3, + ZXDH_LPM_TBL_REQ = 4, + ZXDH_DDR_TBL_REQ = 5, + ZXDH_STAT_CFG_REQ = 6, + ZXDH_RES_REQ_MAX +} ZXDH_MSG_SE_RES_OPER_E; + +typedef enum zxdh_agent_msg_res_e { + ZXDH_RES_STD_NIC_MSG = 0, + ZXDH_RES_OFFLOAD_MSG, + ZXDH_RES_MAX_MSG +} MSG_RES_TYPE_E; + +typedef enum zxdh_se_res_type_e { + ZXDH_SE_STD_NIC_RES_TYPE = 0, + ZXDH_SE_NON_STD_NIC_RES_TYPE = 1, + ZXDH_SE_RES_TYPE_BUTT +} ZXDH_SE_RES_TYPE_E; + typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t { uint32_t cpu_ind_rw; uint32_t cpu_ind_rd_mode; @@ -1114,6 +1291,123 @@ typedef struct __rte_aligned(2) zxdh_agent_channel_dtb_msg_t { uint32_t queue_id; } ZXDH_AGENT_CHANNEL_DTB_MSG_T; +typedef struct __rte_aligned(2) zxdh_agent_se_res_msg_t { + uint8_t dev_id; + uint8_t type; + uint8_t sub_type; + uint8_t oper; +} ZXDH_AGENT_SE_RES_MSG_T; + +typedef struct __rte_aligned(2) sdt_tbl_eram_t { + uint32_t table_type; + uint32_t eram_mode; + uint32_t eram_base_addr; + uint32_t eram_table_depth; + uint32_t eram_clutch_en; +} ZXDH_NP_SDTTBL_ERAM_T; + +typedef struct __rte_aligned(2) sdt_tbl_hash_t { + uint32_t table_type; + uint32_t hash_id; + uint32_t hash_table_width; + uint32_t key_size; + uint32_t hash_table_id; + uint32_t learn_en; + uint32_t keep_alive; + uint32_t keep_alive_baddr; + uint32_t rsp_mode; + uint32_t hash_clutch_en; +} ZXDH_NP_SDTTBL_HASH_T; + +typedef struct __rte_aligned(2) sdt_tbl_etcam_t { + uint32_t table_type; + uint32_t etcam_id; + uint32_t etcam_key_mode; + uint32_t etcam_table_id; + uint32_t no_as_rsp_mode; + uint32_t as_en; + uint32_t as_eram_baddr; + uint32_t as_rsp_mode; + uint32_t etcam_table_depth; + uint32_t etcam_clutch_en; +} ZXDH_NP_SDTTBL_ETCAM_T; + +typedef struct __rte_aligned(2) hash_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_HASH_T hash_sdt; + uint32_t tbl_flag; +} ZXDH_NP_HASH_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_eram_table_t { + uint32_t sdt_no; + ZXDH_NP_SDTTBL_ERAM_T eram_sdt; + uint32_t opr_mode; + uint32_t rd_mode; +} ZXDH_NP_ERAM_TABLE_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_res_t { + uint32_t pri_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t block_index[ZXDH_ETCAM_BLOCK_NUM]; +} ZXDH_NP_ACL_RES_T; + +typedef struct __rte_aligned(2) zxdh_np_acl_table_t { + uint32_t sdt_no; + uint32_t sdt_partner; + ZXDH_NP_SDTTBL_ETCAM_T acl_sdt; + ZXDH_NP_ACL_RES_T acl_res; +} ZXDH_NP_ACL_TABLE_T; + +typedef struct __rte_aligned(2) hash_func_res_t { + uint32_t func_id; + uint32_t zblk_num; + uint32_t zblk_bitmap; + uint32_t ddr_dis; +} ZXDH_NP_HASH_FUNC_RES_T; + +typedef struct __rte_aligned(2) hash_bulk_res_t { + uint32_t func_id; + uint32_t bulk_id; + uint32_t zcell_num; + uint32_t zreg_num; + uint32_t ddr_baddr; + uint32_t ddr_item_num; + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_ecc_en; +} ZXDH_NP_HASH_BULK_RES_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_func_bulk_t { + uint32_t func_num; + uint32_t bulk_num; + ZXDH_NP_HASH_FUNC_RES_T fun[ZXDH_HASH_FUNC_MAX_NUM]; + ZXDH_NP_HASH_BULK_RES_T bulk[ZXDH_HASH_BULK_MAX_NUM]; +} ZXDH_NP_SE_HASH_FUNC_BULK_T; + +typedef struct __rte_aligned(2) zxdh_se_hash_tbl_t { + uint32_t tbl_num; + ZXDH_NP_HASH_TABLE_T table[ZXDH_HASH_TABLE_MAX_NUM]; +} ZXDH_NP_SE_HASH_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_eram_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ERAM_TABLE_T eram[ZXDH_ERAM_MAX_NUM]; +} ZXDH_NP_SE_ERAM_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_acl_tbl_t { + uint32_t tbl_num; + ZXDH_NP_ACL_TABLE_T acl[ZXDH_ETCAM_MAX_NUM]; +} ZXDH_NP_SE_ACL_TBL_T; + +typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { + uint32_t eram_baddr; + uint32_t eram_depth; + uint32_t ddr_baddr; + uint32_t ppu_ddr_offset; +} ZXDH_NP_SE_STAT_CFG_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1149,5 +1443,6 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t drop_flag, uint32_t plcr_en, uint32_t profile_id); +uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 65045 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 08/14] net/zxdh: support hash resources configuration 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (6 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 07/14] net/zxdh: get flow tables resources Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 09/14] net/zxdh: implement tables initialization Bingbin Chen ` (5 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 34908 bytes --] Implement the hash functions and tables configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 783 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 260 ++++++++++++ 2 files changed, 1043 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index e11004183d..5455dff296 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -31,6 +31,23 @@ static const char * const g_dpp_dtb_name[] = { "DOWN TAB", "UP TAB", }; +static ZXDH_SE_CFG *g_apt_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static ZXDH_SE_CFG *dpp_se_cfg[ZXDH_DEV_CHANNEL_MAX]; +static const uint16_t g_lpm_crc[ZXDH_SE_ZBLK_NUM] = { + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b, + 0x1021, 0x8005, 0x3D65, 0xab47, 0x3453, 0x0357, 0x0589, 0xa02b +}; +static uint32_t g_hash_zblk_idx[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM] = {0}; +static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { + 0x04C11DB7, + 0xF4ACFB13, + 0x20044009, + 0x00210801 +}; static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, @@ -451,6 +468,20 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) return ((p_tn == NULL) ? ZXDH_RBT_BLACK : (p_tn)->color_lsv & 0x3); } +#define ZXDH_SE_GET_ZBLK_CFG(p_se, zblk_idx) \ + (&(((ZXDH_SE_CFG *)(p_se))->zblk_info[zblk_idx])) + +#define GET_ZBLK_IDX(zcell_idx) \ + (((zcell_idx) & 0x7F) >> 2) + +#define GET_ZCELL_IDX(zcell_idx) \ + ((zcell_idx) & 0x3) + +#define ZXDH_GET_FUN_INFO(p_se, fun_id) \ + (&(((ZXDH_SE_CFG *)(p_se))->fun_info[fun_id])) + +#define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -751,6 +782,33 @@ zxdh_comm_double_link_insert_pre(ZXDH_D_NODE *p_newnode, return ZXDH_OK; } +static uint32_t +zxdh_comm_double_link_insert_last(ZXDH_D_NODE *p_newnode, ZXDH_D_HEAD *p_head) +{ + ZXDH_D_NODE *p_dnode = NULL; + + RTE_ASSERT(!(!p_head->p_next && p_head->p_prev)); + RTE_ASSERT(!(p_head->p_next && !p_head->p_prev)); + + p_dnode = p_head->p_prev; + + if (!p_dnode) { + p_head->p_next = p_newnode; + p_head->p_prev = p_newnode; + p_newnode->next = NULL; + p_newnode->prev = NULL; + } else { + p_newnode->prev = p_dnode; + p_newnode->next = NULL; + p_head->p_prev = p_newnode; + p_dnode->next = p_newnode; + } + + p_head->used++; + + return ZXDH_OK; +} + static uint32_t zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) { @@ -776,6 +834,46 @@ zxdh_comm_double_link_del(ZXDH_D_NODE *delnode, ZXDH_D_HEAD *p_head) return ZXDH_OK; } +static int32_t +zxdh_comm_double_link_default_cmp_fuc(ZXDH_D_NODE *p_data1, + ZXDH_D_NODE *p_data2, __rte_unused void *p_data) +{ + uint32_t data1 = *(uint32_t *)p_data1->data; + uint32_t data2 = *(uint32_t *)p_data2->data; + + if (data1 > data2) + return 1; + else if (data1 == data2) + return 0; + else + return -1; +} + +static uint32_t +zxdh_comm_double_link_insert_sort(ZXDH_D_NODE *p_newnode, + ZXDH_D_HEAD *p_head, ZXDH_CMP_FUNC cmp_fuc, void *cmp_data) +{ + ZXDH_D_NODE *pre_node = NULL; + + if (cmp_fuc == NULL) + cmp_fuc = zxdh_comm_double_link_default_cmp_fuc; + + if (p_head->used == 0) + return zxdh_comm_double_link_insert_1st(p_newnode, p_head); + + pre_node = p_head->p_next; + + while (pre_node != NULL) { + if (cmp_fuc(p_newnode, pre_node, cmp_data) <= 0) + return zxdh_comm_double_link_insert_pre(p_newnode, + pre_node, p_head); + else + pre_node = pre_node->next; + } + + return zxdh_comm_double_link_insert_last(p_newnode, p_head); +} + static int32_t zxdh_comm_rb_def_cmp(void *p_new, void *p_old, uint32_t key_size) { @@ -5544,6 +5642,688 @@ zxdh_np_agent_se_res_get(uint32_t dev_id, uint32_t type) p_se_res->valid = 1; return rc; } + +static uint32_t +zxdh_np_se_init_ex(uint32_t dev_id, ZXDH_SE_CFG *p_se_cfg) +{ + uint32_t i = 0; + uint32_t j = 0; + + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + if (dpp_se_cfg[dev_id] != NULL) { + PMD_DRV_LOG(DEBUG, "SE global config is already initialized."); + return ZXDH_OK; + } + + memset(p_se_cfg, 0, sizeof(ZXDH_SE_CFG)); + + p_se_cfg->dev_id = dev_id; + dpp_se_cfg[p_se_cfg->dev_id] = p_se_cfg; + + p_se_cfg->p_as_rslt_wrt_fun = NULL; + p_se_cfg->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_se_cfg, i); + + p_zblk_cfg->zblk_idx = i; + p_zblk_cfg->is_used = 0; + p_zblk_cfg->hash_arg = g_lpm_crc[i]; + p_zblk_cfg->zcell_bm = 0; + zxdh_np_init_d_node(&p_zblk_cfg->zblk_dn, p_zblk_cfg); + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + p_zcell_cfg = &p_zblk_cfg->zcell_info[j]; + + p_zcell_cfg->zcell_idx = (i << 2) + j; + p_zcell_cfg->item_used = 0; + p_zcell_cfg->mask_len = 0; + + zxdh_np_init_d_node(&p_zcell_cfg->zcell_dn, p_zcell_cfg); + + p_zcell_cfg->zcell_avl.p_key = p_zcell_cfg; + } + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_global_res_init(uint32_t dev_id) +{ + if (g_apt_se_cfg[dev_id] == NULL) { + g_apt_se_cfg[dev_id] = (ZXDH_SE_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_CFG), 0); + if (g_apt_se_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_se_init_ex(dev_id, g_apt_se_cfg[dev_id]); + + g_apt_se_cfg[dev_id]->p_client = ZXDH_COMM_VAL_TO_PTR(dev_id); + } + + return ZXDH_OK; +} + +static void +se_apt_get_zblock_index(uint32_t zblock_bitmap, uint32_t *zblk_idx) +{ + uint32_t index0 = 0; + uint32_t index1 = 0; + + for (index0 = 0; index0 < 32; index0++) { + if ((zblock_bitmap >> index0) & 0x1) { + *(zblk_idx + index1) = index0; + index1++; + } + } +} + +static uint32_t +zxdh_np_crc32_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint32_t dw_crc_poly) +{ + uint32_t dw_result = 0; + uint32_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint32_t)((dw_result & 0xff000000) ^ (p_input_key[i] << 24)); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x80000000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint16_t +zxdh_np_crc16_calc(uint8_t *p_input_key, uint32_t dw_byte_num, uint16_t dw_crc_poly) +{ + uint16_t dw_result = 0; + uint16_t dw_data_type = 0; + + uint32_t i = 0; + uint32_t j = 0; + + while (i < dw_byte_num) { + dw_data_type = (uint16_t)(((dw_result & 0xff00) ^ (p_input_key[i] << 8)) & 0xFFFF); + for (j = 0; j < 8; j++) { + if (dw_data_type & 0x8000) { + dw_data_type <<= 1; + dw_data_type ^= dw_crc_poly; + } else { + dw_data_type <<= 1; + } + } + dw_result <<= 8; + dw_result ^= dw_data_type; + + i++; + } + + return dw_result; +} + +static uint32_t +zxdh_np_se_fun_init(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = NULL; + + p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used) { + PMD_DRV_LOG(ERR, "Error[0x%x], fun_id [%d] is already used!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_SE_RC_FUN_INVALID; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 1; + + switch (fun_type) { + case (ZXDH_FUN_HASH): + p_fun_info->fun_type = ZXDH_FUN_HASH; + p_fun_info->fun_ptr = rte_zmalloc(NULL, sizeof(ZXDH_HASH_CFG), 0); + if (p_fun_info->fun_ptr == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + ((ZXDH_HASH_CFG *)(p_fun_info->fun_ptr))->p_se_info = p_se_cfg; + break; + default: + PMD_DRV_LOG(ERR, "Error, unrecgnized fun_type[ %d]", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + return ZXDH_OK; +} + +static int32_t +zxdh_np_hash_list_cmp(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void *data) +{ + uint32_t flag = 0; + uint32_t data_new = 0; + uint32_t data_pre = 0; + + flag = *(uint32_t *)data; + + if (flag == ZXDH_HASH_CMP_ZCELL) { + data_new = ((ZXDH_SE_ZCELL_CFG *)data1->data)->zcell_idx; + data_pre = ((ZXDH_SE_ZCELL_CFG *)data2->data)->zcell_idx; + } else if (flag == ZXDH_HASH_CMP_ZBLK) { + data_new = ((ZXDH_SE_ZBLK_CFG *)data1->data)->zblk_idx; + data_pre = ((ZXDH_SE_ZBLK_CFG *)data2->data)->zblk_idx; + } + + if (data_new > data_pre) + return 1; + else if (data_new == data_pre) + return 0; + else + return -1; +} + +static int32_t +zxdh_np_hash_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_old = NULL; + + p_rbkey_new = (ZXDH_HASH_RBKEY_INFO *)(p_new); + p_rbkey_old = (ZXDH_HASH_RBKEY_INFO *)(p_old); + + return memcmp(p_rbkey_new->key, p_rbkey_old->key, ZXDH_HASH_KEY_MAX); +} + +static int32_t +zxdh_np_hash_ddr_cfg_rb_key_cmp(void *p_new, void *p_old, __rte_unused uint32_t key_size) +{ + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_old = NULL; + + p_rbkey_new = (HASH_DDR_CFG *)(p_new); + p_rbkey_old = (HASH_DDR_CFG *)(p_old); + + return memcmp(&p_rbkey_new->ddr_baddr, &p_rbkey_old->ddr_baddr, sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_hash_zcam_resource_init(ZXDH_HASH_CFG *p_hash_cfg, + uint32_t zblk_num, uint32_t *zblk_idx_array) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t cmp_type = 0; + uint32_t zblk_idx = 0; + uint32_t zcell_idx = 0; + uint32_t dev_id = 0; + + ZXDH_D_HEAD *p_zblk_list = NULL; + ZXDH_D_HEAD *p_zcell_free = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + dev_id = p_hash_cfg->p_se_info->dev_id; + + p_zblk_list = &p_hash_cfg->hash_shareram.zblk_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM, p_zblk_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_zcell_free = &p_hash_cfg->hash_shareram.zcell_free_list; + rc = zxdh_comm_double_link_init(ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM, p_zcell_free); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + for (i = 0; i < zblk_num; i++) { + zblk_idx = zblk_idx_array[i]; + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, zblk_idx); + + if (p_zblk_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x]," + "ZBlock[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZBLCK, zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZBLCK; + } + + for (j = 0; j < ZXDH_SE_ZCELL_NUM; j++) { + zcell_idx = p_zblk_cfg->zcell_info[j].zcell_idx; + p_zcell_cfg = &(((ZXDH_SE_CFG *)(p_hash_cfg->p_se_info))-> + zblk_info[GET_ZBLK_IDX(zcell_idx)].zcell_info[GET_ZCELL_IDX(zcell_idx)]); + + if (p_zcell_cfg->is_used) { + PMD_DRV_LOG(ERR, "ErrorCode:[0x%x], ZBlk[%d]," + "ZCell[%d] is already used by other function!", + ZXDH_HASH_RC_INVALID_ZCELL, zblk_idx, zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_ZCELL; + } + + p_zcell_cfg->is_used = 1; + + cmp_type = ZXDH_HASH_CMP_ZCELL; + rc = zxdh_comm_double_link_insert_sort(&p_zcell_cfg->zcell_dn, + p_zcell_free, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_sort"); + } + + p_zblk_cfg->is_used = 1; + cmp_type = ZXDH_HASH_CMP_ZBLK; + rc = zxdh_comm_double_link_insert_sort(&p_zblk_cfg->zblk_dn, + p_zblk_list, zxdh_np_hash_list_cmp, &cmp_type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t zblk_num, + uint32_t *zblk_idx, + uint32_t ddr_dis) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + rc = zxdh_np_se_fun_init(p_se_cfg, (fun_id & 0xff), ZXDH_FUN_HASH); + if (rc == ZXDH_SE_RC_FUN_INVALID) + return ZXDH_OK; + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_init"); + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + p_hash_cfg->fun_id = fun_id; + p_hash_cfg->p_hash32_fun = zxdh_np_crc32_calc; + p_hash_cfg->p_hash16_fun = zxdh_np_crc16_calc; + p_hash_cfg->p_se_info = p_se_cfg; + + if (ddr_dis == 1) + p_hash_cfg->ddr_valid = 0; + else + p_hash_cfg->ddr_valid = 1; + + p_hash_cfg->hash_stat.zblock_num = zblk_num; + rc = zxdh_np_hash_zcam_resource_init(p_hash_cfg, zblk_num, zblk_idx); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_init"); + + for (i = 0; i < zblk_num; i++) + p_hash_cfg->hash_stat.zblock_array[i] = zblk_idx[i]; + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->hash_rb, + 0, + sizeof(ZXDH_HASH_RBKEY_INFO), + zxdh_np_hash_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + rc = (uint32_t)zxdh_comm_rb_init(&p_hash_cfg->ddr_cfg_rb, + 0, + sizeof(HASH_DDR_CFG), + zxdh_np_hash_ddr_cfg_rb_key_cmp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_init"); + + for (i = 0; i < zblk_num; i++) + g_hash_zblk_idx[dev_id][fun_id][i] = zblk_idx[i]; + + return rc; +} + +static uint32_t +zxdh_np_apt_hash_func_res_init(uint32_t dev_id, uint32_t func_num, + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + uint32_t zblk_idx[32] = {0}; + ZXDH_APT_HASH_FUNC_RES_T *p_hash_func_res_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < func_num; index++) { + memset(zblk_idx, 0, sizeof(zblk_idx)); + p_hash_func_res_temp = p_hash_func_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_func_res_temp); + + se_apt_get_zblock_index(p_hash_func_res_temp->zblk_bitmap, zblk_idx); + + rc = zxdh_np_hash_init(p_se_cfg, + p_hash_func_res_temp->func_id, + p_hash_func_res_temp->zblk_num, + zblk_idx, + p_hash_func_res_temp->ddr_dis); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_hash_bulk_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t bulk_id, + ZXDH_HASH_DDR_RESC_CFG_T *p_ddr_resc_cfg, + uint32_t zcell_num, + uint32_t zreg_num) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t j = 0; + uint32_t zblk_idx = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint32_t ddr_item_num = 0; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZREG_CFG *p_zreg_cfg = NULL; + HASH_DDR_CFG *p_ddr_cfg = NULL; + HASH_DDR_CFG *p_rbkey_new = NULL; + HASH_DDR_CFG *p_rbkey_rtn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_ITEM_CFG **p_item_array = NULL; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono = NULL; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, fun_id); + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + if (p_hash_cfg == NULL) { + PMD_DRV_LOG(ERR, "p_hash_cfg point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[bulk_id] != NULL) { + PMD_DRV_LOG(ERR, "fun_id[%u] bulk_id[%u] is already init," + "do not init again!", fun_id, bulk_id); + return ZXDH_OK; + } + + PMD_DRV_LOG(DEBUG, "p_hash_cfg->ddr_valid = %d!", p_hash_cfg->ddr_valid); + if (p_hash_cfg->ddr_valid == 1) { + ddr_item_num = p_ddr_resc_cfg->ddr_item_num; + if (ZXDH_DDR_WIDTH_512b == p_ddr_resc_cfg->ddr_width_mode) + ddr_item_num = p_ddr_resc_cfg->ddr_item_num >> 1; + + p_rbkey_new = (HASH_DDR_CFG *)rte_zmalloc(NULL, sizeof(HASH_DDR_CFG), 0); + if (p_rbkey_new == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->ddr_baddr = p_ddr_resc_cfg->ddr_baddr; + + p_rb_tn_new = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new == NULL) { + rte_free(p_rbkey_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + zxdh_np_init_rbt_tn(p_rb_tn_new, p_rbkey_new); + + rc = zxdh_comm_rb_insert(&p_hash_cfg->ddr_cfg_rb, + (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + PMD_DRV_LOG(DEBUG, "some bulk_id share one bulk!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + + p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + if (p_ddr_cfg->hash_ddr_arg != + GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel) || + p_ddr_cfg->width_mode != p_ddr_resc_cfg->ddr_width_mode || + p_ddr_cfg->ddr_ecc_en != p_ddr_resc_cfg->ddr_ecc_en || + p_ddr_cfg->item_num != ddr_item_num) { + PMD_DRV_LOG(ERR, "The base address is same but other ddr attribute is different"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_hash_cfg->p_bulk_ddr_info[bulk_id] = + p_hash_cfg->p_bulk_ddr_info[p_rbkey_rtn->bulk_id]; + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + } else { + p_item_array = (ZXDH_SE_ITEM_CFG **)rte_zmalloc(NULL, ddr_item_num * + sizeof(ZXDH_SE_ITEM_CFG *), 0); + if (NULL == (p_item_array)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rbkey_new->p_item_array = p_item_array; + p_rbkey_new->bulk_id = bulk_id; + p_rbkey_new->hw_baddr = 0; + p_rbkey_new->width_mode = p_ddr_resc_cfg->ddr_width_mode; + p_rbkey_new->item_num = ddr_item_num; + p_rbkey_new->ddr_ecc_en = p_ddr_resc_cfg->ddr_ecc_en; + p_rbkey_new->hash_ddr_arg = GET_DDR_HASH_ARG(p_ddr_resc_cfg->ddr_crc_sel); + p_rbkey_new->bulk_use = 1; + p_rbkey_new->zcell_num = zcell_num; + p_rbkey_new->zreg_num = zreg_num; + p_hash_cfg->p_bulk_ddr_info[bulk_id] = p_rbkey_new; + + PMD_DRV_LOG(DEBUG, "one new ddr_bulk init!"); + } + } + + p_bulk_zcam_mono = (ZXDH_HASH_BULK_ZCAM_STAT *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_BULK_ZCAM_STAT), 0); + if (NULL == (p_bulk_zcam_mono)) { + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + rte_free(p_item_array); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[bulk_id] = p_bulk_zcam_mono; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM; i++) + p_bulk_zcam_mono->zcell_mono_idx[i] = 0xffffffff; + + for (i = 0; i < ZXDH_SE_ZBLK_NUM; i++) { + for (j = 0; j < ZXDH_SE_ZREG_NUM; j++) { + p_bulk_zcam_mono->zreg_mono_id[i][j].zblk_id = 0xffffffff; + p_bulk_zcam_mono->zreg_mono_id[i][j].zreg_id = 0xffffffff; + } + } + + if (zcell_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + i = 0; + + while (p_zcell_dn) { + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + + if (p_zcell_cfg->is_used) { + if (!(p_zcell_cfg->flag & ZXDH_ZCELL_FLAG_IS_MONO)) { + p_zcell_cfg->flag |= ZXDH_ZCELL_FLAG_IS_MONO; + p_zcell_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zcell_mono_idx[p_zcell_cfg->zcell_idx] = + p_zcell_cfg->zcell_idx; + + if (++i >= zcell_num) + break; + } + } else { + PMD_DRV_LOG(ERR, "zcell[ %d ] is not init before" + " used!", p_zcell_cfg->zcell_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (i < zcell_num) + PMD_DRV_LOG(ERR, "Input param 'zcell_num' is [ %d ]," + "actually bulk[ %d ]monopolize zcells is [ %d ]!", + zcell_num, bulk_id, i); + } + + if (zreg_num > 0) { + p_hash_cfg->bulk_ram_mono[bulk_id] = 1; + + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + j = 0; + + while (p_zblk_dn) { + p_zblk_cfg = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk_cfg->zblk_idx; + + if (p_zblk_cfg->is_used) { + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg_cfg = &p_zblk_cfg->zreg_info[i]; + + if (!(p_zreg_cfg->flag & ZXDH_ZREG_FLAG_IS_MONO)) { + p_zreg_cfg->flag = ZXDH_ZREG_FLAG_IS_MONO; + p_zreg_cfg->bulk_id = bulk_id; + + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zblk_id = + zblk_idx; + p_bulk_zcam_mono->zreg_mono_id[zblk_idx][i].zreg_id = i; + + if (++j >= zreg_num) + break; + } + } + + if (j >= zreg_num) + break; + } else { + PMD_DRV_LOG(ERR, "zblk [ %d ] is not init" + " before used!", p_zblk_cfg->zblk_idx); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_zblk_dn = p_zblk_dn->next; + } + + if (j < zreg_num) + PMD_DRV_LOG(ERR, "Input param 'zreg_num' is [ %d ]," + "actually bulk[ %d ]monopolize zregs is [ %d ]!", + zreg_num, bulk_id, j); + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, + ZXDH_APT_HASH_BULK_RES_T *p_bulk_res) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_BULK_RES_T *p_hash_bulk_res_temp = NULL; + ZXDH_HASH_DDR_RESC_CFG_T ddr_resc_cfg = {0}; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < bulk_num; index++) { + memset(&ddr_resc_cfg, 0, sizeof(ZXDH_HASH_DDR_RESC_CFG_T)); + p_hash_bulk_res_temp = p_bulk_res + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_bulk_res_temp); + + ddr_resc_cfg.ddr_baddr = p_hash_bulk_res_temp->ddr_baddr; + ddr_resc_cfg.ddr_item_num = p_hash_bulk_res_temp->ddr_item_num; + ddr_resc_cfg.ddr_width_mode = p_hash_bulk_res_temp->ddr_width_mode; + ddr_resc_cfg.ddr_crc_sel = p_hash_bulk_res_temp->ddr_crc_sel; + ddr_resc_cfg.ddr_ecc_en = p_hash_bulk_res_temp->ddr_ecc_en; + + rc = zxdh_np_hash_bulk_init(p_se_cfg, + p_hash_bulk_res_temp->func_id, + p_hash_bulk_res_temp->bulk_id, + &ddr_resc_cfg, + p_hash_bulk_res_temp->zcell_num, + p_hash_bulk_res_temp->zreg_num); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_bulk_init"); + } + + return rc; +} + +static uint32_t +zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) +{ + uint32_t rc = ZXDH_OK; + ZXDH_APT_SE_RES_T *p_se_res = NULL; + ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + + p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); + if (!p_se_res->valid) { + PMD_DRV_LOG(ERR, "dev_id[0x%x],se_type[0x%x] invalid!", dev_id, type); + return ZXDH_ERR; + } + + hash_res_init.func_num = p_se_res->hash_func_num; + hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.func_res = p_se_res->hash_func; + hash_res_init.bulk_res = p_se_res->hash_bulk; + + rc = zxdh_np_apt_hash_global_res_init(dev_id); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); + + if (hash_res_init.func_num) { + rc = zxdh_np_apt_hash_func_res_init(dev_id, hash_res_init.func_num, + hash_res_init.func_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_func_res_init"); + } + + if (hash_res_init.bulk_num) { + rc = zxdh_np_apt_hash_bulk_res_init(dev_id, hash_res_init.bulk_num, + hash_res_init.bulk_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); + } + + return rc; +} + uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) { @@ -5552,6 +6332,9 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) rc = zxdh_np_agent_se_res_get(dev_id, type); ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_se_res_get"); + rc = zxdh_np_se_res_init(dev_id, type); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_res_init"); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 23acce3a70..009a50c42f 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -136,6 +136,43 @@ #define ZXDH_ERAM_MAX_NUM (60) #define ZXDH_ETCAM_MAX_NUM (8) +#define ZXDH_SE_RAM_DEPTH (512) +#define ZXDH_SE_ZCELL_NUM (4) +#define ZXDH_SE_ZREG_NUM (4) +#define ZXDH_SE_ALG_BANK_NUM (29) +#define ZXDH_SE_ZBLK_NUM (32) +#define ZXDH_MAX_FUN_NUM (8) +#define ZXDH_HASH_KEY_MAX (49) +#define ZXDH_HASH_RST_MAX (32) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_HASH_BULK_NUM (8) +#define ZXDH_HASH_CMP_ZCELL (1) +#define ZXDH_HASH_CMP_ZBLK (2) +#define ZXDH_HASH_FUNC_ID_NUM (4) +#define ZXDH_ZCELL_FLAG_IS_MONO (1) +#define ZXDH_ZREG_FLAG_IS_MONO (1) +#define ZXDH_HASH_DDR_CRC_NUM (4) +#define ZXDH_HASH_TBL_FLAG_AGE (1 << 0) +#define ZXDH_HASH_TBL_FLAG_LEARN (1 << 1) +#define ZXDH_HASH_TBL_FLAG_MC_WRT (1 << 2) +#define ZXDH_HASH_ACTU_KEY_STEP (1) +#define ZXDH_HASH_KEY_CTR_SIZE (1) +#define ZXDH_ZCELL_IDX_BT_WIDTH (2) +#define ZXDH_ZBLK_IDX_BT_WIDTH (3) +#define ZXDH_ZGRP_IDX_BT_WIDTH (2) +#define ZXDH_HASH_ENTRY_POS_STEP (16) +#define ZXDH_HASH_TBL_ID_NUM (32) +#define ZXDH_SE_ITEM_WIDTH_MAX (64) +#define ZXDH_SE_ENTRY_WIDTH_MAX (64) +#define ZXDH_REG_SRAM_FLAG_BT_START (16) +#define ZXDH_ZBLK_NUM_PER_ZGRP (8) +#define ZXDH_ZBLK_IDX_BT_START (11) +#define ZXDH_ZBLK_WRT_MASK_BT_START (17) +#define ZXDH_ZCELL_ADDR_BT_WIDTH (9) + +#define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) +#define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -253,6 +290,11 @@ #define ZXDH_HASH_RC_INVALID_ITEM_TYPE (ZXDH_SE_RC_HASH_BASE | 0x11) #define ZXDH_HASH_RC_REPEAT_INIT (ZXDH_SE_RC_HASH_BASE | 0x12) +#define ZXDH_SE_RC_CFG_BASE (ZXDH_SE_RC_BASE | 0x1000) +#define ZXDH_SE_RC_ZBLK_FULL (ZXDH_SE_RC_CFG_BASE | 0x1) +#define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) +#define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -412,6 +454,13 @@ typedef struct zxdh_rb_tn { } ZXDH_RB_TN; typedef int32_t (*ZXDH_RB_CMPFUN)(void *p_new, void *p_old, uint32_t keysize); +typedef int32_t (*ZXDH_CMP_FUNC)(ZXDH_D_NODE *data1, ZXDH_D_NODE *data2, void*); +typedef uint32_t (*ZXDH_WRITE32_FUN)(uint32_t dev_id, uint32_t addr, uint32_t write_data); +typedef uint32_t (*ZXDH_READ32_FUN) (uint32_t dev_id, uint32_t addr, uint32_t *read_data); +typedef uint32_t (*ZXDH_LPM_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t as_type, uint32_t tbl_id, uint32_t index, uint8_t *p_data); +typedef uint16_t (*ZXDH_HASH_FUNCTION)(uint8_t *pkey, uint32_t width, uint16_t arg); +typedef uint32_t (*ZXDH_HASH_FUNCTION32)(uint8_t *pkey, uint32_t width, uint32_t arg); typedef struct _rb_cfg { uint32_t key_size; @@ -425,6 +474,217 @@ typedef struct _rb_cfg { uint32_t is_init; } ZXDH_RB_CFG; +typedef enum zxdh_se_fun_type_e { + ZXDH_FUN_HASH = 1, + ZXDH_FUN_LPM, + ZXDH_FUN_ACL, + ZXDH_FUN_MAX +} ZXDH_SE_FUN_TYPE; + +typedef struct zxdh_avl_node_t { + void *p_key; + uint32_t result; + int32_t avl_height; + struct zxdh_avl_node_t *p_avl_left; + struct zxdh_avl_node_t *p_avl_right; + ZXDH_D_NODE avl_node_list; +} ZXDH_AVL_NODE; + +typedef struct zxdh_se_item_cfg_t { + ZXDH_D_HEAD item_list; + uint32_t item_index; + uint32_t hw_addr; + uint32_t bulk_id; + uint32_t item_type; + uint8_t wrt_mask; + uint8_t valid; + uint8_t pad[2]; +} ZXDH_SE_ITEM_CFG; + +typedef struct zxdh_se_zcell_cfg_t { + uint8_t flag; + uint32_t bulk_id; + uint32_t zcell_idx; + uint16_t mask_len; + uint8_t is_used; + uint8_t is_share; + uint32_t item_used; + ZXDH_SE_ITEM_CFG item_info[ZXDH_SE_RAM_DEPTH]; + ZXDH_D_NODE zcell_dn; + ZXDH_AVL_NODE zcell_avl; +} ZXDH_SE_ZCELL_CFG; + +typedef struct zxdh_se_zreg_cfg_t { + uint8_t flag; + uint8_t pad[3]; + uint32_t bulk_id; + ZXDH_SE_ITEM_CFG item_info; +} ZXDH_SE_ZREG_CFG; + +typedef struct zxdh_se_zblk_cfg_t { + uint32_t zblk_idx; + uint16_t is_used; + uint16_t zcell_bm; + uint16_t hash_arg; + uint16_t pad; + ZXDH_SE_ZCELL_CFG zcell_info[ZXDH_SE_ZCELL_NUM]; + ZXDH_SE_ZREG_CFG zreg_info[ZXDH_SE_ZREG_NUM]; + ZXDH_D_NODE zblk_dn; +} ZXDH_SE_ZBLK_CFG; + +typedef struct zxdh_func_id_info_t { + void *fun_ptr; + uint8_t fun_type; + uint8_t fun_id; + uint8_t is_used; + uint8_t pad; +} ZXDH_FUNC_ID_INFO; + +typedef struct zxdh_ddr_mem_t { + uint32_t total_num; + uint32_t base_addr; + uint32_t base_addr_offset; + uint32_t ecc_en; + uint32_t bank_num; + uint32_t bank_info[ZXDH_SE_ALG_BANK_NUM]; + uint32_t share_type; + uint32_t item_used; + ZXDH_LISTSTACK_MANAGER *p_ddr_mng; +} ZXDH_DDR_MEM; + +typedef struct zxdh_share_ram_t { + uint32_t zblk_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_D_HEAD zblk_list; + ZXDH_D_HEAD zcell_free_list; + uint32_t def_route_num; + ZXDH_RB_CFG def_rb; + struct def_route_info *p_dr_info; + ZXDH_DDR_MEM ddr4_info; + ZXDH_DDR_MEM ddr6_info; +} ZXDH_SHARE_RAM; + +typedef struct zxdh_se_cfg_t { + ZXDH_SE_ZBLK_CFG zblk_info[ZXDH_SE_ZBLK_NUM]; + ZXDH_FUNC_ID_INFO fun_info[ZXDH_MAX_FUN_NUM]; + ZXDH_SHARE_RAM route_shareram; + uint32_t reg_base; + ZXDH_WRITE32_FUN p_write32_fun; + ZXDH_READ32_FUN p_read32_fun; + uint32_t lpm_flags; + void *p_client; + uint32_t dev_id; + ZXDH_LPM_AS_RSLT_WRT_FUNCTION p_as_rslt_wrt_fun; +} ZXDH_SE_CFG; + +typedef struct hash_ddr_cfg_t { + uint32_t bulk_use; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; + uint32_t item_num; + uint32_t bulk_id; + uint32_t hash_ddr_arg; + uint32_t width_mode; + uint32_t hw_baddr; + uint32_t zcell_num; + uint32_t zreg_num; + ZXDH_SE_ITEM_CFG **p_item_array; +} HASH_DDR_CFG; + +typedef struct zxdh_hash_tbl_info_t { + uint32_t fun_id; + uint32_t actu_key_size; + uint32_t key_type; + uint8_t is_init; + uint8_t mono_zcell; + uint8_t zcell_num; + uint8_t mono_zreg; + uint8_t zreg_num; + uint8_t is_age; + uint8_t is_lrn; + uint8_t is_mc_wrt; +} ZXDH_HASH_TBL_ID_INFO; + +typedef struct zxdh_hash_rbkey_info_t { + uint8_t key[ZXDH_HASH_KEY_MAX]; + uint8_t rst[ZXDH_HASH_RST_MAX]; + ZXDH_D_NODE entry_dn; + ZXDH_SE_ITEM_CFG *p_item_info; + uint32_t entry_size; + uint32_t entry_pos; +} ZXDH_HASH_RBKEY_INFO; + +typedef struct zxdh_hash_table_stat_t { + float ddr; + float zcell; + float zreg; + float sum; +} ZXDH_HASH_TABLE_STAT; + +typedef struct zxdh_hash_zreg_mono_stat_t { + uint32_t zblk_id; + uint32_t zreg_id; +} ZXDH_HASH_ZREG_MONO_STAT; + +typedef struct zxdh_hash_bulk_zcam_stat_t { + uint32_t zcell_mono_idx[ZXDH_SE_ZBLK_NUM * ZXDH_SE_ZCELL_NUM]; + ZXDH_HASH_ZREG_MONO_STAT zreg_mono_id[ZXDH_SE_ZBLK_NUM][ZXDH_SE_ZREG_NUM]; +} ZXDH_HASH_BULK_ZCAM_STAT; + +typedef struct zxdh_hash_stat_t { + uint32_t insert_ok; + uint32_t insert_fail; + uint32_t insert_same; + uint32_t insert_ddr; + uint32_t insert_zcell; + uint32_t insert_zreg; + uint32_t delete_ok; + uint32_t delete_fail; + uint32_t search_ok; + uint32_t search_fail; + uint32_t zblock_num; + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM]; + ZXDH_HASH_TABLE_STAT insert_table[ZXDH_HASH_TBL_ID_NUM]; + ZXDH_HASH_BULK_ZCAM_STAT *p_bulk_zcam_mono[ZXDH_HASH_BULK_NUM]; +} ZXDH_HASH_STAT; + +typedef struct zxdh_hash_cfg_t { + uint32_t fun_id; + uint8_t ddr_valid; + uint8_t pad[3]; + ZXDH_HASH_FUNCTION32 p_hash32_fun; + ZXDH_HASH_FUNCTION p_hash16_fun; + HASH_DDR_CFG *p_bulk_ddr_info[ZXDH_HASH_BULK_NUM]; + uint8_t bulk_ram_mono[ZXDH_HASH_BULK_NUM]; + ZXDH_SHARE_RAM hash_shareram; + ZXDH_SE_CFG *p_se_info; + ZXDH_RB_CFG hash_rb; + ZXDH_RB_CFG ddr_cfg_rb; + ZXDH_HASH_STAT hash_stat; +} ZXDH_HASH_CFG; + +typedef struct hash_entry_cfg_t { + uint32_t fun_id; + uint8_t bulk_id; + uint8_t table_id; + uint8_t key_type; + uint8_t rsp_mode; + uint32_t actu_key_size; + uint32_t key_by_size; + uint32_t rst_by_size; + ZXDH_SE_CFG *p_se_cfg; + ZXDH_HASH_CFG *p_hash_cfg; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new; +} HASH_ENTRY_CFG; + +typedef struct zxdh_hash_ddr_resc_cfg_t { + uint32_t ddr_width_mode; + uint32_t ddr_crc_sel; + uint32_t ddr_item_num; + uint32_t ddr_baddr; + uint32_t ddr_ecc_en; +} ZXDH_HASH_DDR_RESC_CFG_T; + typedef struct zxdh_dtb_tab_up_user_addr_t { uint32_t user_flag; uint64_t phy_addr; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90514 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 09/14] net/zxdh: implement tables initialization 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (7 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 08/14] net/zxdh: support hash resources configuration Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen ` (4 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35219 bytes --] Implement hash/eram/acl/stat tables initialization. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 672 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 187 +++++++++++ 2 files changed, 859 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 5455dff296..2bacf82ff4 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -22,6 +22,9 @@ static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX]; +static SE_APT_CALLBACK_T g_apt_se_callback[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; +static ZXDH_ACL_CFG_EX_T g_apt_acl_cfg[ZXDH_DEV_CHANNEL_MAX] = {0}; +static ZXDH_ACL_CFG_EX_T *g_p_acl_ex_cfg[ZXDH_DEV_CHANNEL_MAX] = {NULL}; static uint64_t g_np_fw_compat_addr[ZXDH_DEV_CHANNEL_MAX]; static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = { ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} }; @@ -49,6 +52,10 @@ static const uint32_t g_ddr_hash_arg[ZXDH_HASH_DDR_CRC_NUM] = { 0x00210801 }; +static ZXDH_HASH_TBL_ID_INFO g_tbl_id_info[ZXDH_DEV_CHANNEL_MAX] + [ZXDH_HASH_FUNC_ID_NUM] + [ZXDH_HASH_TBL_ID_NUM]; + static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, @@ -482,6 +489,49 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_DDR_HASH_ARG(ddr_crc_sel) (g_ddr_hash_arg[ddr_crc_sel]) +#define ZXDH_SDT_GET_LOW_DATA(source_value, low_width) \ + ((source_value) & ((1 << (low_width)) - 1)) + +#define ZXDH_ACL_AS_RSLT_SIZE_GET_EX(mode) (2U << (mode)) + +#define ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) \ + ((actu_key_size) * ZXDH_HASH_ACTU_KEY_STEP) + +#define ZXDH_GET_KEY_SIZE(actu_key_size) \ + (ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) + ZXDH_HASH_KEY_CTR_SIZE) + +#define ZXDH_ACL_ENTRY_MAX_GET(key_mode, block_num) \ + ((block_num) * ZXDH_ETCAM_RAM_DEPTH * (1U << (key_mode))) + +#define ZXDH_ETCAM_ENTRY_SIZE_GET(entry_mode) \ + ((ZXDH_ETCAM_RAM_WIDTH << (3 - (entry_mode))) / 8) + +#define ZXDH_ACL_KEYSIZE_GET(key_mode) (2 * ZXDH_ETCAM_ENTRY_SIZE_GET(key_mode)) + +#define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) + + +static inline uint32_t +zxdh_np_get_hash_entry_size(uint32_t key_type) +{ + return ((key_type == ZXDH_HASH_KEY_128b) ? 16U : ((key_type == ZXDH_HASH_KEY_256b) ? 32U : + ((key_type == ZXDH_HASH_KEY_512b) ? 64U : 0))); +} + +#define ZXDH_GET_HASH_ENTRY_SIZE(key_type) \ + zxdh_np_get_hash_entry_size(key_type) + +static inline void +zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, + uint32_t start_pos, uint32_t len) +{ + uint32_t mask = ZXDH_COMM_GET_BIT_MASK(uint32_t, len) << start_pos; + *dst = (*dst & mask) | (src & mask); +} + +#define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ + zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -2177,6 +2227,231 @@ zxdh_np_sdt_init(uint32_t dev_num, uint32_t *dev_id_array) return rc; } +static uint32_t +zxdh_np_sdt_mgr_sdt_item_add(uint32_t dev_id, uint32_t sdt_no, + uint32_t sdt_hig32, uint32_t sdt_low32) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl == NULL) { + PMD_DRV_LOG(ERR, "soft sdt table not init!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_SDT_MGR_INVALID; + } + + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft sdt table item invalid!"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_VALID; + p_sdt_item->table_cfg[0] = sdt_hig32; + p_sdt_item->table_cfg[1] = sdt_low32; + + PMD_DRV_LOG(DEBUG, "0x%08x 0x%08x", p_sdt_item->table_cfg[0], p_sdt_item->table_cfg[1]); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_sdt_mgr_sdt_item_del(uint32_t dev_id, uint32_t sdt_no) +{ + ZXDH_SDT_SOFT_TABLE_T *p_sdt_soft_tbl = NULL; + ZXDH_SDT_ITEM_T *p_sdt_item = NULL; + + p_sdt_soft_tbl = ZXDH_SDT_SOFT_TBL_GET(dev_id); + + if (p_sdt_soft_tbl != NULL) { + if (dev_id != p_sdt_soft_tbl->device_id) { + PMD_DRV_LOG(ERR, "soft table item invalid !"); + RTE_ASSERT(0); + return ZXDH_RC_TABLE_PARA_INVALID; + } + + p_sdt_item = &p_sdt_soft_tbl->sdt_array[sdt_no]; + p_sdt_item->valid = ZXDH_SDT_INVALID; + p_sdt_item->table_cfg[0] = 0; + p_sdt_item->table_cfg[1] = 0; + } + PMD_DRV_LOG(DEBUG, "sdt_no: 0x%08x", sdt_no); + return ZXDH_OK; +} + +static void +zxdh_np_soft_sdt_tbl_set(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + ZXDH_SDT_TBL_DATA_T *p_sdt_info) +{ + g_table_type[dev_id][sdt_no] = table_type; + g_sdt_info[dev_id][sdt_no].data_high32 = p_sdt_info->data_high32; + g_sdt_info[dev_id][sdt_no].data_low32 = p_sdt_info->data_low32; +} + +static uint32_t +zxdh_np_sdt_tbl_write(uint32_t dev_id, + uint32_t sdt_no, + uint32_t table_type, + void *p_sdt_info, + uint32_t opr_type) +{ + uint32_t rtn = 0; + + ZXDH_SDT_TBL_DATA_T sdt_tbl = {0}; + ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL; + ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL; + ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL; + ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL; + + if (opr_type) { + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, 0, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_del(dev_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_del"); + } else { + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_mode, + ZXDH_SDT_H_ERAM_MODE_BT_POS, + ZXDH_SDT_H_ERAM_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_eram->eram_base_addr, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, + ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_table_depth, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_eram->eram_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_HASH: + p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_id, + ZXDH_SDT_H_HASH_ID_BT_POS, + ZXDH_SDT_H_HASH_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_width, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, + ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->key_size, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, + ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->hash_table_id, + ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, + ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->learn_en, + ZXDH_SDT_H_LEARN_EN_BT_POS, + ZXDH_SDT_H_LEARN_EN_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_hash->keep_alive, + ZXDH_SDT_H_KEEP_ALIVE_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_hash->keep_alive_baddr) >> + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_hash->keep_alive_baddr), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN), + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, + ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->rsp_mode, + ZXDH_SDT_L_RSP_MODE_BT_POS, + ZXDH_SDT_L_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_hash->hash_clutch_en, + ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_ETCAM: + p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_id, + ZXDH_SDT_H_ETCAM_ID_BT_POS, + ZXDH_SDT_H_ETCAM_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_key_mode, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->etcam_table_id, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, + ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->no_as_rsp_mode, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS, + ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + p_sdt_etcam->as_en, + ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, + ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, + ((p_sdt_etcam->as_eram_baddr) >> + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + ZXDH_SDT_GET_LOW_DATA((p_sdt_etcam->as_eram_baddr), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN), + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS, + ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN); + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, p_sdt_etcam->as_rsp_mode, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, + ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_table_depth, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, + ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN); + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_etcam->etcam_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + case ZXDH_SDT_TBLT_PORTTBL: + p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info; + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_low32, + p_sdt_porttbl->porttbl_clutch_en, ZXDH_SDT_L_CLUTCH_EN_BT_POS, + ZXDH_SDT_L_CLUTCH_EN_BT_LEN); + break; + + default: + PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", + table_type); + return ZXDH_ERR; + } + + ZXDH_COMM_UINT32_WRITE_BITS(sdt_tbl.data_high32, table_type, + ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN); + + zxdh_np_soft_sdt_tbl_set(dev_id, sdt_no, table_type, &sdt_tbl); + + rtn = zxdh_np_sdt_mgr_sdt_item_add(dev_id, sdt_no, sdt_tbl.data_high32, + sdt_tbl.data_low32); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rtn, "zxdh_np_sdt_mgr_sdt_item_add"); + } + + return ZXDH_OK; +} + static void zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id, uint32_t bitmap) @@ -6288,12 +6563,383 @@ zxdh_np_apt_hash_bulk_res_init(uint32_t dev_id, uint32_t bulk_num, return rc; } +static uint32_t +zxdh_np_apt_set_callback(uint32_t dev_id, uint32_t sdt_no, uint32_t table_type, void *p_data) +{ + SE_APT_CALLBACK_T *apt_func = NULL; + + apt_func = &g_apt_se_callback[dev_id][sdt_no]; + + apt_func->sdt_no = sdt_no; + apt_func->table_type = table_type; + switch (table_type) { + case ZXDH_SDT_TBLT_ERAM: + apt_func->se_func_info.eram_func.opr_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->opr_mode; + apt_func->se_func_info.eram_func.rd_mode = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->rd_mode; + apt_func->se_func_info.eram_func.eram_set_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_set_func; + apt_func->se_func_info.eram_func.eram_get_func = + ((ZXDH_APT_ERAM_TABLE_T *)p_data)->eram_get_func; + break; + case ZXDH_SDT_TBLT_HASH: + apt_func->se_func_info.hash_func.sdt_partner = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.hash_func.hash_set_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_set_func; + apt_func->se_func_info.hash_func.hash_get_func = + ((ZXDH_APT_HASH_TABLE_T *)p_data)->hash_get_func; + break; + case ZXDH_SDT_TBLT_ETCAM: + apt_func->se_func_info.acl_func.sdt_partner = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->sdt_partner; + apt_func->se_func_info.acl_func.acl_set_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_set_func; + apt_func->se_func_info.acl_func.acl_get_func = + ((ZXDH_APT_ACL_TABLE_T *)p_data)->acl_get_func; + break; + default: + PMD_DRV_LOG(ERR, "zxdh_np_apt_se_set_callback table_type[ %d ]" + "is invalid!", table_type); + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_tbl_id_info_init(ZXDH_SE_CFG *p_se_cfg, + uint32_t fun_id, + uint32_t tbl_id, + uint32_t tbl_flag, + uint32_t key_type, + uint32_t actu_key_size) +{ + uint32_t key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + uint32_t entry_size = ZXDH_GET_HASH_ENTRY_SIZE(key_type); + uint32_t dev_id = p_se_cfg->dev_id; + ZXDH_HASH_TBL_ID_INFO *p_tbl_id_info = NULL; + + if (key_by_size > entry_size) { + PMD_DRV_LOG(ERR, "ErrorCode[%x]: actu_key_size[%d] not match to key_type[%d].", + ZXDH_HASH_RC_INVALID_PARA, + key_by_size, + entry_size); + RTE_ASSERT(0); + return ZXDH_HASH_RC_INVALID_PARA; + } + + p_tbl_id_info = GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id); + + if (p_tbl_id_info->is_init) { + PMD_DRV_LOG(ERR, "fun_id[%d], table_id[%d] is already init," + "do not init again!", fun_id, tbl_id); + return ZXDH_OK; + } + + p_tbl_id_info->fun_id = fun_id; + p_tbl_id_info->actu_key_size = actu_key_size; + p_tbl_id_info->key_type = key_type; + p_tbl_id_info->is_init = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_AGE) + p_tbl_id_info->is_age = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_LEARN) + p_tbl_id_info->is_lrn = 1; + + if (tbl_flag & ZXDH_HASH_TBL_FLAG_MC_WRT) + p_tbl_id_info->is_mc_wrt = 1; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_hash_tbl_res_init(uint32_t dev_id, uint32_t tbl_num, + ZXDH_APT_HASH_TABLE_T *p_hash_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_HASH_TABLE_T *p_hash_tbl_temp = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_se_cfg = g_apt_se_cfg[dev_id]; + + for (index = 0; index < tbl_num; index++) { + p_hash_tbl_temp = p_hash_tbl + index; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_tbl_temp); + rc = zxdh_np_sdt_tbl_write(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + &p_hash_tbl_temp->hash_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_hash_tbl_id_info_init(p_se_cfg, + p_hash_tbl_temp->hash_sdt.hash_id, + p_hash_tbl_temp->hash_sdt.hash_table_id, + p_hash_tbl_temp->tbl_flag, + p_hash_tbl_temp->hash_sdt.hash_table_width, + p_hash_tbl_temp->hash_sdt.key_size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_tbl_id_info_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_hash_tbl_temp->sdt_no, + p_hash_tbl_temp->hash_sdt.table_type, + (void *)p_hash_tbl_temp); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_apt_eram_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ERAM_TABLE_T *p_eram_tbl) +{ + uint32_t rc = ZXDH_OK; + uint32_t index = 0; + ZXDH_APT_ERAM_TABLE_T *p_temp_eram_tbl = NULL; + + for (index = 0; index < tbl_num; index++) { + p_temp_eram_tbl = p_eram_tbl + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + &p_temp_eram_tbl->eram_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_eram_tbl->sdt_no, + p_temp_eram_tbl->eram_sdt.table_type, + (void *)p_temp_eram_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static uint32_t +zxdh_np_acl_entrynum_to_blocknum(uint32_t entry_num, uint32_t key_mode) +{ + uint32_t value = 0; + + value = entry_num % (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)); + + if (value == 0) + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode))); + else + return (entry_num / (ZXDH_ETCAM_RAM_DEPTH * ((uint32_t)1 << key_mode)) + 1); +} + +static int32_t +zxdh_np_acl_key_cmp(void *p_new_key, void *p_old_key, uint32_t key_len) +{ + return memcmp(&(((ZXDH_ACL_KEY_INFO_T *)p_new_key)->pri), + &(((ZXDH_ACL_KEY_INFO_T *)p_old_key)->pri), key_len - sizeof(uint32_t)); +} + +static uint32_t +zxdh_np_acl_cfg_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + void *p_client, + uint32_t flags, + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_wrt_fun) +{ + uint32_t rc = 0; + + memset(p_acl_cfg, 0, sizeof(ZXDH_ACL_CFG_EX_T)); + + p_acl_cfg->p_client = p_client; + p_acl_cfg->dev_id = (uint32_t)(ZXDH_COMM_PTR_TO_VAL(p_acl_cfg->p_client) & 0xFFFFFFFF); + p_acl_cfg->flags = flags; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (flags & ZXDH_ACL_FLAG_ETCAM0_EN) { + p_acl_cfg->acl_etcamids.is_valid = 1; + + p_acl_cfg->acl_etcamids.as_eram_base = 0; + + rc = zxdh_comm_double_link_init(ZXDH_ACL_TBL_ID_NUM, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_init"); + } + + if (p_as_wrt_fun == NULL) { + p_acl_cfg->p_as_rslt_write_fun = NULL; + p_acl_cfg->p_as_rslt_read_fun = NULL; + + } else { + p_acl_cfg->p_as_rslt_write_fun = p_as_wrt_fun; + } + + return rc; +} + +static uint32_t +zxdh_np_acl_tbl_init_ex(ZXDH_ACL_CFG_EX_T *p_acl_cfg, + uint32_t table_id, + uint32_t as_enable, + uint32_t entry_num, + ZXDH_ACL_PRI_MODE_E pri_mode, + uint32_t key_mode, + ZXDH_ACL_AS_MODE_E as_mode, + uint32_t as_baddr, + uint32_t block_num, + uint32_t *p_block_idx) +{ + uint32_t rc = 0; + uint32_t i = 0; + + g_p_acl_ex_cfg[p_acl_cfg->dev_id] = p_acl_cfg; + + if (p_acl_cfg->acl_tbls[table_id].is_used) { + PMD_DRV_LOG(ERR, "table_id[ %d ] is already used!", table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_TBLID; + } + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(ERR, "etcam is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) > block_num) { + PMD_DRV_LOG(ERR, "key_mode[ %d ], the etcam block_num[ %d ] is not enough for entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKNUM; + } else if (zxdh_np_acl_entrynum_to_blocknum(entry_num, key_mode) < block_num) { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is more than entry_num[ 0x%x ], better to reduce block_num in order to match with entry_num.", + key_mode, block_num, entry_num); + } else { + PMD_DRV_LOG(DEBUG, "key_mode[ %d ], the etcam block_num[ %d ] is match with entry_num[ 0x%x ].", + key_mode, block_num, entry_num); + } + + p_acl_cfg->acl_tbls[table_id].as_enable = as_enable; + + if (as_enable) { + p_acl_cfg->acl_tbls[table_id].as_idx_base = as_baddr; + p_acl_cfg->acl_tbls[table_id].as_rslt_buff = + rte_zmalloc(NULL, entry_num * ZXDH_ACL_AS_RSLT_SIZE_GET_EX(as_mode), 0); + if (p_acl_cfg->acl_tbls[table_id].as_rslt_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + } + + rc = (uint32_t)zxdh_comm_rb_init(&p_acl_cfg->acl_tbls[table_id].acl_rb, 0, + (sizeof(ZXDH_ACL_KEY_INFO_T) & 0xFFFFFFFFU) + ZXDH_ACL_KEYSIZE_GET(key_mode), + zxdh_np_acl_key_cmp); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_rb_init"); + + p_acl_cfg->acl_tbls[table_id].table_id = table_id; + p_acl_cfg->acl_tbls[table_id].pri_mode = pri_mode; + p_acl_cfg->acl_tbls[table_id].key_mode = key_mode; + p_acl_cfg->acl_tbls[table_id].entry_num = entry_num; + p_acl_cfg->acl_tbls[table_id].as_mode = as_mode; + p_acl_cfg->acl_tbls[table_id].is_used = 1; + + zxdh_np_init_d_node(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_tbls[table_id]); + rc = zxdh_comm_double_link_insert_last(&p_acl_cfg->acl_tbls[table_id].entry_dn, + &p_acl_cfg->acl_etcamids.tbl_list); + ZXDH_COMM_CHECK_RC(rc, "zxdh_comm_double_link_insert_last"); + + p_acl_cfg->acl_tbls[table_id].block_num = block_num; + p_acl_cfg->acl_tbls[table_id].block_array = + rte_zmalloc(NULL, block_num * sizeof(uint32_t), 0); + if (p_acl_cfg->acl_tbls[table_id].block_array == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (i = 0; i < block_num; i++) { + if (p_acl_cfg->acl_blocks[p_block_idx[i]].is_used) { + PMD_DRV_LOG(ERR, "the block[ %d ] is already used by table[ %d ]!", + p_block_idx[i], p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_INVALID_BLOCKID; + } + + p_acl_cfg->acl_tbls[table_id].block_array[i] = p_block_idx[i]; + p_acl_cfg->acl_blocks[p_block_idx[i]].is_used = 1; + p_acl_cfg->acl_blocks[p_block_idx[i]].tbl_id = table_id; + p_acl_cfg->acl_blocks[p_block_idx[i]].idx_base = + ((ZXDH_ACL_ENTRY_MAX_GET(key_mode, i)) >> ZXDH_BLOCK_IDXBASE_BIT_OFF) & + ZXDH_BLOCK_IDXBASE_BIT_MASK; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_apt_acl_res_init(uint32_t dev_id, uint32_t tbl_num, ZXDH_APT_ACL_TABLE_T *p_acl_tbl_res) +{ + uint32_t rc = ZXDH_OK; + uint8_t index = 0; + ZXDH_APT_ACL_TABLE_T *p_temp_acl_tbl = NULL; + + rc = zxdh_np_acl_cfg_init_ex(&g_apt_acl_cfg[dev_id], + (void *)ZXDH_COMM_VAL_TO_PTR(dev_id), + ZXDH_ACL_FLAG_ETCAM0_EN, + NULL); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_cfg_init_ex"); + + for (index = 0; index < tbl_num; index++) { + p_temp_acl_tbl = p_acl_tbl_res + index; + rc = zxdh_np_sdt_tbl_write(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + &p_temp_acl_tbl->acl_sdt, + ZXDH_SDT_OPER_ADD); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_sdt_tbl_write"); + + rc = zxdh_np_acl_tbl_init_ex(&g_apt_acl_cfg[dev_id], + p_temp_acl_tbl->acl_sdt.etcam_table_id, + p_temp_acl_tbl->acl_sdt.as_en, + p_temp_acl_tbl->acl_res.entry_num, + p_temp_acl_tbl->acl_res.pri_mode, + p_temp_acl_tbl->acl_sdt.etcam_key_mode, + p_temp_acl_tbl->acl_sdt.as_rsp_mode, + p_temp_acl_tbl->acl_sdt.as_eram_baddr, + p_temp_acl_tbl->acl_res.block_num, + p_temp_acl_tbl->acl_res.block_index); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_acl_tbl_init_ex"); + + rc = zxdh_np_apt_set_callback(dev_id, + p_temp_acl_tbl->sdt_no, + p_temp_acl_tbl->acl_sdt.table_type, + (void *)p_temp_acl_tbl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_apt_set_callback"); + } + + return rc; +} + +static void +zxdh_np_apt_stat_res_init(uint32_t dev_id, uint32_t type, ZXDH_APT_STAT_RES_INIT_T *stat_res_init) +{ + g_ppu_stat_cfg[dev_id].eram_baddr = stat_res_init->eram_baddr; + g_ppu_stat_cfg[dev_id].eram_depth = stat_res_init->eram_depth; + + if (type == ZXDH_SE_NON_STD_NIC_RES_TYPE) { + g_ppu_stat_cfg[dev_id].ddr_base_addr = stat_res_init->ddr_baddr; + g_ppu_stat_cfg[dev_id].ppu_addr_offset = stat_res_init->ppu_ddr_offset; + } +} + static uint32_t zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) { uint32_t rc = ZXDH_OK; ZXDH_APT_SE_RES_T *p_se_res = NULL; ZXDH_APT_HASH_RES_INIT_T hash_res_init = {0}; + ZXDH_APT_ERAM_RES_INIT_T eram_res_init = {0}; + ZXDH_APT_ACL_RES_INIT_T acl_res_init = {0}; p_se_res = (ZXDH_APT_SE_RES_T *)zxdh_np_dev_get_se_res_ptr(dev_id, type); if (!p_se_res->valid) { @@ -6303,8 +6949,14 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) hash_res_init.func_num = p_se_res->hash_func_num; hash_res_init.bulk_num = p_se_res->hash_bulk_num; + hash_res_init.tbl_num = p_se_res->hash_tbl_num; hash_res_init.func_res = p_se_res->hash_func; hash_res_init.bulk_res = p_se_res->hash_bulk; + hash_res_init.tbl_res = p_se_res->hash_tbl; + eram_res_init.tbl_num = p_se_res->eram_num; + eram_res_init.eram_res = p_se_res->eram_tbl; + acl_res_init.tbl_num = p_se_res->acl_num; + acl_res_init.acl_res = p_se_res->acl_tbl; rc = zxdh_np_apt_hash_global_res_init(dev_id); ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_global_res_init"); @@ -6321,6 +6973,26 @@ zxdh_np_se_res_init(uint32_t dev_id, uint32_t type) ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_bulk_res_init"); } + if (hash_res_init.tbl_num) { + rc = zxdh_np_apt_hash_tbl_res_init(dev_id, hash_res_init.tbl_num, + hash_res_init.tbl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_hash_tbl_res_init"); + } + + if (eram_res_init.tbl_num) { + rc = zxdh_np_apt_eram_res_init(dev_id, eram_res_init.tbl_num, + eram_res_init.eram_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_eram_res_init"); + } + + if (acl_res_init.tbl_num) { + rc = zxdh_np_apt_acl_res_init(dev_id, acl_res_init.tbl_num, + acl_res_init.acl_res); + ZXDH_COMM_CHECK_RC(rc, "zxdh_np_apt_acl_res_init"); + } + + zxdh_np_apt_stat_res_init(dev_id, type, &p_se_res->stat_cfg); + return rc; } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 009a50c42f..813afff647 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -103,6 +103,10 @@ #define ZXDH_ETCAM_WR_MASK_MAX (((uint32_t)1 << ZXDH_ETCAM_RAM_NUM) - 1) #define ZXDH_ETCAM_WIDTH_MIN (ZXDH_ETCAM_RAM_WIDTH) #define ZXDH_ETCAM_WIDTH_MAX (ZXDH_ETCAM_RAM_NUM * ZXDH_ETCAM_RAM_WIDTH) +#define ZXDH_ETCAM_RAM_DEPTH (512) +#define ZXDH_ACL_FLAG_ETCAM0_EN (1 << 0) +#define ZXDH_BLOCK_IDXBASE_BIT_OFF (9) +#define ZXDH_BLOCK_IDXBASE_BIT_MASK (0x7f) #define ZXDH_DTB_TABLE_DATA_BUFF_SIZE (16384) #define ZXDH_DTB_TABLE_CMD_SIZE_BIT (128) @@ -173,6 +177,57 @@ #define ZXDH_COMM_PTR_TO_VAL(p) ((uint64_t)(p)) #define ZXDH_COMM_VAL_TO_PTR(v) ((void *)((uint64_t)(v))) +#define ZXDH_SDT_CFG_LEN (2) +#define ZXDH_SDT_VALID (1) +#define ZXDH_SDT_INVALID (0) +#define ZXDH_SDT_OPER_ADD (0) +#define ZXDH_SDT_H_TBL_TYPE_BT_POS (29) +#define ZXDH_SDT_H_TBL_TYPE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_MODE_BT_POS (26) +#define ZXDH_SDT_H_ERAM_MODE_BT_LEN (3) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS (7) +#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN (19) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN (22) +#define ZXDH_SDT_H_HASH_ID_BT_POS (27) +#define ZXDH_SDT_H_HASH_ID_BT_LEN (2) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS (25) +#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN (2) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS (19) +#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN (6) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS (14) +#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN (5) +#define ZXDH_SDT_H_LEARN_EN_BT_POS (13) +#define ZXDH_SDT_H_LEARN_EN_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS (12) +#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN (1) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS (0) +#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN (12) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS (25) +#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN (7) +#define ZXDH_SDT_L_RSP_MODE_BT_POS (23) +#define ZXDH_SDT_L_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_ID_BT_POS (27) +#define ZXDH_SDT_H_ETCAM_ID_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS (25) +#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS (21) +#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN (4) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS (19) +#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN (2) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS (18) +#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN (1) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS (0) +#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN (18) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS (31) +#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN (1) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS (28) +#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN (3) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS (1) +#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN (20) +#define ZXDH_SDT_L_CLUTCH_EN_BT_POS (0) +#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN (1) + /**errco code */ #define ZXDH_RC_BASE (0x1000U) #define ZXDH_PARAMETER_CHK_BASE (ZXDH_RC_BASE | 0x200) @@ -295,6 +350,28 @@ #define ZXDH_SE_RC_FUN_INVALID (ZXDH_SE_RC_CFG_BASE | 0x2) #define ZXDH_SE_RC_PARA_INVALID (ZXDH_SE_RC_CFG_BASE | 0x3) +#define ZXDH_RC_TABLE_BASE (0x800) +#define ZXDH_RC_TABLE_PARA_INVALID (ZXDH_RC_TABLE_BASE | 0x0) +#define ZXDH_RC_TABLE_RANGE_INVALID (ZXDH_RC_TABLE_BASE | 0x1) +#define ZXDH_RC_TABLE_CALL_FUNC_FAIL (ZXDH_RC_TABLE_BASE | 0x2) +#define ZXDH_RC_TABLE_SDT_MSG_INVALID (ZXDH_RC_TABLE_BASE | 0x3) +#define ZXDH_RC_TABLE_SDT_MGR_INVALID (ZXDH_RC_TABLE_BASE | 0x4) +#define ZXDH_RC_TABLE_IF_VALUE_FAIL (ZXDH_RC_TABLE_BASE | 0x5) + +#define ZXDH_ACL_RC_BASE (0x60000) +#define ZXDH_ACL_RC_INVALID_TBLID (ZXDH_ACL_RC_BASE | 0x0) +#define ZXDH_ACL_RC_INVALID_BLOCKNUM (ZXDH_ACL_RC_BASE | 0x1) +#define ZXDH_ACL_RC_INVALID_BLOCKID (ZXDH_ACL_RC_BASE | 0x2) +#define ZXDH_ACL_RC_TBL_NOT_INIT (ZXDH_ACL_RC_BASE | 0x3) +#define ZXDH_ACL_RC_ETCAMID_NOT_INIT (ZXDH_ACL_RC_BASE | 0x4) +#define ZXDH_ACL_RC_AS_ERAM_NOT_ENOUGH (ZXDH_ACL_RC_BASE | 0x5) +#define ZXDH_ACL_RC_RB_TREE_FULL (ZXDH_ACL_RC_BASE | 0x6) +#define ZXDH_ACL_RC_TABLE_FULL (ZXDH_ACL_RC_BASE | 0x7) +#define ZXDH_ACL_RC_INVALID_PARA (ZXDH_ACL_RC_BASE | 0x8) +#define ZXDH_ACL_RC_DEL_SRHFAIL (ZXDH_ACL_RC_BASE | 0x9) +#define ZXDH_ACL_RC_TABLE_UPDATE (ZXDH_ACL_RC_BASE | 0xa) +#define ZXDH_ACL_RC_SRH_FAIL (ZXDH_ACL_RC_BASE | 0xb) + #define ZXDH_SCHE_RSP_LEN (2) #define ZXDH_G_PROFILE_ID_LEN (8) @@ -481,6 +558,21 @@ typedef enum zxdh_se_fun_type_e { ZXDH_FUN_MAX } ZXDH_SE_FUN_TYPE; +typedef enum zxdh_acl_as_mode_e { + ZXDH_ACL_AS_MODE_16b = 0, + ZXDH_ACL_AS_MODE_32b = 1, + ZXDH_ACL_AS_MODE_64b = 2, + ZXDH_ACL_AS_MODE_128b = 3, + ZXDH_ACL_AS_MODE_INVALID, +} ZXDH_ACL_AS_MODE_E; + +typedef enum zxdh_hash_key_type_e { + ZXDH_HASH_KEY_INVALID = 0, + ZXDH_HASH_KEY_128b, + ZXDH_HASH_KEY_256b, + ZXDH_HASH_KEY_512b, +} ZXDH_HASH_KEY_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -904,6 +996,101 @@ typedef struct zxdh_dev_apt_se_tbl_res_t { ZXDH_APT_SE_RES_T offload_res; } ZXDH_DEV_APT_SE_TBL_RES_T; +typedef struct se_apt_eram_func_t { + uint32_t opr_mode; + uint32_t rd_mode; + ZXDH_APT_ERAM_SET_FUNC eram_set_func; + ZXDH_APT_ERAM_GET_FUNC eram_get_func; +} ZXDH_SE_APT_ERAM_FUNC_T; + +typedef struct se_apt_acl_func_t { + uint32_t sdt_partner; + ZXDH_APT_ACL_ENTRY_SET_FUNC acl_set_func; + ZXDH_APT_ACL_ENTRY_GET_FUNC acl_get_func; +} ZXDH_SE_APT_ACL_FUNC_T; + +typedef struct se_apt_hash_func_t { + uint32_t sdt_partner; + ZXDH_APT_HASH_ENTRY_SET_FUNC hash_set_func; + ZXDH_APT_HASH_ENTRY_GET_FUNC hash_get_func; +} ZXDH_SE_APT_HASH_FUNC_T; + +typedef struct se_apt_callback_t { + uint32_t sdt_no; + uint32_t table_type; + union { + ZXDH_SE_APT_ERAM_FUNC_T eram_func; + ZXDH_SE_APT_ACL_FUNC_T acl_func; + ZXDH_SE_APT_HASH_FUNC_T hash_func; + } se_func_info; +} SE_APT_CALLBACK_T; + +typedef struct zxdh_acl_block_info_t { + uint32_t is_used; + uint32_t tbl_id; + uint32_t idx_base; +} ZXDH_ACL_BLOCK_INFO_T; + +typedef struct zxdh_acl_etcamid_cfg_t { + uint32_t is_valid; + uint32_t as_enable; + uint32_t as_idx_offset; + uint32_t as_eram_base; + ZXDH_D_HEAD tbl_list; +} ZXDH_ACL_ETCAMID_CFG_T; + +typedef struct zxdh_acl_key_info_t { + uint32_t handle; + uint32_t pri; + uint8_t key[0]; +} ZXDH_ACL_KEY_INFO_T; + +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_WR_FUN)(uint32_t dev_id, uint32_t tbl_type, + uint32_t tbl_id, uint32_t dir_tbl_share_type, uint32_t dir_tbl_base_addr, + uint32_t ecc_en, uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_TBL_AS_DDR_RD_FUN)(uint32_t dev_id, uint32_t base_addr, + uint32_t index, uint32_t as_mode, uint8_t *p_data); +typedef uint32_t (*ZXDH_ACL_AS_RSLT_WRT_FUNCTION)(uint32_t dev_id, + uint32_t base_addr, uint32_t index, uint32_t as_mode, uint8_t *p_data); + +typedef struct zxdh_acl_tbl_cfg_t { + uint32_t tbl_type; + uint32_t table_id; + uint8_t is_as_ddr; + uint8_t ddr_bankcp_info; + uint32_t dir_tbl_share_type; + uint8_t ddr_ecc_en; + uint32_t pri_mode; + uint32_t key_mode; + uint32_t entry_num; + uint32_t block_num; + uint32_t *block_array; + uint32_t is_used; + uint32_t as_mode; + uint32_t as_idx_base; + uint32_t as_enable; + uint32_t as_eram_base; + uint32_t ddr_baddr; + uint32_t idx_offset; + ZXDH_ACL_TBL_AS_DDR_WR_FUN p_as_ddr_wr_fun; + ZXDH_ACL_TBL_AS_DDR_RD_FUN p_as_ddr_rd_fun; + ZXDH_D_NODE entry_dn; + ZXDH_RB_CFG acl_rb; + ZXDH_ACL_KEY_INFO_T **acl_key_buff; + uint8_t *as_rslt_buff; +} ZXDH_ACL_TBL_CFG_T; + +typedef struct zxdh_acl_cfg_ex_t { + void *p_client; + uint32_t dev_id; + uint32_t flags; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_write_fun; + ZXDH_ACL_AS_RSLT_WRT_FUNCTION p_as_rslt_read_fun; + ZXDH_ACL_BLOCK_INFO_T acl_blocks[ZXDH_ACL_BLOCK_NUM]; + ZXDH_ACL_ETCAMID_CFG_T acl_etcamids; + ZXDH_ACL_TBL_CFG_T acl_tbls[ZXDH_ACL_TBL_ID_NUM]; +} ZXDH_ACL_CFG_EX_T; + typedef struct zxdh_spin_lock_t { rte_spinlock_t spinlock; } ZXDH_SPINLOCK_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 86317 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 10/14] net/zxdh: support hash tables write and delete ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (8 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 09/14] net/zxdh: implement tables initialization Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 11/14] net/zxdh: get hash table entry result Bingbin Chen ` (3 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 35121 bytes --] Implement hash tables write and delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 932 ++++++++++++++++++++++++++++++++++++- drivers/net/zxdh/zxdh_np.h | 17 + 2 files changed, 948 insertions(+), 1 deletion(-) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 2bacf82ff4..9f33897a57 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -532,6 +532,76 @@ zxdh_np_comm_uint32_write_bits(uint32_t *dst, uint32_t src, #define ZXDH_COMM_UINT32_WRITE_BITS(dst, src, start_pos, len)\ zxdh_np_comm_uint32_write_bits(&(dst), src, start_pos, len) +static inline uint32_t +zxdh_np_zblk_addr_conv(uint32_t zblk_idx) +{ + uint32_t group_size = 1 << ZXDH_ZBLK_IDX_BT_WIDTH; + uint32_t group_number = zblk_idx / ZXDH_ZBLK_NUM_PER_ZGRP; + uint32_t offset_in_group = zblk_idx % ZXDH_ZBLK_NUM_PER_ZGRP; + + return group_number * group_size + offset_in_group; +} + +static inline uint32_t +zxdh_np_zcell_addr_conv(uint32_t zcell_idx) +{ + uint32_t blk_grp_idx = (zcell_idx >> ZXDH_ZCELL_IDX_BT_WIDTH) & + ((1 << (ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1); + + uint32_t cell_idx = zcell_idx & ((1 << ZXDH_ZCELL_IDX_BT_WIDTH) - 1); + + return (zxdh_np_zblk_addr_conv(blk_grp_idx) << ZXDH_ZCELL_IDX_BT_WIDTH) | cell_idx; +} + +#define ZXDH_ZBLK_REG_ADDR_CALC(zblk_idx, offset) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | \ + (0x1 << ZXDH_REG_SRAM_FLAG_BT_START) | \ + ((zxdh_np_zblk_addr_conv(zblk_idx) & 0x1F) << ZXDH_ZBLK_IDX_BT_START) | \ + ((offset) & 0x1FF)) + +#define ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, reg_idx) \ + (ZXDH_ZBLK_REG_ADDR_CALC((zblk_idx), (0xD + (reg_idx)))) + +#define ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx) \ + ((0xF << ZXDH_ZBLK_WRT_MASK_BT_START) | (((zxdh_np_zcell_addr_conv(zcell_idx)) & \ + ((1 << (ZXDH_ZCELL_IDX_BT_WIDTH + ZXDH_ZBLK_IDX_BT_WIDTH + ZXDH_ZGRP_IDX_BT_WIDTH)) - 1)) \ + << ZXDH_ZCELL_ADDR_BT_WIDTH)) +#define ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_idx, item_idx) \ + ((ZXDH_ZCELL_BASE_ADDR_CALC(zcell_idx)) | ((item_idx) & (ZXDH_SE_RAM_DEPTH - 1))) + +static inline uint32_t +zxdh_np_get_rst_size(uint32_t key_type, uint32_t actu_key_size) +{ + return ((ZXDH_GET_HASH_ENTRY_SIZE(key_type) != 0) ? + (ZXDH_GET_HASH_ENTRY_SIZE(key_type) - ZXDH_GET_ACTU_KEY_BY_SIZE(actu_key_size) - + ZXDH_HASH_KEY_CTR_SIZE) : 0xFF); +} + +#define ZXDH_GET_RST_SIZE(key_type, actu_key_size) \ + zxdh_np_get_rst_size(key_type, actu_key_size) + +#define ZXDH_GET_HASH_KEY_TYPE(p_key) (((p_key)[0] >> 5) & 0x3) + +#define ZXDH_GET_HASH_KEY_VALID(p_key) (((p_key)[0] >> 7) & 0x1) + +#define ZXDH_GET_HASH_KEY_CTRL(valid, type, tbl_id) \ + ((((valid) & 0x1) << 7) | (((type) & 0x3) << 5) | ((tbl_id) & 0x1f)) + +static inline uint32_t +zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) +{ + return (((1U << (entry_size / 16U)) - 1U) << (4U - entry_size / 16U - entry_pos)) & 0xF; +} + +#define ZXDH_GET_HASH_ENTRY_MASK(entry_size, entry_pos) \ + zxdh_np_get_hash_entry_mask(entry_size, entry_pos) + +#define GET_HASH_DDR_HW_ADDR(base_addr, item_idx) \ + ((base_addr) + (item_idx)) + +#define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ + (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -1717,6 +1787,16 @@ zxdh_np_dev_dtb_opr_spinlock_get(uint32_t dev_id, uint32_t type, return ZXDH_OK; } +static void +zxdh_np_dev_hash_opr_spinlock_get(uint32_t dev_id, + uint32_t fun_id, ZXDH_SPINLOCK_T **p_spinlock_out) +{ + ZXDH_DEV_MGR_T *p_dev_mgr = &g_dev_mgr; + ZXDH_DEV_CFG_T *p_dev_info = p_dev_mgr->p_dev_array[dev_id]; + + *p_spinlock_out = &p_dev_info->hash_spinlock[fun_id]; +} + static uint32_t zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) { @@ -2156,7 +2236,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); - return 0; + for (i = 0; i < ZXDH_HASH_FUNC_ID_NUM; i++) + rte_spinlock_init(&p_dev_info->hash_spinlock[i].spinlock); + + return ZXDH_OK; } static uint32_t @@ -3778,6 +3861,65 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_write_entry_data(uint32_t dev_id, + uint32_t reg_sram_flag, + uint32_t zgroup_id, + uint32_t zblock_id, + uint32_t zcell_id, + uint32_t sram_addr, + uint32_t mask, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_TABLE_FORM_T dtb_zcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ZCAM, + .ram_reg_flag = reg_sram_flag, + .zgroup_id = zgroup_id, + .zblock_id = zblock_id, + .zcell_id = zcell_id, + .mask = mask, + .sram_addr = sram_addr & 0x1FF, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ZCAM, + &dtb_zcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + memcpy(p_entry->data, p_data, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ZCAM_LEN_SIZE - 1)); + + return rc; +} + +static uint32_t +zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, + uint32_t addr, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t reg_sram_flag = (addr >> 16) & 0x1; + uint32_t zgroup_id = (addr >> 14) & 0x3; + uint32_t zblock_id = (addr >> 11) & 0x7; + uint32_t zcell_id = (addr >> 9) & 0x3; + uint32_t mask = (addr >> 17) & 0xF; + uint32_t sram_addr = addr & 0x1FF; + + rc = zxdh_np_dtb_zcam_write_entry_data(dev_id, reg_sram_flag, zgroup_id, zblock_id, + zcell_id, sram_addr, mask, p_data, p_entry); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_write_entry_data"); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4453,6 +4595,783 @@ zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_hash_get_hash_info_from_sdt(uint32_t dev_id, + uint32_t sdt_no, HASH_ENTRY_CFG *p_hash_entry_cfg) +{ + uint32_t rc = ZXDH_OK; + ZXDH_FUNC_ID_INFO *p_func_info = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_SDT_TBL_HASH_T sdt_hash_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_read"); + + p_hash_entry_cfg->fun_id = sdt_hash_info.hash_id; + p_hash_entry_cfg->table_id = sdt_hash_info.hash_table_id; + p_hash_entry_cfg->bulk_id = ((p_hash_entry_cfg->table_id >> 2) & 0x7); + p_hash_entry_cfg->key_type = sdt_hash_info.hash_table_width; + p_hash_entry_cfg->rsp_mode = sdt_hash_info.rsp_mode; + p_hash_entry_cfg->actu_key_size = sdt_hash_info.key_size; + p_hash_entry_cfg->key_by_size = ZXDH_GET_KEY_SIZE(p_hash_entry_cfg->actu_key_size); + p_hash_entry_cfg->rst_by_size = ZXDH_GET_RST_SIZE(p_hash_entry_cfg->key_type, + p_hash_entry_cfg->actu_key_size); + + p_se_cfg = dpp_se_cfg[dev_id]; + p_hash_entry_cfg->p_se_cfg = p_se_cfg; + + p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, p_hash_entry_cfg->fun_id); + + p_hash_entry_cfg->p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_entry_cfg->p_hash_cfg); + + return ZXDH_OK; +} + +static void +zxdh_np_hash_set_crc_key(HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry, uint8_t *p_temp_key) +{ + uint32_t key_by_size = 0; + uint8_t temp_tbl_id = 0; + + key_by_size = p_hash_entry_cfg->key_by_size; + memcpy(p_temp_key, p_entry->p_key, key_by_size); + + temp_tbl_id = (*p_temp_key) & 0x1F; + memmove(p_temp_key, p_temp_key + 1, key_by_size - ZXDH_HASH_KEY_CTR_SIZE); + p_temp_key[key_by_size - ZXDH_HASH_KEY_CTR_SIZE] = temp_tbl_id; +} + +static uint8_t +zxdh_np_hash_sdt_partner_valid(uint32_t sdt_no, uint32_t sdt_partner, uint8_t *p_key) +{ + uint32_t rc = ZXDH_OK; + uint32_t dev_id = 0; + uint32_t key_valid = 1; + + ZXDH_SDT_TBL_HASH_T sdt_hash1 = {0}; + ZXDH_SDT_TBL_HASH_T sdt_hash2 = {0}; + + if (sdt_no == sdt_partner || + sdt_partner <= ZXDH_DEV_SDT_ID_MAX || + p_key == NULL) { + return ZXDH_FALSE; + } + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash1); + rc |= zxdh_np_soft_sdt_tbl_get(dev_id, sdt_partner, &sdt_hash2); + if (rc != ZXDH_OK) + return ZXDH_FALSE; + + if (sdt_hash1.table_type != (ZXDH_SDT_TBLT_HASH) || + sdt_hash2.table_type != ZXDH_SDT_TBLT_HASH || + sdt_hash1.hash_table_width != sdt_hash2.hash_table_width || + sdt_hash1.key_size != sdt_hash2.key_size || + sdt_hash1.rsp_mode != sdt_hash2.rsp_mode) { + return ZXDH_FALSE; + } + + *p_key = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash2.hash_table_width, + sdt_hash2.hash_table_id); + + return ZXDH_TRUE; +} + +static uint32_t +zxdh_np_hash_red_black_node_alloc(ZXDH_RB_TN **p_rb_tn_new, + ZXDH_HASH_RBKEY_INFO **p_rbkey_new) +{ + ZXDH_RB_TN *p_rb_tn_new_temp = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new_temp = NULL; + + p_rbkey_new_temp = (ZXDH_HASH_RBKEY_INFO *)rte_zmalloc(NULL, + sizeof(ZXDH_HASH_RBKEY_INFO), 0); + if (p_rbkey_new_temp == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_rb_tn_new_temp = (ZXDH_RB_TN *)rte_zmalloc(NULL, sizeof(ZXDH_RB_TN), 0); + if (p_rb_tn_new_temp == NULL) { + rte_free(p_rbkey_new_temp); + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_init_rbt_tn(p_rb_tn_new_temp, p_rbkey_new_temp); + + *p_rb_tn_new = p_rb_tn_new_temp; + *p_rbkey_new = p_rbkey_new_temp; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_hash_rb_insert(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = p_hash_entry_cfg->p_rbkey_new; + ZXDH_RB_TN *p_rb_tn_new = p_hash_entry_cfg->p_rb_tn_new; + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint32_t rst_actual_size = ((p_hash_entry_cfg->rst_by_size) > ZXDH_HASH_RST_MAX) ? + ZXDH_HASH_RST_MAX : p_hash_entry_cfg->rst_by_size; + + rc = zxdh_comm_rb_insert(&p_hash_cfg->hash_rb, (void *)p_rb_tn_new, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_FULL) { + PMD_DRV_LOG(ERR, "The red black tree is full!"); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + RTE_ASSERT(0); + return ZXDH_HASH_RC_RB_TREE_FULL; + } else if (rc == ZXDH_RBT_RC_UPDATE) { + p_hash_cfg->hash_stat.insert_same++; + PMD_DRV_LOG(DEBUG, "Hash update exist entry!"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + + memcpy(p_rbkey_rtn->rst, p_entry->p_rst, rst_actual_size); + + rte_free(p_rbkey_new); + rte_free(p_rb_tn_new); + p_hash_entry_cfg->p_rbkey_new = p_rbkey_rtn; + p_hash_entry_cfg->p_rb_tn_new = p_rb_tn_rtn; + + return ZXDH_HASH_RC_ADD_UPDATE; + } + PMD_DRV_LOG(DEBUG, "Hash insert new entry!"); + + memcpy(p_rbkey_new->rst, p_entry->p_rst, rst_actual_size); + p_rbkey_new->entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + zxdh_np_init_d_node(&p_rbkey_new->entry_dn, p_rbkey_new); + + return rc; +} + +static uint32_t +zxdh_np_hash_get_item_free_pos(uint32_t item_entry_max, + uint32_t wrt_mask, uint32_t entry_size) +{ + uint32_t i = 0; + uint32_t pos = 0xFFFFFFFF; + uint32_t mask = 0; + + for (i = 0; i < item_entry_max; i += entry_size / ZXDH_HASH_ENTRY_POS_STEP) { + mask = ZXDH_GET_HASH_ENTRY_MASK(entry_size, i); + + if (0 == (mask & wrt_mask)) { + pos = i; + break; + } + } + + return pos; +} + +static uint32_t +zxdh_np_hash_insrt_to_item(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey, + ZXDH_SE_ITEM_CFG *p_item, + uint32_t item_idx, + uint32_t item_type, + __rte_unused uint32_t insrt_key_type) +{ + uint32_t rc = ZXDH_OK; + + uint32_t free_pos = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t item_entry_max = 4; + + if (item_type == ZXDH_ITEM_DDR_256) + item_entry_max = 2; + + if (!p_item->valid) { + rc = zxdh_comm_double_link_init(item_entry_max, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_init"); + + p_rbkey->entry_pos = 0; + p_item->wrt_mask = ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, + p_rbkey->entry_pos); + p_item->item_index = item_idx; + p_item->item_type = item_type; + p_item->valid = 1; + } else { + free_pos = zxdh_np_hash_get_item_free_pos(item_entry_max, + p_item->wrt_mask, p_rbkey->entry_size); + + if (free_pos == 0xFFFFFFFF) + return ZXDH_HASH_RC_ITEM_FULL; + p_rbkey->entry_pos = free_pos; + p_item->wrt_mask |= + ZXDH_GET_HASH_ENTRY_MASK(p_rbkey->entry_size, p_rbkey->entry_pos); + } + + PMD_DRV_LOG(DEBUG, "Entry in item pos is: [%d]," + "entry size is: [%d].", free_pos, p_rbkey->entry_size); + + rc = zxdh_comm_double_link_insert_last(&p_rbkey->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_insert_last"); + + p_rbkey->p_item_info = p_item; + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_ddr(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + HASH_DDR_CFG *p_ddr_cfg = p_hash_cfg->p_bulk_ddr_info[bulk_id]; + uint8_t key_type = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + uint32_t key_by_size = 0; + uint32_t crc_value = 0; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t rc = ZXDH_OK; + + key_type = p_hash_entry_cfg->key_type; + if (ZXDH_HASH_KEY_512b == key_type && ZXDH_DDR_WIDTH_256b == p_ddr_cfg->width_mode) { + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Hash DDR width mode" + " is not match to the key type.", ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR); + return ZXDH_HASH_RC_DDR_WIDTH_MODE_ERR; + } + + key_by_size = p_hash_entry_cfg->key_by_size; + crc_value = p_hash_cfg->p_hash32_fun(p_temp_key, key_by_size, p_ddr_cfg->hash_ddr_arg); + PMD_DRV_LOG(DEBUG, "hash ddr arg is: 0x%x.crc_value is 0x%x", + p_ddr_cfg->hash_ddr_arg, crc_value); + + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_256; + if (ZXDH_DDR_WIDTH_512b == p_ddr_cfg->width_mode) { + item_idx = crc_value % p_ddr_cfg->item_num; + item_type = ZXDH_ITEM_DDR_512; + } + + PMD_DRV_LOG(DEBUG, "Hash insert in ITEM_DDR_%s," + "item_idx is: 0x%x.", + ((item_type == ZXDH_ITEM_DDR_256) ? "256" : "512"), item_idx); + + p_item = p_ddr_cfg->p_item_array[item_idx]; + if (p_item == NULL) { + p_item = (ZXDH_SE_ITEM_CFG *)rte_zmalloc(NULL, sizeof(ZXDH_SE_ITEM_CFG), 0); + if (p_item == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_ddr_cfg->p_item_array[item_idx] = p_item; + } + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + key_type); + + if (rc != ZXDH_HASH_RC_ITEM_FULL) { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_ddr++; + p_hash_cfg->hash_stat.insert_table[table_id].ddr++; + + p_item->hw_addr = GET_HASH_DDR_HW_ADDR(p_ddr_cfg->hw_baddr, item_idx); + p_item->bulk_id = p_hash_entry_cfg->bulk_id; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zcell(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + uint32_t zblk_idx = 0; + uint32_t zcell_id = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t rc = ZXDH_OK; + uint32_t crc_value = 0; + uint8_t table_id = p_hash_entry_cfg->table_id; + ZXDH_SE_CFG *p_se_cfg = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + PMD_DRV_LOG(DEBUG, "insert zcell start"); + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_zcell); + + if (((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && p_zcell->bulk_id != bulk_id) || + ((!(p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + p_zcell_dn = p_zcell_dn->next; + continue; + } + + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc_value = p_hash_cfg->p_hash16_fun(p_temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + PMD_DRV_LOG(DEBUG, "zblk_idx is [0x%x]," + "p_zblk->hash_arg is [0x%x], crc_value is [0x%x]", + zblk_idx, p_zblk->hash_arg, crc_value); + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc_value); + p_item = &p_zcell->item_info[item_idx]; + item_type = ZXDH_ITEM_RAM; + + PMD_DRV_LOG(DEBUG, "zcell_id is [0x%x]," + "item_idx is [0x%x]", zcell_id, item_idx); + + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zcell++; + p_hash_cfg->hash_stat.insert_table[table_id].zcell++; + + p_item->hw_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_insert_zreg(uint32_t dev_id, HASH_ENTRY_CFG *p_hash_entry_cfg, + __rte_unused uint8_t *p_temp_key, uint8_t *p_end_flag) +{ + ZXDH_HASH_CFG *p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_D_NODE *p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + uint8_t reg_index = 0; + uint32_t zblk_idx = 0; + uint32_t rc = ZXDH_OK; + uint8_t bulk_id = p_hash_entry_cfg->bulk_id; + uint32_t item_idx = 0xFFFFFFFF; + uint32_t item_type = 0; + uint32_t table_id = p_hash_entry_cfg->table_id; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (reg_index = 0; reg_index < ZXDH_SE_ZREG_NUM; reg_index++) { + p_zreg = &p_zblk->zreg_info[reg_index]; + + if (((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id != bulk_id) || + ((!(p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO)) && + p_hash_cfg->bulk_ram_mono[bulk_id])) { + continue; + } + + p_item = &p_zblk->zreg_info[reg_index].item_info; + item_type = ZXDH_ITEM_REG; + item_idx = reg_index; + rc = zxdh_np_hash_insrt_to_item(p_hash_cfg, + p_hash_entry_cfg->p_rbkey_new, + p_item, + item_idx, + item_type, + p_hash_entry_cfg->key_type); + + if (rc == ZXDH_HASH_RC_ITEM_FULL) { + PMD_DRV_LOG(DEBUG, "The item is full, check next."); + } else { + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_insrt_to_item"); + *p_end_flag = 1; + + p_hash_cfg->hash_stat.insert_zreg++; + p_hash_cfg->hash_stat.insert_table[table_id].zreg++; + + p_item->hw_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, + reg_index); + break; + } + } + + if (*p_end_flag) + break; + + p_zblk_dn = p_zblk_dn->next; + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_form_write(ZXDH_HASH_CFG *p_hash_cfg, + ZXDH_HASH_RBKEY_INFO *p_rbkey_new, + uint32_t actu_key_size, + ZXDH_DTB_ENTRY_T *p_entry, + __rte_unused uint32_t opr_mode) +{ + uint32_t key_type = 0; + uint32_t key_by_size = 0; + uint32_t rst_by_size = 0; + uint32_t byte_offset = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t addr; + + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + uint8_t entry_data[ZXDH_SE_ENTRY_WIDTH_MAX] = {0}; + ZXDH_SE_ITEM_CFG *p_item_info = p_rbkey_new->p_item_info; + + if (p_item_info == NULL) { + PMD_DRV_LOG(ERR, "p_item_info point null!"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + PMD_DRV_LOG(DEBUG, "zcam p_item_info->hw_addr is 0x%x", + p_item_info->hw_addr); + addr = p_item_info->hw_addr; + + p_entry_dn = p_item_info->item_list.p_next; + + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)(p_entry_dn->data); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + key_by_size = ZXDH_GET_KEY_SIZE(actu_key_size); + rst_by_size = ZXDH_GET_RST_SIZE(key_type, actu_key_size); + + byte_offset = p_rbkey->entry_pos * ZXDH_HASH_ENTRY_POS_STEP; + memcpy(entry_data + byte_offset, p_rbkey->key, key_by_size); + + byte_offset += key_by_size; + memcpy(entry_data + byte_offset, p_rbkey->rst, + ((rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size)); + + p_entry_dn = p_entry_dn->next; + } + + zxdh_np_comm_swap(entry_data, ZXDH_SE_ENTRY_WIDTH_MAX); + + zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + entry_data, + p_entry); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_RBKEY_INFO temp_rbkey = {0}; + HASH_DDR_CFG *bulk_ddr_info = NULL; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + memcpy(temp_rbkey.key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, &temp_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(ERR, "Error!there is not item in hash!"); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + memset(p_rbkey_rtn->rst, 0, sizeof(p_rbkey_rtn->rst)); + hash_entry_cfg.p_rbkey_new = p_rbkey_rtn; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_rtn; + + p_item = p_rbkey_rtn->p_item_info; + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_comm_double_link_del failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + rc = zxdh_np_dtb_hash_form_write(hash_entry_cfg.p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_DELETE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + bulk_ddr_info = p_hash_cfg->p_bulk_ddr_info[hash_entry_cfg.bulk_id]; + if (p_item->item_index > bulk_ddr_info->item_num) { + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_PAR_CHK_INVALID_INDEX; + } + bulk_ddr_info->p_item_array[p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t end_flag = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_RB_TN *p_rb_tn_new = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_new = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_np_hash_red_black_node_alloc(&p_rb_tn_new, &p_rbkey_new); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_hash_red_black_node_alloc failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + memcpy(p_rbkey_new->key, p_hash_entry->p_key, + hash_entry_cfg.key_by_size); + hash_entry_cfg.p_rbkey_new = p_rbkey_new; + hash_entry_cfg.p_rb_tn_new = p_rb_tn_new; + + rc = zxdh_np_hash_rb_insert(dev_id, &hash_entry_cfg, p_hash_entry); + if (rc != ZXDH_OK) { + if (rc == ZXDH_HASH_RC_ADD_UPDATE) { + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "dtb_hash_form_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; + } + + zxdh_np_hash_set_crc_key(&hash_entry_cfg, p_hash_entry, temp_key); + + if (p_hash_cfg->ddr_valid) { + rc = zxdh_np_hash_insert_ddr(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_ddr failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zcell(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zcell failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + rc = zxdh_np_hash_insert_zreg(dev_id, &hash_entry_cfg, temp_key, &end_flag); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + } + + if (!end_flag) { + p_hash_cfg->hash_stat.insert_fail++; + memcpy(temp_key, p_hash_entry->p_key, hash_entry_cfg.key_by_size); + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey_new, &p_rb_tn_rtn); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash_insert_zreg failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + RTE_ASSERT(p_rb_tn_new == p_rb_tn_rtn); + rte_free(p_rbkey_new); + rte_free(p_rb_tn_rtn); + PMD_DRV_LOG(ERR, "ZXDH_HASH_RC_TBL_FULL.sdt_no=%u", sdt_no); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_RC_DTB_DOWN_HASH_CONFLICT; + } + + rc = zxdh_np_dtb_hash_form_write(p_hash_cfg, + hash_entry_cfg.p_rbkey_new, + hash_entry_cfg.actu_key_size, + p_dtb_one_entry, + ZXDH_DTB_ITEM_ADD_OR_UPDATE); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "hash form write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_ERR; + } + + p_hash_cfg->hash_stat.insert_ok++; + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_apt_get_sdt_partner(uint32_t dev_id, uint32_t sdt_no) +{ + SE_APT_CALLBACK_T *p_apt_callback = NULL; + + p_apt_callback = &g_apt_se_callback[dev_id][sdt_no]; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_HASH) + return p_apt_callback->se_func_info.hash_func.sdt_partner; + + if (p_apt_callback->table_type == ZXDH_SDT_TBLT_ETCAM) + return p_apt_callback->se_func_info.acl_func.sdt_partner; + + return UINT32_MAX; +} + +static uint32_t +zxdh_np_dtb_hash_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + ZXDH_DTB_ENTRY_T *p_dtb_one_entry) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t key_valid = 1; + uint8_t key = 0; + uint32_t sdt_partner = 0; + uint8_t valid = 0; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_entry = NULL; + ZXDH_HASH_ENTRY entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + entry.p_key = temp_key; + entry.p_rst = temp_rst; + entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + sdt_hash.hash_table_width, + sdt_hash.hash_table_id); + p_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_data; + memcpy(&entry.p_key[1], p_entry->p_actu_key, + ZXDH_GET_ACTU_KEY_BY_SIZE(sdt_hash.key_size)); + memcpy(entry.p_rst, p_entry->p_rst, 4 * (0x1 << sdt_hash.rsp_mode)); + + if (del_en) { + do { + rc = zxdh_np_dtb_hash_delete(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_DEL_SRHFAIL) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_delete"); + } else { + do { + rc = zxdh_np_dtb_hash_insert(dev_id, sdt_no, &entry, p_dtb_one_entry); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + entry.p_key[0] = key; + sdt_no = sdt_partner; + } while ((rc == ZXDH_RC_DTB_DOWN_HASH_CONFLICT) && (valid == ZXDH_TRUE)); + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_insert"); + } + + *p_dtb_len = p_dtb_one_entry->data_size / ZXDH_DTB_LEN_POS_SETP + 1; + + return rc; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -4491,6 +5410,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -4568,6 +5491,13 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id, rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_HASH: + rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, + ZXDH_DTB_ITEM_DELETE, pentry->p_entry_data, + &one_dtb_len, &dtb_one_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 813afff647..90834db3d8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -10,6 +10,8 @@ #define ZXDH_OK (0) #define ZXDH_ERR (1) +#define ZXDH_TRUE (1) +#define ZXDH_FALSE (0) #define ZXDH_DISABLE (0) #define ZXDH_ENABLE (1) #define ZXDH_PORT_NAME_MAX (32) @@ -94,6 +96,12 @@ #define ZXDH_DTB_LEN_POS_SETP (16) #define ZXDH_DTB_ITEM_ADD_OR_UPDATE (0) #define ZXDH_DTB_ITEM_DELETE (1) +#define ZXDH_DTB_ZCAM_LEN_SIZE (5) +#define ZXDH_DTB_DUMP_ZCAM_TYPE (0) +#define ZXDH_DTB_DUMP_DDR_TYPE (1) +#define ZXDH_DTB_DMUP_DATA_MAX (64 * 1024 * 1024) +#define ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE (1024 * 4) +#define ZXDH_DTB_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_LEN_SIZE (6) #define ZXDH_ETCAM_BLOCK_NUM (8) @@ -573,6 +581,14 @@ typedef enum zxdh_hash_key_type_e { ZXDH_HASH_KEY_512b, } ZXDH_HASH_KEY_TYPE; +typedef enum zxdh_se_item_type_e { + ZXDH_ITEM_INVALID = 0, + ZXDH_ITEM_RAM, + ZXDH_ITEM_DDR_256, + ZXDH_ITEM_DDR_512, + ZXDH_ITEM_REG, +} ZXDH_SE_ITEM_TYPE; + typedef struct zxdh_avl_node_t { void *p_key; uint32_t result; @@ -1132,6 +1148,7 @@ typedef struct dpp_dev_cfg_t { ZXDH_SPINLOCK_T dtb_spinlock; ZXDH_SPINLOCK_T smmu0_spinlock; ZXDH_SPINLOCK_T dtb_queue_spinlock[ZXDH_DTB_QUEUE_NUM_MAX]; + ZXDH_SPINLOCK_T hash_spinlock[ZXDH_HASH_FUNC_ID_NUM]; ZXDH_DEV_APT_SE_TBL_RES_T dev_apt_se_tbl_res; } ZXDH_DEV_CFG_T; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90744 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 11/14] net/zxdh: get hash table entry result 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (9 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 12/14] net/zxdh: delete all hash entries Bingbin Chen ` (2 subsequent siblings) 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 16534 bytes --] Implement hash tables get operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 479 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 7 + 2 files changed, 486 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 9f33897a57..e6793ba09e 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -1304,6 +1304,40 @@ zxdh_comm_rb_insert(ZXDH_RB_CFG *p_rb_cfg, return ZXDH_OK; } +static uint32_t +zxdh_comm_rb_search(ZXDH_RB_CFG *p_rb_cfg, + void *p_key, + void *out_val) +{ + int32_t cmprtn = 0; + ZXDH_RB_TN *p_cur_tn = NULL; + + p_cur_tn = p_rb_cfg->p_root; + + while (p_cur_tn) { + cmprtn = p_rb_cfg->p_cmpfun(p_key, p_cur_tn->p_key, p_rb_cfg->key_size); + + if (cmprtn > 0) + p_cur_tn = p_cur_tn->p_right; + else if (cmprtn < 0) + p_cur_tn = p_cur_tn->p_left; + else + break; + } + + if (!p_cur_tn) { + PMD_DRV_LOG(DEBUG, "rb srh fail"); + return ZXDH_RBT_RC_SRHFAIL; + } + + if (p_rb_cfg->is_dynamic) + *(ZXDH_RB_TN **)out_val = p_cur_tn; + else + *(uint32_t *)out_val = zxdh_np_get_tn_lsv(p_cur_tn); + + return ZXDH_OK; +} + static uint32_t zxdh_comm_rb_handle_del(__rte_unused ZXDH_RB_CFG *p_rb_cfg, ZXDH_RB_TN ***stack_tn, @@ -3946,6 +3980,38 @@ zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ZCAM_DUMP_FORM_T dtb_zcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ZCAM, + .tb_width = tb_width, + .sram_addr = addr & 0x1FF, + .ram_reg_flag = (addr >> 16) & 0x1, + .z_reg_cell_id = (addr >> 9) & 0x3, + .zblock_id = (addr >> 11) & 0x7, + .zgroup_id = (addr >> 14) & 0x3, + .tb_depth = depth, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ZCAM, + &dtb_zcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5989,6 +6055,397 @@ zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no, return rc; } +static uint32_t +zxdh_np_dtb_se_zcam_dma_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t *p_data, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_dst_phy_haddr = 0; + uint32_t dump_dst_phy_laddr = 0; + uint32_t queue_item_index = 0; + uint32_t data_len = 0; + uint32_t desc_len = 0; + uint32_t tb_width_len = 0; + uint8_t form_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + PMD_DRV_LOG(DEBUG, "table up item queue_element_id is: %d.", + queue_item_index); + + *element_id = queue_item_index; + + rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, queue_item_index, + &dump_dst_phy_haddr, &dump_dst_phy_laddr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get"); + + rc = zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + dump_dst_phy_haddr, + dump_dst_phy_laddr, + (uint32_t *)form_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_zcam_dump_info_write"); + + tb_width_len = ZXDH_DTB_LEN_POS_SETP << tb_width; + data_len = depth * tb_width_len / 4; + desc_len = ZXDH_DTB_LEN_POS_SETP / 4; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, queue_id, queue_item_index, + (uint32_t *)form_buff, data_len, desc_len, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_desc_info"); + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_parse(uint32_t item_type, + uint32_t key_by_size, + ZXDH_HASH_ENTRY *p_entry, + uint8_t *p_item_data, + uint32_t *p_data_offset) +{ + uint32_t data_offset = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint32_t temp_entry_size = 0; + uint8_t srh_key_type = 0; + uint32_t srh_entry_size = 0; + uint32_t rst_by_size = 0; + uint8_t srh_succ = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_srh_key = NULL; + uint8_t *p_temp_key = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_temp_key = p_item_data; + p_srh_key = p_entry->p_key; + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_srh_key); + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(srh_key_type); + + while (data_offset < item_width) { + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + + if (temp_key_valid && srh_key_type == temp_key_type) { + if (memcmp(p_srh_key, p_temp_key, key_by_size) == 0) { + PMD_DRV_LOG(DEBUG, "Hash search hardware successfully."); + srh_succ = 1; + break; + } + + data_offset += srh_entry_size; + } else if (temp_key_valid && (srh_key_type != temp_key_type)) { + temp_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(temp_key_type); + data_offset += temp_entry_size; + } else { + data_offset += ZXDH_HASH_ENTRY_POS_STEP; + } + + p_temp_key = p_item_data; + p_temp_key += data_offset; + } + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "Hash search hardware fail."); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + rst_by_size = srh_entry_size - key_by_size; + memcpy(p_entry->p_rst, p_temp_key + key_by_size, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + *p_data_offset = data_offset; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get_hardware(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + p_zblk = &p_se_cfg->zblk_info[zblk_idx]; + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_software_item_check(ZXDH_HASH_ENTRY *p_entry, + uint32_t key_by_size, + uint32_t rst_by_size, + ZXDH_SE_ITEM_CFG *p_item_info) +{ + uint8_t srh_succ = 0; + uint8_t temp_key_type = 0; + uint8_t srh_key_type = 0; + uint32_t dev_id = 0; + ZXDH_D_NODE *p_entry_dn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + + srh_key_type = ZXDH_GET_HASH_KEY_TYPE(p_entry->p_key); + p_entry_dn = p_item_info->item_list.p_next; + while (p_entry_dn) { + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_entry_dn->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rbkey); + + RTE_ASSERT(p_rbkey->p_item_info == p_item_info); + + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + + if (ZXDH_GET_HASH_KEY_VALID(p_rbkey->key) && srh_key_type == temp_key_type) { + if (memcmp(p_entry->p_key, p_rbkey->key, key_by_size) == 0) { + srh_succ = 1; + break; + } + } + + p_entry_dn = p_entry_dn->next; + } + + if (p_rbkey == NULL) + return ZXDH_PAR_CHK_POINT_NULL; + + if (!srh_succ) { + PMD_DRV_LOG(DEBUG, "hash search failed!"); + return ZXDH_HASH_RC_MATCH_ITEM_FAIL; + } + + memcpy(p_entry->p_rst, p_rbkey->rst, + (rst_by_size > ZXDH_HASH_RST_MAX) ? ZXDH_HASH_RST_MAX : rst_by_size); + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_hash_get_software(uint32_t dev_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SPINLOCK_T *p_hash_spinlock = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + zxdh_np_dev_hash_opr_spinlock_get(dev_id, p_hash_cfg->fun_id, &p_hash_spinlock); + rte_spinlock_lock(&p_hash_spinlock->spinlock); + + rc = zxdh_comm_rb_search(&p_hash_cfg->hash_rb, (void *)&srh_rbkey, (void *)(&p_rb_tn_rtn)); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + PMD_DRV_LOG(DEBUG, "zxdh_comm_rb_search fail."); + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return ZXDH_OK; + } + + p_rbkey = p_rb_tn_rtn->p_key; + p_item = p_rbkey->p_item_info; + + rc = zxdh_np_dtb_hash_software_item_check(p_hash_entry, + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size, + p_item); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search software succ."); + *p_srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + } + + rte_spinlock_unlock(&p_hash_spinlock->spinlock); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_get(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + uint32_t srh_mode, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + + if (srh_mode == ZXDH_HASH_SRH_MODE_HDW) { + rc = zxdh_np_dtb_hash_zcam_get_hardware(dev_id, queue_id, + p_hash_entry_cfg, p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get_hardware"); + } else { + rc = zxdh_np_dtb_hash_get_software(dev_id, p_hash_entry_cfg, + p_hash_entry, p_srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_get_software"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry, + uint32_t srh_mode) +{ + uint32_t rc = ZXDH_OK; + uint8_t srh_succ = 0; + uint8_t key_valid = 1; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_HASH_ENTRY hash_entry = {0}; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t temp_rst[ZXDH_HASH_RST_MAX] = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + hash_entry.p_key = temp_key; + hash_entry.p_rst = temp_rst; + hash_entry.p_key[0] = ZXDH_GET_HASH_KEY_CTRL(key_valid, + hash_entry_cfg.key_type, + hash_entry_cfg.table_id); + + memcpy(&hash_entry.p_key[1], p_dtb_hash_entry->p_actu_key, + hash_entry_cfg.actu_key_size); + + if (!srh_succ) { + rc = zxdh_np_dtb_hash_zcam_get(dev_id, queue_id, &hash_entry_cfg, + &hash_entry, srh_mode, &srh_succ); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_zcam_get"); + } + + if (!srh_succ) { + p_hash_cfg->hash_stat.search_fail++; + PMD_DRV_LOG(DEBUG, "Hash search key fail!"); + return ZXDH_HASH_RC_SRH_FAIL; + } + + memcpy(p_dtb_hash_entry->p_rst, hash_entry.p_rst, + 1 << (hash_entry_cfg.rsp_mode + 2)); + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -5999,6 +6456,9 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t tbl_type = 0; uint32_t rc; uint32_t sdt_no; + uint32_t sdt_partner = 0; + uint32_t valid = 0; + uint8_t key = 0; sdt_no = get_entry->sdt_no; zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl); @@ -6013,6 +6473,25 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data); ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get"); break; + case ZXDH_SDT_TBLT_HASH: + do { + rc = zxdh_np_dtb_hash_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_HASH_ENTRY_INFO_T *)get_entry->p_entry_data, + srh_mode); + sdt_partner = zxdh_np_apt_get_sdt_partner(dev_id, sdt_no); + valid = zxdh_np_hash_sdt_partner_valid(sdt_no, sdt_partner, &key); + sdt_no = sdt_partner; + } while ((rc == ZXDH_HASH_RC_SRH_FAIL) && (valid == ZXDH_TRUE)); + + if (rc == ZXDH_HASH_RC_SRH_FAIL) { + PMD_DRV_LOG(DEBUG, "hash search failed"); + return rc; + } + + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 90834db3d8..14d6cc2e9d 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1320,6 +1320,13 @@ typedef enum zxdh_dtb_tab_up_user_addr_type_e { ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_MAX, } ZXDH_DTB_TAB_UP_USER_ADDR_TYPE_E; +typedef enum zxdh_dtb_dump_zcam_width_e { + ZXDH_DTB_DUMP_ZCAM_128b = 0, + ZXDH_DTB_DUMP_ZCAM_256b = 1, + ZXDH_DTB_DUMP_ZCAM_512b = 2, + ZXDH_DTB_DUMP_ZCAM_RSV = 3, +} ZXDH_DTB_DUMP_ZCAM_WIDTH_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 47559 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 12/14] net/zxdh: delete all hash entries 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (10 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 11/14] net/zxdh: get hash table entry result Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 14/14] net/zxdh: modify parameters of the plcr function Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 37788 bytes --] Implement hash table entries all delete operation by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_ethdev.c | 57 ++ drivers/net/zxdh/zxdh_np.c | 1050 ++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 10 + 3 files changed, 1117 insertions(+) diff --git a/drivers/net/zxdh/zxdh_ethdev.c b/drivers/net/zxdh/zxdh_ethdev.c index ea34b9229b..8e1c5274ad 100644 --- a/drivers/net/zxdh/zxdh_ethdev.c +++ b/drivers/net/zxdh/zxdh_ethdev.c @@ -1119,6 +1119,30 @@ zxdh_np_dtb_data_res_free(struct zxdh_hw *hw) zxdh_shared_data->np_init_done = 0; } +static int +zxdh_tbl_entry_online_destroy(struct rte_eth_dev *dev) +{ + struct zxdh_hw *hw = dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + uint32_t sdt_no; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d ", + dev->data->name, sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_online_delete(hw->dev_id, dtb_data->queueid, sdt_no); + if (ret) + PMD_DRV_LOG(ERR, "%s sdt_no %d failed. code:%d", + dev->data->name, sdt_no, ret); + } + return ret; +} + static void zxdh_np_uninit(struct rte_eth_dev *dev) { @@ -1130,6 +1154,8 @@ zxdh_np_uninit(struct rte_eth_dev *dev) if (!dtb_data->init_done && !dtb_data->dev_refcnt) return; + zxdh_tbl_entry_online_destroy(dev); + if (--dtb_data->dev_refcnt == 0) zxdh_np_dtb_data_res_free(hw); } @@ -1796,18 +1822,49 @@ zxdh_init_once(struct rte_eth_dev *eth_dev) return ret; } +static int +zxdh_tbl_entry_offline_destroy(struct zxdh_hw *hw) +{ + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; + int ret = 0; + if (!dtb_data->init_done) + return ret; + if (hw->is_pf) { + uint32_t sdt_no; + sdt_no = ZXDH_SDT_L2_ENTRY_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + sdt_no = ZXDH_SDT_MC_TABLE0 + hw->hash_search_index; + ret = zxdh_np_dtb_hash_offline_delete(hw->dev_id, dtb_data->queueid, sdt_no, 0); + if (ret) + PMD_DRV_LOG(ERR, "sdt_no %d delete failed. code:%d ", sdt_no, ret); + } + return ret; +} + static int zxdh_np_init(struct rte_eth_dev *eth_dev) { struct zxdh_hw *hw = eth_dev->data->dev_private; + struct zxdh_dtb_shared_data *dtb_data = &hw->dev_sd->dtb_sd; int ret = 0; + if (hw->is_pf && dtb_data->init_done) { + dtb_data->dev_refcnt++; + zxdh_tbl_entry_offline_destroy(hw); + PMD_DRV_LOG(INFO, "no need to init dtb dtb chanenl %d devref %d", + dtb_data->queueid, dtb_data->dev_refcnt); + return 0; + } + if (hw->is_pf) { ret = zxdh_np_dtb_res_init(eth_dev); if (ret) { PMD_DRV_LOG(ERR, "np dtb init failed, ret:%d", ret); return ret; } + zxdh_tbl_entry_offline_destroy(hw); } if (hw->is_pf) { diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index e6793ba09e..110629f903 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -510,6 +510,7 @@ zxdh_np_get_tn_color(ZXDH_RB_TN *p_tn) #define GET_HASH_TBL_ID_INFO(dev_id, fun_id, tbl_id) (&g_tbl_id_info[dev_id][fun_id][tbl_id]) +#define ZXDH_GET_HASH_TBL_ID(p_key) ((p_key)[0] & 0x1F) static inline uint32_t zxdh_np_get_hash_entry_size(uint32_t key_type) @@ -1724,6 +1725,20 @@ zxdh_np_se_apt_rb_delete(ZXDH_RB_CFG *rb_cfg, void *p_data, __rte_unused uint32_ return rc; } +static uint32_t +zxdh_np_se_apt_rb_search(ZXDH_RB_CFG *rb_cfg, void *p_data, uint32_t len) +{ + uint32_t rc = ZXDH_OK; + ZXDH_RB_TN *p_rb_rtn = NULL; + + rc = zxdh_comm_rb_search(rb_cfg, p_data, &p_rb_rtn); + if (rc != ZXDH_OK) + return rc; + + memcpy(p_data, p_rb_rtn->p_key, len); + return rc; +} + static uint32_t zxdh_np_dev_init(void) { @@ -3741,6 +3756,219 @@ zxdh_np_dev_del(uint32_t dev_id) } } +static uint32_t +zxdh_np_hash_soft_all_entry_delete(ZXDH_SE_CFG *p_se_cfg, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t dev_id = p_se_cfg->dev_id; + uint8_t table_id = 0; + uint32_t bulk_id = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey_rtn = NULL; + ZXDH_SE_ITEM_CFG *p_item = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_HASH_CFG *p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + ZXDH_D_HEAD *p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + + while (p_head_hash_rb->used) { + p_node = p_head_hash_rb->p_next; + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + bulk_id = ((table_id >> 2) & 0x7); + + rc = zxdh_comm_rb_delete(&p_hash_cfg->hash_rb, p_rbkey, &p_rb_tn_rtn); + if (rc == ZXDH_RBT_RC_SRHFAIL) { + p_hash_cfg->hash_stat.delete_fail++; + PMD_DRV_LOG(DEBUG, "Error!there is not item in hash!"); + return ZXDH_HASH_RC_DEL_SRHFAIL; + } + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_rbkey_rtn = (ZXDH_HASH_RBKEY_INFO *)(p_rb_tn_rtn->p_key); + p_item = p_rbkey_rtn->p_item_info; + + rc = zxdh_comm_double_link_del(&p_rbkey_rtn->entry_dn, &p_item->item_list); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_item->wrt_mask &= ~(ZXDH_GET_HASH_ENTRY_MASK(p_rbkey_rtn->entry_size, + p_rbkey_rtn->entry_pos)) & 0xF; + + if (p_item->item_list.used == 0) { + if (p_item->item_type == ZXDH_ITEM_DDR_256 || + p_item->item_type == ZXDH_ITEM_DDR_512) { + p_hash_cfg->p_bulk_ddr_info[bulk_id]->p_item_array + [p_item->item_index] = NULL; + rte_free(p_item); + } else { + p_item->valid = 0; + } + } + + rte_free(p_rbkey_rtn); + rte_free(p_rb_tn_rtn); + p_hash_cfg->hash_stat.delete_ok++; + } + + return rc; +} + +static uint32_t +zxdh_np_hash_zcam_resource_deinit(ZXDH_HASH_CFG *p_hash_cfg) +{ + uint32_t rc = 0; + uint32_t dev_id = p_hash_cfg->p_se_info->dev_id; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_D_HEAD *p_head = &p_hash_cfg->hash_shareram.zcell_free_list; + ZXDH_SE_ZBLK_CFG *p_zblk_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell_cfg = NULL; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + p_zcell_cfg = (ZXDH_SE_ZCELL_CFG *)p_node->data; + p_zcell_cfg->is_used = 0; + p_zcell_cfg->flag = 0; + } + + p_head = &p_hash_cfg->hash_shareram.zblk_list; + + while (p_head->used) { + p_node = p_head->p_next; + + rc = zxdh_comm_double_link_del(p_node, p_head); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_double_link_del"); + + p_zblk_cfg = ZXDH_SE_GET_ZBLK_CFG(p_hash_cfg->p_se_info, + ((ZXDH_SE_ZBLK_CFG *)p_node->data)->zblk_idx); + p_zblk_cfg->is_used = 0; + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) + p_zblk_cfg->zreg_info[i].flag = 0; + } + + return rc; +} + +static uint32_t +zxdh_np_se_fun_deinit(ZXDH_SE_CFG *p_se_cfg, + uint8_t id, + uint32_t fun_type) +{ + ZXDH_FUNC_ID_INFO *p_fun_info = ZXDH_GET_FUN_INFO(p_se_cfg, id); + + if (p_fun_info->is_used == 0) { + PMD_DRV_LOG(ERR, " Error[0x%x], fun_id [%d] is already deinit!", + ZXDH_SE_RC_FUN_INVALID, id); + return ZXDH_OK; + } + + switch (fun_type) { + case (ZXDH_FUN_HASH): + if (p_fun_info->fun_ptr) { + rte_free(p_fun_info->fun_ptr); + p_fun_info->fun_ptr = NULL; + } + break; + default: + PMD_DRV_LOG(ERR, " Error, unrecgnized fun_type[ %d] ", fun_type); + RTE_ASSERT(0); + return ZXDH_SE_RC_BASE; + } + + p_fun_info->fun_id = id; + p_fun_info->is_used = 0; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_one_hash_soft_uninstall(uint32_t dev_id, uint32_t hash_id) +{ + uint32_t rc = 0; + uint32_t i = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_SE_CFG *p_se_cfg = dpp_se_cfg[dev_id]; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_RB_TN *p_rb_tn_rtn = NULL; + HASH_DDR_CFG *p_rbkey = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_FUNC_ID_INFO *p_func_info = ZXDH_GET_FUN_INFO(p_se_cfg, hash_id); + ZXDH_D_HEAD *p_head_ddr_cfg_rb = NULL; + HASH_DDR_CFG *p_temp_rbkey = NULL; + + if (p_func_info->is_used == 0) { + PMD_DRV_LOG(INFO, "Error[0x%x], fun_id [%d] is not init!", + ZXDH_SE_RC_FUN_INVALID, hash_id); + return ZXDH_OK; + } + + rc = zxdh_np_hash_soft_all_entry_delete(p_se_cfg, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_soft_all_entry_delete"); + + p_hash_cfg = (ZXDH_HASH_CFG *)p_func_info->fun_ptr; + for (i = 0; i < ZXDH_HASH_BULK_NUM; i++) { + if (p_hash_cfg->hash_stat.p_bulk_zcam_mono[i] != NULL) { + rte_free((&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i]); + (&p_hash_cfg->hash_stat)->p_bulk_zcam_mono[i] = NULL; + } + } + + p_head_ddr_cfg_rb = &p_hash_cfg->ddr_cfg_rb.tn_list; + while (p_head_ddr_cfg_rb->used) { + p_node = p_head_ddr_cfg_rb->p_next; + + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + p_rbkey = p_rb_tn->p_key; + + rc = zxdh_comm_rb_delete(&p_hash_cfg->ddr_cfg_rb, p_rbkey, &p_rb_tn_rtn); + + if (rc == ZXDH_RBT_RC_SRHFAIL) + PMD_DRV_LOG(ERR, "ddr_cfg_rb delete key is not exist, key: 0x"); + else + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_comm_rb_delete"); + + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn_rtn); + p_temp_rbkey = (HASH_DDR_CFG *)(p_rb_tn_rtn->p_key); + rte_free(p_temp_rbkey->p_item_array); + p_temp_rbkey->p_item_array = NULL; + rte_free(p_temp_rbkey); + rte_free(p_rb_tn_rtn); + } + + rc = zxdh_np_hash_zcam_resource_deinit(p_hash_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_zcam_resource_deinit"); + + rc = zxdh_np_se_fun_deinit(p_se_cfg, (hash_id & 0xff), ZXDH_FUN_HASH); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_se_fun_deinit"); + + memset(g_tbl_id_info[dev_id][hash_id], 0, + ZXDH_HASH_TBL_ID_NUM * sizeof(ZXDH_HASH_TBL_ID_INFO)); + + return rc; +} + +static uint32_t +zxdh_np_hash_soft_uninstall(uint32_t dev_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t hash_id = 0; + + for (hash_id = 0; hash_id < ZXDH_HASH_FUNC_ID_NUM; hash_id++) { + rc = zxdh_np_one_hash_soft_uninstall(dev_id, hash_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_one_hash_soft_uninstall"); + } + + return rc; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3752,6 +3980,10 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != 0) PMD_DRV_LOG(ERR, "dtb release port name %s queue id %d", port_name, queue_id); + rc = zxdh_np_hash_soft_uninstall(dev_id); + if (rc != ZXDH_OK) + PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4012,6 +4244,25 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, + uint32_t addr, + uint32_t tb_width, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_zcam_dump_info_write(dev_id, + addr, + tb_width, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5747,6 +5998,29 @@ zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id, return rc; } +static void +zxdh_np_dtb_tab_up_item_offset_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint32_t addr_offset, + uint32_t *p_phy_haddr, + uint32_t *p_phy_laddr) +{ + uint64_t addr = 0; + + if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) == + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) + addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index); + else + addr = ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) + + ZXDH_DTB_ITEM_ACK_SIZE; + + addr = addr + addr_offset; + + *p_phy_haddr = (addr >> 32) & 0xffffffff; + *p_phy_laddr = addr & 0xffffffff; +} + static uint32_t zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id, uint32_t queue_id, @@ -5960,6 +6234,101 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id, return 0; } +static uint32_t +zxdh_np_dtb_tab_up_item_user_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t item_index, + uint64_t phy_addr, + uint64_t vir_addr) +{ + ZXDH_DTB_MGR_T *p_dtb_mgr = NULL; + + p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id); + if (p_dtb_mgr == NULL) { + PMD_DRV_LOG(ERR, "DTB Manager is not exist!"); + return ZXDH_RC_DTB_MGR_NOT_EXIST; + } + + if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) { + PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id); + return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT; + } + + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].phy_addr = phy_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].vir_addr = vir_addr; + p_dtb_mgr->queue_info[queue_id].tab_up.user_addr[item_index].user_flag = + ZXDH_DTB_TAB_UP_USER_ADDR_TYPE; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_dump_sdt_addr_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint64_t *phy_addr, + uint64_t *vir_addr, + uint32_t *size) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ADDR_INFO_T dtb_dump_addr_info = {0}; + ZXDH_RB_CFG *p_dtb_dump_addr_rb = NULL; + + dtb_dump_addr_info.sdt_no = sdt_no; + p_dtb_dump_addr_rb = zxdh_np_dtb_dump_addr_rb_get(dev_id, queue_id); + rc = zxdh_np_se_apt_rb_search(p_dtb_dump_addr_rb, &dtb_dump_addr_info, + sizeof(ZXDH_DTB_ADDR_INFO_T)); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(INFO, "search sdt_no %d success.", sdt_no); + } else { + PMD_DRV_LOG(ERR, "search sdt_no %d fail.", sdt_no); + return rc; + } + + *phy_addr = dtb_dump_addr_info.phy_addr; + *vir_addr = dtb_dump_addr_info.vir_addr; + *size = dtb_dump_addr_info.size; + + return rc; +} + +static uint32_t +zxdh_np_dtb_dump_addr_set(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t dump_element_id = 0; + uint64_t phy_addr = 0; + uint64_t vir_addr = 0; + uint32_t size = 0; + + rc = zxdh_np_dtb_dump_sdt_addr_get(dev_id, + queue_id, + sdt_no, + &phy_addr, + &vir_addr, + &size); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_sdt_addr_get"); + memset((uint8_t *)vir_addr, 0, size); + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_free_item_get"); + + rc = zxdh_np_dtb_tab_up_item_user_addr_set(dev_id, + queue_id, + dump_element_id, + phy_addr, + vir_addr); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_set"); + + *element_id = dump_element_id; + + return rc; +} + static uint32_t zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id, uint32_t queue_id, @@ -8419,6 +8788,687 @@ zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type) return rc; } +static uint32_t +zxdh_np_dtb_hash_zcam_del_one_hw(uint32_t dev_id, + uint32_t queue_id, + HASH_ENTRY_CFG *p_hash_entry_cfg, + ZXDH_HASH_ENTRY *p_hash_entry, + ZXDH_DTB_ENTRY_T *p_entry, + uint8_t *p_srh_succ) +{ + uint32_t rc = ZXDH_OK; + ZXDH_HASH_RBKEY_INFO srh_rbkey = {0}; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + + uint32_t zblk_idx = 0; + uint32_t pre_zblk_idx = 0xFFFFFFFF; + uint16_t crc16_value = 0; + uint32_t zcell_id = 0; + uint32_t item_idx = 0; + uint32_t element_id = 0; + uint32_t byte_offset = 0; + uint32_t addr = 0; + uint32_t i = 0; + uint8_t srh_succ = 0; + uint8_t temp_key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rd_buff[ZXDH_SE_ITEM_WIDTH_MAX] = {0}; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_D_NODE *p_zcell_dn = NULL; + ZXDH_SE_CFG *p_se_cfg = NULL; + + memcpy(srh_rbkey.key, p_hash_entry->p_key, p_hash_entry_cfg->key_by_size); + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_se_cfg = p_hash_entry_cfg->p_se_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_se_cfg); + + zxdh_np_hash_set_crc_key(p_hash_entry_cfg, p_hash_entry, temp_key); + + p_zcell_dn = p_hash_cfg->hash_shareram.zcell_free_list.p_next; + while (p_zcell_dn) { + p_zcell = (ZXDH_SE_ZCELL_CFG *)p_zcell_dn->data; + zblk_idx = GET_ZBLK_IDX(p_zcell->zcell_idx); + + if (zblk_idx != pre_zblk_idx) { + pre_zblk_idx = zblk_idx; + crc16_value = p_hash_cfg->p_hash16_fun(temp_key, + p_hash_entry_cfg->key_by_size, p_zblk->hash_arg); + } + + zcell_id = GET_ZCELL_IDX(p_zcell->zcell_idx); + item_idx = GET_ZCELL_CRC_VAL(zcell_id, crc16_value); + addr = ZXDH_ZBLK_ITEM_ADDR_CALC(p_zcell->zcell_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, p_hash_entry_cfg->key_by_size, + p_hash_entry, rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zcell."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + + p_zcell_dn = p_zcell_dn->next; + } + + if (srh_succ == 0) { + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblk_idx = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + item_idx = i; + addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblk_idx, item_idx); + rc = zxdh_np_dtb_se_zcam_dma_dump(dev_id, + queue_id, + addr, + ZXDH_DTB_DUMP_ZCAM_512b, + 1, + (uint32_t *)rd_buff, + &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_zcam_dma_dump"); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + + rc = zxdh_np_dtb_hash_data_parse(ZXDH_ITEM_RAM, + p_hash_entry_cfg->key_by_size, p_hash_entry, + rd_buff, &byte_offset); + if (rc == ZXDH_OK) { + PMD_DRV_LOG(DEBUG, "Hash search hardware succ in zreg."); + srh_succ = 1; + p_hash_cfg->hash_stat.search_ok++; + break; + } + } + p_zblk_dn = p_zblk_dn->next; + } + } + + if (srh_succ) { + memset(rd_buff + byte_offset, 0, + ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type)); + zxdh_np_comm_swap(rd_buff, sizeof(rd_buff)); + rc = zxdh_np_dtb_se_alg_zcam_data_write(dev_id, + addr, + rd_buff, + p_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_alg_zcam_data_write"); + p_hash_cfg->hash_stat.delete_ok++; + } + + *p_srh_succ = srh_succ; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_zcam_del_hw(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t entry_num, + ZXDH_DTB_HASH_ENTRY_INFO_T *p_arr_hash_entry, + uint32_t *element_id) +{ + uint32_t rc = ZXDH_OK; + uint32_t item_cnt = 0; + uint32_t key_valid = 1; + uint32_t dtb_len = 0; + uint8_t srh_succ = 0; + uint8_t key[ZXDH_HASH_KEY_MAX] = {0}; + uint8_t rst[ZXDH_HASH_RST_MAX] = {0}; + uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t *p_data_buff = NULL; + + ZXDH_HASH_ENTRY entry = {0}; + ZXDH_DTB_ENTRY_T dtb_one_entry = {0}; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + dtb_one_entry.cmd = entry_cmd; + dtb_one_entry.data = entry_data; + entry.p_key = key; + entry.p_rst = rst; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_data_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0); + if (p_data_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + for (item_cnt = 0; item_cnt < entry_num; ++item_cnt) { + srh_succ = 0; + memset(key, 0, sizeof(key)); + memset(rst, 0, sizeof(rst)); + memset(entry_cmd, 0, sizeof(entry_cmd)); + memset(entry_data, 0, sizeof(entry_data)); + entry.p_key[0] = (uint8_t)(((key_valid & 0x1) << 7) + | ((hash_entry_cfg.key_type & 0x3) << 5) + | (hash_entry_cfg.table_id & 0x1f)); + memcpy(&entry.p_key[1], p_arr_hash_entry[item_cnt].p_actu_key, + hash_entry_cfg.actu_key_size); + + rc = zxdh_np_dtb_hash_zcam_del_one_hw(dev_id, + queue_id, + &hash_entry_cfg, + &entry, + &dtb_one_entry, + &srh_succ); + + if (srh_succ) { + zxdh_np_dtb_data_write(p_data_buff, 0, &dtb_one_entry); + dtb_len = dtb_one_entry.data_size / ZXDH_DTB_LEN_POS_SETP + 1; + zxdh_np_dtb_write_down_table_data(dev_id, queue_id, + dtb_len * ZXDH_DTB_LEN_POS_SETP, p_data_buff, element_id); + rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, + queue_id, *element_id); + } + } + + rte_free(p_data_buff); + + return rc; +} + +static uint32_t +zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + HASH_ENTRY_CFG *p_hash_entry_cfg, + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + + uint32_t i = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_D_NODE *p_zblk_dn = NULL; + ZXDH_SE_ZBLK_CFG *p_zblk = NULL; + ZXDH_SE_ZREG_CFG *p_zreg = NULL; + ZXDH_SE_ZCELL_CFG *p_zcell = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + dtb_dump_entry.cmd = cmd_buff; + + p_hash_cfg = p_hash_entry_cfg->p_hash_cfg; + p_zblk_dn = p_hash_cfg->hash_shareram.zblk_list.p_next; + + while (p_zblk_dn) { + p_zblk = (ZXDH_SE_ZBLK_CFG *)p_zblk_dn->data; + zblock_id = p_zblk->zblk_idx; + + for (i = 0; i < ZXDH_SE_ZCELL_NUM; i++) { + p_zcell = &p_zblk->zcell_info[i]; + + if ((p_zcell->flag & ZXDH_ZCELL_FLAG_IS_MONO) && + p_zcell->bulk_id == p_hash_entry_cfg->bulk_id) { + zcell_id = p_zcell->zcell_idx; + + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d Mono Zcell_id :%d", + zblock_id, p_hash_entry_cfg->bulk_id, zcell_id); + } + } + + for (i = 0; i < ZXDH_SE_ZREG_NUM; i++) { + p_zreg = &p_zblk->zreg_info[i]; + + if ((p_zreg->flag & ZXDH_ZREG_FLAG_IS_MONO) && + p_zreg->bulk_id == p_hash_entry_cfg->bulk_id) { + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, i); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, 1, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, + &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + + PMD_DRV_LOG(DEBUG, "the Zblock[%d]'s bulk_id:%d" + " Mono Zreg_id :%d", zblock_id, p_zreg->bulk_id, i); + } + } + + p_zblk_dn = p_zblk_dn->next; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_table_zcam_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + uint32_t zblock_num, + uint32_t zblock_array[ZXDH_SE_ZBLK_NUM], + uint8_t *p_data, + uint32_t *p_dump_len) +{ + uint32_t rc = ZXDH_OK; + uint32_t zblk_idx = 0; + uint32_t index = 0; + uint32_t zblock_id = 0; + uint32_t zcell_id = 0; + uint32_t start_addr = 0; + uint32_t dtb_desc_len = 0; + uint32_t dump_pa_h = 0; + uint32_t dump_pa_l = 0; + uint32_t dma_addr_offset = 0; + uint32_t desc_addr_offset = 0; + uint32_t element_id = 0; + uint8_t *p_dump_desc_buf = NULL; + + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + rc = zxdh_np_dtb_dump_addr_set(dev_id, queue_id, sdt_no, &element_id); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_addr_set"); + + p_dump_desc_buf = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (p_dump_desc_buf == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + dtb_dump_entry.cmd = cmd_buff; + for (zblk_idx = 0; zblk_idx < zblock_num; zblk_idx++) { + zblock_id = zblock_array[zblk_idx]; + for (index = 0; index < ZXDH_SE_ZCELL_NUM; index++) { + zcell_id = zblock_id * ZXDH_SE_ZCELL_NUM + index; + start_addr = ZXDH_ZBLK_ITEM_ADDR_CALC(zcell_id, 0); + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, + ZXDH_DTB_DUMP_ZCAM_512b, ZXDH_SE_RAM_DEPTH, + dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, + desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_RAM_DEPTH * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + element_id, + dma_addr_offset, + &dump_pa_h, + &dump_pa_l); + + start_addr = ZXDH_ZBLK_HASH_LIST_REG_ADDR_CALC(zblock_id, 0); + zxdh_np_dtb_zcam_dump_entry(dev_id, start_addr, ZXDH_DTB_DUMP_ZCAM_512b, + ZXDH_SE_ZREG_NUM, dump_pa_h, dump_pa_l, &dtb_dump_entry); + + zxdh_np_dtb_data_write(p_dump_desc_buf, desc_addr_offset, &dtb_dump_entry); + + dtb_desc_len++; + dma_addr_offset += ZXDH_SE_ZREG_NUM * 512 / 8; + desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + } + + zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + element_id, + (uint32_t *)p_dump_desc_buf, + dma_addr_offset / 4, + dtb_desc_len * 4, + (uint32_t *)p_data); + + zxdh_np_comm_swap(p_data, dma_addr_offset); + rte_free(p_dump_desc_buf); + + *p_dump_len = dma_addr_offset; + + return rc; +} + +static void +zxdh_np_dtb_dump_hash_parse(HASH_ENTRY_CFG *p_hash_entry_cfg, + uint32_t item_type, + uint8_t *pdata, + uint32_t dump_len, + uint8_t *p_outdata, + uint32_t *p_item_num) +{ + uint32_t item_num = 0; + uint32_t data_offset = 0; + uint32_t index = 0; + uint8_t temp_key_valid = 0; + uint8_t temp_key_type = 0; + uint8_t temp_tbl_id = 0; + uint32_t srh_entry_size = 0; + uint32_t item_width = ZXDH_SE_ITEM_WIDTH_MAX; + uint8_t *p_temp_key = NULL; + uint8_t *p_hash_item = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + + if (item_type == ZXDH_ITEM_DDR_256) + item_width = item_width / 2; + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_outdata; + srh_entry_size = ZXDH_GET_HASH_ENTRY_SIZE(p_hash_entry_cfg->key_type); + + for (index = 0; index < (dump_len / item_width); index++) { + data_offset = 0; + p_hash_item = pdata + index * item_width; + while (data_offset < item_width) { + p_temp_key = p_hash_item + data_offset; + temp_key_valid = ZXDH_GET_HASH_KEY_VALID(p_temp_key); + temp_key_type = ZXDH_GET_HASH_KEY_TYPE(p_temp_key); + temp_tbl_id = ZXDH_GET_HASH_TBL_ID(p_temp_key); + p_temp_entry = p_dtb_hash_entry + item_num; + + if (temp_key_valid && temp_key_type == p_hash_entry_cfg->key_type && + temp_tbl_id == p_hash_entry_cfg->table_id) { + memcpy(p_temp_entry->p_actu_key, p_temp_key + 1, + p_hash_entry_cfg->actu_key_size); + memcpy(p_temp_entry->p_rst, + p_temp_key + p_hash_entry_cfg->key_by_size, + p_hash_entry_cfg->rst_by_size); + item_num++; + } + + data_offset += srh_entry_size; + } + } + + *p_item_num = item_num; +} + +static uint32_t +zxdh_np_dtb_hash_table_dump(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_DUMP_INDEX_T start_index, + uint8_t *p_dump_data, + uint32_t *p_entry_num, + ZXDH_DTB_DUMP_INDEX_T *next_start_index, + uint32_t *finish_flag) +{ + uint32_t rc = ZXDH_OK; + uint8_t *p_data = NULL; + uint32_t data_len = 0; + uint32_t entry_num = 0; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_data = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_DMUP_DATA_MAX, 0); + if (p_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + if (start_index.index_type == ZXDH_DTB_DUMP_ZCAM_TYPE) { + if (p_hash_cfg->bulk_ram_mono[hash_entry_cfg.bulk_id]) { + rc = zxdh_np_dtb_sdt_hash_zcam_mono_space_dump(dev_id, + queue_id, + sdt_no, + &hash_entry_cfg, + p_data, + &data_len); + } else { + rc = zxdh_np_dtb_hash_table_zcam_dump(dev_id, + queue_id, + sdt_no, + p_hash_cfg->hash_stat.zblock_num, + p_hash_cfg->hash_stat.zblock_array, + p_data, + &data_len); + } + + zxdh_np_dtb_dump_hash_parse(&hash_entry_cfg, + ZXDH_ITEM_RAM, + p_data, + data_len, + p_dump_data, + &entry_num); + + if (p_hash_cfg->ddr_valid) { + next_start_index->index = 0; + next_start_index->index_type = ZXDH_DTB_DUMP_DDR_TYPE; + } else { + *finish_flag = 1; + } + *p_entry_num = entry_num; + } + + rte_free(p_data); + return rc; +} + +static uint32_t +zxdh_np_dtb_hash_offline_zcam_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no) +{ + uint32_t rc = ZXDH_OK; + uint32_t entry_num = 0; + uint32_t finish_flag = 0; + uint32_t index = 0; + uint32_t max_item_num = 1024 * 1024; + uint8_t *p_dump_data = NULL; + uint8_t *p_key = NULL; + uint8_t *p_rst = NULL; + uint32_t element_id = 0; + + ZXDH_DTB_HASH_ENTRY_INFO_T *p_dtb_hash_entry = NULL; + ZXDH_DTB_HASH_ENTRY_INFO_T *p_temp_entry = NULL; + ZXDH_DTB_DUMP_INDEX_T start_index = {0}; + ZXDH_DTB_DUMP_INDEX_T next_start_index = {0}; + + ZXDH_SDT_TBL_HASH_T sdt_hash = {0}; + start_index.index = 0; + start_index.index_type = ZXDH_DTB_DUMP_ZCAM_TYPE; + + rc = zxdh_np_soft_sdt_tbl_get(0, sdt_no, &sdt_hash); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + p_dump_data = (uint8_t *)rte_zmalloc(NULL, max_item_num * + sizeof(ZXDH_DTB_HASH_ENTRY_INFO_T), 0); + if (p_dump_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_key = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_KEY_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_rst = (uint8_t *)rte_zmalloc(NULL, max_item_num * ZXDH_HASH_RST_MAX, 0); + if (p_key == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(p_dump_data); + rte_free(p_key); + return ZXDH_PAR_CHK_POINT_NULL; + } + + p_dtb_hash_entry = (ZXDH_DTB_HASH_ENTRY_INFO_T *)p_dump_data; + for (index = 0; index < max_item_num; index++) { + p_temp_entry = p_dtb_hash_entry + index; + p_temp_entry->p_actu_key = p_key + index * ZXDH_HASH_KEY_MAX; + p_temp_entry->p_rst = p_rst + index * ZXDH_HASH_RST_MAX; + } + + rc = zxdh_np_dtb_hash_table_dump(0, queue_id, sdt_no, start_index, + p_dump_data, &entry_num, &next_start_index, &finish_flag); + + if (entry_num) { + rc = zxdh_np_dtb_hash_zcam_del_hw(0, queue_id, sdt_no, + entry_num, p_dtb_hash_entry, &element_id); + } + + rte_free(p_dtb_hash_entry); + rte_free(p_key); + rte_free(p_rst); + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no) +{ + uint32_t rc = 0; + uint8_t key_valid = 0; + uint32_t table_id = 0; + uint32_t key_type = 0; + + ZXDH_D_NODE *p_node = NULL; + ZXDH_RB_TN *p_rb_tn = NULL; + ZXDH_D_HEAD *p_head_hash_rb = NULL; + ZXDH_HASH_CFG *p_hash_cfg = NULL; + ZXDH_HASH_RBKEY_INFO *p_rbkey = NULL; + HASH_ENTRY_CFG hash_entry_cfg = {0}; + ZXDH_DTB_USER_ENTRY_T del_entry = {0}; + ZXDH_DTB_HASH_ENTRY_INFO_T hash_entry = {0}; + + del_entry.sdt_no = sdt_no; + del_entry.p_entry_data = &hash_entry; + + rc = zxdh_np_hash_get_hash_info_from_sdt(dev_id, sdt_no, &hash_entry_cfg); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_hash_get_hash_info_from_sdt"); + + p_hash_cfg = hash_entry_cfg.p_hash_cfg; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_hash_cfg); + + p_head_hash_rb = &p_hash_cfg->hash_rb.tn_list; + p_node = p_head_hash_rb->p_next; + while (p_node) { + p_rb_tn = (ZXDH_RB_TN *)p_node->data; + ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_rb_tn); + p_rbkey = (ZXDH_HASH_RBKEY_INFO *)p_rb_tn->p_key; + hash_entry.p_actu_key = p_rbkey->key + 1; + hash_entry.p_rst = p_rbkey->key; + + key_valid = ZXDH_GET_HASH_KEY_VALID(p_rbkey->key); + table_id = ZXDH_GET_HASH_TBL_ID(p_rbkey->key); + key_type = ZXDH_GET_HASH_KEY_TYPE(p_rbkey->key); + if (!key_valid || + table_id != hash_entry_cfg.table_id || + key_type != hash_entry_cfg.key_type) { + p_node = p_node->next; + continue; + } + p_node = p_node->next; + + rc = zxdh_np_dtb_table_entry_delete(dev_id, queue_id, 1, &del_entry); + if (rc == ZXDH_HASH_RC_DEL_SRHFAIL) + continue; + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_table_entry_delete"); + } + + return rc; +} + +uint32_t +zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode) +{ + uint32_t rc = ZXDH_OK; + + rc = zxdh_np_dtb_hash_offline_zcam_delete(dev_id, queue_id, sdt_no); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_offline_zcam_delete"); + + return rc; +} + static uint32_t zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) { diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 14d6cc2e9d..228d217a50 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1879,6 +1879,11 @@ typedef struct __rte_aligned(2) zxdh_se_stat_cfg_t { uint32_t ppu_ddr_offset; } ZXDH_NP_SE_STAT_CFG_T; +typedef struct zxdh_dtb_dump_index_t { + uint32_t index; + uint32_t index_type; +} ZXDH_DTB_DUMP_INDEX_T; + int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl); int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id); int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -1915,5 +1920,10 @@ uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t plcr_en, uint32_t profile_id); uint32_t zxdh_np_se_res_get_and_init(uint32_t dev_id, uint32_t type); +uint32_t zxdh_np_dtb_hash_online_delete(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no); +uint32_t zxdh_np_dtb_hash_offline_delete(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + __rte_unused uint32_t flush_mode); #endif /* ZXDH_NP_H */ -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 107422 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 13/14] net/zxdh: add acl tables ops 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (11 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 12/14] net/zxdh: delete all hash entries Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 14/14] net/zxdh: modify parameters of the plcr function Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 31244 bytes --] Implement acl table entry write/read/delete operations by dtb channel. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_np.c | 895 +++++++++++++++++++++++++++++++++++++ drivers/net/zxdh/zxdh_np.h | 31 ++ 2 files changed, 926 insertions(+) diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 110629f903..0303d4885f 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -603,6 +603,11 @@ zxdh_np_get_hash_entry_mask(uint32_t entry_size, uint32_t entry_pos) #define GET_ZCELL_CRC_VAL(zcell_id, crc16_val) \ (((crc16_val) >> (zcell_id)) & (ZXDH_SE_RAM_DEPTH - 1)) +#define ZXDH_COMM_DM_TO_X(d, m) ((d) & ~(m)) +#define ZXDH_COMM_DM_TO_Y(d, m) (~(d) & ~(m)) +#define ZXDH_COMM_XY_TO_MASK(x, y) (~(x) & ~(y)) +#define ZXDH_COMM_XY_TO_DATA(x, y) (x) + static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = { {"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0}, {"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0}, @@ -3969,6 +3974,65 @@ zxdh_np_hash_soft_uninstall(uint32_t dev_id) return rc; } +static uint32_t +zxdh_np_acl_cfg_get(uint32_t dev_id, ZXDH_ACL_CFG_EX_T **p_acl_cfg) +{ + if (g_p_acl_ex_cfg[dev_id] == NULL) { + PMD_DRV_LOG(ERR, "etcam_is not init!"); + RTE_ASSERT(0); + return ZXDH_ACL_RC_ETCAMID_NOT_INIT; + } + + *p_acl_cfg = g_p_acl_ex_cfg[dev_id]; + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_acl_res_destroy(uint32_t dev_id) +{ + uint32_t table_id = 0; + uint32_t as_enable = 0; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + if (!p_acl_cfg->acl_etcamids.is_valid) { + PMD_DRV_LOG(DEBUG, "etcam is not init!"); + return ZXDH_OK; + } + + for (table_id = ZXDH_ACL_TBL_ID_MIN; table_id <= ZXDH_ACL_TBL_ID_MAX; table_id++) { + p_tbl_cfg = p_acl_cfg->acl_tbls + table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(DEBUG, "table_id[ %d ] is not used!", table_id); + continue; + } + + zxdh_comm_rb_destroy(&p_tbl_cfg->acl_rb); + + as_enable = p_tbl_cfg->as_enable; + if (as_enable) { + if (p_tbl_cfg->as_rslt_buff) { + rte_free(p_tbl_cfg->as_rslt_buff); + p_tbl_cfg->as_rslt_buff = NULL; + } + } + + if (p_tbl_cfg->block_array) { + rte_free(p_tbl_cfg->block_array); + p_tbl_cfg->block_array = NULL; + } + + p_tbl_cfg->is_used = 0; + } + + p_acl_cfg->acl_etcamids.is_valid = 0; + + return ZXDH_OK; +} + int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, @@ -3984,6 +4048,7 @@ zxdh_np_online_uninit(uint32_t dev_id, if (rc != ZXDH_OK) PMD_DRV_LOG(ERR, "zxdh_np_hash_soft_uninstall error! "); + zxdh_np_acl_res_destroy(dev_id); zxdh_np_dtb_mgr_destroy(dev_id); zxdh_np_sdt_mgr_destroy(dev_id); zxdh_np_dev_del(dev_id); @@ -4186,6 +4251,70 @@ zxdh_np_dtb_se_alg_zcam_data_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_write_entry_data(uint32_t dev_id, + uint32_t block_idx, + uint32_t row_or_col_msk, + uint32_t vben, + uint32_t reg_tcam_flag, + uint32_t flush, + uint32_t rd_wr, + uint32_t wr_mode, + uint32_t data_or_mask, + uint32_t ram_addr, + uint32_t vbit, + uint8_t *p_data, + ZXDH_DTB_ENTRY_T *p_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t *p_temp = NULL; + + uint8_t buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_DTB_ETCAM_TABLE_FORM_T dtb_etcam_form_info = { + .valid = 1, + .type_mode = ZXDH_DTB_TABLE_MODE_ETCAM, + .block_sel = block_idx, + .init_en = 0, + .row_or_col_msk = row_or_col_msk, + .vben = vben, + .reg_tcam_flag = reg_tcam_flag, + .uload = flush, + .rd_wr = rd_wr, + .wr_mode = wr_mode, + .data_or_mask = data_or_mask, + .addr = ram_addr, + .vbit = vbit, + }; + + p_entry->data_in_cmd_flag = 0; + p_entry->data_size = ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1); + + rc = zxdh_np_dtb_write_table_cmd(dev_id, ZXDH_DTB_TABLE_ETCAM, + &dtb_etcam_form_info, p_entry->cmd); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_table_cmd"); + + p_temp = p_data; + + for (i = 0; i < ZXDH_ETCAM_RAM_NUM; i++) { + offset = i * ((uint32_t)ZXDH_ETCAM_WIDTH_MIN / 8); + + if ((wr_mode >> (ZXDH_ETCAM_RAM_NUM - 1 - i)) & 0x1) { + memcpy(buff + offset, p_temp, ZXDH_ETCAM_WIDTH_MIN / 8); + p_temp += ZXDH_ETCAM_WIDTH_MIN / 8; + } + } + + zxdh_np_comm_swap((uint8_t *)buff, ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + memcpy(p_entry->data, buff, + ZXDH_DTB_LEN_POS_SETP * (ZXDH_DTB_ETCAM_LEN_SIZE - 1)); + + return rc; +} + static uint32_t zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id, uint32_t base_addr, @@ -4244,6 +4373,35 @@ zxdh_np_dtb_zcam_dump_info_write(uint32_t dev_id, return rc; } +static uint32_t +zxdh_np_dtb_etcam_dump_info_write(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + uint32_t *p_dump_info) +{ + uint32_t rc = ZXDH_OK; + + ZXDH_DTB_ETCAM_DUMP_FORM_T dtb_etcam_dump_form_info = { + .valid = 1, + .up_type = ZXDH_DTB_DUMP_MODE_ETCAM, + .block_sel = p_etcam_dump_info->block_sel, + .addr = p_etcam_dump_info->addr, + .rd_mode = p_etcam_dump_info->rd_mode, + .data_or_mask = p_etcam_dump_info->data_or_mask, + .tb_depth = p_etcam_dump_info->tb_depth, + .tb_width = p_etcam_dump_info->tb_width, + .tb_dst_addr_h = addr_high32, + .tb_dst_addr_l = addr_low32, + }; + + rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ETCAM, + &dtb_etcam_dump_form_info, p_dump_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd"); + + return rc; +} + static void zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, uint32_t addr, @@ -4263,6 +4421,38 @@ zxdh_np_dtb_zcam_dump_entry(uint32_t dev_id, p_entry->data_in_cmd_flag = 1; } +static void +zxdh_np_dtb_smmu0_dump_entry(uint32_t dev_id, + uint32_t base_addr, + uint32_t depth, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_smmu0_dump_info_write(dev_id, + base_addr, + depth, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + +static void +zxdh_np_dtb_etcam_dump_entry(uint32_t dev_id, + ZXDH_ETCAM_DUMP_INFO_T *p_etcam_dump_info, + uint32_t addr_high32, + uint32_t addr_low32, + ZXDH_DTB_ENTRY_T *p_entry) +{ + zxdh_np_dtb_etcam_dump_info_write(dev_id, + p_etcam_dump_info, + addr_high32, + addr_low32, + (uint32_t *)p_entry->cmd); + p_entry->data_in_cmd_flag = 1; +} + static uint32_t zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id, uint32_t base_addr, @@ -5689,6 +5879,317 @@ zxdh_np_dtb_hash_one_entry(uint32_t dev_id, return rc; } +static void +zxdh_np_acl_hdw_addr_get(ZXDH_ACL_TBL_CFG_T *p_tbl_cfg, uint32_t handle, + uint32_t *p_block_idx, uint32_t *p_addr, uint32_t *p_wr_mask) +{ + uint32_t block_entry_num = ZXDH_ACL_ENTRY_MAX_GET(p_tbl_cfg->key_mode, 1); + uint32_t entry_pos = (handle % block_entry_num) % (1U << p_tbl_cfg->key_mode); + + *p_block_idx = p_tbl_cfg->block_array[handle / block_entry_num]; + *p_addr = (handle % block_entry_num) / (1U << p_tbl_cfg->key_mode); + *p_wr_mask = (((1U << (8U >> (p_tbl_cfg->key_mode))) - 1) << + ((8U >> (p_tbl_cfg->key_mode)) * (entry_pos))) & 0xFF; +} + +static void +zxdh_np_etcam_dm_to_xy(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_xy->p_data[i] = ZXDH_COMM_DM_TO_X(p_dm->p_data[i], p_dm->p_mask[i]); + p_xy->p_mask[i] = ZXDH_COMM_DM_TO_Y(p_dm->p_data[i], p_dm->p_mask[i]); + } +} + +static uint32_t +zxdh_np_eram_opr_mode_get(uint32_t as_mode) +{ + uint32_t opr_mode = 0; + + switch (as_mode) { + case ZXDH_ERAM128_TBL_128b: + opr_mode = ZXDH_ERAM128_OPR_128b; + break; + case ZXDH_ERAM128_TBL_64b: + opr_mode = ZXDH_ERAM128_OPR_64b; + break; + case ZXDH_ERAM128_TBL_1b: + opr_mode = ZXDH_ERAM128_OPR_1b; + break; + default: + break; + } + + return opr_mode; +} + +static uint32_t +zxdh_np_dtb_etcam_entry_add(uint32_t dev_id, + uint32_t addr, + uint32_t block_idx, + uint32_t wr_mask, + uint32_t opr_type, + ZXDH_ETCAM_ENTRY_T *p_entry, + ZXDH_DTB_ENTRY_T *p_entry_data, + ZXDH_DTB_ENTRY_T *p_entry_mask) +{ + uint32_t rc = ZXDH_OK; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + RTE_ASSERT(p_entry->p_data && p_entry->p_mask); + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_dm_to_xy(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(entry_xy.p_data, p_entry->p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(entry_xy.p_mask, p_entry->p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_DATA, addr, 0, entry_xy.p_data, p_entry_data); + + rc = zxdh_np_dtb_etcam_write_entry_data(dev_id, block_idx, 0, 1, 0, 0, 0, + wr_mask, ZXDH_ETCAM_DTYPE_MASK, addr, 0xFF, entry_xy.p_mask, p_entry_mask); + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_delete(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8]; + uint8_t temp_buf[16] = {0}; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + memset(temp_data, 0xff, ZXDH_ETCAM_WIDTH_MAX / 8); + memset(temp_mask, 0, ZXDH_ETCAM_WIDTH_MAX / 8); + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = temp_data; + etcam_entry.p_mask = temp_mask; + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + memset(temp_buf, 0, sizeof(temp_buf)); + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)temp_buf, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_insert(uint32_t dev_id, + uint32_t sdt_no, + ZXDH_ACL_ENTRY_EX_T *p_acl_entry, + ZXDH_DTB_ENTRY_T *p_dtb_data_entry, + ZXDH_DTB_ENTRY_T *p_dtb_mask_entry, + ZXDH_DTB_ENTRY_T *p_dtb_as_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t as_eram_baddr = 0; + uint32_t as_enable = 0; + uint32_t etcam_table_id = 0; + uint32_t etcam_as_mode = 0; + uint32_t opr_mode = 0; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mask = 0; + + ZXDH_SDT_TBL_ETCAM_T sdt_acl = {0}; + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + ZXDH_ETCAM_ENTRY_T etcam_entry = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_acl); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + + etcam_as_mode = sdt_acl.as_rsp_mode; + etcam_table_id = sdt_acl.etcam_table_id; + as_enable = sdt_acl.as_en; + as_eram_baddr = sdt_acl.as_eram_baddr; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_acl_entry->pri, + &block_idx, &ram_addr, &etcam_wr_mask); + + etcam_entry.mode = p_tbl_cfg->key_mode; + etcam_entry.p_data = p_acl_entry->key_data; + etcam_entry.p_mask = p_acl_entry->key_mask; + + rc = zxdh_np_dtb_etcam_entry_add(dev_id, + ram_addr, + block_idx, + etcam_wr_mask, + ZXDH_ETCAM_OPR_DM, + &etcam_entry, + p_dtb_data_entry, + p_dtb_mask_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_add"); + + if (as_enable) { + opr_mode = zxdh_np_eram_opr_mode_get(etcam_as_mode); + rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id, + as_eram_baddr, + p_acl_entry->pri, + opr_mode, + (uint32_t *)p_acl_entry->p_as_rslt, + p_dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_ind_write"); + } + + return rc; +} + +static uint32_t +zxdh_np_dtb_acl_one_entry(uint32_t dev_id, + uint32_t sdt_no, + uint32_t del_en, + void *p_data, + uint32_t *p_dtb_len, + uint8_t *p_data_buff) +{ + uint32_t rc = ZXDH_OK; + uint32_t addr_offset = 0; + ZXDH_ACL_ENTRY_EX_T acl_entry = {0}; + ZXDH_DTB_ACL_ENTRY_INFO_T *p_entry = NULL; + + uint8_t data_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t mask_buff[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t data_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t mask_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint8_t as_cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + uint32_t as_data_buff[4] = {0}; + + ZXDH_DTB_ENTRY_T dtb_data_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_mask_entry = {0}; + ZXDH_DTB_ENTRY_T dtb_as_entry = {0}; + + dtb_data_entry.cmd = data_cmd_buff; + dtb_data_entry.data = data_buff; + dtb_mask_entry.cmd = mask_cmd_buff; + dtb_mask_entry.data = mask_buff; + dtb_as_entry.cmd = as_cmd_buff; + dtb_as_entry.data = (uint8_t *)as_data_buff; + + p_entry = (ZXDH_DTB_ACL_ENTRY_INFO_T *)p_data; + acl_entry.pri = p_entry->handle; + acl_entry.key_data = p_entry->key_data; + acl_entry.key_mask = p_entry->key_mask; + acl_entry.p_as_rslt = p_entry->p_as_rslt; + if (del_en) { + rc = zxdh_np_dtb_acl_delete(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_delete"); + } else { + rc = zxdh_np_dtb_acl_insert(dev_id, + sdt_no, + &acl_entry, + &dtb_data_entry, + &dtb_mask_entry, + &dtb_as_entry); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_insert"); + } + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_data_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + *p_dtb_len += ZXDH_DTB_ETCAM_LEN_SIZE; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_mask_entry); + + addr_offset = (*p_dtb_len) * ZXDH_DTB_LEN_POS_SETP; + if (dtb_as_entry.data_in_cmd_flag) + *p_dtb_len += 1; + else + *p_dtb_len += 2; + + rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_as_entry); + + return ZXDH_OK; +} + int zxdh_np_dtb_table_entry_write(uint32_t dev_id, uint32_t queue_id, @@ -5731,6 +6232,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id, rc = zxdh_np_dtb_hash_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, pentry->p_entry_data, &one_dtb_len, &dtb_one_entry); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_ADD_OR_UPDATE, + pentry->p_entry_data, &dtb_len, p_data_buff); + continue; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); rte_free(p_data_buff); @@ -6815,6 +7320,389 @@ zxdh_np_dtb_hash_data_get(uint32_t dev_id, return rc; } +static void +dtb_etcam_dump_data_len(uint32_t etcam_key_mode, + uint32_t *p_etcam_dump_len, + uint32_t *p_etcam_dump_inerval) +{ + uint32_t dump_data_len = 0; + uint8_t etcam_dump_inerval = 0; + + if (ZXDH_ETCAM_KEY_640b == etcam_key_mode) { + dump_data_len = 5 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 0; + } else if (ZXDH_ETCAM_KEY_320b == etcam_key_mode) { + dump_data_len = 3 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 8; + } else if (ZXDH_ETCAM_KEY_160b == etcam_key_mode) { + dump_data_len = 2 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 12; + } else if (ZXDH_ETCAM_KEY_80b == etcam_key_mode) { + dump_data_len = 1 * ZXDH_DTB_LEN_POS_SETP; + etcam_dump_inerval = 6; + } + + *p_etcam_dump_len = dump_data_len; + *p_etcam_dump_inerval = etcam_dump_inerval; +} + +static void +zxdh_np_dtb_get_etcam_xy_from_dump_data(uint8_t *p_data, + uint8_t *p_mask, + uint32_t etcam_dump_len, + uint32_t etcam_dump_inerval, + ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint8_t *p_entry_data = NULL; + uint8_t *p_entry_mask = NULL; + + zxdh_np_comm_swap(p_data, etcam_dump_len); + zxdh_np_comm_swap(p_mask, etcam_dump_len); + + p_entry_data = p_data + etcam_dump_inerval; + p_entry_mask = p_mask + etcam_dump_inerval; + + memcpy(p_entry_xy->p_data, p_entry_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); + memcpy(p_entry_xy->p_mask, p_entry_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry_xy->mode)); +} + + +static void +zxdh_np_etcam_xy_to_dm(ZXDH_ETCAM_ENTRY_T *p_dm, + ZXDH_ETCAM_ENTRY_T *p_xy, + uint32_t len) +{ + uint32_t i = 0; + + RTE_ASSERT(p_dm->p_data && p_dm->p_mask && p_xy->p_data && p_xy->p_mask); + + for (i = 0; i < len; i++) { + p_dm->p_data[i] = ZXDH_COMM_XY_TO_DATA(p_xy->p_data[i], p_xy->p_mask[i]); + p_dm->p_mask[i] = ZXDH_COMM_XY_TO_MASK(p_xy->p_data[i], p_xy->p_mask[i]); + } +} + +static uint32_t +zxdh_np_dtb_etcam_entry_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t block_idx, + uint32_t addr, + uint32_t rd_mode, + uint32_t opr_type, + uint32_t as_en, + uint32_t as_eram_baddr, + uint32_t as_eram_index, + uint32_t as_rsp_mode, + ZXDH_ETCAM_ENTRY_T *p_entry, + uint8_t *p_as_rslt) +{ + uint32_t rc = ZXDH_OK; + + uint32_t etcam_key_mode = 0; + + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy = {0}; + + uint32_t etcam_data_dst_phy_haddr = 0; + uint32_t etcam_data_dst_phy_laddr = 0; + uint32_t etcam_mask_dst_phy_haddr = 0; + uint32_t etcam_mask_dst_phy_laddr = 0; + uint32_t as_rst_dst_phy_haddr = 0; + uint32_t as_rst_dst_phy_laddr = 0; + + uint32_t dump_element_id = 0; + uint32_t etcam_dump_one_data_len = 0; + uint32_t etcam_dump_inerval = 0; + uint32_t dtb_desc_addr_offset = 0; + uint32_t dump_data_len = 0; + uint32_t dtb_desc_len = 0; + + uint32_t eram_dump_base_addr = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + uint8_t *p_data = NULL; + uint8_t *p_mask = NULL; + uint8_t *p_rst = NULL; + uint8_t *temp_dump_out_data = NULL; + uint8_t *dump_info_buff = NULL; + ZXDH_ETCAM_DUMP_INFO_T etcam_dump_info = {0}; + ZXDH_DTB_ENTRY_T dtb_dump_entry = {0}; + uint8_t cmd_buff[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0}; + + dtb_dump_entry.cmd = cmd_buff; + + entry_xy.p_data = temp_data; + entry_xy.p_mask = temp_mask; + + etcam_key_mode = p_entry->mode; + + etcam_dump_info.block_sel = block_idx; + etcam_dump_info.addr = addr; + etcam_dump_info.tb_width = 3 - etcam_key_mode; + etcam_dump_info.rd_mode = rd_mode; + etcam_dump_info.tb_depth = 1; + + rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &dump_element_id); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_dtb_tab_up_free_item_get failed!"); + return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY; + } + + dtb_etcam_dump_data_len(etcam_key_mode, &etcam_dump_one_data_len, &etcam_dump_inerval); + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_DATA; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_data_dst_phy_haddr, + &etcam_data_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_data_dst_phy_haddr, + etcam_data_dst_phy_laddr, + &dtb_dump_entry); + + dump_info_buff = (uint8_t *)rte_zmalloc(NULL, ZXDH_DTB_TABLE_DUMP_INFO_BUFF_SIZE, 0); + if (dump_info_buff == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + return ZXDH_PAR_CHK_POINT_NULL; + } + + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + etcam_dump_info.data_or_mask = ZXDH_ETCAM_DTYPE_MASK; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &etcam_mask_dst_phy_haddr, + &etcam_mask_dst_phy_laddr); + + zxdh_np_dtb_etcam_dump_entry(dev_id, + &etcam_dump_info, + etcam_mask_dst_phy_haddr, + etcam_mask_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += etcam_dump_one_data_len; + + if (as_en) { + zxdh_np_eram_index_cal(as_rsp_mode, as_eram_index, &row_index, &col_index); + + eram_dump_base_addr = as_eram_baddr + row_index; + zxdh_np_dtb_tab_up_item_offset_addr_get(dev_id, + queue_id, + dump_element_id, + dump_data_len, + &as_rst_dst_phy_haddr, + &as_rst_dst_phy_laddr); + + zxdh_np_dtb_smmu0_dump_entry(dev_id, + eram_dump_base_addr, + 1, + as_rst_dst_phy_haddr, + as_rst_dst_phy_laddr, + &dtb_dump_entry); + zxdh_np_dtb_data_write(dump_info_buff, dtb_desc_addr_offset, &dtb_dump_entry); + memset(cmd_buff, 0, ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8); + dtb_desc_len += 1; + dtb_desc_addr_offset += ZXDH_DTB_LEN_POS_SETP; + dump_data_len += ZXDH_DTB_LEN_POS_SETP; + } + + temp_dump_out_data = (uint8_t *)rte_zmalloc(NULL, dump_data_len, 0); + if (temp_dump_out_data == NULL) { + PMD_DRV_LOG(ERR, "malloc memory failed"); + rte_free(dump_info_buff); + return ZXDH_PAR_CHK_POINT_NULL; + } + p_data = temp_dump_out_data; + + rc = zxdh_np_dtb_write_dump_desc_info(dev_id, + queue_id, + dump_element_id, + (uint32_t *)dump_info_buff, + dump_data_len / 4, + dtb_desc_len * 4, + (uint32_t *)temp_dump_out_data); + + p_data = temp_dump_out_data; + p_mask = p_data + etcam_dump_one_data_len; + + zxdh_np_dtb_get_etcam_xy_from_dump_data(p_data, + p_mask, + etcam_dump_one_data_len, + etcam_dump_inerval, + &entry_xy); + + if (opr_type == ZXDH_ETCAM_OPR_DM) { + zxdh_np_etcam_xy_to_dm(p_entry, &entry_xy, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } else { + memcpy(p_entry->p_data, entry_xy.p_data, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + memcpy(p_entry->p_mask, entry_xy.p_mask, + ZXDH_ETCAM_ENTRY_SIZE_GET(p_entry->mode)); + } + + if (as_en) { + p_rst = p_mask + etcam_dump_one_data_len; + memcpy(p_as_rslt, p_rst, (128 / 8)); + } + + rte_free(dump_info_buff); + rte_free(temp_dump_out_data); + + return rc; +} + +static uint32_t +zxdh_np_etcam_entry_cmp(ZXDH_ETCAM_ENTRY_T *p_entry_dm, ZXDH_ETCAM_ENTRY_T *p_entry_xy) +{ + uint32_t data_mask_len = 0; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + ZXDH_ETCAM_ENTRY_T entry_xy_temp = {0}; + + entry_xy_temp.mode = p_entry_dm->mode; + entry_xy_temp.p_data = temp_data; + entry_xy_temp.p_mask = temp_mask; + + data_mask_len = ZXDH_ETCAM_ENTRY_SIZE_GET(entry_xy_temp.mode); + + zxdh_np_etcam_dm_to_xy(p_entry_dm, &entry_xy_temp, data_mask_len); + + if ((memcmp(entry_xy_temp.p_data, p_entry_xy->p_data, data_mask_len) != 0) || + (memcmp(entry_xy_temp.p_mask, p_entry_xy->p_mask, data_mask_len) != 0)) { + return ZXDH_ERR; + } + + return ZXDH_OK; +} + +static uint32_t +zxdh_np_dtb_acl_data_get(uint32_t dev_id, + uint32_t queue_id, + uint32_t sdt_no, + ZXDH_DTB_ACL_ENTRY_INFO_T *p_dump_acl_entry) +{ + uint32_t rc = ZXDH_OK; + uint32_t block_idx = 0; + uint32_t ram_addr = 0; + uint32_t etcam_wr_mode = 0; + uint32_t etcam_key_mode = 0; + uint32_t etcam_table_id = 0; + uint32_t as_enable = 0; + uint32_t as_eram_baddr = 0; + uint32_t etcam_as_mode = 0; + uint32_t row_index = 0; + uint32_t col_index = 0; + + ZXDH_ETCAM_ENTRY_T etcam_entry_dm = {0}; + ZXDH_ETCAM_ENTRY_T etcam_entry_xy = {0}; + uint32_t as_eram_data[4] = {0}; + uint8_t temp_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + uint8_t temp_mask[ZXDH_ETCAM_WIDTH_MAX / 8] = {0}; + + ZXDH_ACL_CFG_EX_T *p_acl_cfg = NULL; + ZXDH_ACL_TBL_CFG_T *p_tbl_cfg = NULL; + + ZXDH_SDT_TBL_ETCAM_T sdt_etcam_info = {0}; + + rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_etcam_info); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_soft_sdt_tbl_get"); + etcam_key_mode = sdt_etcam_info.etcam_key_mode; + etcam_as_mode = sdt_etcam_info.as_rsp_mode; + etcam_table_id = sdt_etcam_info.etcam_table_id; + as_enable = sdt_etcam_info.as_en; + as_eram_baddr = sdt_etcam_info.as_eram_baddr; + + etcam_entry_xy.mode = etcam_key_mode; + etcam_entry_xy.p_data = temp_data; + etcam_entry_xy.p_mask = temp_mask; + etcam_entry_dm.mode = etcam_key_mode; + etcam_entry_dm.p_data = p_dump_acl_entry->key_data; + etcam_entry_dm.p_mask = p_dump_acl_entry->key_mask; + + zxdh_np_acl_cfg_get(dev_id, &p_acl_cfg); + + p_tbl_cfg = p_acl_cfg->acl_tbls + etcam_table_id; + + if (!p_tbl_cfg->is_used) { + PMD_DRV_LOG(ERR, "table[ %d ] is not init!", etcam_table_id); + RTE_ASSERT(0); + return ZXDH_ACL_RC_TBL_NOT_INIT; + } + + zxdh_np_acl_hdw_addr_get(p_tbl_cfg, p_dump_acl_entry->handle, + &block_idx, &ram_addr, &etcam_wr_mode); + + rc = zxdh_np_dtb_etcam_entry_get(dev_id, + queue_id, + block_idx, + ram_addr, + etcam_wr_mode, + ZXDH_ETCAM_OPR_XY, + as_enable, + as_eram_baddr, + p_dump_acl_entry->handle, + etcam_as_mode, + &etcam_entry_xy, + (uint8_t *)as_eram_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_etcam_entry_get"); + + if (zxdh_np_etcam_entry_cmp(&etcam_entry_dm, &etcam_entry_xy) == 0) { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware success: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + } else { + PMD_DRV_LOG(DEBUG, "Acl table[ %d ] search in hardware fail: handle[ 0x%x ]," + "block[ %d ], ram_addr[ %d ], rd_mode[ %x ].", + p_tbl_cfg->table_id, p_dump_acl_entry->handle, block_idx, + ram_addr, etcam_wr_mode); + + return ZXDH_ERR; + } + + if (as_enable) { + zxdh_np_eram_index_cal(etcam_as_mode, p_dump_acl_entry->handle, + &row_index, &col_index); + switch (etcam_as_mode) { + case ZXDH_ERAM128_TBL_128b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data, (128 / 8)); + break; + + case ZXDH_ERAM128_TBL_64b: + memcpy(p_dump_acl_entry->p_as_rslt, as_eram_data + + ((1 - col_index) << 1), (64 / 8)); + break; + + case ZXDH_ERAM128_TBL_1b: + ZXDH_COMM_UINT32_GET_BITS(*(uint32_t *)p_dump_acl_entry->p_as_rslt, + *(as_eram_data + (3 - col_index / 32)), (col_index % 32), 1); + break; + default: + break; + } + } + + return rc; +} + int zxdh_np_dtb_table_entry_get(uint32_t dev_id, uint32_t queue_id, @@ -6861,6 +7749,13 @@ zxdh_np_dtb_table_entry_get(uint32_t dev_id, ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_hash_data_get"); break; + case ZXDH_SDT_TBLT_ETCAM: + rc = zxdh_np_dtb_acl_data_get(dev_id, + queue_id, + sdt_no, + (ZXDH_DTB_ACL_ENTRY_INFO_T *)get_entry->p_entry_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_acl_data_get"); + break; default: PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type); return 1; diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 228d217a50..3cbfc7946b 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1327,6 +1327,24 @@ typedef enum zxdh_dtb_dump_zcam_width_e { ZXDH_DTB_DUMP_ZCAM_RSV = 3, } ZXDH_DTB_DUMP_ZCAM_WIDTH_E; +typedef enum zxdh_etcam_opr_type_e { + ZXDH_ETCAM_OPR_DM = 0, + ZXDH_ETCAM_OPR_XY = 1, +} ZXDH_ETCAM_OPR_TYPE_E; + +typedef enum zxdh_etcam_data_type_e { + ZXDH_ETCAM_DTYPE_MASK = 0, + ZXDH_ETCAM_DTYPE_DATA = 1, +} ZXDH_ETCAM_DATA_TYPE_E; + +typedef enum zxdh_etcam_entry_mode_e { + ZXDH_ETCAM_KEY_640b = 0, + ZXDH_ETCAM_KEY_320b = 1, + ZXDH_ETCAM_KEY_160b = 2, + ZXDH_ETCAM_KEY_80b = 3, + ZXDH_ETCAM_KEY_INVALID, +} ZXDH_ETCAM_ENTRY_MODE_E; + typedef struct zxdh_dtb_lpm_entry_t { uint32_t dtb_len0; uint8_t *p_data_buff0; @@ -1341,6 +1359,19 @@ typedef struct zxdh_dtb_entry_t { uint32_t data_size; } ZXDH_DTB_ENTRY_T; +typedef struct zxdh_etcam_entry_t { + uint32_t mode; + uint8_t *p_data; + uint8_t *p_mask; +} ZXDH_ETCAM_ENTRY_T; + +typedef struct zxdh_dtb_acl_entry_info_t { + uint32_t handle; + uint8_t *key_data; + uint8_t *key_mask; + uint8_t *p_as_rslt; +} ZXDH_DTB_ACL_ENTRY_INFO_T; + typedef struct zxdh_dtb_eram_table_form_t { uint32_t valid; uint32_t type_mode; -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 90463 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* [PATCH v3 14/14] net/zxdh: modify parameters of the plcr function 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen ` (12 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 13/14] net/zxdh: add acl tables ops Bingbin Chen @ 2025-03-05 8:13 ` Bingbin Chen 13 siblings, 0 replies; 114+ messages in thread From: Bingbin Chen @ 2025-03-05 8:13 UTC (permalink / raw) To: stephen, wang.junlong1, yang.yonggang; +Cc: dev, Bingbin Chen [-- Attachment #1.1.1: Type: text/plain, Size: 20985 bytes --] Add dev_id to the parameter of plcr function to support multi card configuration. Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> --- drivers/net/zxdh/zxdh_msg.c | 3 +- drivers/net/zxdh/zxdh_mtr.c | 8 +- drivers/net/zxdh/zxdh_np.c | 251 +++++++++++++++++++++++------------- drivers/net/zxdh/zxdh_np.h | 8 +- 4 files changed, 173 insertions(+), 97 deletions(-) diff --git a/drivers/net/zxdh/zxdh_msg.c b/drivers/net/zxdh/zxdh_msg.c index 96ad638e83..f43f272cff 100644 --- a/drivers/net/zxdh/zxdh_msg.c +++ b/drivers/net/zxdh/zxdh_msg.c @@ -2043,7 +2043,8 @@ zxdh_vf_mtr_hw_profile_cfg(struct zxdh_hw *pf_hw __rte_unused, (struct zxdh_plcr_profile_cfg *)cfg_data; union zxdh_offload_profile_cfg *plcr_param = &zxdh_plcr_profile_cfg->plcr_param; - ret = zxdh_np_car_profile_cfg_set(vport, + ret = zxdh_np_car_profile_cfg_set(pf_hw->dev_id, + vport, zxdh_plcr_profile_cfg->car_type, zxdh_plcr_profile_cfg->packet_mode, zxdh_plcr_profile_cfg->hw_profile_id, diff --git a/drivers/net/zxdh/zxdh_mtr.c b/drivers/net/zxdh/zxdh_mtr.c index 3797a5b29b..809456d73f 100644 --- a/drivers/net/zxdh/zxdh_mtr.c +++ b/drivers/net/zxdh/zxdh_mtr.c @@ -281,7 +281,7 @@ zxdh_hw_profile_free_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type, { struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_delete(vport, car_type, + int ret = zxdh_np_car_profile_id_delete(hw->dev_id, vport, car_type, (uint64_t)hw_profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u free hw profile %u failed", vport, hw_profile_id); @@ -299,7 +299,7 @@ zxdh_hw_profile_alloc_direct(struct rte_eth_dev *dev, ZXDH_PROFILE_TYPE car_type uint64_t profile_id = HW_PROFILE_MAX; struct zxdh_hw *hw = dev->data->dev_private; uint16_t vport = hw->vport.vport; - int ret = zxdh_np_car_profile_id_add(vport, car_type, &profile_id); + int ret = zxdh_np_car_profile_id_add(hw->dev_id, vport, car_type, &profile_id); if (ret) { PMD_DRV_LOG(ERR, "port %u alloc hw profile failed", vport); @@ -551,7 +551,9 @@ zxdh_hw_profile_config_direct(struct rte_eth_dev *dev __rte_unused, struct zxdh_meter_profile *mp, struct rte_mtr_error *error) { - int ret = zxdh_np_car_profile_cfg_set(mp->hw_profile_owner_vport, + struct zxdh_hw *hw = dev->data->dev_private; + int ret = zxdh_np_car_profile_cfg_set(hw->dev_id, + mp->hw_profile_owner_vport, car_type, mp->profile.packet_mode, (uint32_t)hw_profile_id, &mp->plcr_param); if (ret) { diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c index 0303d4885f..0238c78d06 100644 --- a/drivers/net/zxdh/zxdh_np.c +++ b/drivers/net/zxdh/zxdh_np.c @@ -2287,6 +2287,8 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, rte_spinlock_init(&p_dev_info->dtb_spinlock.spinlock); + rte_spinlock_init(&p_dev_info->smmu0_spinlock.spinlock); + for (i = 0; i < ZXDH_DTB_QUEUE_NUM_MAX; i++) rte_spinlock_init(&p_dev_info->dtb_queue_spinlock[i].spinlock); @@ -3328,6 +3330,32 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no, return rc; } +static uint32_t +zxdh_np_reg_read32(uint32_t dev_id, uint32_t reg_no, + uint32_t m_offset, uint32_t n_offset, uint32_t *p_data) +{ + uint32_t rc = 0; + uint32_t addr = 0; + ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no]; + uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0}; + uint32_t reg_real_no = p_reg_info->reg_no; + uint32_t reg_type = p_reg_info->flags; + uint32_t reg_module = p_reg_info->module_no; + + addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset); + + if (reg_module == DTB4K) { + rc = p_reg_info->p_read_fun(dev_id, addr, p_data); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun"); + } else { + rc = zxdh_np_agent_channel_reg_read(dev_id, reg_type, reg_real_no, 4, addr, p_buff); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_agent_channel_reg_read"); + *p_data = p_buff[0]; + } + + return rc; +} + static uint32_t zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id, uint32_t queue_id, @@ -10374,9 +10402,9 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos) uint32_t done_flag = 0; while (!done_flag) { - rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data); + rc = zxdh_np_reg_read32(dev_id, reg_no, 0, 0, &data); if (rc != 0) { - PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read Fail!", rc); + PMD_DRV_LOG(ERR, "[ErrorCode:0x%x]!-- zxdh_np_reg_read32 Fail!", rc); return rc; } @@ -10402,15 +10430,26 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, uint32_t rd_clr_mode, uint32_t *p_data) { - uint32_t rc = 0; + uint32_t rc = ZXDH_OK; uint32_t i = 0; uint32_t row_index = 0; uint32_t col_index = 0; uint32_t temp_data[4] = {0}; uint32_t *p_temp_data = NULL; ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0}; + ZXDH_SPINLOCK_T *p_ind_spinlock = NULL; + + rc = zxdh_np_dev_opr_spinlock_get(dev_id, ZXDH_DEV_SPINLOCK_T_SMMU0, &p_ind_spinlock); + ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_opr_spinlock_get"); + + rte_spinlock_lock(&p_ind_spinlock->spinlock); rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; + } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD; @@ -10419,42 +10458,47 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: - if ((0xFFFFFFFF - (base_addr)) < (index)) + if ((0xFFFFFFFF - (base_addr)) < (index)) { + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); return ZXDH_PAR_CHK_INVALID_INDEX; - + } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } - row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } - row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x1; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } - row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x3; break; case ZXDH_ERAM128_OPR_1b: if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } row_index = index & ZXDH_ERAM128_BADDR_MASK; col_index = index & 0x7F; break; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; @@ -10465,56 +10509,77 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, switch (rd_mode) { case ZXDH_ERAM128_OPR_128b: if ((0xFFFFFFFF - (base_addr)) < (index)) { - PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index); + PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); return ZXDH_PAR_CHK_INVALID_INDEX; } if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } row_index = (index << 7); cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b; break; case ZXDH_ERAM128_OPR_64b: if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } - row_index = (index << 6); cpu_ind_cmd.cpu_req_mode = 2; break; case ZXDH_ERAM128_OPR_32b: if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) { - PMD_DRV_LOG(ERR, "%s : index out of range !", __func__); - return -1; + PMD_DRV_LOG(ERR, "index out of range!"); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; } row_index = (index << 5); cpu_ind_cmd.cpu_req_mode = 1; break; case ZXDH_ERAM128_OPR_1b: - PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ", + PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error!", rd_clr_mode, rd_mode); - return -1; + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; + default: + break; } cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index; } rc = zxdh_np_reg_write(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, - 0, - 0, - &cpu_ind_cmd); + ZXDH_SMMU0_SMMU0_CPU_IND_CMDR, + 0, + 0, + &cpu_ind_cmd); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; + } rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; + } p_temp_data = temp_data; for (i = 0; i < 4; i++) { rc = zxdh_np_reg_read(dev_id, - ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, - 0, - 0, - p_temp_data + 3 - i); + ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i, + 0, + 0, + p_temp_data + 3 - i); + if (rc != ZXDH_OK) { + PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc); + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return ZXDH_ERR; + } } if (rd_clr_mode == ZXDH_RD_MODE_HOLD) { @@ -10532,6 +10597,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1); break; + default: + break; } } else { switch (rd_mode) { @@ -10544,9 +10611,13 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id, case ZXDH_ERAM128_OPR_32b: memcpy(p_data, p_temp_data, (64 / 8)); break; + default: + break; } } + rte_spinlock_unlock(&p_ind_spinlock->spinlock); + return rc; } @@ -10599,14 +10670,14 @@ zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MS uint32_t *p_data, uint32_t rep_len) { uint32_t ret = 0; - ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0}; - - agent_msg.msg = (void *)p_msg; - agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T); + ZXDH_AGENT_CHANNEL_MSG_T agent_msg = { + .msg = (void *)&p_msg, + .msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T), + }; ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_sync_send failed."); return 1; } @@ -10620,19 +10691,19 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport, uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_REQUEST; - msgcfg.vport = vport; - msgcfg.car_type = car_type; - msgcfg.profile_id = 0xFFFF; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_REQUEST, + .vport = vport, + .car_type = car_type, + .profile_id = 0xFFFF, + }; ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -10675,7 +10746,7 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_a_type failed."); return 1; } @@ -10709,7 +10780,7 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id, ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__); + PMD_DRV_LOG(ERR, "stat_car_b_type failed."); return 1; } @@ -10727,18 +10798,18 @@ zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport, uint32_t ret = 0; uint32_t resp_buffer[2] = {0}; - ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0}; - - msgcfg.dev_id = 0; - msgcfg.type = ZXDH_PLCR_MSG; - msgcfg.oper = ZXDH_PROFILEID_RELEASE; - msgcfg.vport = vport; - msgcfg.profile_id = profileid; + ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = { + .dev_id = 0, + .type = ZXDH_PLCR_MSG, + .oper = ZXDH_PROFILEID_RELEASE, + .vport = vport, + .profile_id = profileid, + }; ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg, resp_buffer, sizeof(resp_buffer)); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__); + PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed."); return 1; } @@ -10756,11 +10827,12 @@ zxdh_np_stat_cara_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0}; + ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = { + .cara_drop = drop_flag, + .cara_plcr_en = plcr_en, + .cara_profile_id = profile_id, + }; - queue_cfg.cara_drop = drop_flag; - queue_cfg.cara_plcr_en = plcr_en; - queue_cfg.cara_profile_id = profile_id; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARA_QUEUE_RAM0, 0, @@ -10780,11 +10852,11 @@ zxdh_np_stat_carb_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0}; - - queue_cfg.carb_drop = drop_flag; - queue_cfg.carb_plcr_en = plcr_en; - queue_cfg.carb_profile_id = profile_id; + ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = { + .carb_drop = drop_flag, + .carb_plcr_en = plcr_en, + .carb_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARB_QUEUE_RAM0, @@ -10805,10 +10877,11 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, { uint32_t rc = 0; - ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0}; - queue_cfg.carc_drop = drop_flag; - queue_cfg.carc_plcr_en = plcr_en; - queue_cfg.carc_profile_id = profile_id; + ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = { + .carc_drop = drop_flag, + .carc_plcr_en = plcr_en, + .carc_profile_id = profile_id, + }; rc = zxdh_np_reg_write(dev_id, ZXDH_STAT_CAR0_CARC_QUEUE_RAM0, @@ -10821,7 +10894,8 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id, } uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id) { @@ -10833,10 +10907,10 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, profile_id = (uint32_t *)rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0); if (profile_id == NULL) { - PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__); + PMD_DRV_LOG(ERR, "profile_id point null!"); return ZXDH_PAR_CHK_POINT_NULL; } - ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id); + ret = zxdh_np_agent_channel_plcr_profileid_request(dev_id, vport_id, flags, profile_id); profile_id_h = *(profile_id + 1); profile_id_l = *profile_id; @@ -10844,7 +10918,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, temp_profile_id = (((uint64_t)profile_id_l) << 32) | ((uint64_t)profile_id_h); if (0 != (uint32_t)(temp_profile_id >> 56)) { - PMD_DRV_LOG(ERR, "%s: profile_id is overflow!", __func__); + PMD_DRV_LOG(ERR, "profile_id is overflow!"); return 1; } @@ -10854,19 +10928,19 @@ zxdh_np_car_profile_id_add(uint32_t vport_id, } uint32_t -zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, +zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id __rte_unused, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg) { uint32_t ret = 0; - uint32_t dev_id = 0; ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type, pkt_sign, profile_id, p_car_profile_cfg); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__); + PMD_DRV_LOG(ERR, "plcr_car_rate set failed!"); return 1; } @@ -10874,18 +10948,15 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused, } uint32_t -zxdh_np_car_profile_id_delete(uint32_t vport_id, +zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id) { uint32_t ret = 0; - uint32_t profileid = 0; - uint32_t dev_id = 0; - - profileid = profile_id & 0xFFFF; + uint32_t profileid = profile_id & 0xFFFF; ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid); if (ret != 0) { - PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__); + PMD_DRV_LOG(ERR, "plcr profiled id release failed!"); return 1; } @@ -10904,32 +10975,32 @@ zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, if (car_type == ZXDH_STAT_CAR_A_TYPE) { if (flow_id > ZXDH_CAR_A_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_A_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car a type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car a type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else if (car_type == ZXDH_STAT_CAR_B_TYPE) { if (flow_id > ZXDH_CAR_B_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_B_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car b type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car b type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } else { if (flow_id > ZXDH_CAR_C_FLOW_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type flow_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type flow_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } if (profile_id > ZXDH_CAR_C_PROFILE_ID_MAX) { - PMD_DRV_LOG(ERR, "%s: stat car c type profile_id invalid!", __func__); + PMD_DRV_LOG(ERR, "stat car c type profile_id invalid!"); return ZXDH_PAR_CHK_INVALID_INDEX; } } diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h index 3cbfc7946b..4c3fcbc0c8 100644 --- a/drivers/net/zxdh/zxdh_np.h +++ b/drivers/net/zxdh/zxdh_np.h @@ -1934,15 +1934,17 @@ uint32_t zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id, uint32_t clr_mode, uint32_t *p_data); uint32_t -zxdh_np_car_profile_id_add(uint32_t vport_id, +zxdh_np_car_profile_id_add(uint32_t dev_id, + uint32_t vport_id, uint32_t flags, uint64_t *p_profile_id); -uint32_t zxdh_np_car_profile_cfg_set(uint32_t vport_id, +uint32_t zxdh_np_car_profile_cfg_set(uint32_t dev_id, + uint32_t vport_id, uint32_t car_type, uint32_t pkt_sign, uint32_t profile_id, void *p_car_profile_cfg); -uint32_t zxdh_np_car_profile_id_delete(uint32_t vport_id, +uint32_t zxdh_np_car_profile_id_delete(uint32_t dev_id, uint32_t vport_id, uint32_t flags, uint64_t profile_id); uint32_t zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id, uint32_t car_type, -- 2.27.0 [-- Attachment #1.1.2: Type: text/html , Size: 55606 bytes --] ^ permalink raw reply related [flat|nested] 114+ messages in thread
* Re: [PATCH v1 01/14] net/zxdh: add network processor registers ops 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen ` (6 preceding siblings ...) 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen @ 2025-03-10 23:19 ` Stephen Hemminger 7 siblings, 0 replies; 114+ messages in thread From: Stephen Hemminger @ 2025-03-10 23:19 UTC (permalink / raw) To: Bingbin Chen; +Cc: dev On Mon, 10 Feb 2025 09:44:41 +0800 Bingbin Chen <chen.bingbin@zte.com.cn> wrote: > Add (np)network processor registers read/write interfaces. > > Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn> When sending followup patches, please use the convention of using a new version number and a reply-to so that it stays in same thread in mail. This appears to be v2 of a previous patchset. > --- > drivers/net/zxdh/zxdh_np.c | 792 +++++++++++++++++++++++++++++++------ > drivers/net/zxdh/zxdh_np.h | 94 ++++- > 2 files changed, 761 insertions(+), 125 deletions(-) > > diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c > index 1e6e8f0e75..cbab2a3aaa 100644 > --- a/drivers/net/zxdh/zxdh_np.c > +++ b/drivers/net/zxdh/zxdh_np.c > @@ -14,7 +14,6 @@ > #include "zxdh_np.h" > #include "zxdh_logs.h" > > -static uint64_t g_np_bar_offset; > static ZXDH_DEV_MGR_T g_dev_mgr; > static ZXDH_SDT_MGR_T g_sdt_mgr; > static uint32_t g_dpp_dtb_int_enable; > @@ -22,14 +21,185 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; > ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX]; > ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX]; > ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX]; > -ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX]; > -ZXDH_REG_T g_dpp_reg_info[4]; > -ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4]; > ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX]; > ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg; New tables appear to be immutable and should be marked as const. This will allow compiler to catch bugs where table value gets changed. > > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = { > + {"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, > + {"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, > + {"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0}, > + {"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = { > + {"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = { > + {"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = { > + {"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = { > + {"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = { > + {"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0}, > +}; > + > +ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = { > + {"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0}, > +}; > + > +ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = { > + {"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0}, > +}; > + > +ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = { > + {"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0}, > + {"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0}, > + {"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0}, > + {"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0}, > + {"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0}, > + {"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0}, > + {"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"rw_len", 123, 2}, > + {"v46_flag", 121, 1}, > + {"lpm_wr_vld", 120, 1}, > + {"baddr", 119, 20}, > + {"ecc_en", 99, 1}, > + {"rw_addr", 29, 30}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"data_mode", 123, 2}, > + {"cpu_wr", 121, 1}, > + {"cpu_rd", 120, 1}, > + {"cpu_rd_mode", 119, 1}, > + {"addr", 113, 26}, > + {"data_h", 0, 1}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"data_mode", 123, 2}, > + {"cpu_wr", 121, 1}, > + {"cpu_rd", 120, 1}, > + {"cpu_rd_mode", 119, 1}, > + {"addr", 113, 26}, > + {"data_h", 63, 32}, > + {"data_l", 31, 32}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"data_mode", 123, 2}, > + {"cpu_wr", 121, 1}, > + {"cpu_rd", 120, 1}, > + {"cpu_rd_mode", 119, 1}, > + {"addr", 113, 26}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"ram_reg_flag", 123, 1}, > + {"zgroup_id", 122, 2}, > + {"zblock_id", 120, 3}, > + {"zcell_id", 117, 2}, > + {"mask", 115, 4}, > + {"sram_addr", 111, 9}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"block_sel", 123, 3}, > + {"init_en", 120, 1}, > + {"row_or_col_msk", 119, 1}, > + {"vben", 118, 1}, > + {"reg_tcam_flag", 117, 1}, > + {"uload", 116, 8}, > + {"rd_wr", 108, 1}, > + {"wr_mode", 107, 8}, > + {"data_or_mask", 99, 1}, > + {"addr", 98, 9}, > + {"vbit", 89, 8}, > +}; > + > +ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = { > + {"valid", 127, 1}, > + {"type_mode", 126, 3}, > + {"std_h", 63, 32}, > + {"std_l", 31, 32}, > +}; > + > +ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = { > + { > + "ddr", > + ZXDH_DTB_TABLE_DDR, > + 8, > + g_dtb_ddr_table_cmd_info, > + }, > + { > + "eram 1 bit", > + ZXDH_DTB_TABLE_ERAM_1, > + 8, > + g_dtb_eram_table_cmd_1_info, > + }, > + { > + "eram 64 bit", > + ZXDH_DTB_TABLE_ERAM_64, > + 9, > + g_dtb_eram_table_cmd_64_info, > + }, > + { > + "eram 128 bit", > + ZXDH_DTB_TABLE_ERAM_128, > + 7, > + g_dtb_eram_table_cmd_128_info, > + }, > + { > + "zcam", > + ZXDH_DTB_TABLE_ZCAM, > + 8, > + g_dtb_zcam_table_cmd_info, > + }, > + { > + "etcam", > + ZXDH_DTB_TABLE_ETCAM, > + 13, > + g_dtb_etcam_table_cmd_info, > + }, > + { > + "mc_hash", > + ZXDH_DTB_TABLE_MC_HASH, > + 4, > + g_dtb_mc_hash_table_cmd_info > + }, > +}; All those tables can be const. > #define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr) > #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id]) > +#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id]) > + > +#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \ > + (((data_len) & 0x3ff) | \ > + ((int_en) << 29) | \ > + ((cmd_type) << 30)) > > #define ZXDH_COMM_MASK_BIT(_bitnum_)\ > (0x1U << (_bitnum_)) > @@ -115,8 +285,23 @@ do {\ > } \ > } while (0) > > +static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data) > +{ > + return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8; > +} > + > +static inline uint32_t > +zxdh_np_comm_convert32(uint32_t dw_data) > +{ > + return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 | > + ((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24; > +} > + > #define ZXDH_COMM_CONVERT16(w_data) \ > - (((w_data) & 0xff) << 8) > + zxdh_np_comm_convert16(w_data) > + > +#define ZXDH_COMM_CONVERT32(w_data) \ > + zxdh_np_comm_convert32(w_data) > > #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID) \ > (p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index) > @@ -174,7 +359,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len) > uc_byte_mode = dw_byte_len % 4 & 0xff; > > for (i = 0; i < dw_byte_num; i++) { > - (*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp); > + (*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp); > p_dw_tmp++; > } > > @@ -198,6 +383,329 @@ zxdh_np_dev_init(void) > return 0; > } > > +static uint32_t > +zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) > +{ > + ZXDH_DEV_CFG_T *p_dev_info = NULL; > + > + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); > + > + if (p_dev_info == NULL) { > + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", > + dev_id); > + return ZXDH_ERR; > + } > + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { > + p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data); > + } else { > + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", > + p_dev_info->access_type); Use %u not %d here. > + return ZXDH_ERR; > + } > + > + return ZXDH_OK; > +} > + > +static uint32_t > +zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) > +{ > + ZXDH_DEV_CFG_T *p_dev_info = NULL; > + > + p_dev_info = ZXDH_DEV_INFO_GET(dev_id); > + > + if (p_dev_info == NULL) { > + PMD_DRV_LOG(ERR, "Error: Channel[%d] dev is not exist", > + dev_id); > + return ZXDH_ERR; > + } > + if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) { > + p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data); > + } else { > + PMD_DRV_LOG(ERR, "Dev access type[ %d ] is invalid", > + p_dev_info->access_type); > + return ZXDH_ERR; > + } > + > + return ZXDH_OK; > +} > + > +static void > +zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data) > +{ > + uint32_t data = 0; > + uint64_t addr = 0; > + > + data = *p_data; > + > + if (zxdh_np_comm_is_big_endian()) > + data = ZXDH_COMM_CONVERT32(data); > + > + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; > + *((volatile uint32_t *)addr) = data; > +} > + > +static void > +zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data) > +{ > + uint32_t data = 0; > + uint64_t addr = 0; > + > + addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET; > + data = *((volatile uint32_t *)addr); > + > + if (zxdh_np_comm_is_big_endian()) > + data = ZXDH_COMM_CONVERT32(data); > + > + *p_data = data; > +} > + > +static uint64_t > +zxdh_np_dev_get_pcie_addr(uint32_t dev_id) > +{ > + ZXDH_DEV_MGR_T *p_dev_mgr = NULL; > + ZXDH_DEV_CFG_T *p_dev_info = NULL; > + > + p_dev_mgr = &g_dev_mgr; > + p_dev_info = p_dev_mgr->p_dev_array[dev_id]; > + > + if (p_dev_info == NULL) > + return ZXDH_DEV_TYPE_INVALID; > + > + return p_dev_info->pcie_addr; > +} > + > +static void > +zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) > +{ > + uint32_t i; > + uint64_t abs_addr = 0; > + > + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; > + > + for (i = 0; i < size; i++) > + zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i); > +} > + > +static void > +zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data) > +{ > + uint32_t i; > + uint64_t abs_addr = 0; > + > + abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr; > + > + for (i = 0; i < size; i++) > + zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i); > +} > + > +static uint32_t > +zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) > +{ > + return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data); > +} > + > +static uint32_t > +zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) > +{ > + return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data); > +} > + > +static uint32_t > +zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data) > +{ > + return zxdh_np_write(dev_id, addr, p_data); > +} > + > +static uint32_t > +zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data) > +{ > + return zxdh_np_read(dev_id, addr, p_data); > +} > + > +ZXDH_REG_T g_dpp_reg_info[] = { > + { > + "cpu_ind_cmd", > + 669, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000014, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 4, > + g_smmu0_smmu0_cpu_ind_cmd_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, Please use named initializers for complex structures. There was a case in another driver where one element in list like this was skipped leading to a bug. > + { > + "cpu_ind_rd_done", > + 670, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000040, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_cpu_ind_rd_done_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "cpu_ind_rdat0", > + 671, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000044, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_cpu_ind_rdat0_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "cpu_ind_rdat1", > + 672, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000048, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_cpu_ind_rdat1_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "cpu_ind_rdat2", > + 673, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x0000004c, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_cpu_ind_rdat2_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "cpu_ind_rdat3", > + 674, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x00000050, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_cpu_ind_rdat3_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "wr_arb_cpu_rdy", > + 676, > + SMMU0, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_NUL_ARRAY, > + ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x0000010c, > + (32 / 8), > + 0, > + 0, > + 0, > + 0, > + 1, > + g_smmu0_smmu0_wr_arb_cpu_rdy_reg, > + zxdh_np_se_smmu0_write, > + zxdh_np_se_smmu0_read, > + }, > + { > + "info_queue_buf_space_left_0_127", > + 820, > + DTB4K, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_UNI_ARRAY, > + ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x000c, > + (32 / 8), > + 0, > + 127 + 1, > + 0, > + 32, > + 1, > + g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg, > + zxdh_np_write, > + zxdh_np_read, > + }, > + { > + "cfg_epid_v_func_num_0_127", > + 821, > + DTB4K, > + ZXDH_REG_FLAG_DIRECT, > + ZXDH_REG_UNI_ARRAY, > + ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010, > + (32 / 8), > + 0, > + 127 + 1, > + 0, > + 32, > + 7, > + g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg, > + zxdh_np_write, > + zxdh_np_read, > + } > +}; > + > +static uint32_t > +zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset) > +{ > + uint32_t addr = 0; > + ZXDH_REG_T *p_reg_info = NULL; > + > + p_reg_info = &g_dpp_reg_info[reg_no]; > + > + addr = p_reg_info->addr; > + > + if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) { > + if (n_offset > (p_reg_info->n_size - 1)) > + PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%d, n:%d," > + "size:%d", reg_no, n_offset, p_reg_info->n_size - 1); Avoid wrapping format string instead use: PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%d, n:%d size:%d", reg_no, n_offset, p_reg_info->n_size - 1); Also since m_offset and n_offset are unsigned, you should use %u not %d > + > + addr += n_offset * p_reg_info->n_step; > + } else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) { > + if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1))) > + PMD_DRV_LOG(ERR, "reg n_offset or m_offset is out of range, reg_no:%d," > + "n:%d, n_size:%d, m:%d, m_size:%d,", reg_no, n_offset, > + p_reg_info->n_size - 1, m_offset, p_reg_info->m_size - 1); > + > + addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step; > + } > + > + return addr; > +} > + > static uint32_t > zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, > ZXDH_DEV_ACCESS_TYPE_E access_type, uint64_t pcie_addr, > @@ -221,7 +729,10 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, > } else { > /* device is new. */ > p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0); > - ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info); > + if (p_dev_info == NULL) { > + PMD_DRV_LOG(ERR, "%s point null!", __func__); The function name is already added by PMD_DRV_LOG > + return ZXDH_PAR_CHK_POINT_NULL; > + } > p_dev_mgr->p_dev_array[dev_id] = p_dev_info; > p_dev_mgr->device_num++; > } > @@ -234,6 +745,9 @@ zxdh_np_dev_add(uint32_t dev_id, ZXDH_DEV_TYPE_E dev_type, > p_dev_info->dma_vir_addr = dma_vir_addr; > p_dev_info->dma_phy_addr = dma_phy_addr; > > + p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write; > + p_dev_info->p_pcie_read_fun = zxdh_np_dev_pcie_default_read; > + > return 0; > } > > @@ -335,6 +849,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id) > return p_dpp_dtb_mgr[dev_id]; > } > > +static uint32_t > +zxdh_np_dtb_mgr_create(uint32_t dev_id) > +{ > + if (p_dpp_dtb_mgr[dev_id] != NULL) { > + PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager" > + " is exist!!!", ZXDH_RC_DTB_MGR_EXIST); > + return ZXDH_RC_DTB_MGR_EXIST; > + } > + > + p_dpp_dtb_mgr[dev_id] = (ZXDH_DTB_MGR_T *)rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0); Cast of rte_zmalloc() return is unnecessary since it returns void *. ^ permalink raw reply [flat|nested] 114+ messages in thread
end of thread, other threads:[~2025-04-08 13:34 UTC | newest] Thread overview: 114+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-02-10 17:25 ` Stephen Hemminger 2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen 2025-02-10 17:28 ` Stephen Hemminger 2025-02-10 17:30 ` Stephen Hemminger 2025-02-10 17:31 ` Stephen Hemminger 2025-02-10 18:23 ` Stephen Hemminger 2025-02-10 1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-02-10 17:31 ` Stephen Hemminger 2025-02-10 1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-02-10 17:33 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-02-10 17:35 ` Stephen Hemminger 2025-02-10 17:35 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-02-10 17:36 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-02-10 17:40 ` Stephen Hemminger 2025-02-10 17:43 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-02-10 17:45 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-02-10 17:46 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-02-10 17:47 ` Stephen Hemminger 2025-02-10 1:50 ` [PATCH v1 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 17:50 ` Stephen Hemminger 2025-02-10 18:19 ` Stephen Hemminger 2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 03/14] net/zxdh: add agent channel Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-02-22 7:22 ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen 2025-02-22 17:34 ` Stephen Hemminger 2025-03-05 8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 03/14] net/zxdh: add agent channel Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-03-19 8:57 ` [PATCH v5 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-19 8:58 ` [PATCH v5 14/14] net/zxdh: fix debugging errors Bingbin Chen 2025-03-20 19:50 ` Stephen Hemminger 2025-03-21 3:07 ` Bingbin Chen 2025-03-19 9:31 ` [v5,00/14] net/zxdh: add network processor ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 00/14] " Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 01/14] net/zxdh: add network processor registers ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 03/14] net/zxdh: add agent channel Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-03-21 7:31 ` [PATCH v6 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-21 7:32 ` [PATCH v6 14/14] net/zxdh: optimize msg processing ops and modify some issues Bingbin Chen 2025-04-08 13:34 ` Stephen Hemminger 2025-03-27 18:12 ` [PATCH v6 00/14] net/zxdh: add network processor ops Stephen Hemminger 2025-03-17 14:57 ` [PATCH v4 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 03/14] net/zxdh: add agent channel Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-03-17 14:57 ` [PATCH v4 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-17 14:58 ` [PATCH v4 14/14] net/zxdh: fix debugging errors Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 02/14] net/zxdh: support compatibility check Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 03/14] net/zxdh: add agent channel Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 04/14] net/zxdh: modify dtb queue ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 05/14] net/zxdh: add tables dump address ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 06/14] net/zxdh: add eram tables ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 07/14] net/zxdh: get flow tables resources Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 08/14] net/zxdh: support hash resources configuration Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 09/14] net/zxdh: implement tables initialization Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 11/14] net/zxdh: get hash table entry result Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 12/14] net/zxdh: delete all hash entries Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 13/14] net/zxdh: add acl tables ops Bingbin Chen 2025-03-05 8:13 ` [PATCH v3 14/14] net/zxdh: modify parameters of the plcr function Bingbin Chen 2025-03-10 23:19 ` [PATCH v1 01/14] net/zxdh: add network processor registers ops Stephen Hemminger
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