From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
Nicolas Saenz Julienne <nsaenz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Cyril Brulebois <kibi@debian.org>,
Stanimir Varbanov <svarbanov@suse.de>,
bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 3/8] PCI: brcmstb: Do not assume that reg field starts at LSB
Date: Fri, 14 Feb 2025 12:39:31 -0500 [thread overview]
Message-ID: <20250214173944.47506-4-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20250214173944.47506-1-james.quinlan@broadcom.com>
When setting a register field it was assumed that the field started at the
lsb of the register. Although the masks do indeed start at the lsb, and
this will probably not change, it is prudent to use a method that makes no
assumption about the mask's placement in the register.
The uXXp_replace_bits() calls are used since they are already prevalent
in this driver.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
drivers/pci/controller/pcie-brcmstb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 98542e74aa16..e0b20f58c604 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -415,10 +415,10 @@ static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
- lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
+ u32p_replace_bits(&lnkcap, gen, PCI_EXP_LNKCAP_SLS);
writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
- lnkctl2 = (lnkctl2 & ~0xf) | gen;
+ u16p_replace_bits(&lnkctl2, gen, PCI_EXP_LNKCTL2_TLS);
writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
}
--
2.43.0
next prev parent reply other threads:[~2025-02-14 18:26 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-14 17:39 [PATCH v2 0/8] PCI: brcmstb: Misc small tweaks and fixes Jim Quinlan
2025-02-14 17:39 ` [PATCH v2 1/8] PCI: brcmstb: Set gen limitation before link, not after Jim Quinlan
2025-02-20 17:27 ` Florian Fainelli
2025-03-04 14:51 ` Manivannan Sadhasivam
2025-02-14 17:39 ` [PATCH v2 2/8] PCI: brcmstb: Write to internal register to change link cap Jim Quinlan
2025-02-20 17:28 ` Florian Fainelli
2025-03-04 14:54 ` Manivannan Sadhasivam
2025-02-14 17:39 ` Jim Quinlan [this message]
2025-02-20 17:29 ` [PATCH v2 3/8] PCI: brcmstb: Do not assume that reg field starts at LSB Florian Fainelli
2025-03-04 14:57 ` Manivannan Sadhasivam
2025-02-14 17:39 ` [PATCH v2 4/8] PCI: brcmstb: Fix error path upon call of regulator_bulk_get() Jim Quinlan
2025-02-20 17:29 ` Florian Fainelli
2025-03-03 18:40 ` Bjorn Helgaas
2025-03-04 14:49 ` Jim Quinlan
2025-03-06 15:24 ` Jim Quinlan
2025-03-06 16:24 ` Bjorn Helgaas
2025-03-04 15:03 ` Manivannan Sadhasivam
2025-03-04 16:55 ` Jim Quinlan
2025-03-04 17:07 ` Manivannan Sadhasivam
2025-03-04 17:24 ` Jim Quinlan
2025-03-04 17:32 ` Manivannan Sadhasivam
2025-03-04 17:54 ` Krzysztof Wilczyński
2025-02-14 17:39 ` [PATCH v2 5/8] PCI: brcmstb: Fix potential premature regulator disabling Jim Quinlan
2025-02-20 17:30 ` Florian Fainelli
2025-03-04 15:04 ` Manivannan Sadhasivam
2025-02-14 17:39 ` [PATCH v2 6/8] PCI: brcmstb: Use same constant table for config space access Jim Quinlan
2025-02-20 18:14 ` Florian Fainelli
2025-03-04 15:08 ` Manivannan Sadhasivam
2025-03-04 16:37 ` Jim Quinlan
2025-03-04 16:58 ` Manivannan Sadhasivam
2025-03-04 17:37 ` Jim Quinlan
2025-03-05 5:47 ` Manivannan Sadhasivam
2025-02-14 17:39 ` [PATCH v2 7/8] PCI: brcmstb: Make two changes in MDIO register fields Jim Quinlan
2025-02-20 18:15 ` Florian Fainelli
2025-03-04 15:09 ` Manivannan Sadhasivam
2025-02-14 17:39 ` [PATCH v2 8/8] PCI: brcmstb: Clarify conversion of irq_domain_set_info() param Jim Quinlan
2025-02-20 18:15 ` Florian Fainelli
2025-03-04 15:10 ` Manivannan Sadhasivam
2025-03-01 14:48 ` [PATCH v2 0/8] PCI: brcmstb: Misc small tweaks and fixes Krzysztof Wilczyński
2025-03-04 16:10 ` Krzysztof Wilczyński
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250214173944.47506-4-james.quinlan@broadcom.com \
--to=james.quinlan@broadcom.com \
--cc=bcm-kernel-feedback-list@broadcom.com \
--cc=bhelgaas@google.com \
--cc=florian.fainelli@broadcom.com \
--cc=jim2101024@gmail.com \
--cc=kibi@debian.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rpi-kernel@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=nsaenz@kernel.org \
--cc=robh@kernel.org \
--cc=svarbanov@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.